Method for establishing logical relationship system of integrated circuit and query method

Abstract

The present invention discloses a method for establishing and querying a logical relationship system of an integrated circuit. The method for establishing the logical relationship system includes: traversing all combinational logic devices in the integrated circuit design; creating a signal association table for each combinational logic device; and generating a logical relationship system based on all the signal association tables and all the signals connected to the combinational logic devices in the integrated circuit design. The logical relationship system includes the driving relationships between all the signal association tables and all the signals associated with the combinational logic devices. The present application establishes a logical relationship system containing the logical relationships between signals through the driving relationships between the associated signals of the combinational logic devices and their truth tables. By querying the logical relationship system, the logical relationships between certain signals can be directly and simply known, and thus a better optimization effect can be achieved in the subsequent optimization process based on the logical relationships between certain signals.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more particularly, to a method for establishing and querying a logical relationship system in an integrated circuit. Background Art

[0002] A digital integrated circuit is a digital logic circuit or system formed by integrating components and connections on the same semiconductor chip. The design of a digital integrated circuit generally includes steps such as RTL (Register Transfer Level) design, logic synthesis, layout and routing of the layout, and data streaming of the layout. RTL design refers to using a hardware description language such as Verilog HDL or VHDL to describe the behavioral model of RTL. Logic synthesis converts the RTL-level description into a gate-level netlist closely related to the process based on various constraint conditions. An automated layout and routing tool can read in the synthesized gate-level netlist and cooperate with the process physical information library and the timing library to perform the layout and routing of the entire chip. Then, a chip is obtained by using semiconductor manufacturing technology.

[0003] During the integrated circuit design process, in some scenarios, it is necessary to clarify the logical relationship between several signals in the combinational logic. For example, when implementing optimization in the logic synthesis stage, better optimization effects can be obtained if the logical relationship between signals is clear. Logical relationships include, for example, equality, mutual exclusion, and other situations.

[0004] Therefore, a method for establishing and querying a logical relationship system including the relationship between signals needs to be provided. Summary of the Invention

[0005] To solve the problems existing in the above-mentioned prior art, the present application provides a method for establishing and querying a logical relationship system of an integrated circuit. Among them, the logical relationship system is an architecture in which the truth tables of all combinational logic devices in an integrated circuit design and their associated signals drive each other, and it includes the logical relationship between signals. By querying the logical relationship system, it can be determined whether there is a relationship between signals and what kind of relationship exists. A better optimization effect can be achieved in the subsequent optimization process.

[0006] According to an embodiment of the present invention, a method for establishing a logical relationship system of an integrated circuit is provided, including:

[0007] Traverse all combinational logic devices in the integrated circuit design;

[0008] Create a signal association table for each combinational logic device; and

[0009] Generate a logical relationship system based on all signal association tables and all signals connected to the combinational logic devices in the integrated circuit design,

[0010] Among them, the logical relationship system includes all the signal association tables and the driving relationships between all the signals associated with the combinational logic devices.

[0011] Optionally, the step of creating the signal association table for each combinational logic device includes:

[0012] Invoking the truth table of the combinational logic device; and

[0013] Based on the truth table of the combinational logic device and the signals associated with the combinational logic device, establishing the signal association table.

[0014] Optionally, the step of establishing the signal association table based on the truth table of the combinational logic device and the signals associated with the combinational logic device includes:

[0015] Corresponding each column of the truth table to the connected signals.

[0016] Optionally, it further includes:

[0017] Establishing and storing the truth tables of multiple combinational logic devices.

[0018] Optionally, it further includes:

[0019] Deleting the conflicting rows in the signal association table;

[0020] Merging the columns where the same signals are located in the signal association table,

[0021] Among them, the conflicting rows refer to the rows where the logical values of the same signal located in different columns are mutually exclusive.

[0022] Optionally, it further includes:

[0023] When merging the columns where the same signals are located in the signal association table, replacing any logical value with the determined logical value.

[0024] Optionally, the step of generating the logical relationship system based on all the signal association tables and all the signals connected to the combinational logic devices in the integrated circuit design includes:

[0025] Corresponding each signal among all the signals connected to the combinational logic device to its own signal driving table and driving signal table,

[0026] Among them, the signal driving table of the signal includes the signal association table of the combinational logic device with the signal as an input, and the driving signal table of the signal includes the signal association table of the combinational logic device with the signal as an output.

[0027] Optionally, it further includes:

[0028] Update the logic relationship system according to the changes of all the combinational logic devices.

[0029] The changes of all the combinational logic devices include at least one of adding a combinational logic device, deleting a combinational logic device, and changing the connection relationship of a combinational logic device.

[0030] Optionally, the change of all the combinational logic devices is adding a combinational logic device, and the step of updating the logic relationship system according to the change of all the combinational logic devices includes:

[0031] Create a signal association table for the newly added combinational logic device; and

[0032] Add the driving relationship between the signal association table of the newly added combinational logic device and the associated signals to the logic relationship system.

[0033] Optionally, the change of all the combinational logic devices is deleting a combinational logic device, and the step of updating the logic relationship system according to the change of all the combinational logic devices includes:

[0034] Remove the signal association table of the deleted combinational logic device; and

[0035] Remove the driving relationship between the signal association table of the deleted combinational logic device and the associated signals from the logic relationship system.

[0036] Optionally, the change of all the combinational logic devices is changing the connection relationship of a combinational logic device, and the step of updating the logic relationship system according to the change of all the combinational logic devices includes:

[0037] Rebuild the signal association table of the combinational logic device with the changed connection relationship and overwrite the previous signal association table; and

[0038] Change the driving relationship between the rebuilt signal association table and the associated signals in the logic relationship system.

[0039] Optionally, the change of all the combinational logic devices is at least two of adding a combinational logic device, deleting a combinational logic device, and changing the connection relationship of a combinational logic device, and the step of updating the logic relationship system according to the change of all the combinational logic devices includes:

[0040] Update the logic relationship system in sequence according to the priority of the changes of all the combinational logic devices.

[0041] Optionally, the priority of updating the logic relationship system according to the addition of combinational logic devices is higher than the priority of updating the logic relationship system according to the deletion of combinational logic devices, and the priority of updating the logic relationship system according to the deletion of combinational logic devices is higher than the priority of updating the logic relationship system according to the change of the connection relationship of combinational logic devices.

[0042] Optionally, it further includes:

[0043] Delete the signals without driving relationship in the updated logic relationship system.

[0044] According to another aspect of the present application, there is provided a query method for a logic relationship system of an integrated circuit, including:

[0045] Set the logic value of a signal in the logic relationship system;

[0046] Update the logic value of the signal in the corresponding signal association table in the logic relationship system;

[0047] Deduce the logic values of other signals based on the logic values of the signals with known logic values in the signal association table; and

[0048] Judge whether the logic values of other signals are deduced. If so, return to the step of setting the logic value of the signal in the logic relationship system. Otherwise, end the query.

[0049] Wherein, in the initial stage of the query, the step of setting the logic value of the signal in the logic relationship system includes setting the logic value of at least one signal; in the step of judging whether the logic values of other signals are deduced, the step of returning to the step of setting the logic value of the signal in the logic relationship system includes setting the deduced logic value of the signal in the logic relationship system.

[0050] Optionally, the step of deducing the logic values of other signals based on the logic values of the signals with known logic values in the signal association table includes:

[0051] Establish a flag bit for all rows of the signal association table where the signals with known logic values are located, and set the initial value of the flag bit to OPEN;

[0052] In all rows where the flag bit is OPEN, set the flag bit of the rows whose values are not equal to the logic value of the set signal to CLOSED;

[0053] Judge whether there is an OPEN row in the signal association table. If so, judge whether the values of a certain signal in all OPEN rows are the same. Otherwise, the deduction is incorrect and this query is exited.

[0054] Among them, to determine whether the values of a certain signal in all OPEN lines are the same. If so, deduce the logical value of the certain signal and end this deduction; otherwise, end the query.

[0055] Optionally, for the lines with the flag bit being CLOSED, the value of the flag bit remains unchanged during the next deduction.

[0056] According to another aspect of the present application, there is provided a method for querying a logic relationship system of an integrated circuit, including:

[0057] Set the logical value of the first signal in the logic relationship system and deduce the corresponding first set of system states;

[0058] Set the logical value of the second signal in the logic relationship system and deduce the corresponding second set of system states;

[0059] Compare whether the first set of system states is exactly the same as the second set of system states.

[0060] Among them, the first set of system states is deduced from the driving signal table of the first signal, and the second set of system states is deduced from the driving signal table of the second signal.

[0061] The present invention provides an integrated circuit logic relationship system establishment method and a query method. The establishment method includes traversing all combinational logic devices in the integrated circuit design, creating a signal association table for each combinational logic device based on the truth table of the combinational logic device and the signals connected to the combinational logic device, and generating a logic relationship system including all signal association tables and the driving relationships between all signals associated with the combinational logic devices. The logic relationship system obtained by the above establishment method implies the logical relationships between certain signals. When determining the logical relationships between signals subsequently, by querying the above logic relationship system, it is only necessary to look up the table to obtain whether there is a logical relationship between certain signals and what kind of signal relationship exists. Compared with the method of directly traversing the logic circuit in the prior art, in the present application, by querying the above logic relationship system, it is possible to obtain whether there is a logical relationship between certain signals and what kind of signal relationship exists, reducing the operation cost. And in the case of knowing the logical relationships between signals, a better optimization effect can be achieved in the subsequent optimization process. Description of the Drawings

[0062] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer.

[0063] Figure 1 The flowchart of a method for establishing a logic relationship system provided by an embodiment of the present application is shown.

[0064] Figure 2 The flowchart shows the process of creating a signal association table for a combinational logic device in a method for establishing a logical relationship system provided by an embodiment of the present application.

[0065] Figures 3a - 3e The schematic diagram shows the establishment of a logical relationship system for a logic circuit in the present application.

[0066] Figure 4 The schematic diagram shows the creation of a signal association table for a combinational logic device in the present application.

[0067] Figures 5a - 5e The schematic diagram shows the update of the logical relationship system in the present application.

[0068] Figure 6 The flowchart shows the process of a query method for a logical relationship system provided by an embodiment of the present application.

[0069] Figure 7 The flowchart shows the self-driving process of the signal association table in a query method for a logical relationship system provided by an embodiment of the present application.

[0070] Figure 8 The flowchart shows the self-driving process of the signal association table in another query method for a logical relationship system provided by an embodiment of the present application. Detailed implementation

[0071] The present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, like elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0072] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques, and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0073] It should be understood that the connection / coupling between A and B in the embodiments of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiments of the present application do not limit this.

[0074] This application relates to the field of integrated circuit design technology. Taking the design of an FPGA integrated circuit as an example for illustration below, an FPGA (Field Programmable Gate Array, programmable logic gate array) is a type of semi-custom circuit in the field of integrated circuits. It not only avoids the deficiencies of fully custom circuits but also overcomes the drawback of the limited number of gate circuits in the original programmable logic devices. During the process of synthesizing a logic circuit, in some scenarios, it is necessary to determine the logical relationships between certain signals. For example, if the logical relationships between signals can be known before optimization, the logic circuit can be simplified to a certain extent. Specifically, for example, during the write port merging and various equivalent circuit merging processes in the memory inference process, determining the logical relationships between certain signals in advance can achieve a better merging effect. Further, in the integrated circuit design, there will be a logic synthesis step. When converting the RTL-level netlist to the gate-level netlist, logic synthesis generally includes three processes: translation, optimization, and mapping. In the optimization stage, if the logical associations between signals are known in advance, optimization can be achieved. Furthermore, in the mapping stage, a simpler hardware can be used to implement the functions of the logic circuit.

[0075] This application provides a method for establishing and querying a logical relationship system of an integrated circuit. Among them, the logical relationship system is a truth table of all combinational logic devices in an integrated circuit design and an architecture in which all signals in the integrated circuit design drive each other. By querying the logical relationship system, it can at least serve the verification link for determining whether there is a relationship between signals and what kind of relationship exists. When it is queried that there are mutually exclusive or equal logical relationships between signals, a better optimization effect can be achieved in the subsequent optimization process.

[0076] The embodiments of the method for establishing and querying the logical relationship system provided by this application will be described below with reference to the accompanying drawings.

[0077] Figure 1 The flowchart of a method for establishing a logical relationship system provided by an embodiment of this application is shown. Figure 2 The flowchart of creating a signal association table of combinational logic devices in a method for establishing a logical relationship system provided by an embodiment of this application is shown. Figures 3a - 3e The schematic diagram of establishing a logical relationship system for a logic circuit in this application is shown.

[0078] The present application proposes a method for establishing a logical relationship system, which is illustrated by taking the logic synthesis stage of integrated circuit design as an example. Further, for example, a logical relationship system including the driving relationship between all signals connected to combinational logic devices and the truth tables of combinational logic devices is established based on all combinational logic devices and all signals in circuit design. Combinational logic devices are a type of digital logic device whose output ports are only related to the current input ports of the device.

[0079] As Figure 1 shown, the method for establishing a logical relationship system includes the following steps:

[0080] Step S110: Traverse all combinational logic devices. Further, traverse all combinational logic devices from the integrated circuit design. Specifically, in combination with Figure 3a for illustration, Figure 3a shows a circuit schematic diagram of a logic circuit. As Figure 3a shown, traverse the integrated circuit design to obtain Figure 3a the pre-logic circuit in, which includes the following combinational logic devices: AND gate U0, multiplexer U1, comparator U2, inverter U3, and the connection relationships of each combinational logic device.

[0081] Step S120: Create a signal association table for each combinational logic device. Further, as Figure 2 shown, this step includes:

[0082] Step S121: Establish and store the truth tables of multiple combinational logic devices. Specifically, in combination with Figure 3b for illustration, Figure 3b shows the truth tables of some common combinational logic devices. The truth table of a combinational logic device is established by listing all possible states between the input and output of a logical event and corresponding to form a table, and the created truth table is stored for later use. Each column in the truth table shows the truth value of one input or one output, and each row shows the logical event between the input and output in a certain case. As Figure 3b shown, the truth tables of, for example, AND gate, OR gate, multiplexer, comparator, and inverter are presented. In the truth table, "1" represents a logical high level, "0" represents a logical low level, and "x" represents any value (which can be a logical high level or a logical low level).

[0083] Step S122: Invoke the truth table of a combinational logic device. Invoke the truth table of a certain combinational logic device from the stored truth tables of multiple combinational logic devices. In this embodiment, the truth tables of the AND gate, multiplexer, comparator, and inverter are respectively invoked to create the signal association tables of each combinational logic device in the pre-logic circuit.

[0084] Step S123: Establish a signal association table based on the truth table of the combinational logic device and the signals associated with the combinational logic device. Specifically, with reference to Figure 3c for illustration, Figure 3c shows Figure 3a the signal association tables of all the combinational logic devices in Figure 3c As shown, by corresponding each column in the truth table of the combinational logic device to the signal connected to the combinational logic device, the signal association table of the combinational logic device is obtained. Among them, the first column of the truth table of AND gate U0 corresponds to the signal S0 connected to the first input terminal of AND gate U0, the second column of the truth table of AND gate U0 corresponds to the signal S1 connected to the second input terminal of AND gate U0, and the third column of the truth table of AND gate U0 corresponds to the signal S5 connected to the output terminal of AND gate U0, thereby obtaining the signal association table T0 of AND gate U0. The first column of the truth table of multiplexer U1 corresponds to the signal S2 connected to the first input terminal of multiplexer U1, the second column of the truth table of multiplexer U1 corresponds to the signal S3 connected to the second input terminal of multiplexer U1, the third column of the truth table of multiplexer U1 corresponds to the signal S1 connected to the selection terminal of multiplexer U1, and the fourth column of the truth table of multiplexer U1 corresponds to the signal S4 connected to the output terminal of multiplexer U1, thereby obtaining the signal association table T1 of multiplexer U1. The first column of the truth table of comparator U2 corresponds to the signal S5 connected to the first input terminal of comparator U2, the second column of the truth table of comparator U2 corresponds to the signal S4 connected to the second input terminal of comparator U2, and the third column of the truth table of comparator U2 corresponds to the signal S6 connected to the output terminal of comparator U2, thereby obtaining the signal association table T2 of comparator U2. The first column of the truth table of inverter U3 corresponds to the signal S6 connected to the input terminal of inverter U3, and the second column of the truth table of inverter U3 corresponds to the signal S7 connected to the output terminal of inverter U3, thereby obtaining the signal association table T3 of inverter U3.

[0085] Next, step S130: Generate a logic relationship system based on all the signal association tables and the signals associated with the combinational logic device. Among them, the logic relationship system includes the driving relationship between all the signal association tables in the pre-logic circuit and all the signals connected to the combinational logic device. Subsequently, by querying the logic relationship system, it can be determined whether there is a relationship between certain signals and what kind of relationship exists. Specifically, with reference to Figure 3d for illustration, Figure 3d shows Figure 3a the logic relationship system of the logic circuit in Figure 3dShown is a logical relationship system in tabular form. Among them, each signal in all the signals connected to the combinational logic device corresponds to its own signal drive table and drive signal table to obtain the logical relationship system of the pre-logic circuit. Further, the signal drive table ST of a signal includes the signal association table of the combinational logic device with this signal itself as an input, and the drive signal table DT of a signal includes the signal association table of the combinational logic device with this signal itself as an output. As Figure 3d shown, the signal S0 is only connected to the first input terminal of the AND gate U0 in the Figure 3a logic circuit, that is, the signal S0 is used as the input of the AND gate U0 and is not the output of any combinational logic device in this logic circuit. Therefore, the signal drive table ST of the signal S0 includes the signal association table T0 of the AND gate U0, and the drive signal table DT of the signal S0 has no signal association table. Correspondingly, Figure 3d in the table, the column of the drive signal table DT of the signal S0 is set to "none", and the column of the signal drive table ST of the signal S0 is set to "T0". Subsequently, when querying the logical relationship system, when reading the signal drive table ST of the signal S0, it can jump to the signal association table T0. The signal S1 is respectively connected to Figure 3a the second input terminal of the AND gate U0 in the logic circuit and the selection terminal of the multiplexer U1, that is, the signal S1 is used as the input of the AND gate U0 and the input of the multiplexer U1 and is not the output of any combinational logic device in this logic circuit. Therefore, the signal drive table ST of the signal S1 includes the signal association table T0 of the AND gate U0 and the signal association table T1 of the multiplexer U1, and the drive signal table DT of the signal S1 has no signal association table. Correspondingly, Figure 3d in the table, the column of the drive signal table DT of the signal S1 is set to "none", and the column of the signal drive table ST of the signal S1 is set to "T0, T1". Subsequently, when querying the logical relationship system, when reading the signal drive table ST of the signal S1, it can jump to the signal association table T0 and the signal association table T1. The signal S2 is connected to Figure 3a the first input terminal of the multiplexer U1 in the logic circuit, that is, the signal S2 is used as the input of the multiplexer U1 and is not the output of any combinational logic device in this logic circuit. Therefore, the signal drive table ST of the signal S2 includes the signal association table T1 of the multiplexer U1, and the drive signal table DT of the signal S2 has no signal association table. Correspondingly, Figure 3d in the table, the column of the drive signal table DT of the signal S2 is set to "none", and the column of the signal drive table ST of the signal S2 is set to "T1". Subsequently, when querying the logical relationship system, when reading the signal drive table ST of the signal S2, it can jump to the signal association table T1. The signal S3 is connected to Figure 3ais connected to the second input terminal of the multiplexer U1 in the logic circuit, that is, the signal S3 is used as the input of the multiplexer U1 and is not the output of any combinational logic device in this logic circuit. Therefore, the signal drive table ST of the signal S3 includes the signal association table T1 of the multiplexer U1, and the drive signal table DT of the signal S3 has no signal association table. Correspondingly, Figure 3d in the table, set the drive signal table DT column of the signal S3 to "none", and set the signal drive table ST column of the signal S3 to "T1". When querying the logic relationship system later, when reading the signal drive table ST of the signal S3, it can jump to the signal association table T1. The signal S5 is respectively connected to Figure 3a the output terminal of the AND gate U0 and the first input terminal of the comparator U2 in the logic circuit, that is, the signal S5 is used as the output of the AND gate U0 and the input of the comparator U2. Therefore, the signal drive table ST of the signal S5 includes the signal association table T2 of the comparator U2, and the drive signal table DT of the signal S5 includes the signal association table T0 of the AND gate U0. Correspondingly, Figure 3d in the table, set the drive signal table DT column of the signal S5 to "T0", and set the signal drive table ST column of the signal S5 to "T2". When querying the logic relationship system later, when reading the signal drive table ST of the signal S5, it can jump to the signal association table T2, and when reading the drive signal table DT of the signal S5, it can jump to the signal association table T0. The signal S4 is respectively connected to Figure 3a the output terminal of the multiplexer U1 and the second input terminal of the comparator U2 in the logic circuit, that is, the signal S4 is used as the output of the multiplexer U1 and the input of the comparator U2. Therefore, the signal drive table ST of the signal S4 includes the signal association table T2 of the comparator U2, and the drive signal table DT of the signal S4 includes the signal association table T1 of the multiplexer U1. Correspondingly, Figure 3d in the table, set the drive signal table DT column of the signal S4 to "T1", and set the signal drive table ST column of the signal S4 to "T2". When querying the logic relationship system later, when reading the signal drive table ST of the signal S4, it can jump to the signal association table T2, and when reading the drive signal table DT of the signal S4, it can jump to the signal association table T1. The signal S6 is respectively connected to Figure 3a the output terminal of the comparator U2 and the input terminal of the inverter U3 in the logic circuit, that is, the signal S6 is used as the output of the comparator U2 and the input of the inverter U3. Therefore, the signal drive table ST of the signal S6 includes the signal association table T3 of the inverter U3, and the drive signal table DT of the signal S6 includes the signal association table T2 of the comparator U2. Correspondingly, Figure 3dIn the table, the drive signal table DT of signal S6 is set to "T2", and the signal drive table ST of signal S6 is set to "T3". Subsequently, when querying the logic relationship system, when reading the signal drive table ST of signal S6, it can jump to the signal association table T3, and when reading the drive signal table DT of signal S6, it can jump to the signal association table T2. Signal S7 is only connected to the output terminal of the inverter U3 in the logic circuit in Figure 3a , that is, signal S7 is the output of the inverter U3 and is not the input of any combinational logic device in this logic circuit. Therefore, there is no signal association table in the signal drive table ST of signal S7, and the drive signal table DT of signal S7 includes the signal association table T3 of the inverter U3. Correspondingly, Figure 3d In the table, the drive signal table DT of signal S7 is set to "T3", and the signal drive table ST of signal S7 is set to "none". Subsequently, when querying the logic relationship system, when reading the drive signal table DT of signal S7, it can jump to the signal association table T3.

[0086] In other embodiments, in combination with Figure 3e for illustration, Figure 3e shows Figure 3a the logic relationship system of the logic circuit in Figure 3e shown is a logic relationship system in a topological form. As shown in Figure 3eAs shown in the figure, in the logical relationship system in topological form, a signal is connected to its own signal drive table ST and drive signal table DT. In the logical relationship system in topological form, a signal serves as the input of its own signal drive table ST and as the output of its own drive signal table DT. Among them, the signal drive table ST of signal S0 is the signal association table T0, and signal S0 has no drive signal table DT, so signal S0 only serves as the input of the signal association table T0. The signal drive table ST of signal S1 is the signal association table T0 and the signal association table T1, and signal S1 has no drive signal table DT, so signal S1 only serves as the input of the signal association table T0 and the signal association table T1. The signal drive table ST of signal S2 is the signal association table T1, and signal S2 has no drive signal table DT, so signal S2 only serves as the input of the signal association table T1. The signal drive table ST of signal S3 is the signal association table T1, and signal S3 has no drive signal table DT, so signal S3 only serves as the input of the signal association table T1. The signal drive table ST of signal S4 is the signal association table T2, and the drive signal table DT of signal S4 is the signal association table T1, so signal S4 serves as the input of the signal association table T2 and as the output of the signal association table T1. The signal drive table ST of signal S5 is the signal association table T2, and the drive signal table DT of signal S5 is the signal association table T0, so signal S5 serves as the input of the signal association table T2 and as the output of the signal association table T0. The signal drive table ST of signal S6 is the signal association table T3, and the drive signal table DT of signal S6 is the signal association table T2, so signal S6 serves as the input of the signal association table T3 and as the output of the signal association table T2. The drive signal table DT of signal S7 is the signal association table T3, and signal S0 has no signal drive table ST, so signal S7 only serves as the output of the signal association table T3. The above logical relationship system in topological form has the same function as the logical relationship system in tabular form.

[0087] In other embodiments, in the process of establishing a logical relationship system, it may occur that the signals at at least two input terminals of some combinational logic devices are the same, that is, one signal may drive two or more ports in the same combinational logic device. The following will describe how to create the signal association table of this combinational logic device in this scenario with examples, but the following solutions of the present application are applicable to all cases where the signals at at least two input terminals of the combinational logic device are the same.

[0088] Figure 4 The figure shows a schematic diagram of creating a signal association table for a combinational logic device in the present application.

[0089] As Figure 4As shown, the combinational logic device is illustrated by taking the 4-to-1 multiplexer U4 as an example. Among them, the first input terminal i2 of the 4-to-1 multiplexer U4 is connected to the signal S0, the second input terminal i3 of the 4-to-1 multiplexer U4 is connected to the signal S1, the third input terminal i4 of the 4-to-1 multiplexer U4 is connected to the signal S2, the fourth input terminal i5 of the 4-to-1 multiplexer U4 is connected to the signal S3, the first selection terminal i0 of the 4-to-1 multiplexer U4 is connected to the signal S0, and the second selection terminal i1 of the 4-to-1 multiplexer U4 is connected to the signal S2. First, the truth table of the 4-to-1 multiplexer is called from the pre-stored truth table library. Then, by corresponding each column in the truth table of the 4-to-1 multiplexer with the signals connected to the 4-to-1 multiplexer U4, a signal association table of the 4-to-1 multiplexer U4 is obtained. Further, the above signal association table is simplified. For example, the conflicting rows in the above signal association table are deleted. The conflicting rows refer to the rows where the logical values of the same signal in different columns in the signal association table are mutually exclusive. Among them, in the third row of this signal association table, the logical values of the signal S0 in the first column and the third column are mutually exclusive; and in the seventh row of this signal association table, the logical values of the signal S2 in the second column and the fifth column are mutually exclusive. Therefore, the third row and the seventh row are the conflicting rows in this signal association table and should be deleted. And the columns where the same signal is located in the signal association table are merged. Among them, the logical values of the first column and the third column in this signal association table are for the same signal S0 and should be merged into one column. In a preferred embodiment, when merging the columns where the same signal is located in the signal association table, the determined logical value is used to replace any logical value. For example, in the same row of the signal association table, the determined logical value (0 or 1) of the signal S0 in the first column is used to replace the arbitrary logical value x of the signal S0 in the third column and merged. Similarly, in the same row of the signal association table, the determined logical value (0 or 1) of the signal S2 in the second column is used to replace the arbitrary logical value x of the signal S2 in the fifth column and merged. Furthermore, after deleting the conflicting rows and merging the columns where the same signal is located, a simplified signal association table is obtained.

[0090] The method for establishing the logical relationship system provided in this application also involves the maintenance of the logical relationship system. That is, in the case of a slight change in the circuit structure, the system can be updated at the minimum cost without reconstructing the entire logical relationship system. There are three scenarios in which the logical relationship system changes, namely adding a combinational logic device, changing a combinational logic device, and deleting a combinational logic device. The operation of maintaining the logical relationship system can be manually performed by an upper-layer user who modifies the circuit structure, for example. Here, it continues to take making changes based on the Figure 3a logic circuit as an example for illustration.

[0091] Figures 5a - 5e shows a schematic diagram of updating the logical relationship system in this application.

[0092] AsFigure 5a As shown Figure 3a in the circuit topologies before and after the change of the logic circuit shown. Among them, the combinational logic devices: inverter U5 and OR gate U6 are added to the changed logic circuit. The combinational logic devices: comparator U2 and inverter U3 are deleted from the changed logic circuit. The connection relationship of the multiplexer U1 in the changed logic circuit has changed. The following takes the change of the above logic circuit structure as an example to describe in detail how to update the logic relationship system when adding combinational logic devices, changing combinational logic devices, and deleting combinational logic devices.

[0093] As Figure 5b shown, a schematic diagram of updating the logic relationship system when adding combinational logic devices to the logic circuit is shown. First, create a signal association table for the newly added combinational logic device. Then, add the driving relationship between the signal association table of the newly added combinational logic device and the surrounding associated signals to the logic relationship system. Further, first create a signal association table T5 for the inverter U5 and a signal association table T6 for the OR gate U6. Among them, in the signal association table T5, the signal S5 connected to the input terminal of the inverter U5 corresponds to the first column of the truth table of the inverter U5, and the signal S8 connected to the output terminal of the inverter U5 corresponds to the second column of the truth table of the inverter U5. In the signal association table T6, the signal S8 connected to the first input terminal of the OR gate U6 corresponds to the first column of the truth table of the OR gate U6, the signal S4 connected to the second input terminal of the OR gate U6 corresponds to the second column of the truth table of the OR gate U6, and the signal S7 connected to the output terminal of the OR gate U6 corresponds to the third column of the truth table of the OR gate U6. Then update Figure 3a the initial logic relationship system of the logic circuit in Figure 3d or Figure 3e as shown in Figure 3d for example). On the basis of the initial logic relationship system in Figure 3d , add the driving relationship between the signal association table of the newly added combinational logic device and the surrounding associated signals. Specifically, on the basis of the initial logic relationship system, add the logic that the signal S4 drives the signal association table T6, the logic that the signal S5 drives the signal association table T5, the logic that the signal S8 drives the signal association table T6, the logic that the signal association table T6 drives the signal S7, and the logic that the signal association table T5 drives the signal S8, and then obtain Figure 5b the first intermediate logic relationship system in

[0094] As Figure 5cAs shown, a schematic diagram of updating a logic relationship system when deleting a combinational logic device in a logic circuit is shown. First, the signal association table of the deleted combinational logic device is removed. Then, the driving relationship between the signal association table of the deleted combinational logic device and the surrounding associated signals is removed in the logic relationship system. Further, in this embodiment, the update operation of deleting the combinational logic device is based on Figure 5b the first intermediate logic relationship system in. Further, first, the signal association table T2 of the comparator U2 and the signal association table T3 of the inverter U3 are deleted. Then, the logic having a driving relationship or a driven relationship with the signal association table of the deleted combinational logic device is removed in the first intermediate logic relationship system. That is, based on the first intermediate logic relationship system, the logic of signal S4 driving signal association table T2, the logic of signal S5 driving signal association table T2, the logic of signal S6 driving signal association table T3, the logic of signal association table T2 driving signal S6, and the logic of signal association table T3 driving signal S7 are deleted, and then Figure 5c the second intermediate logic relationship system in is obtained.

[0095] As Figure 5d shown, a schematic diagram of updating a logic relationship system when changing the connection relationship of a combinational logic device in a logic circuit is shown. First, the signal association table of the combinational logic device with the changed connection relationship is reconstructed. Then, the driving relationship between the signal association table of the reconstructed combinational logic device and the surrounding associated signals is changed in the logic relationship system. Further, based on the new connection relationship of the multiplexer U1, the signal association table T1' of the multiplexer U1 is reconstructed, and the signal association table T1' covers the initial signal association table T1. Among them, in Figure 5a the changed logic circuit, the two ends of the multiplexer U1 are connected to the same signal S1, and then the signal association table of the multiplexer U1 can be reconstructed based on Figure 4 the simplified method disclosed in to obtain the simplified signal association table T1' of the multiplexer U1, and the specific steps are not elaborated here. Then, the update operation based on changing the connection relationship of the combinational logic device is based on Figure 5c the second intermediate logic relationship system in. Further, the logic involving the multiplexer U1 is changed in the second intermediate logic relationship system. That is, based on the second intermediate logic relationship system, first, the signal association table T1 is replaced with the signal association table T1', then the logic of signal S1 driving signal association table T1' is added and the logic of signal S2 driving signal association table T1' is deleted, and then Figure 5d the updated logic relationship system in is obtained.

[0096] When operating the above-mentioned update logic relation system that separately processes three operations of logical circuit changes, when a signal has neither a driving signal table nor a signal driving table, the signal is deleted in the intermediate logic relation system. Or after all the update operations are completed, the signals that have neither a driving signal table nor a signal driving table are deleted in the updated logic relation system.

[0097] In this embodiment, a situation where combinational logic devices are simultaneously added and deleted and the connection relationships of the combinational logic devices are changed in the original logic circuit is shown. In this case, the logic relation system is updated in sequence according to the priorities of the changes of all combinational logic devices. Further, the priority of updating the logic relation system according to the addition of combinational logic devices is higher than the priority of updating the logic relation system according to the deletion of combinational logic devices, and the priority of updating the logic relation system according to the deletion of combinational logic devices is higher than the priority of updating the logic relation system according to the change of the connection relationships of the combinational logic devices. In this embodiment, an update method that first processes the operation of updating the logic relation system based on the addition of combinational logic devices, then processes the operation of updating the logic relation system based on the deletion of combinational logic devices, and finally processes the operation of updating the logic relation system based on the change of the connection relationships of the combinational logic devices is adopted to achieve the effect of maintaining the logic relation system. Based on the above, when only one or two of the addition, deletion of combinational logic devices, and change of the connection relationships of combinational logic devices occur in the original logic circuit, it is only necessary to perform in sequence based on the above processing method, and there is no need to process the corresponding update actions for the unappeared change methods.

[0098] By querying the logical relationship system, it is possible to clarify whether there is a logical relationship between certain signals and what kind of logical relationship exists. For example, whether two signals are equal, whether they are opposite, and whether at most one of multiple signals is 1. The present application provides the following methods to query the logical relationship system to achieve the above purpose. For example, query the logical relationship system by direct derivation or indirect derivation. Direct derivation is to assume the values of one or several signals, and then query the logical relationship system to independently derive the logical values of other signals based on the assumed logical values, and observe whether they meet certain conditions. For example, to test whether s0 and s1 are always equal, first assume that signal s0 is 1. If it is deduced that signal s1 is also 1 at this time, then assume that signal s0 is 0, and then deduce that signal s1 is also 0 at this time. Then it can be determined that signal s0 and signal s1 have an equal logical relationship. Indirect derivation is to assume the logical value of the first signal and then perform derivation to obtain the first set of system states. Then, assume the logical value of the second signal and perform derivation to obtain the second set of system states, and compare the first set of system states with the second set of system states. If the two sets of system states are the same, then a certain relationship between the two sets of signals can be obtained. Here, the definition of system state refers to all combinations between the deduced signal logical states. Among them, indirect derivation requires strict comparison of whether the two sets of system states are equal. Therefore, when deriving, only the corresponding system states are derived from the driving signal tables of the first signal and the second signal, and cannot be derived from the signal driving table of the signal.

[0099] The following discloses querying whether there is a logical relationship between signals and what kind of signal relationship exists by directly deriving through querying the logical relationship system.

[0100] Figure 6 The flowchart shows a method for querying a logical relationship system provided by an embodiment of the present application. Figure 7 The flowchart shows the self-driving of the signal association table in a method for querying a logical relationship system provided by an embodiment of the present application. This query method can implement the verification link in direct logical relationship derivation.

[0101] Such as Figure 6 As shown, a method for querying a logical relationship system is shown, including the following steps:

[0102] Step S210: Set the logical values of signals in the logical relationship system. Taking Figure 5d the updated logical relationship system in [5d] as the query object, at the initial stage of the query, set the logical values of at least one signal in the logical relationship system. For example, assume that the logical value of signal S7 is 0 and the logical value of signal S4 is 0. Set signal S7 in the updated logical relationship system in [5d] to 0 and signal S4 to 0. Then, after deriving the logical values of other signals, set the logical values of the derived signals correspondingly in the logical relationship system.

[0103] Step S220: Update the logical values of the signals in the corresponding signal association table in the logical relationship system. Further, update the logical value of signal S4 in signal association table T1' of driving signal S4 and in signal association table T5 of the signal driven by signal S4 to 0. And update the logical value of signal S7 in signal association table T5 of driving signal S7 to 0. And then update the logical values of the signals in the corresponding signal association table based on the derived logical values of other signals.

[0104] Step S230: Deduce the logical values of unknown signals based on the known logical values of the signals in the signal association table. Further, query signal association table T5 and signal association table T1' based on the logical values of the above-mentioned known signals (signal S4, signal S7). This deduction can determine the logical value of signal S8 under the assumed conditions, and the logical values of other unknown signals cannot be deduced temporarily under the assumed conditions.

[0105] Step S240: Determine whether the logical values of unknown signals are deduced. If so, continue to return to execute step S210, otherwise end this query. Among them, when querying signal association table T5, the logical value of signal S8 can be uniquely determined to be 0. Then continue to return to step S210, and set the logical value of signal S8 to 0 in the logical relationship system, and then continue to execute the following steps to complete multiple deductions until the signal values cannot be updated and then end.

[0106] If under the conditions that signal S7 is 0 and signal S4 is 0, all signals can be deduced after multiple deductions. Then it can be known the logical relationship between the signals with assumed logical values (signal S4 and signal S7 in this embodiment) and the signals whose logical values are obtained through deduction. This embodiment is only to illustrate how to query the logical relationship table to complete the direct deduction of the logical relationship between signals, so the query results are not elaborated here.

[0107] In this embodiment, when performing the deduction in step S230, if the logical values of unknown signals can be deduced, this deduction is successful, and then the next deduction is carried out; if a deduction is incorrect, it means that the assumed conditions do not hold, and this query is exited. When querying the logical relationship between signals, generally multiple deductions are required. In this embodiment, a method of self-driving of the signal association table is also proposed to deduce the logical values of unknown signals.

[0108] As Figure 7 shown, when performing step S230, it includes the following steps:

[0109] Step S231: Establish a flag bit for all rows of the signal association table where the signals with known logical values are located, and set the initial value of the flag bit to OPEN.

[0110] Step S232: Among all the rows where the flag bit is OPEN, set the flag bit of the rows whose values are not equal to the logical value of the set signal to CLOSED. Among them, the flag bits of the rows with the flag bit being CLOSED remain unchanged in the next derivation.

[0111] Step S233: Determine whether there is an OPEN row in the corresponding signal association table. If so, continue to execute Step S234; otherwise, the derivation is incorrect and this query is exited.

[0112] Step S234: Determine whether the values of a certain signal in all OPEN rows are the same. If so, derive the logical value of a certain signal and end this derivation; otherwise, end the query.

[0113] The following discloses a method for indirectly deriving through querying a logical relationship system to query whether there is a logical relationship between signals and what kind of signal relationship exists.

[0114] Figure 8 The flowchart shows another method for querying a logical relationship system provided by an embodiment of the present application.

[0115] As Figure 8 shown, another method for querying a logical relationship system is shown, including the following steps:

[0116] Step S310: Set the logical value of the first signal in the logical relationship system and derive the corresponding first set of system states.

[0117] Step S320: Set the logical value of the second signal in the logical relationship system and derive the corresponding second set of system states;

[0118] Step S330: Compare the first set of system states and the second set of system states.

[0119] Among them, the first set of system states is derived from the drive signal table of the first signal, and the second set of system states is derived from the drive signal table of the second signal. When the comparison result obtained in Step S330 is exactly the same, the logical relationship between the first signal and the second signal can be obtained; otherwise, this query is exited.

[0120] Furthermore, Figure 5dTaking the logical relationship system in [as an example], the first signal is, for example, signal S5, whose logical value is set to 0. Then, in the driving signal table DT of signal S5, that is, signal association table T0, the first set of system states is derived, including: signals S0, S1 (10, 01, 00). The second signal is, for example, signal S7, whose logical value is set to 1. Then, in the driving signal table DT of signal S7, that is, signal association table T6, the second set of system states is derived, including: signals S8, S4 (10, 01, 11). Then, in step S330, the comparison result is not exactly the same, so the logical relationship between the first signal and the second signal cannot be directly derived.

[0121] In other embodiments, the present application can also query the logical relationship system by combining direct derivation and indirect derivation to obtain the logical relationship between certain signals.

[0122] At the same time, those of ordinary skill in the art can realize that, in combination with the structures and methods of the various examples described in the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or a reasonable deformation of the structure. However, such implementation should not be considered to exceed the scope of the present application. And it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of the present application are illustrative examples and do not impose any limitations on the embodiments of the present application.

[0123] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0124] According to the embodiments of the present invention as described above, these embodiments do not elaborate on all details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for establishing a logic relationship system of an integrated circuit, characterized in that, comprising: traversing all combinational logic devices in the integrated circuit design; creating a signal association table for each combinational logic device; and generating a logic relationship system based on all the signal association tables and all the signals connected to the combinational logic devices in the integrated circuit design, including corresponding each signal in all the signals connected to the combinational logic devices to the signal drive table and the drive signal table of the signal itself, wherein, the signal drive table of the signal includes the signal association table of the combinational logic device with the signal itself as an input, and the drive signal table of the signal includes the signal association table of the combinational logic device with the signal itself as an output, wherein, the logic relationship system includes the drive relationship between all the signal association tables and all the signals associated with the combinational logic devices.

2. The method for establishing a logic relationship system of an integrated circuit according to claim 1, characterized in that, the step of creating a signal association table for each combinational logic device includes: invoking the truth table of the combinational logic device; and establishing the signal association table based on the truth table of the combinational logic device and the signals associated with the combinational logic device.

3. The method for establishing a logic relationship system of an integrated circuit according to claim 2, characterized in that, the step of establishing the signal association table based on the truth table of the combinational logic device and the signals associated with the combinational logic device includes: corresponding each column of the truth table to the connected signals.

4. The method for establishing a logic relationship system of an integrated circuit according to claim 2, characterized in that, further comprising: establishing and storing the truth tables of multiple combinational logic devices.

5. The method for establishing a logic relationship system of an integrated circuit according to claim 3, characterized in that, further comprising: deleting the conflicting rows in the signal association table; merging the columns where the same signals are located in the signal association table, wherein, the conflicting rows refer to the rows where the logic values of the same signal in different columns are mutually exclusive.

6. The method for establishing a logic relationship system of an integrated circuit according to claim 5, characterized in that, further comprising: when merging the columns where the same signals are located in the signal association table, replacing any logic value with the determined logic value.

7. The method for establishing a logic relationship system of an integrated circuit according to claim 1, characterized in that, further comprising: updating the logic relationship system according to the changes of all the combinational logic devices, wherein the changes of all the combinational logic devices include at least one of adding a combinational logic device, deleting a combinational logic device, and changing the connection relationship of the combinational logic device.

8. The method for establishing a logic relationship system of an integrated circuit according to claim 7, characterized in that, when the change of all the combinational logic devices is adding a combinational logic device, the step of updating the logic relationship system according to the changes of all the combinational logic devices includes: creating a signal association table for the newly added combinational logic device; and adding the drive relationship between the signal association table of the newly added combinational logic device and the associated signals to the logic relationship system.

9. The method for establishing the logic relationship system of an integrated circuit according to claim 7, characterized in that, the change of all the combinational logic devices is to delete the combinational logic devices, and the step of updating the logic relationship system according to the change of all the combinational logic devices includes: removing the signal association table of the deleted combinational logic device; and removing the driving relationship between the signal association table of the deleted combinational logic device and the associated signal in the logic relationship system.

10. The method for establishing the logic relationship system of an integrated circuit according to claim 7, characterized in that, the change of all the combinational logic devices is to change the connection relationship of the combinational logic device, and the step of updating the logic relationship system according to the change of all the combinational logic devices includes: reconstructing the signal association table of the combinational logic device with the changed connection relationship and overwriting the previous signal association table; and changing the driving relationship between the reconstructed signal association table and the associated signal in the logic relationship system.

11. The method for establishing the logic relationship system of an integrated circuit according to claim 7, characterized in that, the change of all the combinational logic devices is at least two of adding combinational logic devices, deleting combinational logic devices, and changing the connection relationship of combinational logic devices, and the step of updating the logic relationship system according to the change of all the combinational logic devices includes: updating the logic relationship system in sequence according to the priority of the change of all the combinational logic devices.

12. The method for establishing the logic relationship system of an integrated circuit according to claim 11, characterized in that, the priority of updating the logic relationship system according to adding combinational logic devices is higher than the priority of updating the logic relationship system according to deleting combinational logic devices, and the priority of updating the logic relationship system according to deleting combinational logic devices is higher than the priority of updating the logic relationship system according to changing the connection relationship of combinational logic devices.

13. The method for establishing the logic relationship system of an integrated circuit according to claim 7, characterized in that, further comprising: deleting the signals without driving relationship in the updated logic relationship system.

14. A method for querying the logic relationship system of an integrated circuit according to any one of claims 1-13, characterized in that, comprising: setting the logic value of a signal in the logic relationship system; updating the logic value of the signal in the corresponding signal association table in the logic relationship system; deriving the logic value of other signals according to the logic value of the signal with the known logic value in the signal association table; and judging whether the logic value of other signals is derived, if so, returning to the step of setting the logic value of the signal in the logic relationship system, otherwise ending the query, wherein, in the initial stage of the query, the step of setting the logic value of the signal in the logic relationship system includes setting the logic value of at least one signal; in the step of judging whether the logic value of other signals is derived, the step of returning to the step of setting the logic value of the signal in the logic relationship system includes setting the derived logic value of the signal in the logic relationship system.

15. The method for querying the logic relationship system according to claim 14, characterized in that, The step of deriving the logical values of other signals based on the logical values of the signals with known logical values in the signal correlation table includes: Establish a flag bit for all rows of the signal correlation table where the signals with known logical values are located, and set the initial value of the flag bit to OPEN; In all rows where the flag bit is OPEN, set the flag bit of the rows whose values are not equal to the logical values of the signals that have been set to CLOSED; Determine whether there is an OPEN row in the signal correlation table. If so, determine whether the values of a certain signal in all OPEN rows are the same. Otherwise, the derivation is incorrect and this query is exited. Among them, when determining whether the values of a certain signal in all OPEN rows are the same, if so, derive the logical value of the certain signal and end this derivation. Otherwise, end the query.

16. The query method of the logical relationship system according to claim 15, characterized in that, The value of the flag bit of the row with the flag bit CLOSED remains unchanged during the next derivation.

17. A query method of the logical relationship system of an integrated circuit according to any one of claims 1-13, characterized in that, includes: Set the logical value of the first signal in the logical relationship system and derive the corresponding first set of system states; Set the logical value of the second signal in the logical relationship system and derive the corresponding second set of system states; Compare the first set of system states and the second set of system states, Among them, the first set of system states is derived from the driving signal table of the first signal, and the second set of system states is derived from the driving signal table of the second signal.

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