Data processing method, device and storage medium

Abstract

The embodiment of the present invention discloses a data processing method, device and storage medium, belonging to the field of communication technology. The method includes: storing the data in the matrix to be processed included in the received task request in the input register file; determining the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and the preset mapping information; configuring the computing resources in the resource pool according to the number of blocks of the matrix to be processed, and determining the computing unit information of parallel between blocks; reading the target processing instructions from the target processing instruction storage address in sequence, and processing the data stored in the input register file in parallel according to the computing units corresponding to the target processing instructions and the computing unit information of parallel between blocks. The data processing method can realize the processing of matrices of multiple dimensions on the one hand, with strong programmability and scalability, and can process data in parallel on the other hand, with low latency and high efficiency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to a data processing method, device and storage medium. Background Art

[0002] Multiple-Input Multiple-Output (MIMO) technology uses multiple antennas (or array antennas) and multiple channels to send and receive signals simultaneously at both the transmitting and receiving ends. The transmission and reception of multiple antennas can greatly improve data transmission efficiency and signal stability, thereby qualitatively improving network quality, network speed, and user capacity. Therefore, MIMO technology is the core technology of the fifth-generation mobile communication technology network and wireless Internet access (Wi-Fi) 6, and is also the core of future wireless network development.

[0003] Signal processing in MIMO requires a large number of matrix operations. Among them, matrix inversion is the most complex matrix operation. Given the conjugate symmetry of matrices in MIMO, the inversion of the lower triangular matrix is ​​particularly important. The calculation speed of the lower triangular matrix inversion operation directly affects the real-time performance of the MIMO system, thereby affecting the performance of the entire MIMO system.

[0004] There are many methods for matrix inversion, and there are different methods for different dimensions to obtain different performance. For example, for a 2*2 matrix, you can directly expand the inversion theorem; for a 4*4 matrix, you can either calculate the adjoint matrix according to the definition or use the block inversion decomposition algorithm in matrix theory; for the inversion implementation method of 6*6 (inclusive) or above dimensions, you can use the Cholesky simplified decomposition algorithm. We have entered the era of large-scale MIMO, and it is necessary to invert matrices of various dimensions, even high-dimensional matrices. The computational complexity of matrix inversion is proportional to the power of the dimension. Therefore, when the matrix dimension is large, the computational complexity and amount of inversion are very high. In short, matrix inversion in MIMO requires many algorithms to be supported, large dimensions, high computational complexity, and short processing time.

[0005] Currently, matrix inversion is mainly performed through application-specific integrated circuits (ASICs), which are hardwired to process one or more types of matrix inversion algorithms, and can achieve optimal efficiency and power consumption.

[0006] However, in the above matrix inversion method, the types of matrices supported by ASIC are limited, and the scalability and scalability are poor. Summary of the invention

[0007] The main purpose of the embodiments of the present invention is to propose a data processing method, device and storage medium, aiming to achieve the function of efficiently determining the inverse matrix of matrices of multiple dimensions.

[0008] To achieve the above object, an embodiment of the present invention provides a data processing method, which includes the following steps:

[0009] storing the data in the matrix to be processed included in the received task request in an input register file; wherein the task request includes: the data in the matrix to be processed, the dimension of the matrix to be processed and the number of blocks of the matrix to be processed;

[0010] According to the dimension of the matrix to be processed and the preset mapping information, a target processing instruction storage address corresponding to the matrix to be processed is determined; wherein the mapping information is used to indicate a mapping relationship between the dimension of the matrix and the processing instruction storage address, and the target processing instruction stored in the target processing instruction storage address is used to determine the inverse matrix of the matrix to be processed;

[0011] According to the number of blocks of the matrix to be processed, the computing resources in the resource pool are configured to determine the computing unit information of the parallel computing between the blocks;

[0012] The target processing instructions are sequentially read from the target processing instruction storage address, and the data stored in the input register file are processed in parallel according to the target processing instructions and the computing units corresponding to the inter-block parallel computing unit information.

[0013] To achieve the above objectives, an embodiment of the present invention further proposes a data processing device, which includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory, and the program implements the steps of the aforementioned method when executed by the processor.

[0014] To achieve the above objectives, an embodiment of the present invention provides a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the aforementioned method.

[0015] The data processing method, device and storage medium proposed in this embodiment include: storing the data in the matrix to be processed included in the received task request in an input register file, wherein the task request includes: the data in the matrix to be processed, the dimension of the matrix to be processed and the number of blocks of the matrix to be processed; determining the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and preset mapping information, wherein the mapping information is used to indicate the mapping relationship between the dimension of the matrix and the processing instruction storage address, and the target processing instruction stored in the target processing execution storage address is used to determine the inverse matrix of the matrix to be processed; configuring the computing resources in the resource pool according to the number of blocks of the matrix to be processed, and determining the computing unit information of parallelism between blocks; reading the target processing instructions from the target processing instruction storage address in sequence, and processing the data stored in the input register file in parallel according to the computing units corresponding to the target processing instructions and the computing unit information of parallelism between blocks. The data processing method can obtain the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed. At the same time, it can also configure the computing resources in the resource pool according to the number of blocks of the matrix to be processed, determine the computing unit information of parallel between blocks, and then, according to the target processing instructions read in sequence from the target processing instruction storage address and the computing units corresponding to the computing unit information of parallel between blocks, parallelly process the data stored in the input register file. On the one hand, it can realize the processing of matrices of various dimensions, with strong programmability and scalability, and on the other hand, it can process data in parallel, with low latency and high efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of a data processing method provided by an embodiment;

[0017] Figure 2 A schematic diagram of a flow chart of a data processing method embodiment provided by another embodiment;

[0018] Figure 3 A schematic diagram of the structure of a data processing device provided by an embodiment;

[0019] Figure 4 A schematic diagram of a lower triangular matrix storage format provided by an embodiment;

[0020] Figure 5 A schematic diagram of the processing instruction format;

[0021] Figure 6 A schematic diagram of access types for data included in a processing instruction;

[0022] Figure 7 A schematic diagram of access channel merging;

[0023] Figure 8A schematic diagram of the structure of a data processing device provided in another embodiment;

[0024] Fig. 9 A schematic diagram of the structure of a data processing device provided by an embodiment. DETAILED DESCRIPTION

[0025] It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention, and are not used to limit the embodiments of the present invention.

[0026] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the embodiments of the present invention, and have no special meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0027] Figure 1 The present invention is a flowchart of a data processing method provided by an embodiment. The present embodiment is applicable to a scenario in which an inverse matrix of a received matrix is ​​determined. The present embodiment can be executed by a data processing device, which can be implemented by software and / or hardware, and the data processing device can be integrated in a communication device such as a multi-mode base station or a multi-mode terminal. Figure 1 As shown, the data processing method provided in this embodiment includes the following steps:

[0028] Step 101: Store the data in the matrix to be processed included in the received task request in an input register file.

[0029] The task request includes: data in the matrix to be processed, the dimension of the matrix to be processed, and the number of blocks of the matrix to be processed.

[0030] The dimension of the matrix to be processed in this embodiment can be any dimension. For example, 1, 2, 4, 8, 16, 24 and 32. The task request in this embodiment can be sent to the data processing device by other devices, or generated by other modules of the data processing device. The number of blocks of the matrix to be processed refers to the number of matrices to be processed.

[0031] Optionally, the matrix to be processed in this embodiment may be a lower triangular matrix. In massive MIMO, matrix inversion operation plays an important role in channel detection algorithms and precoding algorithms.

[0032] Step 102: Determine the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and preset mapping information.

[0033] The mapping information is used to indicate the mapping relationship between the dimension of the matrix and the processing instruction storage address. The target processing instruction stored in the target processing instruction storage address is used to determine the inverse matrix of the matrix to be processed.

[0034] In this embodiment, the application can be analyzed in advance according to the application requirements, and all the matrix dimensions required in the application can be extracted, and the inversion algorithms and processes of various dimensions can be determined according to the algorithm performance simulation. For example, in the 5G MIMO processing process, the required matrix inversion ranges from 1x1 to 64x64, of which 2x2 uses a direct inversion algorithm and 4x4 uses a block inversion algorithm, and the others use a Cholesky decomposition algorithm. At the same time, 64x64 can be decomposed into 4x16x16, 8x8x8, 64x1x1, and 8x2x2, 8x4x4, etc. need to be supported.

[0035] According to the algorithm, these specifications are converted into pseudocode through scripting, mapped to various hardware resources in the form of processing instructions, and then the address ranges of various specification codes are counted and made into a configuration file, waiting to be downloaded to the hardware instruction memory in the data processing device in a dynamic or static manner, for example, downloaded to the random access memory (RAM).

[0036] The data processing device in this embodiment can load the above configuration file after power-on reset, download the processing instruction and mapping information. The processing instruction represents the calculation and control process, and the mapping information stores the mapping relationship between the dimension of the matrix, the starting address of the processing instruction, and the ending address of the processing instruction (i.e., the storage address of the processing instruction).

[0037] In step 102, the target processing instruction storage address corresponding to the matrix to be processed can be determined according to the dimension of the matrix to be processed and the preset mapping table, that is, the correspondence between the matrix dimension and the processing instruction storage address. In this embodiment, the target processing instruction stored in the target processing instruction storage address is used to determine the inverse matrix of the matrix to be processed.

[0038] Step 103: According to the number of blocks of the matrix to be processed, the computing resources in the resource pool are configured, and the information of the computing units for parallel processing between the blocks is determined.

[0039] The computing resources in the resource pool in this embodiment may include computing resources such as multipliers. The throughput of matrix inversion is mainly determined by the multipliers. According to the number of matrix blocks and dimensions extracted as above, the maximum number of multiplication units required to calculate an element is determined, for example, 64 multiplication units. At the same time, in order to support inter-block parallelism, these multiplication units can be grouped. Through the dynamic configuration of various networks, these resources can be organized into a unified large resource pool or multiple small resource pools.

[0040] In step 103, the computing resources in the resource pool are configured according to the number of blocks of the matrix to be processed, and the computing unit information of the parallel operation between the blocks is determined. For example, assuming that the number of blocks of the matrix to be processed is 4, the computing resources in the resource pool can be divided into 4 independent networks, and these 4 independent networks process the data in the 4 matrices to be processed in parallel.

[0041] The computing unit information here is used to indicate the inter-block parallel computing units and the corresponding relationship between the computing units and the matrix to be processed. The inter-block parallel computing units in this embodiment refer to computing units that process data in different matrices to be processed in parallel.

[0042] It should be noted that there is no time sequence relationship between the execution process of step 102 and step 103. Both can be executed at the same time and in any order.

[0043] Step 104: Read the target processing instructions from the target processing instruction storage address in sequence, and process the data stored in the input register file in parallel according to the computing units corresponding to the target processing instructions and the computing unit information of the inter-block parallelism.

[0044] In this embodiment, the number of target processing instructions stored in the target processing instruction storage address can be multiple. In step 104, the target processing instructions are read in sequence. After each target processing instruction is read, the computing unit corresponding to the target processing instruction and the computing unit information of the inter-block parallelism processes the data stored in the input register file in parallel.

[0045] The target processing instruction includes an access address and a processing method, etc. After reading data from the input register file according to the access address in the target processing instruction, the read data is processed according to the processing method included in the target processing instruction.

[0046] In this embodiment, after all target processing instructions in the target processing instruction storage address are executed, the inverse matrix of the matrix to be processed can be obtained.

[0047] In one embodiment, step 104 may be performed by the following process:

[0048] Step 1041: Set the current execution address to the i-th address in the target processing instruction storage address.

[0049] Step 1042: Process the data stored in the input register file in parallel according to the target processing instruction corresponding to the i-th address and the computing units corresponding to the inter-block parallel computing unit information.

[0050] Step 1043: After processing the target processing instruction corresponding to the i-th address, when it is determined that the current running address is not equal to the instruction end address in the target processing instruction storage address, determine that i=i+1, and return to execute the step of setting the current running address to the i-th address in the target processing instruction storage address.

[0051] It should be noted that, during the initial operation, the current operation address is the start address in the target processing instruction storage address. i is an integer greater than or equal to 0.

[0052] Furthermore, since there is a strong dependency between certain data in the matrix inversion algorithm, in order to avoid read-write conflicts, waiting cycles need to be inserted between certain calculation processes. Based on this requirement, the target processing instruction also includes a delay cycle. The implementation process of the above step 1043 is specifically as follows: after determining that the current running address is not equal to the instruction end address in the target processing instruction storage address, after delaying the delay cycle included in the target processing instruction corresponding to the i-th address, determine i=i+1, and return to execute the step of setting the current running address to the i-th address in the target processing instruction storage address. For example, assuming that i=3, the instruction end address in the target processing instruction storage address is the 11th address, after processing the target processing instruction corresponding to the 3rd address, when it is determined that the current running address is not equal to the instruction end address in the target processing instruction storage address, after delaying the delay cycle included in the target processing instruction corresponding to the 3rd address, determine i=4, and return to execute the step of setting the current running address to the 4th address in the target processing instruction storage address.

[0053] The data processing method provided in this embodiment draws on the ideas of Single Instruction Multiple Data (SIMD) and ASIC, and can implement a general configurable matrix inversion method and device, thereby obtaining the advantages of programmability and scalability of SIMD, as well as the advantages of low latency, high efficiency and low power consumption of ASIC.

[0054] The data processing method provided in this embodiment can be applied to MIMO technology fields such as 5G wireless mobile communications, deep space communications, optical fiber communications, satellite digital video and audio broadcasting, etc.

[0055] The present embodiment provides a data processing method, comprising: storing data in a matrix to be processed included in a received task request in an input register file, wherein the task request includes: data in the matrix to be processed, the dimension of the matrix to be processed, and the number of blocks of the matrix to be processed; determining a target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and preset mapping information, wherein the mapping information is used to indicate a mapping relationship between the dimension of the matrix and the processing instruction storage address, and the target processing instruction stored in the target processing execution storage address is used to determine an inverse matrix of the matrix to be processed; configuring computing resources in a resource pool according to the number of blocks of the matrix to be processed, and determining computing unit information for parallelization between blocks; reading target processing instructions from the target processing instruction storage address in sequence, and processing the data stored in the input register file in parallel according to the computing units corresponding to the target processing instructions and the computing unit information for parallelization between blocks. The data processing method can obtain the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed. At the same time, it can also configure the computing resources in the resource pool according to the number of blocks of the matrix to be processed, determine the computing unit information of parallel between blocks, and then, according to the target processing instructions read in sequence from the target processing instruction storage address and the computing units corresponding to the computing unit information of parallel between blocks, parallelly process the data stored in the input register file. On the one hand, it can realize the processing of matrices of various dimensions, with strong programmability and scalability, and on the other hand, it can process data in parallel, with low latency and high efficiency.

[0056] Figure 2 This is a flow chart of a data processing method embodiment provided by another embodiment. Figure 1 Based on the illustrated embodiment and various optional solutions, other steps included in the data processing method are described in detail. Figure 2 As shown, the data processing method provided in this embodiment includes the following steps:

[0057] Step 201: When it is determined that there is a task request in the task interface, it is determined whether the input register file is idle.

[0058] Step 202: When it is determined that the input register file is idle, a task request is received, and the state of the input register file is set to a busy state.

[0059] In step 201, when it is determined that the input register file is idle, a task request is received to avoid write operation errors. At the same time, the state of the input register file is set to a busy state to avoid the input register file being occupied by other tasks and causing errors in the data processing process. In order to improve efficiency, the state of the input register file can be set to a busy state while receiving the task request. Of course, the state of the input register file can also be set to a busy state before receiving the task request.

[0060] Step 203: Store the data in the matrix to be processed included in the received task request in an input register file.

[0061] The task request includes: data in the matrix to be processed, the dimension of the matrix to be processed, and the number of blocks of the matrix to be processed.

[0062] Optionally, the matrix to be processed in this embodiment may be a lower triangular matrix. Step 203 may specifically include: storing the data in the matrix to be processed included in the received task request in an input register file according to a preset storage format of a lower triangular matrix; copying the data in the matrix to be processed included in the received task request, and storing the copied data according to the storage format of an upper triangular matrix.

[0063] Optionally, after the data is stored, preprocessing operations such as data alignment may be performed.

[0064] Figure 4 FIG. 1 is a schematic diagram of a lower triangular matrix storage format provided by an embodiment. Figure 4 As shown, it is assumed that the minimum storage unit of the input register file can store an 8*8 matrix, and the input register file has 4 rows and 4 columns of the minimum storage unit. Then, Figure 4 As shown in Figure (1), the input register file can store 1 to 64 1x1 matrices; Figure 4 As shown in Figure (2), the input register file can store 1 to 8 8x8 matrices, and the storage location is shown in the gray area in Figure (2); Figure 4 As shown in Figure (3), the input register file can store 1 to 4 16x16 matrices, and the storage location is shown in the gray area in Figure (3); Figure 4 As shown in Figure (4), the input register file can store a 32x32 matrix, and the storage location is shown in the gray area in Figure (4). Furthermore, the gray area above the dotted line in Figure (4) can store a 24x24 matrix.

[0065] By analyzing various algorithms for matrix inversion, we can see that the data access in the algorithm mainly includes scalar access, row vector access and column vector access. For the inversion of the lower triangular matrix, the upper triangle can be stored at the same time, thereby converting the column vector access into the row vector access, reducing the complexity of data access.

[0066] Optionally, the data processing device in this embodiment may further include an output register file.

[0067] Figure 3 FIG. 1 is a schematic diagram of the structure of a data processing device provided by an embodiment. Figure 3As shown, the data processing device mainly includes five modules: instruction control, task input, computing resource pool, register file and task output.

[0068] The register file includes: an input register file B (regFileB) and an output register file C (regFileC). The input register file B and the output register file C may be vector register files.

[0069] In order to reduce data access latency and store intermediate calculation processes, two vector register stacks (i.e., vector register files) are used to realize the pipeline operation of data input / output, thereby reducing the overall processing latency. These high-dimensional vector register stacks can store multiple low-dimensional matrices in parallel, thereby completing the parallel inversion of multiple low-dimensional matrices, thereby improving the utilization of the computing unit, increasing the matrix inversion throughput, reducing the control overhead, and reducing the overall power consumption.

[0070] The pipelining operation of data input / output means that in the data input stage, when the input register file is in an idle state, the receiving task request can be realized regardless of whether the output register file is idle; in the data output stage, regardless of whether the data output is completed, the state of the input register file can be set to an idle state. The pipelining operation of data input / output can reduce the overall processing delay of data processing.

[0071] Step 204: Determine whether the output register file is idle.

[0072] Optionally, step 203 may be performed after step 204. After storing the data and before starting to process the data, it may be determined whether the output register file is idle.

[0073] Step 205: When it is determined that the output register file is idle, the state of the output register file is set to a busy state.

[0074] Step 206: after setting the state of the output register file to the busy state, determine the step of executing the step of determining the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and the correspondence between the preset matrix dimension and the processing instruction storage address.

[0075] Before performing step 207, in order to avoid write errors, it is necessary to determine the state of the output register file. When it is determined that the output register file is idle, it is determined to perform step 207. Setting the state of the output register file to a busy state can avoid the output register file being occupied by other tasks and causing errors in the data processing process.

[0076] Step 207: Determine the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and the preset mapping information.

[0077] The mapping information is used to indicate the mapping relationship between the dimension of the matrix and the processing instruction storage address. The target processing instruction stored in the target processing execution storage address is used to determine the inverse matrix of the matrix to be processed.

[0078] In this embodiment, various matrix inversion algorithms are analyzed to extract the basic fine-grained operators required by various inversion algorithms. They mainly include the following categories:

[0079]

[0080]

[0081] Among them, B represents the data in the input register file, C represents the data in the output register file, D represents the execution result of the last target processing instruction, and A represents the processing result of B and C.

[0082] By analyzing the matrix inversion algorithm flow, its control is relatively simple and belongs to large-scale parallel computing. This embodiment adopts off-line programming, which simplifies the control logic and enhances flexibility.

[0083] Figure 5 is a schematic diagram of the processing instruction format. Figure 5 As shown, the meanings of the fields in the processing instruction are as follows:

[0084] Instructions: include the above basic fine-grained operators, mainly used to control the execution of computing units.

[0085] Halt cycle: Since some data in the matrix inversion algorithm have strong dependencies, some calculation processes need to be inserted into a wait cycle to avoid read-write conflicts. This field is used to pause the pipeline for n cycles after executing this instruction.

[0086] Parallelism: This field is used for fine-grained intra-block parallelism, which indicates the number of elements processed in parallel within a block. Combined with the coarse-grained inter-block parallelism in the task parameters (i.e., the number of blocks of the matrix to be processed), computing resources and various networks can be organized into various forms. For example, if the number of blocks is 2 and the parallelism is 2, the accumulation / calibration / broadcast network will organize the resource pool into four independent networks. The accumulation / calibration / broadcast functions are only executed within the independent network and will not cross two independent networks. This can process the inversion of two matrices at the same time, and each matrix can calculate two elements at the same time.

[0087] Calibration control: This field is mainly used for the calculation and propagation of various calibration values ​​in the algorithm process, as well as the selection of calibration values ​​required for fixed-point operation.

[0088] Source / Destination A: This field is mainly used to control the behavior of data A. Through different controls, operands can be obtained from input register file B or output register file C; the results can also be written back to input register file B or output register file C; at the same time, constant values ​​or conjugate values ​​of the fetched data can also be obtained.

[0089] Source B and Source C: These two fields are used to control the behavior of accessing register files B and C respectively. Through different controls, both row access and column access are possible. Type indicates the access type: Type = 0 indicates row access; Type = 1 indicates column access. (From0, To0) indicates the location of data accessed by different resource blocks; (From1, To1) indicates the sequence of data accessed within the same resource block. Different resource blocks indicate different rows or columns, and the same resource block indicates the same row or column.

[0090] Figure 6 Figure 1 is a schematic diagram of the access types of data included in the processing instruction. Figure 6 As shown, when the type in the processing instruction is 1, it indicates column access. From0 and To0 indicate access to different columns, and From1 and To1 indicate which rows in the columns corresponding to From0 and To0 are accessed. For example, From0 and To0 can be From0 and To2, indicating access to columns 0 to 2, and From1 and To1 can be From2 and To4, indicating access to rows 2 to 4 of each column from columns 0 to 2.

[0091] like Figure 6 As shown, when the type in the processing instruction is 0, it indicates row access. From0 and To0 indicate access to different rows, and From1 and To1 indicate which columns in the row corresponding to From0 and To0 are accessed.

[0092] According to different combinations of the above fields, the entire processing pipeline of matrix inversion is controlled through decoding, thereby getting rid of the limitations of hard wiring, increasing control flexibility, simplifying control logic, and reducing hardware implementation complexity.

[0093] Offline instruction programming can encode the matrix inversion process of various algorithms and dimensional combinations according to application requirements, and download them statically and dynamically to the instruction RAM. At the same time, the mapping relationship is configured in the mapping information. According to the dimension of the matrix to be processed in the task parameters, the corresponding program is found from the mapping information and executed. Therefore, offline instruction programming not only enhances flexibility and reduces control complexity, but also helps reduce dynamic power consumption.

[0094] Step 208: According to the number of blocks of the matrix to be processed, the computing resources in the resource pool are configured, and the information of the computing units for parallel processing between the blocks is determined.

[0095] There is no timing relationship between step 207 and step 208 .

[0096] Step 209: After sequentially reading the target processing instructions from the target processing instruction storage address, the parallel computing unit information within the block is determined according to the parallelism within the block.

[0097] The process of sequentially reading the target processing instructions in step 209 is similar to the specific implementation process of step 104, and will not be repeated here.

[0098] like Figure 5 As shown, the parallelism included in the target processing instruction in this embodiment refers to the intra-block parallelism. After the target processing instruction is read from the target processing instruction storage address, the computing unit information of the intra-block parallelism can be determined according to the intra-block parallelism.

[0099] In practical applications, the matrix dimension range is relatively large, such as 1, 2, 4, 8, 16, 24, 32, etc. If resources are reserved according to the maximum capacity, then when processing small-dimensional matrices, the resources cannot be fully utilized, which wastes resources and increases delay. Therefore, in this embodiment, the task request includes the number of blocks of the matrix to be processed, and multiple small matrices are spliced ​​into a large matrix for parallel processing to make full use of its resources, improve resource utilization, and reduce the delay overhead caused by serial processing. Matrix inversion generally performs corresponding calculations for each element point. If only one element point is processed each time, although it is simple, it cannot fully utilize resources, and the delay is also relatively large. This embodiment can organize resources according to demand, and process multiple element points of the same matrix in parallel to achieve the purpose of intra-block parallelism. Among them, intra-block parallelism refers to the number of elements in the same matrix to be processed in parallel.

[0100] This embodiment adopts the idea of ​​computing resource pool, and combines computing resources into a pool with multiple independent computing resources according to a certain granularity. The computing resource pool can be combined into one or more sets of computing units according to application requirements to process a large matrix or multiple small matrices in parallel, and multiple elements of the same matrix in parallel. These resource pools can be combined into multiple parallel processing computing units as needed to process multiple matrices or elements in parallel. In this way, since multiple parallel computing units share the same program and control logic, power consumption overhead is reduced, and when processing small matrices, throughput is improved and time delay is reduced.

[0101] In one implementation, if it is determined that a maximum of 64 multiplication units are required to calculate an element, and to support various coarse / fine-grained parallelism, these multiplication units are divided into 8 groups, each with 8. Through the dynamic configuration of various networks, these resources can be organized into a unified large resource pool or a maximum of 8 small resource pools.

[0102] In step 208, various networks are statically configured at the coarse-grained level according to the number of blocks of the matrix to be processed in the task request, and the computing resource pool is organized into computing units for parallel processing between blocks. In step 209, various networks and computing units are dynamically adjusted at the fine-grained level according to the parallelism in the target processing instruction read from the target processing instruction storage address, and multiple elements in the block are processed in parallel, so as to realize the control of various units to run dynamically according to demand.

[0103] Step 210: Parallel process the data stored in the input register file according to the target processing instruction, the computing units corresponding to the inter-block parallel computing unit information, and the computing units corresponding to the intra-block parallel computing unit information.

[0104] In step 210, the data stored in the input register file may be processed in parallel by the computing units corresponding to the inter-block parallel computing unit information and the computing units corresponding to the intra-block parallel computing unit information based on the target processing instruction. The parallel processing process may realize parallel processing between multiple matrix blocks to be processed, and may also realize parallel processing between multiple elements in the same matrix to be processed.

[0105] In this embodiment, since the target processing instructions are obtained in sequence, after each target processing instruction is processed, the intermediate data obtained during the processing of the data stored in the input register file can be stored in the output register file or the input register file, and the obtained result data can be stored in the output register file. Optionally, the obtained intermediate data can also be stored in the cache unit of the computing unit. That is, the two register files in this embodiment can be used for input storage, output storage or intermediate temporary storage, respectively. At the same time, according to the number of blocks processed in parallel, multiple small matrices can be stored separately.

[0106] like Figure 5 As shown, the target instruction also includes the access address of the target data (i.e. Figure 5In step 210, if it is determined that multiple target data that the computing unit needs to access have the same row or column according to the access address of the target data, the access channels of the multiple target data are merged into one access channel; data is read from the input register file and / or the output register file according to the merged access channel; the target data is obtained from the read data according to the access address of the target data; and the target data is processed in parallel according to the processing mode included in the target processing instruction, the computing unit corresponding to the inter-block parallel computing unit information, and the computing unit corresponding to the intra-block parallel computing unit information.

[0107] The computing unit here may be an inter-block parallel computing unit or an intra-block parallel computing unit, but this embodiment is not limited thereto.

[0108] In specific implementation, after merging the access channels, read control information can be generated. According to the read control information, all data in the merged access channels are read from the input register file and / or the output register file, and then the required target data is selected therefrom. After reading the required target data, relevant preprocessing is performed, such as fixed-point or conjugate processing, etc.; according to the previously collected fixed-point data, it is broadcast or assigned to each fixed-point unit according to the target processing instruction requirements; according to the instructions in the target instructions, the computing units corresponding to the relevant inter-block parallel computing unit information and the computing units corresponding to the intra-block parallel computing unit information are started, and according to the requirements in the instructions, the fixed-point and fixed-point related data are dynamically processed and collected, and the results are written back to the register file and / or the main control unit.

[0109] Due to multiple resource pools, the amount of data required for parallel processing is large. Therefore, a large amount of data needs to be read in parallel from the register file. If the conventional reading is followed, there will be many levels of data selector selection logic, which is difficult to implement on the physical back end due to congestion. In view of the characteristics of matrix inversion, especially the data access of the lower triangular matrix inversion, the register file stores the data of the lower triangle in the upper triangle at the same time, which is equivalent to a copy. In this way, column access can be converted to row access. Moreover, since the data accessed at the same time is only local, after channel merging, the behavior of reading data can be controlled within a certain number of rows, reducing the number of first-level selectors; after reading the row data, column selection is performed separately. Through this technology, the number of row accesses is greatly reduced, thereby reducing a large amount of data selector logic, which is conducive to the implementation of the physical back end.

[0110] Figure 7This is a schematic diagram of access channel merging. To complete 8 8x8 matrices at the same time, when executing the processing instructions shown in the figure, if the channels are independent, 8 channels are required to read 8 rows of data at the same time; but after channel merging, only 4 channels are required to read 4 rows of data at the same time. In this way, the number of read selectors can be greatly reduced, which is beneficial to the back-end wiring.

[0111] In step 209, if it is determined that the current running address is equal to the instruction end address in the target processing instruction storage address, it indicates that the execution of the inversion instruction of the matrix to be processed is completed, and the input register file is released. After that, according to the task parameters and the main control fixed-point result, the output data is post-processed, and the relevant result parameters and data are output, and then the output register file is set to an idle state, completing the lower triangular inversion process of the entire matrix.

[0112] The above data processing process of this embodiment adopts loose coupling of three-level pipelines of input-computation-output, and each pipeline is weakly correlated, and the execution of the lower-level pipeline is triggered only by a trigger signal.

[0113] Please continue to refer to Figure 3 After the task input module receives the task request, the data in the matrix to be processed included in the received task request is stored in the input register file through the data write interface; the computing unit in the resource pool is configured as the computing unit information of the parallel block; according to the task request and mapping information, for example, the mapping table, the target processing instruction storage address is read, and then the target processing instruction is obtained: instruction 0 to instruction N: each target processing instruction is executed in sequence through instruction fetching, decoding and control; according to the target processing instruction, the resources in the resource pool are finely configured to determine the parallel computing unit information within the block; according to the configured computing unit, the data is processed in parallel. During the processing process, data needs to be read from the register file through the data read interface, channel merging, etc. After a target processing instruction is executed, it is stored in the register file through the data write interface. Figure 3 The resource pool in includes the Multiply Accumulate (MAC) unit.

[0114] The data processing method provided in this embodiment overcomes the problem that the traditional matrix inversion method cannot take into account multiple indicators such as universality, throughput, complexity and low latency. It draws on the idea of ​​SIMD+ASIC and proposes a matrix inversion implementation method with high configurability and universality to adapt to different protocols and the continuous evolution of protocols; at the same time, it combines multiple technologies such as channel merging, dual vector register files, inter-block and intra-block parallelism, and various broadcast networks, adopts the idea of ​​resource pool, reduces implementation cost, development and back-end risks, and meets the needs of various algorithms, various dimensions and various application scenarios.

[0115] Figure 8 FIG. 1 is a schematic diagram of the structure of a data processing device provided in another embodiment. Figure 8 As shown, the data processing device provided in this embodiment includes the following modules: a storage module 81 , a first determination module 82 , a second determination module 83 and a processing module 84 .

[0116] The storage module 81 is configured to store the data in the to-be-processed matrix included in the received task request in an input register file.

[0117] The task request includes: data in the matrix to be processed, the dimension of the matrix to be processed, and the number of blocks of the matrix to be processed.

[0118] The first determination module 82 is configured to determine the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and the preset mapping information.

[0119] The mapping information is used to indicate the mapping relationship between the dimension of the matrix and the processing instruction storage address. The target processing instruction stored in the target processing instruction storage address is used to determine the inverse matrix of the matrix to be processed.

[0120] The second determination module 83 is configured to configure the computing resources in the resource pool according to the number of blocks of the matrix to be processed, and determine the computing unit information of the parallelism between the blocks.

[0121] The processing module 84 is configured to sequentially read the target processing instructions from the target processing instruction storage address, and process the data stored in the input register file in parallel according to the computing units corresponding to the target processing instructions and the inter-block parallel computing unit information.

[0122] Optionally, the target processing instruction includes intra-block parallelism. The device further includes: a third determination module configured to determine intra-block parallel computing unit information according to the intra-block parallelism. The processing module 84 is specifically used to: parallelly process the data stored in the input register file according to the target processing instruction, the computing units corresponding to the inter-block parallel computing unit information, and the computing units corresponding to the intra-block parallel computing unit information.

[0123] In one implementation, the processing module 84 is specifically used to: set the current running address to the i-th address in the target processing instruction storage address; process the data stored in the input register file in parallel according to the target processing instruction corresponding to the i-th address and the computing unit corresponding to the inter-block parallel computing unit information; after processing the target processing instruction corresponding to the i-th address, when it is determined that the current running address is not equal to the instruction end address in the target processing instruction storage address, determine that i=i+1, and return to execute the step of setting the current running address to the i-th address in the target processing instruction storage address.

[0124] Furthermore, the target processing instruction also includes a delay cycle. The processing module 84 is specifically used to: after determining that the current running address is not equal to the instruction end address in the target processing instruction storage address, after delaying the delay cycle included in the target processing instruction corresponding to the i-th address, determine that i=i+1, and return to execute the step of setting the current running address to the i-th address in the target processing instruction storage address.

[0125] Optionally, the matrix to be processed is a lower triangular matrix. The storage module 81 is specifically used to: store the data in the matrix to be processed included in the received task request in the input register file according to the preset storage format of the lower triangular matrix; copy the data in the matrix to be processed included in the received task request, and store the copied data according to the storage format of the upper triangular matrix.

[0126] In one implementation, the storage module 81 is further used to: store the intermediate data obtained during the processing of the data stored in the input register file in the output register file or the input register file, and store the obtained result data in the output register file.

[0127] Optionally, the target instruction also includes an access address of the target data and a processing method for the target data. The processing module 84 is specifically used to: if it is determined based on the access address of the target data that multiple target data that the computing unit needs to access have the same row or column, then merge the access channels of the multiple target data into one access channel; read data from the input register file and / or the output register file based on the merged access channel; obtain the target data from the read data based on the access address of the target data; and process the target data in parallel based on the processing method included in the target processing instruction, the computing units corresponding to the inter-block parallel computing unit information, and the computing units corresponding to the intra-block parallel computing unit information.

[0128] In one implementation, the device also includes: a judgment module, configured to judge whether the input register file is idle when it is determined that there is a task request in the task interface; a receiving and setting module, configured to receive the task request and set the status of the input register file to a busy state when it is determined that the input register file is idle.

[0129] In another implementation, the judgment module is further used to judge whether the output register file is idle. In this implementation, the device further includes: a setting module and a fourth determination module. The setting module is configured to set the state of the output register file to a busy state when determining that the output register file is idle. The fourth determination module is configured to determine to execute the step of determining the storage address of the target processing instruction corresponding to the matrix to be processed according to the dimension of the matrix to be processed and the preset mapping information after setting the state of the output register file to the busy state.

[0130] The data processing device provided in this embodiment is used to execute the data processing method of any of the above embodiments. The implementation principle and technical effect of the data processing device provided in this embodiment are similar and will not be repeated here.

[0131] Fig. 9 FIG. 1 is a schematic diagram of the structure of a data processing device provided by an embodiment. Fig. 9 As shown, the data processing device includes a processor 91 and a memory 92; the number of processors 91 in the data processing device can be one or more. Fig. 9 A processor 91 is taken as an example; the processor 91 and the memory 92 in the data processing device may be connected by a bus or other means, Fig. 9 The example of connecting through bus is taken in the following.

[0132] The memory 92, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the data processing method in the embodiment of the present application (for example, the storage module 81, the first determination module 82, the second determination module 83 and the processing module 84 in the data processing device). The processor 91 runs the software programs, instructions and modules stored in the memory 92, thereby implementing various functional applications and data processing of the data processing device, that is, realizing the above-mentioned data processing method.

[0133] The memory 92 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the data processing device, etc. In addition, the memory 92 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices.

[0134] The present application also provides a storage medium containing computer executable instructions. When the computer executable instructions are executed by a computer processor, they are used to perform a data processing method. The method includes:

[0135] storing the data in the matrix to be processed included in the received task request in an input register file; wherein the task request includes: the data in the matrix to be processed, the dimension of the matrix to be processed and the number of blocks of the matrix to be processed;

[0136] According to the dimension of the matrix to be processed and the preset mapping information, a target processing instruction storage address corresponding to the matrix to be processed is determined; wherein the mapping information is used to indicate a mapping relationship between the dimension of the matrix and the processing instruction storage address, and the target processing instruction stored in the target processing instruction storage address is used to determine the inverse matrix of the matrix to be processed;

[0137] According to the number of blocks of the matrix to be processed, the computing resources in the resource pool are configured to determine the computing unit information of the parallel computing between the blocks;

[0138] The target processing instructions are sequentially read from the target processing instruction storage address, and the data stored in the input register file are processed in parallel according to the target processing instructions and the computing units corresponding to the inter-block parallel computing unit information.

[0139] Of course, the storage medium containing computer executable instructions provided by the present application is not limited to the method operations described above, and the computer executable instructions can also execute related operations in the data processing method provided by any embodiment of the present application.

[0140] The above description is merely an exemplary embodiment of the present application and is not intended to limit the protection scope of the present application.

[0141] In general, various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example, some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, microprocessor or other computing device, although the present application is not limited thereto.

[0142] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0143] In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0144] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the embodiments of the present invention is not limited thereby. Any modification, equivalent substitution and improvement made by those skilled in the art without departing from the scope and essence of the embodiments of the present invention shall be within the scope of the rights of the embodiments of the present invention.

Claims

1. A data processing method, characterized in that: The method comprises: storing the data in the matrix to be processed included in the received task request in an input register file; wherein the task request includes: the data in the matrix to be processed, the dimension of the matrix to be processed and the number of blocks of the matrix to be processed; According to the dimension of the matrix to be processed and the preset mapping information, a target processing instruction storage address corresponding to the matrix to be processed is determined; wherein the mapping information is used to indicate a mapping relationship between the dimension of the matrix and the processing instruction storage address, and the target processing instruction stored in the target processing instruction storage address is used to determine the inverse matrix of the matrix to be processed; According to the number of blocks of the matrix to be processed, the computing resources in the resource pool are configured to determine the computing unit information of the parallel computing between the blocks; sequentially read target processing instructions from the target processing instruction storage address, and process the data stored in the input register file in parallel according to the target processing instructions and the computing units corresponding to the inter-block parallel computing unit information; The target processing instruction includes intra-block parallelism; after sequentially reading the target processing instructions from the target processing instruction storage address, the method further includes: determining intra-block parallel computing unit information according to the intra-block parallelism; The step of processing the data stored in the input register file in parallel according to the target processing instruction and the computing unit corresponding to the inter-block parallel computing unit information includes: processing the data stored in the input register file in parallel according to the target processing instruction, the computing unit corresponding to the inter-block parallel computing unit information, and the computing unit corresponding to the intra-block parallel computing unit information; The target processing instruction also includes an access address of the target data and a processing method for the target data; the data stored in the input register file is processed in parallel according to the target processing instruction, the computing unit corresponding to the inter-block parallel computing unit information, and the computing unit corresponding to the intra-block parallel computing unit information, including: if it is determined according to the access address of the target data that multiple target data that the computing unit needs to access have the same row or column, then the access channels of the multiple target data are merged into one access channel; according to the merged access channel, data is read from the input register file and / or the output register file; from the read data, according to the access address of the target data, the target data is obtained; according to the processing method included in the target processing instruction, the computing unit corresponding to the inter-block parallel computing unit information, and the computing unit corresponding to the intra-block parallel computing unit information, the target data is processed in parallel.

2. The method according to claim 1, characterized in that The step of sequentially reading target processing instructions from the target processing instruction storage address and processing the data stored in the input register file in parallel according to the target processing instructions and the computing units corresponding to the inter-block parallel computing unit information includes: Setting the current execution address to the i-th address in the target processing instruction storage address; Processing the data stored in the input register file in parallel according to the target processing instruction corresponding to the i-th address and the computing units corresponding to the inter-block parallel computing unit information; After processing the target processing instruction corresponding to the i-th address, when it is determined that the current running address is not equal to the instruction end address in the target processing instruction storage address, i=i+1 is determined, and the step of setting the current running address to the i-th address in the target processing instruction storage address is returned.

3. The method according to claim 2, characterized in that The target processing instruction also includes a delay cycle; When it is determined that the current running address is not equal to the instruction end address in the target processing instruction storage address, determining i=i+1, and returning to execute the step of setting the current running address to the i-th address in the target processing instruction storage address, comprises: After determining that the current running address is not equal to the instruction end address in the target processing instruction storage address, after delaying the delay cycle included in the target processing instruction corresponding to the i-th address, determine that i=i+1, and return to execute the step of setting the current running address to the i-th address in the target processing instruction storage address.

4. The method according to any one of claims 1 to 3, characterized in that: The matrix to be processed is a lower triangular matrix; The step of storing the data in the to-be-processed matrix included in the received task request in the input register file comprises: storing the data in the matrix to be processed included in the received task request in the input register file according to a preset storage format of the lower triangular matrix; The data in the matrix to be processed included in the received task request is copied, and the copied data is stored in a storage format of an upper triangular matrix.

5. The method according to claim 1, characterized in that After the data stored in the input register file is processed in parallel according to the target processing instruction, the computing units corresponding to the inter-block parallel computing unit information, and the computing units corresponding to the intra-block parallel computing unit information, the method further includes: In the process of processing the data stored in the input register file, the intermediate data obtained are stored in the output register file or the input register file, and the result data obtained are stored in the output register file.

6. The method according to claim 5, characterized in that Before storing the data in the to-be-processed matrix included in the received task request in the input register file, the method further comprises: When it is determined that there is a task request in the task interface, determining whether the input register file is idle; When it is determined that the input register file is idle, the task request is received, and the state of the input register file is set to a busy state.

7. The method according to claim 5, characterized in that Before determining the target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and the preset mapping information, the method further includes: Determining whether the output register file is idle; When determining that the output register file is idle, setting the state of the output register file to a busy state; After the state of the output register file is set to a busy state, a step of determining a target processing instruction storage address corresponding to the matrix to be processed according to the dimension of the matrix to be processed and preset mapping information is performed.

8. A data processing device, characterized in that: The device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory. When the program is executed by the processor, the steps of the data processing method according to any one of claims 1 to 7 are realized.

9. A storage medium for computer-readable storage, characterized in that: The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the data processing method according to any one of claims 1 to 7.

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