Scan driver and display device

Abstract

A scan driver comprising multiple stages and a display device are provided. The scan driver of the display device comprises multiple stages. Each stage includes: a clock line configured to receive a first clock signal and a second clock signal having different phases; a shared input circuit configured to transmit an input signal to a shared control node; a first output circuit, coupled to the shared control node, configured to transmit a voltage of the shared control node to a first control node and configured to output a first scan signal in response to the voltage of the first control node and the first clock signal; and a second output circuit, coupled to the shared control node, configured to transmit a voltage of the shared control node to a second control node and configured to output a second scan signal in response to the voltage of the second control node and the second clock signal.

Description

Technical Field

[0001] The present invention generally relates to a display device, and more specifically, to a scan driver for a display device. Background Technology

[0002] The scan driver of the display device may include multiple stages that output multiple scan signals to multiple pixel rows of the display panel. Typically, the scan driver may include multiple stages, the number of which is substantially the same as the number of pixel rows, and each stage can output one scan signal to a corresponding pixel row. Summary of the Invention

[0003] The embodiment provides a scan driver with a small size.

[0004] An embodiment provides a display device including a scan driver with a small size.

[0005] According to an embodiment, the scan driver includes multiple stages. Each stage includes: at least one clock line configured to receive a first clock signal and a second clock signal having different phases; a shared input circuit configured to transmit an input signal to a shared control node; a first output circuit, coupled to the shared control node, configured to transmit a voltage of the shared control node to the first control node and configured to output a first scan signal in response to the voltage of the first control node and the first clock signal; and a second output circuit, coupled to the shared control node, configured to transmit a voltage of the shared control node to a second control node and configured to output a second scan signal in response to the voltage of the second control node and the second clock signal.

[0006] In an embodiment, the shared input circuit may include: a first transistor, including a gate for receiving an input signal, a first terminal for receiving the input signal, and a second terminal connected to the shared control node.

[0007] In an embodiment, the shared input circuit may include: a first transistor, including a gate for receiving a second clock signal, a first terminal for receiving an input signal, and a second terminal connected to a shared control node.

[0008] In an embodiment, the first output circuit and the second output circuit can be jointly combined to a shared inverting control node. The first output circuit can transmit a gate cutoff voltage to the first output node in response to the voltage of the shared inverting control node, and a first scan signal is output at the first output node. The second output circuit can transmit a gate cutoff voltage to the second output node in response to the voltage of the shared inverting control node, and a second scan signal is output at the second output node.

[0009] In an embodiment, the first output circuit may include: a second transistor, including a gate for receiving a gate on voltage, a first terminal connected to a shared control node, and a second terminal connected to the first control node; a third transistor, including a gate connected to the first control node, a first terminal for receiving a first clock signal, and a second terminal connected to the first output node, wherein a first scan signal is output at the first output node; a first capacitor, including a first electrode connected to the first control node and a second electrode connected to the first output node; and a fourth transistor, including a gate connected to a shared inverting control node, a first terminal connected to the first output node, and a second terminal for receiving a gate off voltage.

[0010] In an embodiment, the second output circuit may include: a fifth transistor, including a gate for receiving a first clock signal, a first terminal connected to a shared control node, and a second terminal connected to a second control node; a sixth transistor, including a gate connected to the second control node, a first terminal for receiving a second clock signal, and a second terminal connected to the second output node, wherein a second scan signal is output at the second output node; a second capacitor, including a first electrode connected to the second control node and a second electrode connected to the second output node; and a seventh transistor, including a gate connected to a shared inverting control node, a first terminal connected to the second output node, and a second terminal for receiving a gate cutoff voltage.

[0011] In an embodiment, the second output circuit may further include: a thirteenth transistor, connected between the second terminal of the fifth transistor and the second control node, and including a gate for receiving a gate conduction voltage, a first terminal connected to the second terminal of the fifth transistor, and a second terminal connected to the second control node.

[0012] In an embodiment, each stage may further include a shared stabilizer circuit configured to transmit a gate cutoff voltage to the shared control node in response to the voltage of the shared inverting control node.

[0013] In one embodiment, the shared stabilizer circuit may include an eighth transistor, comprising a gate coupled to a shared inverting control node, a first terminal coupled to the shared control node, and a second terminal receiving a gate cutoff voltage.

[0014] In an embodiment, each stage may further include a shared inverter circuit configured to control a shared inverter control node in response to a first clock signal and a first scan signal.

[0015] In an embodiment, the shared inverter circuit may include: a ninth transistor, including a gate for receiving a first clock signal, a first terminal for receiving the first clock signal, and a second terminal; a tenth transistor, including a gate connected to the second terminal of the ninth transistor, a first terminal for receiving the first clock signal, and a second terminal connected to the shared inverter control node; an eleventh transistor, including a gate connected to the first output node, a first terminal connected to the gate of the tenth transistor, and a second terminal for receiving a gate cutoff voltage, wherein a first scan signal is output at the first output node; and a twelfth transistor, including a gate connected to the first output node, a first terminal connected to the shared inverter control node, and a second terminal for receiving a gate cutoff voltage.

[0016] In an embodiment, each stage may further include a shared inverter circuit configured to control a shared inverter control node in response to a first clock signal and a voltage of the shared control node.

[0017] In an embodiment, the shared inverter circuit may include: a ninth transistor, including a gate for receiving a first clock signal, a first terminal for receiving the first clock signal, and a second terminal; a tenth transistor, including a gate connected to the second terminal of the ninth transistor, a first terminal for receiving the first clock signal, and a second terminal connected to the shared inverter control node; an eleventh transistor, including a gate connected to the shared control node, a first terminal connected to the gate of the tenth transistor, and a second terminal for receiving a gate cutoff voltage; a twelfth transistor, including a gate connected to the shared control node, a first terminal connected to the shared inverter control node, and a second terminal for receiving a gate cutoff voltage; and a third capacitor, including a first electrode connected to the shared inverter control node and a second electrode for receiving a gate cutoff voltage.

[0018] In an embodiment, the transistor included in one of the first output circuit and the second output circuit of the scan driver may be an NMOS transistor, while the transistor included in the other of the first output circuit and the second output circuit may be a PMOS transistor.

[0019] In an embodiment, the transistor included in at least one of the shared input circuit, shared stabilizer circuit, and shared inverter circuit of the scan driver may be a PMOS transistor, while the transistor included in at least another of the shared input circuit, shared stabilizer circuit, and shared inverter circuit may be an NMOS transistor.

[0020] According to an embodiment, the scan driver includes multiple stages. Each stage includes: at least one clock line configured to receive a first clock signal and a second clock signal having different phases; a first transistor including a gate for receiving an input signal or the second clock signal, a first terminal for receiving the input signal, and a second terminal coupled to a shared control node; a second transistor including a gate for receiving a gate on-state voltage, a first terminal coupled to the shared control node, and a second terminal coupled to the first control node; a third transistor including a gate coupled to the first control node, a first terminal for receiving the first clock signal, and a second terminal coupled to a first output node, wherein a first scan signal is output at the first output node; a first capacitor including a first electrode coupled to the first control node and a second electrode coupled to the first output node; and a fourth transistor. The transistor includes a gate connected to a shared inverting control node, a first terminal connected to a first output node, and a second terminal receiving a gate cutoff voltage; a fifth transistor including a gate receiving a first clock signal, a first terminal connected to a shared control node, and a second terminal connected to a second control node; a sixth transistor including a gate connected to a second control node, a first terminal receiving a second clock signal, and a second terminal connected to a second output node, wherein a second scan signal is output at the second output node; a second capacitor including a first electrode connected to the second control node and a second electrode connected to the second output node; and a seventh transistor including a gate connected to a shared inverting control node, a first terminal connected to the second output node, and a second terminal receiving a gate cutoff voltage.

[0021] In an embodiment, each stage may further include: an eighth transistor including a gate coupled to a shared inverting control node, a first terminal coupled to the shared control node, and a second terminal receiving a gate cutoff voltage; a ninth transistor including a gate receiving a first clock signal, a first terminal receiving the first clock signal, and a second terminal; a tenth transistor including a gate coupled to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal coupled to the shared inverting control node; an eleventh transistor including a gate coupled to a first output node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving a gate cutoff voltage; and a twelfth transistor including a gate coupled to the first output node, a first terminal coupled to the shared inverting control node, and a second terminal receiving a gate cutoff voltage.

[0022] In an embodiment, each stage may further include: a thirteenth transistor, coupled between the second terminal of the fifth transistor and the second control node, and including a gate for receiving a gate on-state voltage, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to the second control node.

[0023] In an embodiment, each stage may further include: an eighth transistor including a gate coupled to a shared inverting control node, a first terminal coupled to the shared control node, and a second terminal receiving a gate cutoff voltage; a ninth transistor including a gate receiving a first clock signal, a first terminal receiving the first clock signal, and a second terminal; a tenth transistor including a gate coupled to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal coupled to the shared inverting control node; an eleventh transistor including a gate coupled to the shared control node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving a gate cutoff voltage; a twelfth transistor including a gate coupled to the shared control node, a first terminal coupled to the shared inverting control node, and a second terminal receiving a gate cutoff voltage; and a third capacitor including a first electrode coupled to the shared inverting control node and a second electrode receiving a gate cutoff voltage.

[0024] According to an embodiment, a display device is provided, the display device comprising: a display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a scan driver configured to provide scan signals to the plurality of pixels and including a plurality of stages; and a controller configured to control the data driver and the scan driver. Each of the plurality of stages includes: at least one clock line configured to receive a first clock signal and a second clock signal having different phases; a shared input circuit configured to transmit an input signal to a shared control node; a first output circuit coupled to the shared control node configured to transmit a voltage of the shared control node to the first control node and configured to output a first scan signal in the scan signals in response to the voltage of the first control node and the first clock signal; and a second output circuit coupled to the shared control node configured to transmit a voltage of the shared control node to a second control node and configured to output a second scan signal in the scan signals in response to the voltage of the second control node and the second clock signal.

[0025] As described above, in the scan driver and display device according to the embodiments, the first output circuit and the second output circuit can share a shared control node and / or a shared inverting control node. The first output circuit can output a first scan signal synchronously with a first clock signal, and the second output circuit can output a second scan signal synchronously with a second clock signal. Therefore, each stage of the scan driver can output two scan signals to two pixel rows using two clock signals, and the size of the scan driver can be reduced compared to the size of a scan driver that outputs one scan signal per stage. Attached Figure Description

[0026] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0028] Figure 2 It is used to describe Figure 1 A timing diagram of an example of a level operation.

[0029] Figures 3 to 6 Each is used to describe Figure 1 Circuit diagrams showing corresponding examples of operations at the [level].

[0030] Figure 7 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0031] Figure 8 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0032] Figure 9 It is used to describe Figure 8 A timing diagram of an example of a level operation.

[0033] Figure 10 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0034] Figure 11 It is used to describe Figure 10 A timing diagram of an example of a level operation.

[0035] Figure 12 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0036] Figure 13 It is used to describe Figure 12 A timing diagram of an example of a level operation.

[0037] Figure 14 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0038] Figure 15 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0039] Figure 16 This is a circuit diagram illustrating each stage included in the scan driver according to an embodiment.

[0040] Figure 17 This is a block diagram illustrating a display device including a scan driver according to an embodiment.

[0041] Figure 18 This is a block diagram illustrating a scan driver included in a display device according to an embodiment.

[0042] Figure 19 This is a block diagram illustrating an electronic device including a display device according to an embodiment. Detailed Implementation

[0043] In the following, embodiments of the inventive concept will be explained in more detail with reference to the accompanying drawings.

[0044] Figure 1 Each level included in the scan driver according to an embodiment is shown.

[0045] Reference Figure 1 According to an embodiment, the scan driver may include multiple stages, wherein each stage 100 receives a first clock signal CK1 and a second clock signal CK2 having different phases from each other via at least one clock line, and each stage 100 may include a shared input circuit 110, a first output circuit 130, and a second output circuit 150. In an embodiment, the first clock signal CK1 and the second clock signal CK2 may have opposite phases. In an embodiment, each stage 100 may further include a shared stabilizer circuit 170 and a shared inverter circuit 190.

[0046] The shared input circuit 110 can transmit the input signal SIN to the shared control node NSQ. In an embodiment, the first stage of a plurality of stages can receive a scan start signal as the input signal SIN, and each of the remaining stages can receive a corresponding second scan signal SS2 from the previous stage as the input signal SIN. In an embodiment, the shared input circuit 110 can receive the input signal SIN synchronized with the second clock signal CK2. In an embodiment, as... Figure 1 As shown, the shared input circuit 110 may include a first transistor T1, which includes a gate for receiving the input signal SIN, a first terminal for receiving the input signal SIN, and a second terminal connected to the shared control node NSQ. Therefore, the gate and the first terminal of the first transistor T1 are connected to each other, and thus the first transistor T1 may be diode-connected.

[0047] The first output circuit 130 and the second output circuit 150 can be jointly coupled to a shared control node NSQ. Furthermore, the first output circuit 130 and the second output circuit 150 can be jointly coupled to a shared inverting control node NSQB. The first output circuit 130 can output a first scan signal SS1 to a first pixel row (e.g., pixels in the first row) based on the voltage of the shared control node NSQ, the gate on-state voltage (e.g., a low gate voltage) VGL, and a first clock signal CK1 synchronized with the first clock signal CK1. The second output circuit 150 can output a second scan signal SS2 to a second pixel row (e.g., pixels in the second row) that is different from the first pixel row, based on the voltage of the shared control node NSQ, the first clock signal CK1, and a second clock signal CK2 synchronized with the second clock signal CK2.

[0048] The first output circuit 130 can be integrated with a shared control node NSQ and can transmit the voltage of the shared control node NSQ to the first control node NQ1. For example, the first output circuit 130 can transmit the voltage of the shared control node NSQ to the first control node NQ1 by using a second transistor T2 that is turned on based on a gate on-state voltage VGL. The first output circuit 130 can output a first scan signal SS1 to the first pixel row in response to the voltage of the first control node NQ1 and a first clock signal CK1. For example, the first output circuit 130 can bootstrap (also known as boost) the first control node NQ1 in response to a first clock signal CK1 having a first on-state level (e.g., a first low level) to change the voltage of the first control node NQ1 from the first on-state level to a second on-state level having an absolute value greater than the absolute value of the first on-state level (e.g., changing from a first low level to a second low level lower than the first low level), and can output the first clock signal CK1 having the first on-state level as the first scan signal SS1 based on the voltage of the first control node NQ1 having the second on-state level. The first output circuit 130 can transmit the gate cutoff voltage (e.g., high gate voltage) VGH to the first output node NO1 in response to the voltage of the shared inverting control node NSQB, and the first scan signal SS1 is output at the first output node NO1.

[0049] In an embodiment, such as Figure 1As shown, the first output circuit 130 may include: a second transistor T2, including a gate for receiving a gate on-state voltage VGL, a first terminal connected to a shared control node NSQ, and a second terminal connected to a first control node NQ1; a third transistor T3, including a gate connected to the first control node NQ1, a first terminal for receiving a first clock signal CK1, and a second terminal connected to the first output node NO1, wherein a first scan signal SS1 is output at the first output node NO1; a first capacitor C1, including a first electrode connected to the first control node NQ1 and a second electrode connected to the first output node NO1; and a fourth transistor T4, including a gate connected to a shared inverting control node NSQB, a first terminal connected to the first output node NO1, and a second terminal for receiving a gate off-state voltage VGH.

[0050] The second output circuit 150 can be integrated with the shared control node NSQ and can transmit the voltage of the shared control node NSQ to the second control node NQ2. For example, the second output circuit 150 can transmit the voltage of the shared control node NSQ to the second control node NQ2 by using a fifth transistor T5 that is turned on based on a first clock signal CK1. The second output circuit 150 can output a second scan signal SS2 to the second pixel row in response to the voltage of the second control node NQ2 and the second clock signal CK2. For example, the second output circuit 150 can bootstrap the second control node NQ2 in response to a second clock signal CK2 having a first on level to change the voltage of the second control node NQ2 from the first on level to a second on level having an absolute value greater than the absolute value of the first on level, and can output the second clock signal CK2 having the first on level as the second scan signal SS2 based on the voltage of the second control node NQ2 having the second on level. The second output circuit 150 can transmit the gate cutoff voltage VGH to the second output node NO2 in response to the voltage of the shared inverting control node NSQB, and the second scan signal SS2 is output at the second output node NO2.

[0051] In an embodiment, such as Figure 1As shown, the second output circuit 150 may include: a fifth transistor T5, including a gate for receiving a first clock signal CK1, a first terminal connected to a shared control node NSQ, and a second terminal connected to a second control node NQ2; a sixth transistor T6, including a gate connected to a second control node NQ2, a first terminal for receiving a second clock signal CK2, and a second terminal connected to a second output node NO2, wherein a second scan signal SS2 is output at the second output node NO2; a second capacitor C2, including a first electrode connected to a second control node NQ2 and a second electrode connected to a second output node NO2; and a seventh transistor T7, including a gate connected to a shared inverting control node NSQB, a first terminal connected to a second output node NO2, and a second terminal for receiving a gate cutoff voltage VGH.

[0052] The shared stabilizer circuit 170 can transfer the gate cutoff voltage VGH to the shared control node NSQ in response to the voltage of the shared inverting control node NSQB. For example, the voltage of the shared inverting control node NSQB can periodically have a first on-level before and / or after the output of the first scan signal SS1 and the second scan signal SS2, and the shared stabilizer circuit 170 can periodically transfer the gate cutoff voltage VGH to the shared control node NSQ in response to the voltage of the shared inverting control node NSQB having the first on-level. In an embodiment, as... Figure 1 As shown, the shared stabilizer circuit 170 may include an eighth transistor T8, which includes a gate coupled to the shared inverting control node NSQB, a first terminal coupled to the shared control node NSQ, and a second terminal receiving the gate cutoff voltage VGH.

[0053] The shared inverter circuit 190 can control the shared inverting control node NSQB in response to a first clock signal CK1 and a first scan signal SS1. For example, before and / or after outputting the first scan signal SS1 and the second scan signal SS2, the shared inverter circuit 190 can cause the voltage of the shared inverting control node NSQB to have a first on-level in response to the first clock signal CK1 having a first on-level. When the first scan signal SS1 with the first on-level is output, although the first clock signal CK1 has a first on-level, the shared inverter circuit 190 can cause the voltage of the shared inverting control node NSQB to have a cutoff level (e.g., a high level). In an embodiment, as... Figure 1As shown, the shared inverter circuit 190 may include: a ninth transistor T9, including a gate for receiving a first clock signal CK1, a first terminal for receiving the first clock signal CK1, and a second terminal; a tenth transistor T10, including a gate connected to the second terminal of the ninth transistor T9, a first terminal for receiving the first clock signal CK1, and a second terminal connected to the shared inverter control node NSQB; an eleventh transistor T11, including a gate connected to the first output node NO1, a first terminal connected to the gate of the tenth transistor T10, and a second terminal for receiving the gate cutoff voltage VGH, wherein a first scan signal SS1 is output at the first output node NO1; and a twelfth transistor T12, including a gate connected to the first output node NO1, a first terminal connected to the shared inverter control node NSQB, and a second terminal for receiving the gate cutoff voltage VGH.

[0054] In an embodiment, such as Figure 1 As shown, transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, and T12 included in the scan driver or each stage 100 can be, but are not necessarily limited to, PMOS transistors. In embodiments, as Figure 12 , Figure 14 , Figure 15 and / or Figure 16 As shown, the transistors included in the scan driver can be, but are not limited to, NMOS transistors.

[0055] As described above, in the scan driver according to the embodiment, the first output circuit 130 and the second output circuit 150 of each stage 100 can share a shared control node NSQ and a shared inverting control node NSQB. The first output circuit 130 can output a first scan signal SS1 synchronously with a first clock signal CK1, and the second output circuit 150 can output a second scan signal SS2 synchronously with a second clock signal CK2. Therefore, each stage 100 of the scan driver can output two scan signals SS1 and SS2 to two pixel rows using only two clock signals CK1 and CK2, and the size of the scan driver can be reduced compared to a scan driver that outputs only one scan signal per stage.

[0056] In the following text, we will refer to... Figures 1 to 6 Example of operation describing level 100.

[0057] Figure 2 Used to describe Figure 1 Examples of operations at the level, Figures 3 to 6 Used to describe Figure 1 Examples of operations at the level of [level].

[0058] Reference Figure 1 and Figure 2Each stage 100 can receive an input signal SIN, a first clock signal CK1, and a second clock signal CK2. The input signal SIN can be a scan start signal associated with the first stage among multiple stages, and can be a second scan signal SS2 of the previous stage associated with the remaining stages among multiple stages. The first clock signal CK1 and the second clock signal CK2 can have different phases (e.g., opposite phases, but not limited thereto). In an embodiment, as... Figure 2 As shown, for each of the first clock signal CK1 and the second clock signal CK2, the on-time (e.g., low-time period) can be shorter than the off-time (e.g., high-time period). For example, the duty cycle of each of the first clock signal CK1 and the second clock signal CK2 can be, but is not limited to, about 20% to about 40%. In other embodiments, the on-time of each of the first clock signal CK1 and the second clock signal CK2 can be longer than or equal to the off-time of each of the first clock signal CK1 and the second clock signal CK2. Figures 1 to 6 The example shown is as follows: transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, and T12 are PMOS transistors, with a first turn-on level of a first low level L, a second turn-on level of a second low level 2L, a turn-off level of a high level H, a gate turn-on voltage VGL of a low gate voltage VGL, and a gate turn-off voltage VGH of a high gate voltage VGH.

[0059] like Figure 2 and Figure 3 As shown, during the period from the first time point TP1 to the second time point TP2, an input signal SIN with a first low level L can be applied. The first clock signal CK1 can have a high level H, and the second clock signal CK2 can have a first low level L. A diode-connected first transistor T1 can transmit the input signal SIN with the first low level L to the shared control node NSQ, and can change the voltage V_NSQ of the shared control node NSQ to the first low level L. A second transistor T2 can be turned on in response to a low gate voltage VGL. The turned-on second transistor T2 can transmit the voltage V_NSQ of the shared control node NSQ with the first low level L to the first control node NQ1, and the voltage V_NQ1 of the first control node NQ1 can be changed to the first low level L. The third transistor T3 can be turned on in response to the voltage V_NQ1 of the first control node NQ1 having a first low level L. The turned-on third transistor T3 can transmit the first clock signal CK1 having a high level H to the first output node NO1. The voltage V_NQ1 of the first control node NQ1 or the voltage of the first electrode of the first capacitor C1 can have a first low level L, while the voltage of the first output node NO1 or the voltage of the second electrode of the first capacitor C1 can have a high level H.

[0060] like Figure 2 and Figure 4 As shown, during the period from the third time point TP3 to the fourth time point TP4, the first clock signal CK1 may have a first low level L, and the second clock signal CK2 may have a high level H. If the first clock signal CK1 with the first low level L is applied to the first output node NO1 through the turned-on third transistor T3, then the voltage of the first output node NO1 or the voltage of the second electrode of the first capacitor C1 can change from the high level H to the first low level L. If the voltage of the second electrode of the first capacitor C1 changes from the high level H to the first low level L, then the voltage of the first electrode of the first capacitor C1 or the voltage V_NQ1 of the first control node NQ1 can change from the first low level L to a second low level 2L, which is lower than the first low level L. In the embodiment, the voltage level difference between the first low level L and the second low level 2L may correspond to, but is not limited to, the voltage level difference between the high level H and the first low level L. In the embodiment, the operation of changing the voltage V_NQ1 of the first control node NQ1 from the first low level L to the second low level 2L can be called a bootstrapoperation, and the first capacitor C1 can be called a bootstrap capacitor.

[0061] The third transistor T3 can remain in the ON state based on the voltage V_NQ1 of the first control node NQ1 having a second low level 2L, and the ON third transistor T3 can output a first clock signal CK1 with a first low level L at the first output node NO1 as a first scan signal SS1. The twelfth transistor T12 can be turned on in response to the first scan signal SS1 with a first low level L, and the ON twelfth transistor T12 can transmit a high gate voltage VGH to the shared inverting control node NSQB, so the voltage V_NSQB of the shared inverting control node NSQB can remain at a high level H. The eleventh transistor T11 can also be turned on in response to the first scan signal SS1 with a first low level L, and the ON eleventh transistor T11 can transmit a high gate voltage VGH to the gate of the tenth transistor T10. Therefore, although the ninth transistor T9 is turned on in response to the first clock signal CK1 having a first low level L, the tenth transistor T10 may not be turned on due to the high gate voltage VGH transmitted through the eleventh transistor T11, and the first clock signal CK1 having a first low level L will not be transmitted to the shared inverting control node NSQB through the tenth transistor T10. In an embodiment, in order to prevent the tenth transistor T10 from conducting, the eleventh transistor T11 may have a larger size than the ninth transistor T9, but the sizes of the ninth transistor T9 and the eleventh transistor T11 are not limited thereto.

[0062] The fifth transistor T5 can be turned on in response to a first clock signal CK1 having a first low level L. The turned-on fifth transistor T5 can transmit the voltage V_NSQ of the shared control node NSQ having a first low level L to the second control node NQ2, and the voltage V_NQ2 of the second control node NQ2 can be changed to the first low level L. The sixth transistor T6 can be turned on in response to the voltage V_NQ2 of the second control node NQ2 having a first low level L, and the turned-on sixth transistor T6 can transmit the second clock signal CK2 having a high level H to the second output node NO2. The voltage V_NQ2 of the second control node NQ2 or the voltage at the first electrode of the second capacitor C2 can have a first low level L, while the voltage of the second output node NO2 or the voltage at the second electrode of the second capacitor C2 can have a high level H.

[0063] At the fourth time point TP4, if the first clock signal CK1 changes from a first low level L to a high level H, then the third transistor T3 can transmit the first clock signal CK1 with a high level H to the first output node NO1, and the first scan signal SS1 at the first output node NO1 can change from a first low level L to a high level H. Furthermore, if the voltage of the first output node NO1 or the voltage of the second electrode of the first capacitor C1 changes from a first low level L to a high level H, then the voltage of the first electrode of the first capacitor C1 or the voltage V_NQ1 of the first control node NQ1 can change from a second low level 2L to a first low level L.

[0064] like Figure 2 and Figure 5 As shown, during the period from the fifth time point TP5 to the sixth time point TP6, the first clock signal CK1 can have a high level H, and the second clock signal CK2 can have a first low level L. If the second clock signal CK2 with the first low level L is applied to the second output node NO2 through the turned-on sixth transistor T6, then the voltage of the second output node NO2 or the voltage of the second electrode of the second capacitor C2 can change from the high level H to the first low level L. If the voltage of the second electrode of the second capacitor C2 changes from the high level H to the first low level L, then the voltage of the first electrode of the second capacitor C2 or the voltage V_NQ2 of the second control node NQ2 can change from the first low level L to a second low level 2L, which is lower than the first low level L. In the embodiment, like the first capacitor C1, the second capacitor C2 is also referred to as a bootstrap capacitor. The sixth transistor T6 can remain in the turned-on state based on the voltage V_NQ2 of the second control node NQ2 with the second low level 2L, and the turned-on sixth transistor T6 can output the second clock signal CK2 with the first low level L at the second output node NO2 as the second scan signal SS2.

[0065] At the sixth time point TP6, if the second clock signal CK2 changes from the first low level L to the high level H, then the sixth transistor T6 can transmit the second clock signal CK2 with the high level H to the second output node NO2, and the second scan signal SS2 at the second output node NO2 can change from the first low level L to the high level H. Furthermore, if the voltage of the second output node NO2 or the voltage of the second electrode of the second capacitor C2 changes from the first low level L to the high level H, then the voltage of the first electrode of the second capacitor C2 or the voltage V_NQ2 of the second control node NQ2 can change from the second low level 2L to the first low level L.

[0066] like Figure 2 and Figure 6As shown, during the period from the seventh time point TP7 to the eighth time point TP8, the first clock signal CK1 can have a first low level L, while the second clock signal CK2 can have a high level H. The ninth transistor T9 can be turned on in response to the first clock signal CK1 having the first low level L, and the turned-on ninth transistor T9 can transmit the first clock signal CK1 having the first low level L to the gate of the tenth transistor T10. The tenth transistor T10 can be turned on in response to the first clock signal CK1 having the first low level L transmitted through the ninth transistor T9, and the turned-on tenth transistor T10 can transmit the first clock signal CK1 having the first low level L to the shared inverting control node NSQB, and the voltage V_NSQB of the shared inverting control node NSQB can be changed to the first low level L. The eighth transistor T8 can be turned on in response to a voltage V_NSQB with a first low level L at the shared inverting control node NSQB. The turned-on eighth transistor T8 can transmit a high gate voltage VGH to the shared control node NSQ, and the voltage V_NSQ at the shared control node NSQ can change to a high level H. The second transistor T2 can be turned on in response to a low gate voltage VGL. The turned-on second transistor T2 can transmit a voltage V_NSQ with a high level H at the shared control node NSQ to the first control node NQ1, and the voltage V_NQ1 at the first control node NQ1 can change to a high level H. The fifth transistor T5 can be turned on in response to a first clock signal CK1 with a first low level L. The turned-on fifth transistor T5 can transmit a voltage V_NSQ with a high level H at the shared control node NSQ to the second control node NQ2, and the voltage V_NQ2 at the second control node NQ2 can change to a high level H. The fourth transistor T4 and the seventh transistor T7 can be turned on in response to a voltage V_NSQB with a first low level L at the shared inverting control node NSQB. The turned-on fourth transistor T4 can transmit a high gate voltage VGH to the first output node NO1, and the turned-on seventh transistor T7 can transmit a high gate voltage VGH to the second output node NO2. In an embodiment, before the first time point TP1 and / or after the eighth time point TP8, whenever the first clock signal CK1 has a first low level L, the voltage V_NSQB of the shared inverting control node NSQB can periodically have a first low level L, and whenever the voltage V_NSQB of the shared inverting control node NSQB has a first low level L, the high gate voltage VGH can be periodically transmitted to the first output node NO1, the second output node NO2, and the shared control node NSQB through the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8, respectively.

[0067] Figure 7 Each level included in the scan driver according to an embodiment is shown.

[0068] Reference Figure 7 Each stage 200 of the scan driver according to the embodiment may include a shared input circuit 110, a first output circuit 130, a second output circuit 250, a shared stabilizer circuit 170, and a shared inverter circuit 190. In addition to the second output circuit 250, it may also include a thirteenth transistor T13 coupled between the second terminal of the fifth transistor T5 and the second control node NQ2. Figure 7 Level 200 can have the same Figure 1 The construction (configuration) and operation of level 100 are similar to those of other constructions (configurations) and operations.

[0069] The thirteenth transistor T13 may include a gate that receives the gate on-state voltage VGL, a first terminal connected to the second terminal of the fifth transistor T5, and a second terminal connected to the second control node NQ2. For example... Figure 5 As shown, in the first case where the second output circuit 250 does not include the thirteenth transistor T13, when the second control node NQ2 bootstraps, the voltage V_NQ2 of the second control node NQ2 with a second low level 2L can be applied to the second terminal of the fifth transistor T5, and the first clock signal CK1 with a high level H can be applied to the gate of the fifth transistor T5. Therefore, in this case, high gate stress can be applied to the fifth transistor T5. However, in the second case where the second output circuit 250 includes the thirteenth transistor T13, although the voltage V_NQ2 of the second control node NQ2 with a second low level 2L is applied to the second terminal of the thirteenth transistor T13, the gate on-state voltage VGL with a first low level L can be applied to the gate of the thirteenth transistor T13. Therefore, the gate stress on the thirteenth transistor T13 can be reduced compared to the high gate stress on the fifth transistor T5 in the first case. Furthermore, since the voltage V_NQ2 of the second control node NQ2 with the second low level 2L is not transmitted to the second terminal of the fifth transistor T5 through the thirteenth transistor T13, the gate stress of the fifth transistor T5 can also be reduced compared to the high gate stress in the first case.

[0070] Figure 8 The illustration shows each level included in the scan driver according to an embodiment. Figure 9 Used to describe Figure 8 Examples of operations at the level of [level].

[0071] Reference Figure 8Each stage 300 of the scan driver according to the embodiment may include a shared input circuit 310, a first output circuit 130, a second output circuit 150, a shared stabilizer circuit 170, and a shared inverter circuit 190. Except that the first transistor T1a of the shared input circuit 310 can receive the second clock signal CK2 instead of the input signal SIN, Figure 8 The level 300 can have the same Figure 1 The construction of level 100 is similar to that of the previous construction. Furthermore, as... Figure 9 As shown, except that the voltage V_NSQ of the shared control node NSQ and the voltage V_NQ1 of the first control node NQ1 can be changed to a high level H at the fifth time point TP5 when the second clock signal CK2 changes to the first low level L, Figure 8 The level 300 can have the same Figure 1 The operation is similar to that of level 100.

[0072] The shared input circuit 310 may include a first transistor T1a, which includes a gate for receiving the second clock signal CK2, a first terminal for receiving the input signal SIN, and a second terminal connected to the shared control node NSQ. Figure 9 As shown, during the period from the first time point TP1 to the second time point TP2, the second clock signal CK2 may have a first low level L. The first transistor T1a, in response to the second clock signal CK2 having the first low level L, can transmit the input signal SIN having the first low level L to the shared control node NSQ, and the voltage V_NSQ of the shared control node NSQ can change to the first low level L. Furthermore, at the fifth time point TP5, when the second clock signal CK2 changes to the first low level L, the first transistor T1a, in response to the second clock signal CK2 having the first low level L, can transmit the input signal SIN having a high level H to the shared control node NSQ, and the voltage V_NSQ of the shared control node NSQ can change to a high level H. The second transistor T2 can be turned on in response to a low gate voltage VGL. The turned-on second transistor T2 can transmit the voltage V_NSQ of the shared control node NSQ having a high level H to the first control node NQ1, and the voltage V_NQ1 of the first control node NQ1 can change to a high level H. The fifth transistor T5 can be turned off in response to the first clock signal CK1 with a high level H, and the voltage V_NSQ of the shared control node NSQ with a high level H will not be transmitted to the second control node NQ2 through the turned-off fifth transistor T5.

[0073] Figure 10 The illustration shows each level included in the scan driver according to an embodiment. Figure 11 Used to describe Figure 10 Examples of operations at the level of [level].

[0074] Reference Figure 10 Each stage 400 of the scan driver according to the embodiment may include a shared input circuit 110, a first output circuit 130, a second output circuit 150, a shared stabilizer circuit 170, and a shared inverter circuit 490. In addition to the gates of the eleventh transistor T11a and the twelfth transistor T12a of the shared inverter circuit 490 being coupled to a shared control node NSQ instead of the first output node NO1, and the shared inverter circuit 490 also including a third capacitor C3, Figure 10 The level 400 can have the same Figure 1 The construction of level 100 is similar to that of the previous construction. Furthermore, as... Figure 11 As shown, except that the voltage V_NSQB of the shared inverting control node NSQB can remain at the first low level L during the period before the first time point TP1 and after the seventh time point TP7, Figure 10 The level 400 can have the same Figure 1 The operation is similar to that of level 100.

[0075] The shared inverter circuit 490 can control the shared inverter control node NSQB in response to the first clock signal CK1 and the voltage V_NSQ of the shared control node NSQ. In an embodiment, as shown... Figure 10 As shown, the shared inverter circuit 490 may include: a ninth transistor, including a gate for receiving a first clock signal CK1, a first terminal for receiving the first clock signal CK1, and a second terminal; a tenth transistor T10, including a gate connected to the second terminal of the ninth transistor T9, a first terminal for receiving the first clock signal CK1, and a second terminal connected to the shared inverter control node NSQB; an eleventh transistor T11a, including a gate connected to the shared control node NSQ, a first terminal connected to the gate of the tenth transistor T10, and a second terminal for receiving the gate cutoff voltage VGH; a twelfth transistor T12a, including a gate connected to the shared control node NSQ, a first terminal connected to the shared inverter control node NSQB, and a second terminal for receiving the gate cutoff voltage VGH; and a third capacitor C3, including a first electrode connected to the shared inverter control node NSQB and a second electrode for receiving the gate cutoff voltage VGH. For example, as... Figure 11As shown, during the period before the first time point TP1 and after the seventh time point TP7, the shared inverter circuit 490 can periodically apply a first clock signal CK1 with a first low level L to the shared inverter control node NSQB, and can maintain the voltage V_NSQB of the shared inverter control node NSQB at the first low level L by using the third capacitor C3. During the period from the first time point TP1 to the seventh time point TP7, the shared inverter circuit 490 can transfer the gate cutoff voltage VGH to the shared inverter control node NSQB in response to the voltage V_NSQ of the shared control node NSQ, and can maintain the voltage V_NSQB of the shared inverter control node NSQB at a high level H.

[0076] although Figure 1 An example of stage 100 is shown, comprising a shared input circuit 110, a first output circuit 130, a second output circuit 150, a shared stabilizer circuit 170, and a shared inverter circuit 190. Figure 7 The diagram shows a second output circuit 250 instead of... Figure 1 Example of stage 200 of the second output circuit 150, Figure 8 The diagram shows a shared input circuit 310 instead of Figure 1 An example of stage 300 of the shared input circuit 110, and Figure 10 The diagram shows a shared inverter circuit 490 instead of... Figure 1 An example of a stage 400 of a shared inverter circuit 190; according to an embodiment, each stage may include Figure 7 The second output circuit 250 Figure 8 The shared input circuit 310 and Figure 10 Two or more of the shared inverter circuit 490 instead of Figure 1 Two or more of the shared input circuit 110, the second output circuit 150, and the shared inverter circuit 190.

[0077] Figure 12 The illustration shows each level included in the scan driver according to an embodiment. Figure 13 Used to describe Figure 12 Examples of operations at the level of [level].

[0078] Reference Figure 12Each stage 500 of the scan driver according to the embodiment may include a shared input circuit 510, a first output circuit 530, a second output circuit 550, a shared stabilizer circuit 570, and a shared inverter circuit 590. Except that the transistors T1′, T2′, T3′, T4′, T5′, T6′, T7′, T8′, T9′, T10′, T11′, and T12′ included in the scan driver or each stage 500 can be implemented using NMOS transistors instead of PMOS transistors, and the gate on-voltage can be a high gate voltage VGH and the gate off-voltage can be a low gate voltage VGL, Figure 12 The level 500 can have the same Figure 1 The construction of level 100 is similar to that of the previous construction. Furthermore, as... Figure 13 As shown, the first conduction level can be a first high level H instead of... Figure 2 The first low level L, the second conduction level can be the second high level 2H instead of Figure 2 The second low level 2L and the cutoff level can be low level L instead of high level H. Figure 12 The level 500 can have the same Figure 1 The operation is similar to that of level 100.

[0079] In an optional embodiment, the transistor in one of the first output circuit and the second output circuit may be an NMOS transistor, while the transistor in the other of the first output circuit and the second output circuit may be a PMOS transistor. In an optional embodiment, the transistor in at least one of the shared input circuit, the shared stabilizer circuit, and the shared inverter circuit may be an NMOS transistor, while the transistor in at least one of the shared input circuit, the shared stabilizer circuit, and the shared inverter circuit may be a PMOS transistor.

[0080] Figure 14 Each level included in the scan driver according to an embodiment is shown.

[0081] Reference Figure 14 Each stage 600 of the scan driver according to the embodiment may include a shared input circuit 510, a first output circuit 530, a second output circuit 650, a shared stabilizer circuit 570, and a shared inverter circuit 590. Except that the transistors T1′, T2′, T3′, T4′, T5′, T6′, T7′, T8′, T9′, T10′, T11′, T12′, and T13′ included in the scan driver or each stage 600 can be implemented using NMOS transistors instead of PMOS transistors, and the gate on-voltage can be a high gate voltage VGH and the gate off-voltage can be a low gate voltage VGL, Figure 14 The level 600 can have the same Figure 7The construction and operation of level 200 are similar to those of other constructions and operations.

[0082] Figure 15 Each level included in the scan driver according to an embodiment is shown.

[0083] Reference Figure 15 Each stage 700 of the scan driver according to the embodiment may include a shared input circuit 710, a first output circuit 530, a second output circuit 550, a shared stabilizer circuit 570, and a shared inverter circuit 590. Except that the transistors T1a′, T2′, T3′, T4′, T5′, T6′, T7′, T8′, T9′, T10′, T11′, and T12′ included in the scan driver or each stage 700 can be implemented using NMOS transistors instead of PMOS transistors, and the gate on-voltage can be a high gate voltage VGH and the gate off-voltage can be a low gate voltage VGL, Figure 15 The level 700 can have the same Figure 8 The construction and operation of level 300 are similar to those of other constructions and operations.

[0084] Figure 16 Each level included in the scan driver according to an embodiment is shown.

[0085] Reference Figure 16 Each stage 800 of the scan driver according to the embodiment may include a shared input circuit 510, a first output circuit 530, a second output circuit 550, a shared stabilizer circuit 570, and a shared inverter circuit 890. Except that the transistors T1′, T2′, T3′, T4′, T5′, T6′, T7′, T8′, T9′, T10′, T11a′, and T12a′ included in the scan driver or each stage 800 can be implemented using NMOS transistors instead of PMOS transistors, and the gate on-voltage can be a high gate voltage VGH and the gate off-voltage can be a low gate voltage VGL, Figure 16 The level 800 can have the same Figure 10 The construction and operation of level 400 are similar to those of other constructions and operations.

[0086] Figure 17 A display device including a scan driver according to an embodiment is shown. Figure 18 A scan driver included in a display device according to an embodiment is shown.

[0087] Reference Figure 17The display device 900 according to the embodiment may include: a display panel 910 including a plurality of pixels PX; a data driver 930 providing data signals DS to the plurality of pixels PX; a scan driver 950 providing scan signals SS to the plurality of pixels PX; and a controller 970 controlling the data driver 930 and the scan driver 950.

[0088] Display panel 910 may include data lines, scan lines, and a plurality of pixels PX combined with the data lines and scan lines. In an embodiment, each pixel PX may include a storage capacitor, a switching transistor that stores a data signal DS in the storage capacitor in response to a scan signal SS, a driving transistor that generates a driving current based on the data signal DS stored in the storage capacitor, and an organic light-emitting diode (OLED) that emits light based on the driving current, and display panel 910 may be an OLED display panel. However, the construction of each pixel PX according to the embodiment is not limited to a 2T1C structure including a storage capacitor, a switching transistor, and a driving transistor. In other embodiments, display panel 910 may be a liquid crystal display (LCD) panel, etc.

[0089] The data driver 930 can generate a data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 970, and can provide the data signal DS to multiple pixels PX via data lines. In embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. In embodiments, the data driver 930 and the controller 970 can be implemented using a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other embodiments, the data driver 930 and the controller 970 can be implemented using separate integrated circuits.

[0090] The scan driver 950 can generate a scan signal SS based on a scan control signal received from the controller 970, and can provide the scan signal SS to multiple pixels PX via scan lines. In embodiments, the scan control signal may include, but is not limited to, a scan start signal FLM, a first clock signal CK1, and a second clock signal CK2. In embodiments, the scan driver 950 may be integrated or formed in the peripheral portion of the display panel 910. In other embodiments, the scan driver 950 may be implemented using one or more integrated circuits.

[0091] like Figure 18As shown, the scan driver 950 may include multiple stages 951, 952, 953, ..., 955 that receive a first clock signal CK1 and a second clock signal CK2 with different phases (e.g., opposite phases). For example, if the display panel 910 includes N (where N is an integer greater than 1) pixel rows (e.g., N rows of pixels PX), the scan driver 950 may include N / 2 stages 951, 952, 953, ..., 955 or the first stage to the N / 2th stage 951, 952, 953, ..., 955. Each stage 951, 952, 953, ..., 955 can receive a scan start signal FLM or a scan signal from the previous stage (e.g., SS2, SS4, SS6, ..., SSN-2) as an input signal. It can output a scan signal (e.g., SS1, SS3, SS5, ..., SSN-1) to a pixel row in synchronization with a first clock signal CK1, and can output another scan signal (e.g., SS2, SS4, SS6, ..., SSN) to another pixel row in synchronization with a second clock signal CK2. For example, the first stage 951 can receive the scan start signal FLM, output the first scan signal SS1 to the first pixel row in synchronization with the first clock signal CK1, and output the second scan signal SS2 to the second pixel row in synchronization with the second clock signal CK2. The second stage 952 can receive the second scan signal SS2, output the third scan signal SS3 to the third pixel row in synchronization with the first clock signal CK1, and output the fourth scan signal SS4 to the fourth pixel row in synchronization with the second clock signal CK2. The third stage 953 can receive the fourth scan signal SS4, output the fifth scan signal SS5 to the fifth pixel row synchronously with the first clock signal CK1, and output the sixth scan signal SS6 to the sixth pixel row synchronously with the second clock signal CK2. In this way, the N / 2th stage 955 can receive the (N-2)th scan signal SSN-2, output the (N-1)th scan signal SSN-1 to the (N-1)th pixel row synchronously with the first clock signal CK1, and output the Nth scan signal SSN to the Nth pixel row synchronously with the second clock signal CK2. As described above, each of the multiple stages 951, 952, 953, ..., 955 can output two scan signals (e.g., SS1 and SS2) to two pixel rows using only two clock signals CK1 and CK2, and the size of the scan driver 950 can be reduced compared to a scan driver that outputs only one scan signal per stage.

[0092] The controller (e.g., a timing controller (TCON)) 970 can receive input image data IDAT and control signals CTRL from an external host (e.g., a graphics processing unit (GPU) or graphics card). In embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The controller 970 can generate output image data ODAT, a data control signal DCTRL, and a scan control signal based on the input image data IDAT and the control signal CTRL. The controller 970 can control the operation of the data driver 930 by providing the output image data ODAT and the data control signal DCTRL to the data driver 930, and can control the operation of the scan driver 950 by providing the scan control signal to the scan driver 950.

[0093] Figure 19 An electronic device including a display device is shown according to an embodiment.

[0094] Reference Figure 19 Electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, a display device 1160, and a communication bus 1170. Electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, and other electronic devices.

[0095] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (AP), microprocessor, central processing unit (CPU), etc. Processor 1110 can be connected to other components via communication bus 1170, which may include address bus, control bus, data bus, etc. In addition, in embodiments, processor 1110 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0096] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0097] Storage device 1130 may be a solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. Display device 1160 can be connected to other components via a bus or other communication link.

[0098] In the display device 1160, the scan driver may include multiple stages that receive a first clock signal and a second clock signal with different phases, and the first output circuit and the second output circuit of each stage may share a shared control node and a shared inverting control node. The first output circuit of each stage may output a first scan signal synchronously with the first clock signal, and the second output circuit of each stage may output a second scan signal synchronously with the second clock signal. Therefore, each stage of the scan driver can output two scan signals to two pixel rows using only two clock signals, and the size of the scan driver can be reduced compared to a scan driver where each stage outputs only one scan signal.

[0099] The inventive concept can be applied to any display device 1160 and any electronic device 1100 that includes the display device 1160. For example, the inventive concept can be applied to mobile phones, smartphones, wearable electronic devices, tablet computers, televisions (TV), digital TVs, 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0100] The foregoing is illustrative of the inventive concept and should not be construed as limiting it. Although embodiments have been described, it will be readily understood by those skilled in the art that numerous modifications are possible in the described and other embodiments without substantially departing from the novel teachings of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. It should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A scan driver comprising multiple levels, each of the multiple levels comprising: At least one clock line is configured to receive a first clock signal and a second clock signal with different phases; The shared input circuit is configured to transmit the input signal to the shared control node; A first output circuit, combined with the shared control node, is configured to transmit the voltage of the shared control node to the first control node, and is configured to output a first scan signal in response to the voltage of the first control node and the first clock signal. as well as A second output circuit, integrated with the shared control node, is configured to transmit the voltage of the shared control node to the second control node, and is configured to output a second scan signal in response to the voltage of the second control node and the second clock signal. The shared input circuit includes a first transistor, comprising a gate for receiving the second clock signal, a first terminal for receiving the input signal, and a second terminal connected to the shared control node.

2. The scan driver according to claim 1, wherein, The first output circuit and the second output circuit are combined together to a shared inverting control node. Specifically, the first output circuit transmits a gate cutoff voltage to the first output node in response to the voltage of the shared inverting control node, and the first scan signal is output at the first output node. The second output circuit transmits the gate cutoff voltage to the second output node in response to the voltage of the shared inverting control node, and the second scan signal is output at the second output node.

3. The scan driver according to claim 1, wherein, The first output circuit includes: The second transistor includes a gate for receiving a gate turn-on voltage, a first terminal coupled to the shared control node, and a second terminal coupled to the first control node. The third transistor includes a gate coupled to the first control node, a first terminal receiving the first clock signal, and a second terminal coupled to the first output node, wherein the first scan signal is output at the first output node; A first capacitor includes a first electrode coupled to the first control node and a second electrode coupled to the first output node; and The fourth transistor includes a gate coupled to a shared inverting control node, a first terminal coupled to the first output node, and a second terminal receiving a gate cutoff voltage.

4. The scan driver according to claim 1, wherein, The second output circuit includes: The fifth transistor includes a gate for receiving the first clock signal, a first terminal connected to the shared control node, and a second terminal connected to the second control node; The sixth transistor includes a gate coupled to the second control node, a first terminal receiving the second clock signal, and a second terminal coupled to the second output node, wherein the second scan signal is output at the second output node; The second capacitor includes a first electrode coupled to the second control node and a second electrode coupled to the second output node; and The seventh transistor includes a gate coupled to a shared inverting control node, a first terminal coupled to the second output node, and a second terminal receiving a gate cutoff voltage.

5. The scan driver according to claim 4, wherein, The second output circuit also includes: The thirteenth transistor is coupled between the second terminal of the fifth transistor and the second control node, and includes a gate for receiving a gate on-state voltage, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to the second control node.

6. The scan driver according to claim 1, wherein, Each of the plurality of levels also includes: The shared stabilizer circuit is configured to transmit a gate cutoff voltage to the shared control node in response to the voltage of the shared inverting control node.

7. The scan driver according to claim 6, wherein, The shared stabilizer circuit includes: The eighth transistor includes a gate coupled to the shared inverting control node, a first terminal coupled to the shared control node, and a second terminal receiving the gate cutoff voltage.

8. The scan driver according to claim 1, wherein, Each of the plurality of levels also includes: A shared inverter circuit is configured to control a shared inverter control node in response to the first clock signal and the first scan signal.

9. The scan driver according to claim 8, wherein, The shared inverter circuit includes: The ninth transistor includes a gate for receiving the first clock signal, a first terminal for receiving the first clock signal, and a second terminal; The tenth transistor includes a gate connected to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal connected to the shared inverting control node; The eleventh transistor includes a gate coupled to a first output node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving a gate cutoff voltage; the first scan signal is output at the first output node; and The twelfth transistor includes a gate coupled to the first output node, a first terminal coupled to the shared inverting control node, and a second terminal receiving the gate cutoff voltage.

10. The scan driver according to claim 1, wherein, Each of the plurality of levels also includes: A shared inverter circuit is configured to control a shared inverter control node in response to the first clock signal and the voltage of the shared control node.

11. The scan driver according to claim 10, wherein, The shared inverter circuit includes: The ninth transistor includes a gate for receiving the first clock signal, a first terminal for receiving the first clock signal, and a second terminal; The tenth transistor includes a gate connected to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal connected to the shared inverting control node; The eleventh transistor includes a gate coupled to the shared control node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving a gate cutoff voltage. The twelfth transistor includes a gate coupled to the shared control node, a first terminal coupled to the shared inverting control node, and a second terminal receiving the gate cutoff voltage; and The third capacitor includes a first electrode coupled to the shared inverting control node and a second electrode receiving the gate cutoff voltage.

12. The scan driver according to claim 1, wherein, The transistor included in one of the first output circuit and the second output circuit of the scan driver is an NMOS transistor, while the transistor included in the other of the first output circuit and the second output circuit is a PMOS transistor.

13. The scan driver according to claim 1, wherein, The transistor included in at least one of the shared input circuit, the shared stabilizer circuit, and the shared inverter circuit of the scan driver is a PMOS transistor, while the transistor included in at least another of the shared input circuit, the shared stabilizer circuit, and the shared inverter circuit is an NMOS transistor.

14. A scan driver comprising multiple levels, each of the multiple levels comprising: At least one clock line is configured to receive a first clock signal and a second clock signal with different phases; The first transistor includes a gate for receiving an input signal or the second clock signal, a first terminal for receiving the input signal, and a second terminal connected to a shared control node; The second transistor includes a gate for receiving a gate turn-on voltage, a first terminal coupled to the shared control node, and a second terminal coupled to the first control node. The third transistor includes a gate coupled to the first control node, a first terminal receiving the first clock signal, and a second terminal coupled to the first output node, wherein the first scan signal is output at the first output node; The first capacitor includes a first electrode coupled to the first control node and a second electrode coupled to the first output node; The fourth transistor includes a gate coupled to a shared inverting control node, a first terminal coupled to the first output node, and a second terminal receiving a gate cutoff voltage. The fifth transistor includes a gate for receiving the first clock signal, a first terminal connected to the shared control node, and a second terminal connected to the second control node; The sixth transistor includes a gate coupled to the second control node, a first terminal receiving the second clock signal, and a second terminal coupled to the second output node, wherein the second scan signal is output at the second output node; The second capacitor includes a first electrode coupled to the second control node and a second electrode coupled to the second output node; as well as The seventh transistor includes a gate coupled to the shared inverting control node, a first terminal coupled to the second output node, and a second terminal receiving the gate cutoff voltage.

15. The scan driver according to claim 14, wherein, Each of the plurality of levels also includes: The eighth transistor includes a gate coupled to the shared inverting control node, a first terminal coupled to the shared control node, and a second terminal receiving the gate cutoff voltage; The ninth transistor includes a gate for receiving the first clock signal, a first terminal for receiving the first clock signal, and a second terminal; The tenth transistor includes a gate connected to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal connected to the shared inverting control node; The eleventh transistor includes a gate coupled to the first output node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving the gate cutoff voltage; and The twelfth transistor includes a gate coupled to the first output node, a first terminal coupled to the shared inverting control node, and a second terminal receiving the gate cutoff voltage.

16. The scan driver according to claim 14, wherein, Each of the plurality of levels also includes: The thirteenth transistor is coupled between the second terminal of the fifth transistor and the second control node, and includes a gate for receiving the gate on-state voltage, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to the second control node.

17. The scan driver according to claim 14, wherein, Each of the plurality of levels also includes: The eighth transistor includes a gate coupled to the shared inverting control node, a first terminal coupled to the shared control node, and a second terminal receiving the gate cutoff voltage; The ninth transistor includes a gate for receiving the first clock signal, a first terminal for receiving the first clock signal, and a second terminal; The tenth transistor includes a gate connected to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal connected to the shared inverting control node; The eleventh transistor includes a gate coupled to the shared control node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving the gate cutoff voltage; The twelfth transistor includes a gate coupled to the shared control node, a first terminal coupled to the shared inverting control node, and a second terminal receiving the gate cutoff voltage; and The third capacitor includes a first electrode coupled to the shared inverting control node and a second electrode receiving the gate cutoff voltage.

18. A display device, the display device comprising: The display panel includes multiple pixels; A data driver is configured to provide data signals to the plurality of pixels; A scan driver is configured to provide scan signals to the plurality of pixels and includes multiple stages; as well as The controller is configured to control the data driver and the scan driver. Each of the plurality of levels includes: At least one clock line is configured to receive a first clock signal and a second clock signal with different phases; The shared input circuit is configured to transmit the input signal to the shared control node; A first output circuit, coupled to the shared control node, is configured to transmit the voltage of the shared control node to the first control node, and is configured to output a first scan signal from the scan signals in response to the voltage of the first control node and the first clock signal; and The second output circuit, integrated with the shared control node, is configured to transmit the voltage of the shared control node to the second control node, and is configured to output a second scan signal from the scan signals in response to the voltage of the second control node and the second clock signal. The shared input circuit includes a first transistor, comprising a gate for receiving the second clock signal, a first terminal for receiving the input signal, and a second terminal connected to the shared control node.

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