Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and a method for operating the same are provided herein. The semiconductor memory device includes: a memory cell array including a plurality of memory cells to be programmed into a plurality of program states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on the selected memory cells among the plurality of program states and determine a result of the program operation for each of the plurality of program states; and control logic configured to control the peripheral circuit and the current sensing circuit so that an operation period of the overall state current sensing operation at least partially overlaps an operation period of a bit line setting operation of the program operation.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to a semiconductor memory device and a method of operating the semiconductor memory device. Background Art

[0002] Recently, the paradigm of computing has shifted to ubiquitous computing, enabling computer systems to be used anywhere, anytime. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices typically utilize memory systems employing semiconductor memory devices, or in other words, data storage devices. These data storage devices serve as primary or secondary memory devices in portable electronic devices.

[0003] Advantages of data storage devices using semiconductor memory devices include excellent stability and durability, increased information access speed, and reduced power consumption due to the absence of mechanical drive components. Examples of data storage devices proposed as memory systems having these advantages include universal serial bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs).

[0004] Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.

[0005] Although the read and write speeds are relatively low, non-volatile memory devices can retain the data stored therein even when the power supply is interrupted. Therefore, non-volatile memory devices are used when it is necessary to store data that must be maintained regardless of the power supply. Representative examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified into NOR type memory and NAND type memory. Summary of the Invention

[0006] An embodiment of the present disclosure may provide a semiconductor memory device, which includes: a memory cell array, which includes a plurality of memory cells to be programmed into a plurality of programming states; a peripheral circuit, which is configured to perform a programming operation on a selected memory cell among the plurality of memory cells; a current sensing circuit, which is configured to perform an individual state current sensing operation and an overall state current sensing operation on the selected memory cell among the plurality of memory cells, and determine a result of the programming operation for each of the plurality of programming states; and control logic, which is configured to control the peripheral circuit and the current sensing circuit so that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line setting operation of the programming operation.

[0007] Embodiments of the present disclosure may provide a method for operating a semiconductor memory device, the method comprising the steps of: performing a first programming operation corresponding to a first programming state among a plurality of programming states; performing a first bulk current sensing operation corresponding to the first programming operation and determining whether the first programming operation has passed; performing a second programming operation corresponding to a second programming state having a threshold voltage distribution higher than that of the first programming state based on a result of the first bulk current sensing operation; performing a second bulk current sensing operation corresponding to the second programming operation and determining whether the second programming operation has passed; performing an overall state current sensing operation; and when the result of the overall state current sensing operation indicates a failure, performing an additional programming operation and then re-performing the process from the overall state current sensing operation. An operation period of the overall state current sensing operation and an operation period of the additional programming operation may at least partially overlap with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 The embodiment according to the present disclosure is shown Figure 1 Diagram of a memory cell array.

[0010] Figure 3 The embodiment according to the present disclosure is shown Figure 2 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0011] Figure 4 The embodiment according to the present disclosure is shown Figure 2 A circuit diagram of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0012] Figure 5 The embodiment according to the present disclosure is shown Figure 1 1 and 2. A circuit diagram of any one memory block BLKc among the memory blocks BLK1 to BLKz included in the memory cell array 110 of FIG.

[0013] Figure 6 is used to describe Figure 1 Circuit diagram of the page buffer.

[0014] Figure 7 is a graph showing the programming state of a triple level cell.

[0015] Figure 8 is a diagram for describing a program operation based on an individual state current sensing operation and an overall state current sensing operation according to an embodiment of the present disclosure.

[0016] Figure 9 and Figure 10 is a flowchart for describing a programming operation and an individual state current sensing operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 11 Is used to describe the Figure 9 and Figure 10 A flowchart of an overall state current sensing operation of a programming operation of a semiconductor memory device according to an embodiment of the present invention.

[0018] Figure 12 is a diagram for describing the operation time overlap of a bit line setting operation and an overall current sensing operation.

[0019] Figure 13 It is shown that Figure 1 A block diagram of an embodiment of a memory system of a semiconductor memory device.

[0020] Figure 14 It shows Figure 13 A block diagram of an example of an application of a memory system.

[0021] Figure 15 It is shown including reference Figure 14 A block diagram of a computing system with a memory system is shown. DETAILED DESCRIPTION

[0022] The specific structural or functional descriptions of the embodiments of the present disclosure introduced in this specification or application are only used to describe the embodiments of the present disclosure, and the descriptions should not be interpreted as being limited to the embodiments described in this specification or application.

[0023] Various embodiments of the present disclosure may relate to a semiconductor memory device capable of reducing a program operation time and a method of operating the semiconductor memory device.

[0024] Figure 1is a block diagram illustrating a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0025] Reference Figure 1 , the semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic 140, a voltage generator 150, and a current sensing circuit 160. The control logic 140 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0026] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz may be coupled to the address decoder 120 via word lines WL. The memory blocks BLK1 to BLKz may be coupled to the read / write circuit 130 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. In embodiments, the memory cells may be nonvolatile memory cells and may be formed from nonvolatile memory cells having a vertical channel structure. The memory cell array 110 may be formed from a memory cell array having a two-dimensional structure. In embodiments, the memory cell array 110 may be formed from a memory cell array having a three-dimensional structure. Each memory cell included in the memory cell array may store at least one bit of data. In embodiments, each memory cell included in the memory cell array 110 may be a single-level cell (SLC) capable of storing one bit of data. In embodiments, each memory cell included in the memory cell array 110 may be a multi-level cell (MLC) capable of storing two bits of data. In embodiments, each memory cell included in the memory cell array 110 may be a triple-level cell (TLC) capable of storing three bits of data. In an embodiment, each memory cell included in the memory cell array 110 may be a quad level cell (QLC) storing 4 bits of data. In various embodiments, the memory cell array 110 may include a plurality of memory cells, each of which may store 5 or more bits of data.

[0027] The address decoder 120 may be coupled to the memory cell array 110 through word lines WL. The address decoder 120 may operate under the control of the control logic 140. The address decoder 120 may receive an address through an input / output buffer (not shown) provided in the semiconductor memory device 100.

[0028] The address decoder 120 may decode a block address from among the received addresses. The address decoder 120 may select at least one memory block based on the decoded block address. In addition, during a program pulse application operation of a program operation, the address decoder 120 may apply a program voltage Vpgm generated from the voltage generator 150 to a selected word line of a selected memory block, and apply a pass voltage Vpass to other unselected word lines. During a program verification operation, the address decoder 120 may apply a verification voltage Vverify generated from the voltage generator 150 to a selected word line of a selected memory block, and apply a pass voltage Vpass to other unselected word lines. During a read voltage application operation of a read operation, the address decoder 120 may apply a read voltage Vread generated from the voltage generator 150 to a selected word line of a selected memory block, and apply a pass voltage Vpass to other unselected word lines.

[0029] The address decoder 120 may decode a column address from among the received addresses and may transmit the decoded column address to the read / write circuit 130 .

[0030] Programming and reading operations of the semiconductor memory device 100 can be performed on a page basis. The address received in a request for a programming or reading operation may include a block address, a row address, and a column address. The address decoder 120 may select a memory block and a word line based on the block address and the row address. The column address may be decoded by the address decoder 120 and provided to the read / write circuit 130. In this specification, memory cells connected to a word line may be designated as a "physical page."

[0031] The read / write circuit 130 includes a plurality of page buffers PB1 to PBm. The read / write circuit 130 can operate as a read circuit during a read operation of the memory cell array 110 and as a write circuit during a write operation. The page buffers PB1 to PBm are coupled to the memory cell array 110 via bit lines BL1 to BLm.

[0032] Each of the page buffers PB1 to PBm may temporarily store data DATA received from an external device and to be programmed during a program operation, and control a potential level of a corresponding one of the bit lines BL1 to BLm based on the temporarily stored data DATA.

[0033] During a program verification operation, page buffers PB1 to PBm can continuously supply a sensing current to a bit line connected to the memory cell in order to sense the threshold voltage of the memory cell. Each page buffer can sense a change in the amount of current flowing through the sensing node according to the program state of the corresponding memory cell and latch the change as sensing data. Page buffers PB1 to PBm can generate a verification data bit QS_BIT using temporarily stored data DATA to be programmed and the latched sensing data.

[0034] The read / write circuit 130 may operate in response to a page buffer control signal output from the control logic 140 .

[0035] The control logic 140 may be coupled to the address decoder 120, the read / write circuit 130, the voltage generator 150, and the current sensing circuit 160. The control logic 140 may receive a command CMD and a control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 may control the overall operation of the semiconductor memory device 100 in response to the control signal CTRL.

[0036] During a programming operation, the control logic 140 may control the peripheral circuits to sequentially program a plurality of memory cells into a plurality of programming states, and control the current sensing circuit 160 to perform a program loop corresponding to one target programming state, and then perform an individual state current sensing operation for the specific target programming state. Furthermore, the control logic 140 may count the number of program loops performed during the programming operation, and when the number of program loops performed is a set count or more, control the current sensing circuit 160 to perform an overall state current sensing operation for the overall target programming state.

[0037] In response to a pass signal PASS or a fail signal FAIL received from the current sensing circuit 160 , the control logic 140 may determine whether a program operation for a specific target program state or an overall target program state passes or fails.

[0038] The control logic 140 according to an embodiment of the present disclosure may control the current sensing circuit 160 and the read / write circuit 130 so that, during a programming operation, a bit line setting operation of the page buffer and an overall state current sensing operation to be performed to determine whether programming operations for all programming states have passed overlap with each other.

[0039] In response to a control signal output from the control logic 140, the voltage generator 150 may generate a program voltage Vpgm and a pass voltage Vpass during a program pulse application operation of a program operation, and generate a verification voltage Vverify and a pass voltage Vpass during a program verification operation of the program operation. In addition, the voltage generator 150 may generate a read voltage Vread and a pass voltage Vpass during a read operation.

[0040] The current sensing circuit 160 may generate a reference current in response to an enable bit VRY_BIT<#> received from the control logic 140 during a current sensing operation, and may generate a reference voltage based on the reference current. The current sensing circuit 160 may generate a verification current based on verification data bits QS_BIT received from the page buffers PB1 to PBm included in the read / write circuit 130, and may generate a verification voltage based on the verification current. The current sensing circuit 160 may compare the reference voltage and the verification voltage and output a pass signal PASS or a fail signal FAIL.

[0041] For example, the current sensing circuit 160 may generate a verification current and a verification voltage using the verification data bit QS_BIT based on the value of the verification data stored in the sub-latch circuit included in each of the page buffers PB1 to PBm during an individual state current sensing operation or an overall state current sensing operation, compare the generated verification voltage with a reference voltage generated based on the reference current, and determine whether the programming operation corresponding to the specific target programming state has passed or the programming operation corresponding to the overall target programming state has passed.

[0042] For example, when the number of memory cells that failed programming among the m memory cells to be programmed to a specific programming state during the individual state current sensing operation is a preset number or less, the current sensing circuit 160 may determine that the programming operation for the specific programming state has passed and output a pass signal PASS. When the number of memory cells that failed programming among the m memory cells to be programmed to a specific programming state during the individual state current sensing operation is greater than a preset number, the current sensing circuit 160 may determine that the programming operation for the specific programming state has failed and output a fail signal FAIL.

[0043] Furthermore, when the number of memory cells that have failed programming among n memory cells to be programmed into a plurality of program states (e.g., among memory cells included in one page) during the overall state current sensing operation is a preset number or less, the current sensing circuit 160 may determine that the program operation for the overall program state has passed and output a pass signal PASS. When the number of memory cells that have failed programming among n memory cells to be programmed into the overall program state during the overall state current sensing operation is greater than a preset number, the current sensing circuit 160 may determine that the program operation for the overall program state has failed and output a fail signal FAIL.

[0044] The address decoder 120, the read / write circuit 130, and the voltage generator 150 may function as a “peripheral circuit” that performs a read operation, a program operation, or an erase operation on the memory cell array 110. The peripheral circuit may perform a read operation, a program operation, or an erase operation on the memory cell array 110 under the control of the control logic 140.

[0045] Figure 2 The embodiment according to the present disclosure is shown Figure 1 FIG. 1 is a diagram of a memory cell array 110 .

[0046] Reference Figure 2 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The memory cells are arranged in the +X direction, the +Y direction, and the +Z direction. Figure 3 and Figure 4 Describes the structure of each storage block.

[0047] Figure 3 The embodiment according to the present disclosure is shown Figure 2 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0048] Reference Figure 3 , the memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in a row direction (ie, +X direction). Figure 3 , two cell strings are shown arranged in the column direction (ie, +Y direction). However, this illustration is made only for convenience of description, and it will be understood that three or more cell strings may be arranged in the column direction.

[0049] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0050] The select transistors SST and DST and the memory cells MC1 to MCn may each have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. In an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0051] The source selection transistors SST of the respective cell strings are coupled between the common source line CSL and the memory cells MC1 to MCp.

[0052] In an embodiment, source selection transistors of cell strings arranged in the same row are coupled to a source selection line extending in a row direction, and source selection transistors of cell strings arranged in different rows are coupled to different source selection lines. Figure 3 , source selection transistors of cell strings CS11 to CS1m in a first row are coupled to a first source selection line SSL1 , and source selection transistors of cell strings CS21 to CS2m in a second row are coupled to a second source selection line SSL2 .

[0053] In an embodiment, source select transistors of cell strings CS11 to CS1m and CS21 to CS2m may be commonly coupled to a single source select line.

[0054] The first to nth memory cells MC1 to MCn in each cell string are coupled between a source select transistor SST and a drain select transistor DST.

[0055] The first to nth memory cells MC1 to MCn can be divided into first to pth memory cells MC1 and p+1th to nth memory cells MCp+1. The first to pth memory cells MCp are arranged sequentially in a direction opposite to the +Z direction and are connected in series between a source select transistor SST and a tube transistor PT. The p+1th to nth memory cells MCp+1 are arranged sequentially in the +Z direction and are connected in series between a tube transistor PT and a drain select transistor DST. The first to pth memory cells MC1 and p+1th to nth memory cells MCn are connected to each other via the tube transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

[0056] Each gate of the tube transistor PT of the cell string is coupled to the pipeline PL.

[0057] The drain select transistors DST of each cell string are connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected in series to drain select lines extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to a first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to a second drain select line DSL2.

[0058] The cell strings arranged in the column direction may be coupled to the bit lines extending in the column direction. Figure 3 , the cell strings CS11 and CS21 in the first column are coupled to the first bit line BL1, and the cell strings CS1m and CS2m in the m-th column are coupled to the m-th bit line BLm.

[0059] Memory cells connected to the same word line in cell strings arranged in a row form a single page. For example, memory cells connected to the first word line WL1 among cell strings CS11 to CS1m in the first row form a single page. Memory cells connected to the first word line WL1 among cell strings CS21 to CS2m in the second row form another single page. When either drain select line DSL1 or DSL2 is selected, the corresponding cell string arranged in a single row can be selected. When either word line WL1 to WLn is selected, the corresponding single page can be selected from the selected cell string.

[0060] In an embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in a row direction may be coupled to the respective even bit lines. Odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in a row direction may be coupled to the respective odd bit lines.

[0061] In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As the number of dummy memory cells increases, the operational reliability of the memory block BLKa may increase, however, the size of the memory block BLKa may increase. As the number of dummy memory cells decreases, the size of the memory block BLKa may decrease, but the operational reliability of the memory block BLKa may decrease.

[0062] To efficiently control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after performing an erase operation on the memory block BLKa, a program operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after a program operation, the dummy memory cells may have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the dummy memory cells.

[0063] Figure 4 The embodiment according to the present disclosure is shown Figure 2 A circuit diagram of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0064] Reference Figure 4 , the memory block BLKb may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' extends in the +Z direction. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source select transistor SST, first to n-th memory cells MC1 to MCn, and at least one drain select transistor DST, which are stacked on a substrate (not shown) provided at a lower portion of the memory block BLK1'.

[0065] The source select transistors SST of each cell string are coupled between a common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are coupled to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row may be coupled to a first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row may be coupled to a second source select line SSL2. In an embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be coupled together to a single source select line.

[0066] The first to nth memory cells MC1 to MCn in each cell string are connected in series between source select transistors SST and drain select transistors DST. Gates of the first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively.

[0067] The drain select transistors DST of each cell string are coupled between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction can be coupled to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' in the first row are coupled to a first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' in the second row can be coupled to a second drain select line DSL2.

[0068] Therefore, in addition to excluding the tube transistor PT from each cell string, Figure 4 The memory block BLKb may have Figure 3 The equivalent circuit of the storage block BLKa is similar.

[0069] In an embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in a row direction may be connected to the respective even bit lines, and odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in a row direction may be connected to the respective odd bit lines.

[0070] In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. As the number of dummy memory cells increases, the operational reliability of the memory block BLKb may increase, however, the size of the memory block BLKb may increase. As the number of dummy memory cells decreases, the size of the memory block BLKb may decrease, but the operational reliability of the memory block BLKb may decrease.

[0071] To efficiently control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. A programming operation may be performed on all or some of the dummy memory cells before or after an erase operation is performed on memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cells may have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the dummy memory cells.

[0072] Figure 5 The embodiment according to the present disclosure is shown Figure 1 1 and 2. A circuit diagram of any one memory block BLKc among the memory blocks BLK1 to BLKz included in the memory cell array 110 of FIG.

[0073] Reference Figure 5 The memory block BLKc may include a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm may be respectively connected to a plurality of bit lines BL1 to BLm. Each of the cell strings CS1 to CSm includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0074] The select transistors SST and DST and the memory cells MC1 to MCn may each have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing a channel layer may be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating layer, the charge storage layer, and the blocking insulating layer may be provided in each cell string.

[0075] The source selection transistors SST of the respective cell strings are coupled between the common source line CSL and the memory cells MC1 to MCn.

[0076] The first to nth memory cells MC1 to MCn in each cell string are coupled between a source select transistor SST and a drain select transistor DST.

[0077] The drain select transistor DST of each cell string is coupled between a corresponding bit line and the memory cells MC1 to MCn.

[0078] Memory cells connected to the same word line may form a single page. Cell strings CS1 to CSm may be selected by selecting a drain select line DSL. When any one of word lines WL1 to WLn is selected, a corresponding single page may be selected from the selected cell string.

[0079] In an embodiment, even and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even-numbered cell strings among cell strings CS1 to CSm may be coupled to the even bit lines, and odd-numbered cell strings may be coupled to the odd bit lines.

[0080] As described above, memory cells connected to one word line can form one physical page. Figure 5 In an embodiment, among memory cells belonging to the memory block BLKc, m memory cells coupled to any one word line of a plurality of word lines WL1 to WLn may form one physical page.

[0081] like Figures 2 to 4As shown, the memory cell array 110 of the semiconductor memory device 100 may have a three-dimensional structure, but as shown in FIG. Figure 5 As shown, the memory cell array 110 may have a two-dimensional structure.

[0082] Figure 6 is used to describe Figure 1 Circuit diagram of the page buffer.

[0083] Figure 1 Each of the page buffers PB1 to PBm may have a similar structure, and for illustration, the page buffer PB1 will be described as a representative example.

[0084] Reference Figure 6 , the page buffer PB1 may include a bit line controller 131 , a bit line discharger 132 , a sense node precharger 133 , a sub latch circuit 134 , and a main latch circuit 135 .

[0085] During a bit line set operation of a programming operation, the bit line controller 131 may control the potential level of the bit line BL1 to a program enable level or a program inhibit level based on the potential of the node QS of the sub-latch circuit 134. In addition, during a sensing operation of a read operation or a verification operation, the bit line controller 131 may control the potential level of the sense node SO based on the amount of current flowing through the bit line BL1 that varies according to the program state of the memory cell coupled to the bit line BL1.

[0086] The bit line controller 131 may include a plurality of NMOS transistors N1 and N3 to N6 and a plurality of PMOS transistors P1 and P2 .

[0087] The NMOS transistor N1 may be coupled between the bit line BL1 and the node ND1 and electrically couple the bit line BL1 and the node ND1 in response to the page buffer select signal PBSEL.

[0088] The NMOS transistor N3 may be coupled between the node ND1 and the common sensing node CSO and electrically couple the node ND1 and the common sensing node CSO in response to a page buffer sensing signal PB_SENSE.

[0089] The PMOS transistor P1 and the PMOS transistor P2 may be coupled in series between the power supply voltage VDD and the sensing node SO, and may be turned on in response to the potential of the node QS of the sub latch circuit 134 and the precharge signal SA_PRECH_N, respectively.

[0090] The NMOS transistor N4 may be coupled between the common sensing node CSO and a node between the PMOS transistors P1 and P2 and supply the power supply voltage VDD supplied through the PMOS transistor P1 to the common sensing node CSO in response to a control signal SA_CSOC.

[0091] The NMOS transistor N5 may be coupled between the sensing node SO and the common sensing node CSO, and electrically couple the sensing node SO and the common sensing node CSO in response to a transmission signal TRANSO.

[0092] The NMOS transistor N6 may be coupled between the common sensing node CSO and the node ND2 of the sub latch circuit 134 and electrically couple the common sensing node CSO and the node ND2 in response to the discharge signal SA_DISCH.

[0093] The operation of the bit line controller 131 during the bit line setting operation will be described below.

[0094] The PMOS transistor P1 can be turned on or off based on the potential of the node QS of the sub-latch circuit 134. The potential of the node QS can be controlled based on the data to be programmed or the verification data sensed after the verification operation. For example, when the data to be programmed is latched to the sub-latch circuit 134 and corresponds to an erased state, or when the verification data corresponding to a program pass condition is latched to the sub-latch circuit 134 as a result of the verification operation, the node QS may have a logic high level, and the PMOS transistor P1 may be turned off in response to the potential of the node QS. On the other hand, when the data to be programmed is latched to the sub-latch circuit 134 and corresponds to any one of a plurality of program states, or when the verification data corresponding to a program fail condition is latched to the sub-latch circuit 134 as a result of the verification operation, the node QS may have a logic low level, and the PMOS transistor P1 may be turned on in response to the potential of the node QS.

[0095] The NMOS transistor N4 may be turned on in response to the control signal SA_CSOC. The NMOS transistor N3 may be turned on in response to the page buffer sense signal PB_SENSE. The NMOS transistor N1 may be turned on in response to the page buffer select signal PBSEL. Therefore, the bit line BL1 may be controlled to a program enable level (e.g., a ground voltage level) or a program disable level (e.g., a power supply voltage level) based on the potential of the node QS of the sub-latch circuit 134.

[0096] The operation of the bit line controller 131 during the sensing operation will be described below.

[0097] The PMOS transistor P1 and the PMOS transistor P2 may precharge the sensing node SO to the level of the power supply voltage VDD in response to the node QS of the sub latch circuit 134 set to a logic low level and the precharge signal SA_PRECH_N having a logic low level.

[0098] The NMOS transistor N4 may be turned on in response to the control signal SA_CSOC. The NMOS transistor N5 may be turned on in response to the transfer signal TRANSO having a logic high level. The common sense node CSO may be precharged to a predetermined level VDD-Vth. The term "predetermined" (e.g., a predetermined level) used herein with respect to a parameter means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0099] Thereafter, an evaluation operation may be performed from the time the precharge signal SA_PRECH_N transitions to a logic high level to the time the transfer signal TRANSO transitions to a logic low level. In response to the precharge signal SA_PRECH_N transitioning to a logic high level, the PMOS transistor P2 may be turned off, and the power supply voltage VDD applied to the sense node SO may be interrupted. The potential levels of the sense node SO and the common sense node CSO may vary depending on the programming state of the memory cell coupled to the bit line BL1. For example, if the threshold voltage of a memory cell is higher than the programmed state of the read voltage or verify voltage to be applied to the word line of the memory cell during a read or verify operation, current does not flow through the bit line BL1. Therefore, the potentials of the common sense node CSO and the sense node SO may remain at the precharge level. On the other hand, if the threshold voltage of a memory cell is lower than the programmed state of the read voltage or verify voltage to be applied to the word line of the memory cell during a read or verify operation, current flows through the bit line BL1. Therefore, the potentials of the common sense node CSO and the sense node SO may decrease from the precharge state to a discharge level (e.g., SA_CSOC-Vth).

[0100] The bit line discharger 132 may be coupled to the node ND1 of the bit line controller 131 and discharge a potential level of the bit line BL1 .

[0101] The bit line discharger 132 may include an NMOS transistor N2 coupled between the node ND1 and a ground voltage VSS. The NMOS transistor N2 may apply the ground voltage VSS to the node ND1 in response to a bit line discharge signal BL_DIS.

[0102] The sense node precharger 133 may be coupled between the sense node SO and the power supply voltage VDD and precharge the sense node SO to a level of the power supply voltage VDD.

[0103] The sense node precharger 133 may include a PMOS transistor P3. The PMOS transistor P3 may apply the power supply voltage VDD to the sense node SO in response to a sense node precharge signal PRECHSO_N.

[0104] The sub latch circuit 134 may include a plurality of NMOS transistors N7 to N11 and inverters IV1 and IV2 .

[0105] Inverters IV1 and IV2 may be coupled in anti-parallel between the node QS and the node QS_N and form a latch.

[0106] NMOS transistors N7 and NMOS transistors N8 may be coupled in series between the sensing node SO and the ground voltage VSS. NMOS transistor N7 may be turned on in response to a transmission signal TRANS. NMOS transistor N8 may be turned on or off according to a potential level of node QS.

[0107] NMOS transistor N9 may be coupled between node QS and node ND3 and electrically couple node QS to node ND3 in response to a reset signal SRST. NMOS transistor N10 may be coupled between node QS_N and node ND3 and electrically couple node QS_N to node ND3 in response to a set signal SSET. NMOS transistor N11 may be coupled between node ND3 and ground voltage VSS and, in response to the potential of sensing node SO, conduct to electrically couple node ND3 to ground voltage VSS. For example, when reset signal SRST having a logic high level is applied to NMOS transistor N9 while sensing node SO is precharged to a high level, node QS and node QS_N may be initialized to a logic low level and a logic high level, respectively. Furthermore, when set signal SSET having a logic high level is applied to NMOS transistor N10 while sensing node SO is precharged to a high level, node QS and node QS_N may be set to a logic high level and a logic low level, respectively.

[0108] During a verification operation of a programming operation, the sub-latch circuit 134 may latch verification data. For example, during a verification operation, if the bit line controller 131 changes the potential level of the sense node SO, the sub-latch circuit 134 may generate verification data based on the potential level of the sense node SO and latch the verification data. For example, if the threshold voltage of the target memory cell connected to the bit line BL1 is lower than the verification voltage, the target memory cell may be turned on so that the potential level of the sense node SO can be discharged. If the threshold voltage of the target memory cell connected to the bit line BL1 is higher than the verification voltage, the target memory cell may be turned off so that the potential level of the sense node SO can be maintained at a precharge level (power supply voltage level). The NMOS transistor N9 may be turned on in response to the reset signal SRST, and the NMOS transistor N11 may be turned off or on based on the potential level of the sense node SO so that the sub-latch circuit 134 can latch the verification data. For example, if the sub-latch circuit 134 latches verification data corresponding to a fail condition as a result of the verification operation, the node QS may have a logic high level. In a case where the sub latch circuit 134 latches verification data corresponding to a pass condition as a result of a verification operation, the node QS may have a logic low level.

[0109] During the current sensing operation following the verification operation, the sub-latch circuit 134 may transmit the latched verification data to the sensing node SO. During the current sensing operation, the verification data transmitted by each of the plurality of page buffers PB1 to PBm to the sensing node SO may be used as Figure 1 The verification data bit QS_BIT is sent to the current sensing circuit 160 .

[0110] The master latch circuit 135 may include a plurality of NMOS transistors N12 to N16 and inverters IV3 and IV4 .

[0111] Inverters IV3 and IV4 may be coupled in anti-parallel between the node QM and the node QM_N and form a latch.

[0112] NMOS transistors N12 and NMOS transistors N13 may be coupled in series between the sensing node SO and the ground voltage VSS. NMOS transistor N12 may be turned on in response to a transmission signal TRANM. NMOS transistor N13 may be turned on or off according to a potential level of node QM.

[0113] NMOS transistor N14 may be coupled between node QM and node ND4. NMOS transistor N14 may be turned on or off in response to reset signal MRST. NMOS transistor N15 may be coupled between node QM_N and node ND4, and electrically couple node QM_N and node ND4 in response to set signal MSET. NMOS transistor N16 may be coupled between node ND4 and ground voltage VSS, and couple node ND4 to ground voltage VSS according to the potential of sense node SO.

[0114] Figure 7 is a graph showing the programming state of a triple level cell.

[0115] Reference Figure 7 A triple-level cell (TLC) may have threshold voltage states corresponding to one erased state E and seven programmed states P1 to P7, respectively. The erased state E and the first to seventh programmed states P1 to P7 may each have a corresponding bit code. Various bit codes may be assigned to the erased state E and the first to seventh programmed states P1 to P7 as needed.

[0116] Threshold voltage states may be divided from one another based on the first to seventh read voltages R1 to R7. In addition, the first to seventh verification voltages VR1 to VR7 may be used to determine whether memory cells corresponding to respective program states have been programmed.

[0117] For example, in order to verify the memory cells corresponding to the second program state P2 among the memory cells included in the selected physical page, the second verification voltage VR2 may be applied to the corresponding word line. Here, Figure 6 The illustrated page buffer PB1 may sense the current of the bit line BL1 to determine whether a target memory cell coupled to the bit line BL1 is in a program incomplete state or a program complete state.

[0118] When the second verification voltage VR2 is applied to the word line and the bit line BL is sensed, if the threshold voltage of the target memory cell is less than the second verification voltage VR2, the node QS of the sub-latch circuit 134 may be maintained at a logic high level. If the threshold voltage of the target memory cell is greater than the second verification voltage VR2, the node QS of the sub-latch circuit 134 may change to a logic low level. During a subsequent programming cycle, a program inhibit voltage is applied to the bit line BL1 coupled to the target memory cell. Therefore, even if a programming pulse is applied to the word line, the threshold voltage of the target memory cell no longer increases.

[0119] The operation of determining whether the program operation of the memory cell to be programmed to the second program state P2 has been completed (ie, the operation of determining whether the program operation has passed or failed) may be performed by Figure 1 The current sensing circuit 160 performs

[0120] exist Figure 1 In the example of FIG. 1 , current sensing circuit 160 can determine whether a programming operation has passed or failed by comparing a reference voltage based on a reference current corresponding to the number of memory cells to be programmed to the second programming state P2 with a verification voltage based on verification data bits QS_BIT, the reference current corresponding to the number of memory cells to be programmed to the second programming state P2 whose threshold voltage is greater than verification voltage VR2. In other words, by comparing the number of memory cells to be programmed to the second programming state P2 that have passed programming with a preset number, current sensing circuit 160 can determine whether a programming operation for the second programming state P2 has passed or failed. The term "preset" as used herein with respect to a parameter (e.g., a preset number) means that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0121] As described above, the current sensing circuit 160 can determine whether a program operation for a specific program state (e.g., P2) has passed or failed. Hereinafter, throughout the specification, the operation of determining whether a program operation for a specific program state among a plurality of program states has passed or failed will be referred to as an "individual state current sensing operation." During the individual state current sensing operation, it is determined whether the program operation for the memory cell to be programmed to the specific program state has been completed.

[0122] On the other hand, the operation of determining whether the verification operation for the overall program states P1 to P7 has passed / failed will be referred to as an "overall state current sensing operation." During the overall state current sensing operation, whether the overall program operation has been completed is determined by comparing a reference voltage corresponding to the total number of memory cells included in the selected physical page with a verification voltage based on a verification data bit QS_BIT, the verification data bit QS_BIT corresponding to the number of program-completed memory cells (including memory cells corresponding to the erased state) among the memory cells included in the selected physical page. In other words, during the overall state current sensing operation, the current sensing circuit 160 can determine whether the program operation for all of the plurality of program states P1 to P7 has passed or failed by comparing a verification voltage determined according to the number of program-passed memory cells among all the memory cells included in the selected physical page with a reference voltage.

[0123] although Figure 7The target programming state of a three-level cell is shown, but this is for illustration only. The plurality of memory cells included in the semiconductor memory device according to the embodiment of the present disclosure may each be a multi-level cell (MLC). Alternatively, the plurality of memory cells included in the semiconductor memory device according to the embodiment of the present disclosure may each be a quad-level cell (QLC).

[0124] Figure 8 is a diagram for describing a program operation based on an individual state current sensing operation and an overall state current sensing operation according to an embodiment of the present disclosure.

[0125] Reference Figure 7 and Figure 8 , shows an example of performing a program operation for the first program state P1 to the seventh program state P7 according to an embodiment of the present disclosure. During the program operation, a plurality of program loops LOOP1 to LOOP16 corresponding to the first program state P1 to the seventh program state P7 may be sequentially performed. For example, program loops LOOP1 to LOOP5 may correspond to the first program state P1, and program loops LOOP6 to LOOP9 may correspond to the second program state P2. Program loops LOOP10 to LOOP12 may correspond to the third program state P3. Program loop LOOP13 may correspond to the sixth program state P6. Program loops LOOP14 to LOOP16 may correspond to the seventh program state P7. Although Figure 8 The program loops corresponding to the fourth program state P4 and the fifth program state P5 are not shown, but not illustrating some program loops is for illustrative purposes only. It is generally preferred that the program loops corresponding to the fourth program state P4 and the fifth program state P5 be set and executed between the program loops LOOP12 and LOOP13. Furthermore, additional program loops may be executed based on the results of the overall state current sensing operation CSC-ALL performed after the program loop LOOP16.

[0126] Each of the plurality of program loops LOOP1 to LOOP16 may include a program pulse applying operation and at least one verification operation. After executing each program loop, an individual state current sensing operation for a program state corresponding to the program loop may be performed.

[0127] This operation will be further described below.

[0128] During a program operation for a first program state P1 having a lowest threshold voltage distribution among a plurality of program states P1 to P7, a program loop LOOP1 may include applying a first program pulse VP1 and performing a verification operation using a verification voltage VR1 corresponding to the first program state P1, followed by performing an individual state current sensing operation corresponding to the first program state P1. When the result of the individual state current sensing operation indicates a failure CSC1-FAIL, a subsequent program loop (e.g., LOOP2) may be performed for the first program state P1. Program loop LOOP2 may include applying a second program pulse VP2 and performing a verification operation using the verification voltage VR1, followed by performing an individual state current sensing operation corresponding to the first program state P1. When the result of the individual state current sensing operation indicates a failure CSC1-FAIL, a subsequent program loop (e.g., LOOP3) may be performed for the first program state P1. Program loop LOOP3 may include applying a third program pulse VP3 and performing a verification operation using the verification voltage VR1, followed by performing an individual state current sensing operation corresponding to the first program state P1. When the result of the individual state current sensing operation indicates a fail CSC1-FAIL, a subsequent program loop (e.g., LOOP4) for the first program state P1 may be executed. Program loop LOOP4 may include performing an operation of applying a fourth program pulse VP4 and a verification operation using a verification voltage VR1 and a verification voltage VR2 corresponding to the second program state P2, followed by performing an individual state current sensing operation corresponding to the first program state P1. When the result of the individual state current sensing operation indicates a fail CSC1-FAIL, a subsequent program loop for the first program state P1 may be executed. Program loop LOOP5 may include performing an operation of applying a fifth program pulse VP5 and a verification operation using verification voltages VR1 and VR2, followed by performing an individual state current sensing operation corresponding to the first program state P1. When the result of the individual state current sensing operation indicates a pass CSC1-PASS, it may be determined that the program operation corresponding to the memory cell to be programmed to the first program state P1 has been completed, and program loops LOOP6 to LOOP9 for subsequent program states (e.g., the second program state P2) may be executed.

[0129] During a program operation for the second program state P2, program loop LOOP6 may include applying a sixth program pulse VP6 and performing a verification operation using a second verification voltage VR2 corresponding to the second program state P2 and a verification voltage VR3 corresponding to the third program state P3, followed by performing an individual state current sensing operation corresponding to the second program state P2. When the result of the individual state current sensing operation indicates a failure CSC2-FAIL, a subsequent program loop for the second program state P2 may be performed. Program loop LOOP7 may include applying a seventh program pulse VP7 and performing a verification operation using verification voltages VR2 and VR3, followed by performing an individual state current sensing operation corresponding to the second program state P2. When the result of the individual state current sensing operation corresponding to the second program state P2 indicates a failure CSC2-FAIL, a subsequent program loop LOOP8 may include applying an eighth program pulse VP8 and performing a verification operation using verification voltages VR2 and VR3, followed by performing an individual state current sensing operation corresponding to the second program state P2. When the result of the individual state current sensing operation corresponding to the second program state P2 indicates a fail CSC2-FAIL, a subsequent program loop LOOP9 may include an operation of applying a ninth program pulse VP9 and a verification operation using verification voltages VR2 and VR3, as well as an individual state current sensing operation corresponding to the second program state P2. When the result of the individual state current sensing operation corresponding to the second program state P2 indicates a pass CSC2-PASS, it can be determined that the program operation corresponding to the memory cell to be programmed to the second program state P2 has been completed, and program loops LOOP10 to LOOP12 for the subsequent program state (e.g., the third program state P3) can be executed.

[0130] During a program operation for the third program state P3, program loop LOOP10 may include applying a tenth program pulse VP10 and performing a verification operation using a third verification voltage VR3, a fourth verification voltage VR4 corresponding to the fourth program state P4, and a verification voltage VR5 corresponding to the fifth program state P5, followed by performing an individual state current sensing operation corresponding to the third program state P3. When the result of the individual state current sensing operation indicates a failure CSC3-FAIL, a subsequent program loop for the third program state P3 may be performed. Program loop LOOP11 may include applying an eleventh program pulse VP11 and performing a verification operation using the verification voltages VR3, the fourth verification voltage VR4, and the verification voltage VR5 corresponding to the fifth program state P5, followed by performing an individual state current sensing operation corresponding to the third program state P3. When the result of the individual state current sensing operation indicates a failure CSC3-FAIL, a subsequent program loop for the third program state P3 may be performed. Program loop LOOP12 may include performing an operation of applying a twelfth program pulse VP12 and a verification operation using a verification voltage VR3, a fourth verification voltage VR4, and a verification voltage VR5 corresponding to the fifth program state P5, followed by performing an individual state current sensing operation corresponding to the third program state P3. When the result of the individual state current sensing operation indicates a pass CSC3-PASS, it may be determined that the program operation corresponding to the memory cell to be programmed to the third program state P3 has been completed, and a program loop for a subsequent program state (e.g., the fourth program state P4) may be performed.

[0131] In the program loop LOOP13 corresponding to the sixth program state P6, an operation of applying a thirteenth program pulse VP13 and a verification operation using a verification voltage VR6 corresponding to the sixth program state P6 and a verification voltage VR7 corresponding to the seventh program state P7 may be performed, and an individual state current sensing operation corresponding to the sixth program state P6 may be performed. When the result of the individual state current sensing operation corresponding to the sixth program state P6 indicates a pass CSC6-PASS, it may be determined that the program operation corresponding to the memory cell to be programmed to the sixth program state P6 has been completed, and program loops LOOP14 to LOOP16 for the subsequent program state (e.g., the seventh program state P7) may be performed.

[0132] Program loop LOOP14 during a program operation for the seventh program state P7 may include performing an operation of applying a fourteenth program pulse VP14 and a verification operation using a verification voltage VR7, followed by performing an individual state current sensing operation corresponding to the seventh program state P7. When the result of the individual state current sensing operation indicates a failure CSC7-FAIL, a subsequent program loop for the seventh program state P7 may be performed. Program loop LOOP15 may include performing an operation of applying a fifteenth program pulse VP15 and a verification operation using a verification voltage VR7, followed by performing an individual state current sensing operation corresponding to the seventh program state P7. When the result of the individual state current sensing operation indicates a failure CSC7-FAIL, a subsequent program loop for the seventh program state P7 may be performed. Program loop LOOP16 may include performing an operation of applying a sixteenth program pulse VP16 and a verification operation using a verification voltage VR7, followed by performing an individual state current sensing operation corresponding to the seventh program state P7.

[0133] During a program operation including a plurality of program loops LOOP1 to LOOP16, a global state current sensing operation CSC-ALL may be performed from a set program loop (e.g., LOOP13). For example, after program loop LOOP13 has been executed, an individual state current sensing operation corresponding to the sixth program state P6 is performed, and a global state current sensing operation CSC-ALL may be performed to determine whether the program operation for the global program states P1 to P7 has been completed. The global state current sensing operation CSC-ALL may be performed after each program loop from subsequent program loop LOOP14 to the final program loop is executed.

[0134] Figure 9 and Figure 10 is a flowchart for describing a programming operation and an individual state current sensing operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0135] Will refer to Figure 1 、 Figures 6 to 10 The operation of the semiconductor memory device according to the embodiment of the present disclosure is described.

[0136] In an embodiment of the present disclosure, an example will be described in which each of a plurality of memory cells is programmed into a plurality of program states P1 to P7 , and respective program operations for the plurality of program states P1 to P7 are sequentially performed.

[0137] In step S1010, a programming pulse may be applied to a selected word line to perform a programming operation to increase the threshold voltage of a memory cell connected to a bit line to which a programming enable voltage is applied. For example, each of the page buffers PB1 to PBm of the read / write circuit 130 may temporarily store data DATA received from an external device and to be programmed, and control a potential level of a corresponding one of the bit lines BL1 to BLm based on the temporarily stored data DATA. The voltage generator 150 may generate a programming voltage Vpgm and a pass voltage Vpass. The programming voltage Vpgm may be Figure 8 The address decoder 120 may apply a program voltage Vpgm to a selected word line and a pass voltage Vpass to unselected word lines. The first program pulse VP1 may be a start program pulse of incremental step pulse programming (ISPP).

[0138] In step S1020, the voltage generator 150 may generate a verification voltage Vverify and a pass voltage Vpass. The verification voltage Vverify may be Figure 8 The address decoder 120 may apply a verification voltage Vverify to the selected word line and a pass voltage Vpass to the unselected word lines. Each of the plurality of page buffers PB1 to PBm of the read / write circuit 130 may perform a verification operation based on the amount of current flowing through a corresponding one of the bit lines BL1 to BLm. Each of the plurality of page buffers PB1 to PBm may store the result of the verification operation as verification data in the sub-latch circuit 134 and control the corresponding bit line using a program inhibit voltage or a program enable voltage based on the verification data during a bit line set operation period. For example, based on the verification data stored in the sub-latch circuit 134, when it is determined that the programming operation for the memory cell connected to the corresponding bit line has been completed, the bit line controller 131 may apply a program inhibit voltage to the corresponding bit line, and when it is determined that the programming operation for the memory cell connected to the corresponding bit line has not been completed, the bit line controller 131 may apply a program enable voltage to the corresponding bit line.

[0139] At step S1030, the current sensing circuit 160 may perform an individual state current sensing operation for the first program state. For example, the current sensing circuit 160 may generate a verification current and a verification voltage based on the value of the verification data stored in the sub-latch circuit 134 of each page buffer among the page buffers PB1 to PBm that temporarily stores data corresponding to the first program state and to be programmed, using the verification data bit QS_BIT, and determine whether the program operation corresponding to the first program state P1 passes or fails by comparing the generated verification voltage with a reference voltage generated by a reference current, and generate and output a pass signal PASS or a fail signal FAIL.

[0140] When latching the verification data corresponding to the program pass condition, the page buffers PB1 to PBm, which temporarily store data corresponding to the first program state and to be programmed, may continue to maintain the same verification data in subsequent program loops.

[0141] In step S1040 , the control logic 140 may receive a pass signal PASS or a fail signal FAIL from the current sensing circuit 160 and determine whether a program operation corresponding to the first program state P1 passes or fails.

[0142] When the control logic 140 determines that the program operation corresponding to the first program state P1 has failed (FAIL), the control logic 140 may set a program pulse to be used in a subsequent program loop at step S1050. For example, the control logic 140 may set a new program pulse with a step voltage increased compared to the program pulse used in the previous program loop as the program pulse to be used in the subsequent program loop. Thereafter, the process may be re-executed from step S1010.

[0143] When the control logic 140 determines that the programming operation corresponding to the first programming state P1 has passed (PASS), in step S1060, the control logic 140 may set a programming pulse to be used in a programming loop corresponding to a subsequent programming state (e.g., P2) and a verification voltage corresponding to the subsequent programming state (e.g., P2).

[0144] At step S1070, the threshold voltage of the memory cell connected to the bit line to which the program enable voltage is applied may be increased by applying a newly set program pulse to the selected word line. The voltage generator 150 may generate the newly set program pulse and the pass voltage Vpass. The address decoder 120 may apply the program pulse generated by the voltage generator 150 to the selected word line and apply the pass voltage Vpass to the unselected word lines.

[0145] In step S1080, voltage generator 150 may generate at least one newly set verification voltage and pass voltage Vpass. Address decoder 120 may apply verification voltage Vverify to the selected word line and pass voltage Vpass to unselected word lines. Each of the plurality of page buffers PB1 to PBm of read / write circuit 130 may perform a verification operation based on the amount of current flowing through a corresponding one of bit lines BL1 to BLm. Each of the plurality of page buffers PB1 to PBm may store the result of the verification operation as verification data in sub-latch circuit 134 and control the corresponding bit line using a program inhibit voltage or a program enable voltage based on the verification data during a bit line set operation period. For example, based on the verification data stored in sub-latch circuit 134, bit line controller 131 may apply a program inhibit voltage to the corresponding bit line when determining that the programming operation for the memory cells connected to the corresponding bit line has been completed. If the programming operation for the memory cells connected to the corresponding bit line has not been completed, bit line controller 131 may apply a program enable voltage to the corresponding bit line.

[0146] When latching the verification data corresponding to the program pass condition, the page buffers PB1 to PBm, which temporarily store data corresponding to a subsequent program state and to be programmed, may continue to maintain the same verification data in a subsequent program loop.

[0147] At step S1090, the current sensing circuit 160 may perform an individual state current sensing operation for a subsequent programming state (e.g., P2). For example, the current sensing circuit 160 may generate a verification current and a verification voltage based on the value of the verification data stored in the sub-latch circuit 134 of each page buffer among the page buffers PB1 to PBm that temporarily stores data corresponding to the subsequent programming state and to be programmed, using the verification data bit QS_BIT, and determine whether the program operation corresponding to the subsequent programming state (e.g., P2) passes or fails by comparing the generated verification voltage with a reference voltage generated by a reference current, and then generate and output a pass signal PASS or a fail signal FAIL.

[0148] At step S1100 , the control logic 140 may receive a pass signal PASS or a fail signal FAIL from the current sensing circuit 160 and determine whether a program operation corresponding to a subsequent program state (eg, P2 ) passes or fails.

[0149] When the control logic 140 determines that the program operation corresponding to the subsequent program state (e.g., P2) has failed (FAIL), the control logic 140 may set a program pulse to be used in the subsequent program loop at step S1110. For example, the control logic 140 may set a new program pulse with a step voltage increased compared to the program pulse used in the previous program loop as the program pulse to be used in the subsequent program loop. Thereafter, the process may be re-executed from step S1070.

[0150] When the control logic 140 determines that the program operation corresponding to the subsequent program state (e.g., P2) has passed (PASS), the control logic 140 may check in step S1120 whether the individual state current sensing operation performed from step S1090 to the current step is the individual state current sensing operation for the last program state (e.g., P7). For example, if it is determined that the individual state current sensing operation for the last program state (e.g., P7) has not been performed in the current step (designated by "No"), the process may be re-executed from the above-described step S1060. For example, if it is determined that the individual state current sensing operation for the last program state (e.g., P7) has been performed in the current step (designated by "Yes"), the process may be terminated.

[0151] Figure 11 Is used to describe the Figure 9 and Figure 10 A flowchart of an overall state current sensing operation of a programming operation of a semiconductor memory device according to an embodiment of the present invention.

[0152] The following will refer to Figure 11 An overall state current sensing operation of a semiconductor memory device is described.

[0153] In step S1210, the number of times the program loop has been executed may be checked. Figure 1 The control logic 140 counts the programming loops.

[0154] In step S1220, it may be determined whether the number of times the program loop has been performed is a set count or more.

[0155] In the above step S1220, if the number of times the program loop has been performed is less than the set count, a subsequent program loop may be performed in step S1230, and the process may be re-performed from the above step S1210.

[0156] In step S1220, if the number of program loops executed is equal to or greater than the set count, a global current sensing operation may be performed in step S1240. For example, the sub-latch circuit 134 of each of the page buffers PB1 to PBm may continuously latch verification data corresponding to one of the plurality of program states P1 to P7. The current sensing circuit 160 may generate a verification current and a verification voltage using the verification data bit QS_BIT based on the value of the verification data stored in the sub-latch circuit 134 included in each of the page buffers PB1 to PBm, and determine whether the program operation corresponding to the global target program state P1 to P7 has passed by comparing the generated verification voltage with a reference voltage generated by a reference current. For example, when the number of memory cells that failed programming among n memory cells to be programmed to the plurality of program states (e.g., among the memory cells included in a page) during the global current sensing operation is a preset number or less, the current sensing circuit 160 may determine that the program operation for the global program state has passed and output a pass signal PASS. When the number of memory cells that have failed programming among n memory cells to be programmed to the overall programming state is greater than a preset number during the overall state current sensing operation, the current sensing circuit 160 may determine that the programming operation for the overall programming state has failed and output a fail signal FAIL.

[0157] In step S1250, the control logic 140 may receive a pass signal PASS or a fail signal FAIL from the current sensing circuit 160 and determine whether the program operation corresponding to the overall program state has passed or failed. For example, when a fail signal FAIL (designated by "FAIL") is received from the current sensing circuit 160, the process may be re-executed from the above-described step S1230. In an embodiment, when the result of the overall state current sensing operation indicates that the program operation has failed, the control logic controls the peripheral circuit to perform a new program loop including a bit line setting operation, a program pulse application operation, and a verification operation on the selected memory cell. When the pass signal PASS is received from the current sensing circuit 160, the program operation may be terminated.

[0158] In an embodiment of the present disclosure, at step S1240, before a program pulse is applied to a selected word line, the operation period of the overall state current sensing operation of the current sensing circuit 160 may overlap with the operation period of the bit line setting operation of the page buffers PB1 to PBm storing verification data corresponding to a program failure. This will be described in reference to Figure 12 This is further described in the following description.

[0159] Figure 12 is a diagram for describing the overlap of operation times of a bit line setting operation and an entire current sensing operation.

[0160] Reference Figure 8 and Figures 10 to 12 To program memory cells to the seventh program state P7 in program loop LOOP14, each of page buffers PB1 to PBm may perform a bit line set operation of applying a program inhibit voltage or a program enable voltage to a corresponding bit line, and a program pulse application operation of applying a set program pulse. Thereafter, a verification operation using a verification voltage VR7 corresponding to the seventh program state may be performed.

[0161] Subsequently, at step S1090, an individual state current sensing operation CSC7 corresponding to the seventh program state P7 may be performed. An operation period of the individual state current sensing operation CSC7 may partially overlap with an operation period of the verification operation.

[0162] If the individual state current sensing operations are completed, an overall state current sensing operation CSC-ALL may be performed at step S1240 .

[0163] During the period in which the overall state current sensing operation CSC-ALL is being performed, the control logic 140 may control the page buffers PB1 to PBm of the read / write circuit 130 to thereby perform a bit line set operation corresponding to a subsequent programming loop LOOP15 (i.e., a new programming loop). Programming loop LOOP15 may be an additional programming operation. For example, in programming loop LOOP15, each of the page buffers PB1 to PBm may perform a bit line set operation in which a program inhibit voltage or a program enable voltage is applied to a corresponding bit line based on the verification data stored in the sub-latch circuit 134. Here, the operation period of the bit line set operation and the operation period of the overall state current sensing operation CSC-ALL of the current sensing circuit 160 may partially or entirely overlap with each other. In an embodiment, for example, if the bit line set operation occurs within a first time interval and the overall state current sensing operation CSC-ALL occurs within a second time interval, the first interval and the second interval at least partially overlap with each other, such that there is a time when both the bit line set operation and the overall state current sensing operation CSC-ALL occur.

[0164] Subsequently, the control logic 140 may control the peripheral circuits to apply a program voltage to the selected word line and then perform a verify operation on the corresponding memory cell. Thereafter, the current sensing circuit 160 may perform a global current sensing operation CSC-ALL. While performing the global current sensing operation CSC-ALL, the control logic 140 may control the page buffers PB1 to PBm of the read / write circuit 130 to perform a bit line set operation corresponding to the subsequent program loop LOOP16. Program loop LOOP16 may be an additional programming operation.

[0165] In the embodiment of the present disclosure, as described above, after the last individual state current sensing operation has been performed, the operation period of the overall state current sensing operation and a portion or the entire period of the bit line setting operation can overlap with each other. Thus, the program operation time of the semiconductor memory device can be reduced.

[0166] Figure 13 It is shown that Figure 1 A block diagram of an embodiment of a memory system of a semiconductor memory device.

[0167] Reference Figure 13 , the memory system 1000 may include a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 may be a reference Figure 1 Hereinafter, repeated description will be omitted.

[0168] The controller 1100 is coupled to the host and the semiconductor memory device 100. The controller 1100 may access the semiconductor memory device 100 in response to a request from the host. For example, the controller 1100 may control read operations, write operations, erase operations, and background operations of the semiconductor memory device 100. The controller 1100 may provide an interface between the semiconductor memory device 100 and the host. The controller 1100 may drive firmware for controlling the semiconductor memory device 100.

[0169] The controller 1100 may include a random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 may be used as at least one of an operating memory for the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 may control the overall operation of the controller 1100. In addition, the controller 1100 may temporarily store program data provided from the host during a programming operation.

[0170] The host interface 1130 may include a protocol for performing data exchange between the host and the controller 1100. In an embodiment, the controller 1100 may communicate with the host through at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a MultiMediaCard (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Mini Interface (SCSI) protocol, an Enhanced MiniDisk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a proprietary protocol.

[0171] The memory interface 1140 may interface with the semiconductor memory device 100. For example, the memory interface may include a NAND interface or a NOR interface.

[0172] The error correction block 1150 may use an error correction code (ECC) to detect and correct errors in data received from the semiconductor memory device 100. The processing unit 1120 may control the semiconductor memory device 100 to adjust a read voltage and perform a reread according to an error detection result from the error correction block 1150. In an embodiment, the error correction block 1250 may be provided as a component of the controller 1100.

[0173] The controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device. In an embodiment, the controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device and form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), and a Universal Flash Storage (UFS).

[0174] The controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a solid-state drive (SSD). An SSD may include a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of a host connected to the memory system 2000 may be significantly improved.

[0175] In an embodiment, the memory system 1000 may be provided as one of various elements of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a device capable of sending / receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming an information communication network, an RFID device, one of various elements for forming a computing system, etc.

[0176] In embodiments, the semiconductor memory device 100 or the memory system 1000 may be embedded in various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 may be packaged in a package-on-package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic chip carrier with leads (PLCC), a plastic dual in-line package (PDIP), a waffle chip package, a wafer-form chip, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi-chip package (MCP), a wafer-level fabrication package (WFP), or a wafer-level processing stacked package (WSP).

[0177] Figure 14 It shows Figure 13 A block diagram of an example of an application of a memory system.

[0178] Reference Figure 14 , the memory system 2000 may include a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 may include a plurality of semiconductor memory chips. These semiconductor memory chips are divided into a plurality of groups.

[0179] exist Figure 14 , it is shown that each group communicates with the controller 2200 through the first channel CH1 to the kth channel CHk. Each semiconductor memory chip can be connected in the same manner as in the reference Figure 1 The semiconductor memory device 100 is configured and operates in the same manner as described above.

[0180] Each group can communicate with the controller 2200 through a common channel. The controller 2200 may have a common channel with the reference Figure 14 The controller 1100 described above has the same configuration as that of FIG. 1 , and controls a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

[0181] Figure 15 It is shown including reference Figure 14 A block diagram of a computing system with a memory system is shown.

[0182] The computing system 3000 may include a central processing unit (CPU) 3100 , a RAM 3200 , a user interface 3300 , a power supply 3400 , a system bus 3500 , and a memory system 2000 .

[0183] The memory system 2000 may be electrically coupled to the CPU 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or data processed by the CPU 3100 may be stored in the memory system 2000.

[0184] exist Figure 15 , the semiconductor memory device 2100 is shown as being coupled to the system bus 3500 through the controller 2200. Alternatively, the semiconductor memory device 2100 may be directly coupled to the system bus 3500. The functions of the controller 2200 may be performed by the CPU 3100 and the RAM 3200.

[0185] exist Figure 15 In the example, reference is made to Figure 14 In an embodiment, the memory system 2000 may be configured as follows: Figure 13 In an embodiment, the computing system 3000 may include a memory system 1000 described in the embodiment of the present invention. Figure 14 and Figure 13 Memory systems 1000 and 2000 are described in their entirety.

[0186] In various embodiments of the present disclosure, during a program operation of a semiconductor memory device, an operation period of a bit line set operation and an operation period of a program verification operation may overlap with each other, so that a program operation time may be reduced.

[0187] Examples of embodiments are disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to those skilled in the art that, upon submission of this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

[0188] CROSS-REFERENCE TO RELATED APPLICATIONS

[0189] This application claims the benefit of Korean Patent Application No. 10-2020-0094761, filed on July 29, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor memory device, comprising: a memory cell array comprising a plurality of memory cells to be programmed into a plurality of programmed states; a peripheral circuit configured to perform a program operation on a selected memory cell among the plurality of memory cells, wherein the programming operation includes a plurality of programming loops, and each of the plurality of programming loops includes a bit line setting operation, a programming pulse applying operation, and a verification operation; a current sensing circuit configured to perform individual state current sensing operations and an overall state current sensing operation on the selected memory cell among the plurality of memory cells and determine a result of the programming operation for each of the plurality of program states, wherein, when the number of times the program loop has been executed is a set count or more, the current sensing circuit performs the overall state current sensing operation; and Control logic is configured to control the peripheral circuit and the current sensing circuit so that an operation period of the overall state current sensing operation at least partially overlaps an operation period of the bit line setting operation of a subsequent programming loop.

2. The semiconductor memory device according to claim 1, wherein The peripheral circuit includes a read / write circuit configured to apply at least one of a program inhibit voltage and a program enable voltage to a bit line of the memory cell array according to data to be programmed during the bit line set operation of the program operation.

3. The semiconductor memory device according to claim 2, wherein The read / write circuit latches verification data corresponding to the selected memory cell during the verification operation and applies at least one of the program inhibition voltage and the program enable voltage to the bit line based on the verification data during the bit line setting operation performed after the verification operation.

4. The semiconductor memory device according to claim 3, wherein The read / write circuit generates a verify data bit based on the verify data latched after the verify operation.

5. The semiconductor memory device according to claim 4, wherein The current sensing circuit performs the individual state current sensing operation based on the verify data bits after the verify operation of each of the plurality of programming loops.

6. The semiconductor memory device according to claim 5, wherein During the individual state current sensing operation, when the number of memory cells in which programming has failed among a plurality of memory cells to be programmed to any one of the plurality of programming states is a first set number or less, the current sensing circuit determines that the programming operation for the any one programming state has passed, and when the number of memory cells in which programming has failed is greater than the first set number, the current sensing circuit determines that the programming operation for the any one programming state has failed.

7. The semiconductor memory device according to claim 4, wherein During the overall state current sensing operation, when the number of memory cells in which programming has failed among the selected memory cells is a second set number or less, the current sensing circuit determines that the programming operation on the selected memory cells has passed, and when the number of memory cells in which programming has failed is greater than the second set number, the current sensing circuit determines that the programming operation on the selected memory cells has failed.

8. The semiconductor memory device according to claim 7, wherein When a result of the overall state current sensing operation indicates that the program operation has failed, the control logic controls the peripheral circuit to perform a new program loop including the bit line setting operation, the program pulse applying operation, and the verifying operation on the selected memory cell.

9. The semiconductor memory device according to claim 8, wherein The control logic controls the peripheral circuit and the current sensing circuit to overlap an operation period of the overall state current sensing operation with an operation period of the bit line setting operation of the new program loop.

10. The semiconductor memory device according to claim 9, wherein After executing the new programming loop, the current sensing circuit re-performs the overall state current sensing operation.

11. A method of operating a semiconductor memory device, the method comprising the steps of: performing a first programming operation corresponding to a first programming state among a plurality of programming states; performing a first bulk state current sensing operation corresponding to the first programming operation, and determining whether the first programming operation has passed; performing a second programming operation corresponding to a second programming state having a higher threshold voltage distribution than that of the first programming state based on a result of the first individual state current sensing operation; performing a second body state current sensing operation corresponding to the second programming operation, and determining whether the second programming operation has passed; performing overall status current sensing operations; as well as When a result of the overall state current sensing operation indicates a failure, performing an additional programming operation and then re-performing a process from the overall state current sensing operation, wherein each of the first program operation, the second program operation, and the additional program operation includes a bit line setting operation, a program pulse applying operation, and a verification operation, wherein an operation period of the overall state current sensing operation and an operation period of the bit line setting operation of the additional programming operation at least partially overlap with each other.

12. The method according to claim 11, wherein An operation period of the overall state current sensing operation and an operation period of the additional programming operation overlap with each other.

13. The method according to claim 11, wherein During the first individual state current sensing operation, when the number of memory cells that have failed programming among the multiple memory cells to be programmed to the first programming state is a first set number or less, the first programming operation is determined to have passed, and when the number of memory cells that have failed programming is greater than the first set number, the first programming operation is determined to have failed.

14. The method according to claim 11, wherein During the second individual state current sensing operation, when the number of memory cells in which programming has failed among the plurality of memory cells to be programmed to the second programming state is a second set number or less, the second programming operation is determined to have passed, and when the number of memory cells in which programming has failed is greater than the second set number, the second programming operation is determined to have failed.

15. The method according to claim 11, wherein During the overall state current sensing operation, when the number of memory cells in which programming has failed among all the memory cells to be programmed to the first programming state and the second programming state is a third set number or less, the programming operation on the all memory cells is determined to have passed, and when the number of memory cells in which programming has failed is greater than the third set number, the programming operation on the all memory cells is determined to have failed.

16. The method according to claim 11, wherein The overall state current sensing operation is performed when program loops each including the bit line setting operation, the program pulse applying operation, and the verifying operation have been performed a set count or more.

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