Implementation of a Memory Built-in Self-Test System and Method for Fast Testing

Abstract

The present invention relates to a memory built-in self-test system capable of rapid testing, including a test control circuit module that receives an external test enable signal bist_en and is used to control the operation of the test circuit; a test vector selection circuit module that is used to select one or more test vectors for testing according to a test vector selection signal pattern_sel; a test vector generation circuit module that is used to generate test vectors; and a response analysis circuit module that is used to compare the values read from the memory with the test vectors. The present invention also relates to a method for realizing a memory built-in self-test capable of rapid testing. By adopting the memory built-in self-test system and method capable of rapid testing of the present invention, it is also applicable to other memories and algorithms. One or more different test vectors are selected according to specific memory faults, and different test vectors can be selected for different memory faults, which is applicable to different memories and algorithms.

Description

Technical Field

[0001] The present invention relates to the field of information technology, and particularly to the field of test circuit design, and specifically refers to a memory built-in self-test system and method that can achieve rapid testing. Background Art

[0002] With the development of information technology, IC design has become increasingly complex, and embedded memories also occupy an increasing area in SoC chips. Due to their high unit density, embedded memories are prone to causing silicon wafer defects and reducing the chip yield. Therefore, it is becoming increasingly important to achieve rapid and effective memory testing.

[0003] Currently, memory built-in self-test (MBIST) is an important and cost-effective technology for testing embedded memories. MBIST usually adopts one or more algorithms specially designed for testing the defect types of memories. For traditional testing methods, if the bit width of the memory is N, then X sets of test vectors are required, where X = log 2 N + 1. The following takes the example of a 2K×32bit SRAM tested by the March C-algorithm for introduction.

[0004] The March C-algorithm is an algorithm with complete test functions, and the memory faults it covers include stuck-at fault SAF, transition fault TF, coupling fault CF, and address decoding fault AF. The expression of the March C-algorithm is as follows:

[0005] {↑(W0); ↑(R0, W1); ↑(R1, W0); ↓(R0, W1); ↓(R1, W0); ↓(R0)}

[0006] Among them, ↑ and ↓ respectively represent reading and writing operations on address units in ascending and descending order of memory addresses. R0 represents reading 0 from the storage unit, W0 represents writing 0 to the storage unit, similarly R1 represents reading 1, and W1 represents writing 1. Only after all the operations specified for the current storage unit are completed can the operation on the next storage unit be continued. One set of test vectors needs to complete 6 stages (traversing the address 6 times) of the above algorithm before the next set of test vectors can be carried out. For a 2K×32bit SRAM, its test vectors are altogether 6 sets, which are respectively:

[0007]

[0008] That is to say, the algorithm needs to be executed 6 times (traversing the address 36 times) for the test to be completed.

[0009] Nowadays, the processes for manufacturing memories are already relatively mature. A mature process usually only produces one or several identical memory defects, while some defects have never appeared before. At this time, if all test vectors are still used for testing, a lot of useless work will be done, wasting test time. Therefore, it is necessary to select one or several test vectors for this specific defect to achieve fast and effective testing.

[0010] MBIST designs the test circuit inside the chip. All test processes are carried out inside the chip, and only excitation signals need to be applied externally and test results need to be observed. Generally, the built-in self-test circuit for memories usually includes three parts: a test vector generation circuit, a test control circuit, and a response analysis circuit. The function of the test vector generation circuit is to generate test vectors. The number and value of the test vectors are determined by the bit width of the memory under test. The larger the bit width, the more test vectors there are. The function of the test control circuit is to control the operation of the entire test circuit, including controlling the ascending and descending order of addresses and the reading and writing of the memory. The function of the response analysis circuit is to compare the values read from the memory with the test vectors and obtain the result of whether the test is successful. As Figure 1 shown, as long as an external test enable signal bist_en is given, the test circuit can perform self-testing and finally give a test completion signal bist_done and a test success signal bist_ok.

[0011] Taking a 2K×32bit SRAM as an example, its test vector generation circuit will generate a total of 6 groups of test vectors. Each test requires these 6 groups of test vectors to be tested, and 36 addresses need to be traversed. For known memory faults that will not occur, using the test vectors covering them for testing will become very inefficient and waste test costs. Summary of the Invention

[0012] The object of the present invention is to overcome the above-mentioned disadvantages of the prior art and provide a built-in self-test system and method for memories that can achieve fast testing, which meet the requirements of short test time, low test cost, and relatively wide application range.

[0013] In order to achieve the above object, the built-in self-test system and method for memories that can achieve fast testing of the present invention are as follows:

[0014] The built-in self-test system for memories that can achieve fast testing mainly has the following characteristics: the system includes:

[0015] A test control circuit module, which receives an external test enable signal bist_en, and its output terminals are respectively connected to a test vector selection circuit module and a circuit under test, and is used to control the operation of the test circuit;

[0016] The test vector selection circuit module receives the test vector selection signal pattern_sel. Its receiving end is connected to the output end of the test control circuit module and is used to select one or more test vectors for testing according to the test vector selection signal pattern_sel.

[0017] The test vector generation circuit module has its receiving end connected to the output end of the test vector selection circuit module and its output end connected to the circuit under test, and is used to generate test vectors.

[0018] The response analysis circuit module has its input end connected to the test vector selection circuit module and the circuit under test, and is used to compare the value read from the memory with the test vector and output the test completion signal bist_done and the test success signal bist_ok.

[0019] Preferably, the test vector selection circuit module includes:

[0020] The test vector selection signal temporary storage unit is connected to the test control circuit module, receives the test vector selection signal pattern_sel configured by the user and the one-time algorithm completion signal fsm_complete output by the test control circuit module, and outputs the temporary storage intermediate value psel_temp.

[0021] The test vector encoding signal generation unit has its receiving end connected to the test vector selection signal temporary storage unit and its output end connected to the test vector generation circuit module, receives the test vector selection signal pattern_sel configured by the user, outputs the test vector encoding signal pattern_id, and the vector test completion signal pattern_complete is used to generate the test vector signal bist_pattern.

[0022] Preferably, the test vector selection circuit module further includes:

[0023] The NOR operation unit has its receiving end connected to the test vector selection signal temporary storage unit and its output end connected to the response analysis circuit module, and outputs the all-vector test completion signal pattern_complete, which is used to generate the test completion signal bist_done.

[0024] Preferably, the test vector selection signal temporary storage unit includes X groups of output sub-units. The X groups of output sub-units are connected in sequence and are used to test the test vectors in order of operation priority. Each group of output sub-units corresponds to the number of bits of the temporary storage intermediate value psel_temp in sequence. When the nth output sub-unit finishes testing, the value of psel_temp[n - 1] is output as 0, where n is greater than or equal to 1 and less than or equal to X.

[0025] Preferably, the test vector selection signal storage unit includes six D flip - flops, five AND gates, and five NOT gates. The D terminals of the six D flip - flops all receive the test vector selection signal pattern_sel, the clock terminals are all connected to the same clock signal, and the Q terminals all output the temporarily stored intermediate value psel_temp. The five AND gates and five NOT gates form five NAND gates, and the six D flip - flops are connected through the five NAND gates.

[0026] Preferably, the test vector encoding signal generation unit includes X groups of encoding sub - units, which are connected in sequence and are used to calculate and output the test vector encoding signal pattern_id according to the operation priority based on the temporarily stored intermediate value in sequence. Each group of encoding sub - units sequentially determines whether the number of bits of the temporarily stored intermediate value psel_temp is valid. When the value of psel_temp[m] is 1, the corresponding test vector encoding signal pattern_id is output.

[0027] Preferably, the test vector encoding signal generation unit includes a D flip - flop, seven two - to - one multiplexers, four OR gates, five AND gates, and five NOT gates. The seven two - to - one multiplexers are connected in sequence. The two - to - one multiplexer with the highest priority is connected to the D terminal of the D flip - flop. The five AND gates and five NOT gates form five NAND gates. The five two - to - one multiplexers with lower priority are connected to the output terminals of the five NAND gates. The output terminals of the four OR gates are respectively connected to the input terminals of the NAND gates of the four two - to - one multiplexers with lower priority. The NAND gates and OR gates all input the temporarily stored intermediate value psel_temp. The two - to - one multiplexer with the highest priority receives the test enable signal bist_en, and the Q terminal of the D flip - flop outputs the test vector encoding signal pattern_id.

[0028] Preferably, the test control circuit module controls the ascending and descending order of the address and the reading and writing of the memory.

[0029] Preferably, the bit width of the test vector selection signal pattern_sel is X bits, and each bit width corresponds to a group of test vectors.

[0030] The method for implementing a memory built - in self - test that can be quickly tested using the above system mainly includes the following steps:

[0031] (1) Input the test vector selection signal pattern_sel;

[0032] (2) Assign the temporary intermediate value psel_temp equal to the test vector selection signal pattern_sel. The initial value of the test vector encoding signal pattern_id is 0, and the initial value of the internal signal n is 0;

[0033] (3) Calculate pattern_complete = ~(|psel_temp), output pattern_complete, and determine whether pattern_complete is 1. If it is, continue to step (5); otherwise, continue to step (4);

[0034] (4) Test this group of test vectors;

[0035] (5) Output the all-vector test completion signal pattern_complete = 1.

[0036] Preferably, step (4) described above specifically includes the following steps:

[0037] (4.1) Output the all-vector test completion signal pattern_complete = 0;

[0038] (4.2) Input the algorithm completion signal fsm_complete once;

[0039] (4.3) Determine whether the algorithm completion signal fsm_complete is equal to 1. If it is, continue to step (4.6); otherwise, continue to step (4.4);

[0040] (4.4) Determine whether the temporary intermediate value psel_temp[n] is equal to 1. If it is, continue to step (4.5); otherwise, increment the value of n by 1 and continue to step (4.4);

[0041] (4.5) Assign pattern_id as n + 1, output the test vector encoding signal pattern_id at this moment, and continue to step (4.2);

[0042] (4.6) Assign psel_temp[n] as 0, n as n + 1, the test of this group of test vectors is completed, and continue to step (3).

[0043] The implementation of the built-in self-test system and method for a memory that can perform fast testing according to the present invention is also applicable to other memories and algorithms. One or more different test vectors are selected according to specific memory faults. Different memory faults can select different test vectors, which are applicable to different memories and algorithms. The present invention can select test vectors according to memory faults, has a short test time, low test cost, and a wide application range. Description of the Drawings

[0044] Figure 1 It is a block diagram of a memory built-in self-test circuit structure of the prior art.

[0045] Figure 2 It is a block diagram of a memory built-in self-test system that can achieve fast testing according to the present invention.

[0046] Figure 3 It is a block diagram of a test vector selection circuit of a memory built-in self-test system that can achieve fast testing according to the present invention.

[0047] Figure 4 It is a schematic circuit diagram of a test vector selection signal storage unit of a memory built-in self-test system that can achieve fast testing according to the present invention.

[0048] Figure 5 It is a schematic circuit diagram of a test vector encoding signal generation unit of a memory built-in self-test system that can achieve fast testing according to the present invention.

[0049] Figure 6 It is a flowchart of the operation of a test vector selection circuit of a memory built-in self-test method that can achieve fast testing according to the present invention. Detailed implementation manners

[0050] In order to more clearly describe the technical content of the present invention, the following will be further described in combination with specific embodiments.

[0051] The memory built-in self-test system that can achieve fast testing according to the present invention includes:

[0052] A test control circuit module, which receives an external test enable signal bist_en, and its output terminals are respectively connected to a test vector selection circuit module and a circuit under test, and is used to control the operation of the test circuit;

[0053] A test vector selection circuit module, which receives a test vector selection signal pattern_sel, and its receiving terminal is connected to the output terminal of the test control circuit module, and is used to select one or more test vectors for testing according to the test vector selection signal pattern_sel;

[0054] A test vector generation circuit module, its receiving terminal is connected to the output terminal of the test vector selection circuit module, and its output terminal is connected to the circuit under test, and is used to generate test vectors;

[0055] A response analysis circuit module, its input terminals are connected to the test vector selection circuit module and the circuit under test, and is used to compare the value read from the memory with the test vector, and output a test completion signal bist_done and a test success signal bist_ok.

[0056] As a preferred embodiment of the present invention, the test vector selection circuit module includes:

[0057] A test vector selection signal temporary storage unit, connected to the test control circuit module, receiving the test vector selection signal pattern_sel configured by the user and the one-time algorithm completion signal fsm_complete output by the test control circuit module, and outputting a temporary storage intermediate value psel_temp;

[0058] A test vector encoding signal generation unit, with its receiving end connected to the test vector selection signal temporary storage unit and its output end connected to the test vector generation circuit module, receiving the test vector selection signal pattern_sel configured by the user; outputting a test vector encoding signal pattern_id for generating a test vector signal bist_pattern.

[0059] As a preferred embodiment of the present invention, the test vector selection circuit module further includes:

[0060] A NOR operation unit, with its receiving end connected to the test vector selection signal temporary storage unit and its output end connected to the response analysis circuit module, outputting an all-vector test completion signal pattern_complete, and the vector test completion signal pattern_complete is used to generate a test completion signal bist_done.

[0061] As a preferred embodiment of the present invention, the test vector selection signal temporary storage unit includes X groups of output sub-units, and the X groups of output sub-units are connected in sequence for testing test vectors in order of operation priority; the number of bits of each group of output sub-units corresponds to the number of bits of the temporary storage intermediate value psel_temp in sequence. When the nth output sub-unit finishes testing, the value of psel_temp[n - 1] is output as 0, where n is greater than or equal to 1 and less than or equal to X.

[0062] As a preferred embodiment of the present invention, the test vector selection signal temporary storage unit includes 6 D flip-flops, 5 AND gates, and 5 NOT gates. The D terminals of the 6 D flip-flops all receive the test vector selection signal pattern_sel, the clock terminals are all connected to the same clock signal, and the Q terminals all output the temporary storage intermediate value psel_temp. The 5 AND gates and 5 NOT gates form 5 NAND gates, and the 6 D flip-flops are connected through the 5 NAND gates.

[0063] As a preferred embodiment of the present invention, the test vector encoding signal generation unit includes X groups of encoding sub-units, and the X groups of encoding sub-units are connected in sequence, and are used to sequentially output a test vector encoding signal pattern_id according to the operation priority based on the temporarily stored intermediate value operation; each group of encoding sub-units sequentially determines whether the number of bits of the temporarily stored intermediate value psel_temp is valid, and when the value of psel_temp[m] is 1, outputs the corresponding test vector encoding signal pattern_id.

[0064] As a preferred embodiment of the present invention, the test vector encoding signal generation unit includes a D flip-flop, 7 two-to-one multiplexers, 4 OR gates, 5 AND gates, and 5 NOT gates. The 7 two-to-one multiplexers are connected in sequence. The two-to-one multiplexer with the highest priority is connected to the D terminal of the D flip-flop. The 5 AND gates and 5 NOT gates form 5 NAND gates. The 5 two-to-one multiplexers with lower priority are connected to the output terminals of the 5 NAND gates. The output terminals of the 4 OR gates are respectively connected to the input terminals of the NAND gates of the 4 two-to-one multiplexers with lower priority. The NAND gates and OR gates all input the temporarily stored intermediate value psel_temp. The two-to-one multiplexer with the highest priority receives the test enable signal bist_en. The Q terminal of the D flip-flop outputs the test vector encoding signal pattern_id.

[0065] As a preferred embodiment of the present invention, the test control circuit module controls the ascending and descending order of the addresses and the reading and writing of the memory.

[0066] As a preferred embodiment of the present invention, the bit width of the test vector selection signal pattern_sel is X bits, and each bit width corresponds to a group of test vectors.

[0067] The built-in self-test method for a memory that can be quickly tested by using the above system according to the present invention includes the following steps:

[0068] (1) Input the test vector selection signal pattern_sel;

[0069] (2) Assign the temporarily stored intermediate value psel_temp equal to the test vector selection signal pattern_sel, the initial value of the test vector encoding signal pattern_id is 0, and the initial value of the internal signal n is 0;

[0070] (3) Calculate pattern_complete = ~(|psel_temp), output pattern_complete, and determine whether pattern_complete is 1. If so, continue to step (5); otherwise, continue to step (4);

[0071] (4) Test this group of test vectors;

[0072] (4.1) Output the signal that all vector tests are completed, pattern_complete = 0;

[0073] (4.2) Input the signal that the algorithm is completed once, fsm_complete;

[0074] (4.3) Judge whether the signal that the algorithm is completed once, fsm_complete, is equal to 1. If so, continue to step (4.6);

[0075] Otherwise, continue to step (4.4);

[0076] (4.4) Judge whether the temporarily stored intermediate value psel_temp[n] is equal to 1. If so, continue to step (4.5); otherwise, increase the value of n by 1 and continue to step (4.4);

[0077] (4.5) Assign pattern_id as n + 1, output the test vector encoding signal pattern_id at this moment, and continue to step (4.2);

[0078] (4.6) Assign psel_temp[n] as 0, n as n + 1, the test of this group of test vectors is completed, and continue to step (3);

[0079] (5) Output the signal that all vector tests are completed, pattern_complete = 1.

[0080] In the specific implementation manner of the present invention, the present invention provides a memory built-in self-test method, which can effectively and quickly test one or more test vectors for specific defects, shorten the test time, and reduce the test cost.

[0081] The present invention only needs to externally provide an additional test vector selection signal pattern_sel to select the required test vectors for testing.

[0082] Taking a 2K×32-bit SRAM as an example, if we want to test the coupling faults between two adjacent memory cells, we can select pattern1 and pattern2 for testing; if we want to test the coupling faults between two memory cells with a 1-bit interval, we can only select pattern3 for testing; if we want to test the coupling faults between two memory cells with a 3-bit interval, we can only select pattern4 for testing; if we want to test the coupling faults between two memory cells with a 7-bit interval, we can only select pattern5 for testing; if we want to test the coupling faults between two memory cells with a 15-bit interval, we can only select pattern6 for testing; of course, if we want to completely test the coupling faults, we can also select all patterns for testing. Compared with the March C– algorithm, this testing method can still cover the stuck-at fault SAF, transition fault TF, coupling fault CF, and address decoding fault AF, while the testing time can be shortened to at most 1 / 6 of the traditional testing time. Users only need to freely select the test vectors for testing according to the requirements of covered faults and testing time.

[0083] As Figure 2 shown, the present invention adds a test vector selection circuit on the basis of the traditional MBIST circuit, which can control the signal pattern_sel according to the requirements of covered faults to select one or more test vectors for testing, achieving the testing purpose while shortening the testing time and reducing the testing cost.

[0084] The bit width of the test vector selection signal pattern_sel is X bits, and each bit corresponds to a group of patterns. pattern_sel[n]=1 indicates selecting the (n + 1)-th pattern for testing. For example:

[0085] pattern_sel[0]=1 indicates selecting pattern1 for testing,

[0086] pattern_sel[1]=1 indicates selecting pattern2 for testing,

[0087] pattern_sel[2]=1 indicates selecting pattern3 for testing,

[0088] pattern_sel[4]=1 indicates selecting pattern4 for testing,

[0089] And so on. When selecting all patterns for testing, all bits of pattern_sel should be 1, that is, pattern_sel[X - 1:0]=X'b111...1.

[0090] The function of the test vector selection circuit is that the user selects test vectors through the control test vector selection signal pattern_sel according to the possible fault types for targeted and rapid testing. Its functional structure is as Figure 3 shown.

[0091] The input signals of the test vector selection circuit are the test vector selection signal pattern_sel and the one-time algorithm completion signal fsm_complete. pattern_sel is configured by the user, and fsm_complete is an internal signal generated when the test control circuit finishes executing one algorithm;

[0092] The output signals of the test vector selection circuit are the test vector encoding signal pattern_id and the all-vector test completion signal pattern_complete. pattern_id is sent to the test vector generation circuit to generate the test vector signal bist_pattern, and pattern_complete is sent to the response analysis circuit to generate the test completion signal bist_done.

[0093] Taking a 2K×32bit SRAM as an example, the correspondence between the test vector bist_patten and the test vector encoding pattern_id is as Figure 3 shown. When pattern_id = 3’b001, bist_pattern selects pattern1; when pattern_id = 3’b010, bist_pattern selects pattern2; when pattern_id = 3’b011, bist_pattern selects pattern3; when pattern_id = 3’b100, bist_pattern selects pattern4; when pattern_id = 3’b101, bist_pattern selects pattern5; when pattern_id = 3’b110, bist_pattern selects pattern6.

[0094] The specific structure of the test vector selection circuit is related to the bit width of the test memory. Taking a 2K×32bit SRAM as an example, the structure of the test vector selection circuit is discussed in detail below.

[0095] The main circuit structure of the pattern_sel temporary storage module is as Figure 4 shown, containing 6 D flip-flops, 5 AND gates and 5 NOT gates.

[0096] Six D flip-flops are numbered DFF0 to DFF5 respectively, and the operation priority is DFF0 > DFF1 > DFF2 > DFF3 > DFF4 > DFF5. When the MBIST circuit starts to work, the D terminals of the D flip-flops are assigned the initial value psel_temp[5:0] = pattern_sel[5:0] for psel_temp;

[0097] Subsequently, when the first group of pattern tests is completed, the test algorithm completion signal fsm_complete = 1, the output of D flip-flop DFF0 psel_temp[0] = 0, and the output values of DFF1 to DFF5 remain their initial values psel_temp[5:1] = pattern_sel[5:1];

[0098] When the second group of pattern tests is completed, the test algorithm completion signal fsm_complete = 1, the output of D flip-flop DFF1 psel_temp[1] = 0, and the output values of DFF2 to DFF5 remain their initial values psel_temp[5:2] = pattern_sel[5:2];

[0099] When the third group of pattern tests is completed, the test algorithm completion signal fsm_complete = 1, the output of D flip-flop DFF0 psel_temp[2] = 0, and the output values of DFF3 to DFF5 remain their initial values psel_temp[5:3] = pattern_sel[5:3];

[0100] When the fourth group of pattern tests is completed, the test algorithm completion signal fsm_complete = 1, the output of D flip-flop DFF3 psel_temp[3] = 0, and the output values of DFF4 to DFF5 remain their initial values psel_temp[5:4] = pattern_sel[5:4];

[0101] When the fifth group of pattern tests is completed, the test algorithm completion signal fsm_complete = 1, the output of D flip-flop DFF4 psel_temp[4] = 0, and the output value of DFF5 remains its initial value psel_temp[5] = pattern_sel[5];

[0102] When the sixth group of pattern tests is completed, the test algorithm completion signal fsm_complete = 1, the output of D flip-flop DFF5 psel_temp[5] = 0. At this time, psel_temp[5:0] = 6'b000000, and all vector tests are completed.

[0103] The main circuit structure of the pattern_id generation module is as follows Figure 5 shown, which consists of 1 D flip-flop, 7 two-to-one multiplexers, 4 OR gates, 5 AND gates and 5 NOT gates.

[0104] The 7 two-to-one multiplexers are numbered MUX0 to MUX6 respectively, and their operation priorities are MUX0 > MUX1 > MUX2 > MUX3 > MUX4 > MUX5 > MUX6.

[0105] When the test has not started, bist_en = 0 and pattern_id is the default value 3'b000. When the test starts, bist_en = 1, and the multiplexer MUX1 operates first. It judges whether psel_temp[0] is valid (active high). If psel_temp[0] = 1, it selects 3'b001 for output, that is, pattern_id = 3'b001;

[0106] If psel_temp[0] = 0, the multiplexer MUX2 starts to operate. When the multiplexer MUX2 operates, it judges whether psel_temp[1] is valid. If psel_temp[1] = 1, it selects 3'b010 for output, that is, pattern_id = 3'b010;

[0107] If psel_temp[1] = 0, the multiplexer MUX3 starts to operate. When the multiplexer MUX3 operates, it judges whether psel_temp[2] is valid. If psel_temp[2] = 1, it selects 3'b011 for output, that is, pattern_id = 3'b011;

[0108] If psel_temp[2] = 0, the multiplexer MUX4 starts to operate. When the multiplexer MUX4 operates, it judges whether psel_temp[3] is valid. If psel_temp[3] = 1, it selects 3'b100 for output, that is, pattern_id = 3'b100;

[0109] If psel_temp[3] = 0, the multiplexer MUX5 starts to operate. When the multiplexer MUX5 operates, it judges whether psel_temp[4] is valid. If psel_temp[4] = 1, it selects 3'b101 for output, that is, pattern_id = 3'b101;

[0110] If psel_temp[4] = 0, the multiplexer MUX6 starts to operate. When the multiplexer MUX6 operates, it judges whether psel_temp[5] is valid. If psel_temp[5] = 1, it selects 3'b110 for output, that is, pattern_id = 3'b110;

[0111] If psel_temp[5] = 0, it indicates that all vector tests are completed.

[0112] The NOR operation unit ORs each bit of the signal psel_temp[5:0] and then takes the inverse. It consists of 5 OR gates and 1 NOT gate.

[0113] The overall working process of the test vector selection circuit is as Figure 6 shown. Taking a 2K×32bit SRAM as an example for illustration below. There are a total of 6 groups of test vectors for the 2K×32bit SRAM. Assuming the user needs to test all the test vectors, the input signal pattern_sel = 6'b111111. The input signal fsm_complete changes in real time. It becomes valid (active high) when the test control circuit finishes executing an algorithm once, and the valid time is only one clk cycle. It automatically becomes invalid after one clk cycle, and then waits for the test control circuit to finish executing the next algorithm to become valid again. It actually experiences multiple clk cycles from invalid to valid. For the sake of simplifying the process, assume that the time from invalid to valid is only one clk cycle. At this time, the inputs of fsm_complete are successively 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1.

[0114] The process is as follows:

[0115] (1) Input the test vector selection signal pattern_sel = 6'b111111, go to step (2);

[0116] (2) Assign psel_temp = pattern_sel = 6'b111111, n = 0, pattern_id = 3'b00, go to step (3);

[0117] (3) Calculate pattern_complete = ~(|psel_temp) = 0, go to step (3.1);

[0118] (3.1) Output pattern_complete, go to step (3.2);

[0119] (3.2) Determine whether pattern_complete is equal to 1. If it is, the step ends; if not, go to step (3.3);

[0120] (3.3) Input the algorithm completion signal fsm_complete = 0 once, go to step (3.4);

[0121] (3.4) Determine whether fsm_complete is equal to 1. If it is, go to step (3.10); if not, go to step (3.5);

[0122] (3.5) Determine whether psel_temp[0] is equal to 1. If it is, go to step (3.6); otherwise, increment the value of n by 1 and continue with step (3.5);

[0123] (3.6) Calculate pattern_id = n + 1 = 1 (3’b001), and go to step (3.7);

[0124] (3.7) Output pattern_id, and go to step (3.8);

[0125] (3.8) Input the algorithm completion signal fsm_complete = 1 once, and go to step (3.9);

[0126] (3.9) Determine whether fsm_complete is equal to 1. If it is, go to step (3.10); if not, go to step (3.5);

[0127] (3.10) Calculate psel_temp[0] = 0, n = 1. At this time, the first group of patterns has been tested, and go to step (4);

[0128] (4) Calculate pattern_complete = ~(|psel_temp) = 0, and go to step (4.1);

[0129] (4.1) Output pattern_complete, and go to step (4.2);

[0130] (4.2) Determine whether pattern_complete is equal to 1. If it is, the step ends; if not, go to step (4.3);

[0131] (4.3) Input the algorithm completion signal fsm_complete = 0 once, and go to step (4.4);

[0132] (4.4) Determine whether fsm_complete is equal to 1. If it is, go to step (4.10); if not, go to step (4.5);

[0133] (4.5) Determine whether psel_temp[1] is equal to 1. If it is, go to step (4.6); otherwise, increment the value of n by 1 and continue with step (4.5);

[0134] (4.6) Calculate pattern_id = n + 1 = 2 (3’b010), and go to step (4.7);

[0135] (4.7) Output pattern_id and go to step (4.8);

[0136] (4.8) Input the algorithm completion signal fsm_complete = 1 and go to step (4.9);

[0137] (4.9) Check if fsm_complete is equal to 1. If yes, go to step (4.10); if not, go to step (4.5);

[0138] (4.10) Calculate psel_temp[1] = 0 and n = 2. At this time, the second group of patterns has been tested, and go to step (5);

[0139] (5) Calculate pattern_complete = ~(|psel_temp) = 0 and go to step (5.1);

[0140] (5.1) Output pattern_complete and go to step (5.2);

[0141] (5.2) Check if pattern_complete is equal to 1. If yes, the step ends; if not, go to step (5.3);

[0142] (5.3) Input the algorithm completion signal fsm_complete = 0 and go to step (5.4);

[0143] (5.4) Check if fsm_complete is equal to 1. If yes, go to step (5.10); if not, go to step (5.5);

[0144] (5.5) Check if psel_temp[2] is equal to 1. If yes, go to step (5.6); otherwise, increment the value of n by 1 and continue with step (5.5);

[0145] (5.6) Calculate pattern_id = n + 1 = 3 (3’b011) and go to step (5.7);

[0146] (5.7) Output pattern_id and go to step (5.8);

[0147] (5.8) Input the algorithm completion signal fsm_complete = 1 and go to step (5.9);

[0148] (5.9) Check if fsm_complete is equal to 1. If yes, go to step (5.10); if not, go to step (5.5);

[0149] (5.10) Calculate psel_temp[2] = 0, n = 3. At this time, the 3rd group of patterns has been tested, and go to step (6);

[0150] (6) Calculate pattern_complete = ~(|psel_temp) = 0, and go to step (6.1);

[0151] (6.1) Output pattern_complete, and go to step (6.2);

[0152] (6.2) Determine whether pattern_complete is equal to 1. If it is, the step ends; if not, go to step (6.3);

[0153] (6.3) Input the algorithm completion signal fsm_complete = 0 once, and go to step (6.4);

[0154] (6.4) Determine whether fsm_complete is equal to 1. If it is, go to step (6.10); if not, go to step (6.5);

[0155] (6.5) Determine whether psel_temp[3] is equal to 1. If it is, go to step (6.6); otherwise, increment the value of n by 1 and continue with step (6.5);

[0156] (6.6) Calculate pattern_id = pattern_id = 4 (3'b100), and go to step (6.7);

[0157] (6.7) Output pattern_id, and go to step (6.8);

[0158] (6.8) Input the algorithm completion signal fsm_complete = 1 once, and go to step (6.9);

[0159] (6.9) Determine whether fsm_complete is equal to 1. If it is, go to step (6.10); if not, go to step (6.5);

[0160] (6.10) Calculate psel_temp[3] = 0, n = 4. At this time, the 4th group of patterns has been tested, and go to step (7);

[0161] (7) Calculate pattern_complete = ~(|psel_temp) = 0, and go to step (7.1);

[0162] (7.1) Output pattern_complete, and go to step (7.2);

[0163] (7.2) Determine whether pattern_complete is equal to 1. If it is, the step ends; if not, go to step (7.3);

[0164] (7.3) Input the algorithm completion signal fsm_complete = 0 once, and go to step (7.4);

[0165] (7.4) Determine whether fsm_complete is equal to 1. If it is, go to step (7.10); if not, go to step (7.5);

[0166] (7.5) Determine whether psel_temp[4] is equal to 1. If it is, go to step (7.6); otherwise, increment the value of n by 1 and continue with step (7.5);

[0167] (7.6) Calculate pattern_id = pattern_id = 5 (3’b101), and go to step (7.7);

[0168] (7.7) Output pattern_id, and go to step (7.8);

[0169] (7.8) Input the algorithm completion signal fsm_complete = 1 once, and go to step (7.9);

[0170] (7.9) Determine whether fsm_complete is equal to 1. If it is, go to step (7.10); if not, go to step (7.5);

[0171] (7.10) Calculate psel_temp[4] = 0, n = 5. At this time, the 5th group of patterns has been tested, and go to step (8);

[0172] (8) Calculate pattern_complete = ~(|psel_temp) = 0, and go to step (8.1);

[0173] (8.1) Output pattern_complete, and go to step (8.2);

[0174] (8.2) Determine whether pattern_complete is equal to 1. If it is, the step ends; if not, go to step (8.3);

[0175] (8.3) Input the algorithm completion signal fsm_complete = 0 once, and go to step (8.4);

[0176] (8.4) Determine whether fsm_complete is equal to 1. If it is, go to step (8.10); if not, go to step (8.5);

[0177] (8.5) Determine whether psel_temp[5] is equal to 1. If yes, go to step (8.6); otherwise, increment the value of n by 1 and continue with step (8.5);

[0178] (8.6) Calculate pattern_id = 6 (3’b110), and go to step (8.7);

[0179] (8.7) Output pattern_id and go to step (8.8);

[0180] (8.8) Input the algorithm completion signal fsm_complete = 1 and go to step (8.9);

[0181] (8.9) Determine whether fsm_complete is equal to 1. If yes, go to step (8.10); if not, go to step (8.5);

[0182] (8.10) Calculate psel_temp[5] = 0 and n = 6. At this time, the 6th group of patterns has been tested, and go to step (9);

[0183] (9) Calculate pattern_complete = ~(|psel_temp) = 1 and go to step (10);

[0184] (10) Output pattern_complete and go to step (11);

[0185] (11) Determine whether pattern_complete is equal to 1. If yes, end.

[0186] In the above process, the changes and corresponding relationships of the signals pattern_sel, psel_temp, pattern_id, and bist_pattern are shown in Table 1:

[0187] Table 1. Mapping relationships of the signals pattern_sel, psel_temp, pattern_id, and bist_pattern

[0188]

[0189] The built-in self-test system and method for memory that can achieve fast testing according to the present invention are also applicable to other memories and algorithms. One or more different test vectors are selected according to specific memory faults. Different memory faults can select different test vectors, which are applicable to different memories and algorithms. The present invention can select test vectors according to memory faults, has a short test time, low test cost, and a wide range of applications.

[0190] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A memory built-in self-test system capable of rapid testing, characterized in that, the system includes: A test control circuit module, which receives an external test enable signal bist_en, and its output terminals are respectively connected to a test vector selection circuit module and a circuit under test, and is used to control the operation of the test circuit; A test vector selection circuit module, which receives a test vector selection signal pattern_sel, and its receiving terminal is connected to the output terminal of the test control circuit module, and is used to select one or more test vectors for testing according to the test vector selection signal pattern_sel; A test vector generation circuit module, whose receiving terminal is connected to the output terminal of the test vector selection circuit module, and whose output terminal is connected to the circuit under test, and is used to generate test vectors; A response analysis circuit module, whose input terminals are connected to the test vector selection circuit module and the circuit under test, and is used to compare the values read from the memory with the test vectors, and output a test completion signal bist_done and a test success signal bist_ok; The test vector selection circuit module includes: A test vector selection signal temporary storage unit, which is connected to the test control circuit module, receives a test vector selection signal pattern_sel configured by the user and a one-time algorithm completion signal fsm_complete output by the test control circuit module, and outputs a temporary storage intermediate value psel_temp; A test vector encoding signal generation unit, whose receiving terminal is connected to the test vector selection signal temporary storage unit, and whose output terminal is connected to the test vector generation circuit module, receives a test vector selection signal pattern_sel configured by the user; outputs a test vector encoding signal pattern_id, and is used to generate a test vector signal bist_pattern; The test vector selection circuit module further includes: A NOR operation unit, whose receiving terminal is connected to the test vector selection signal temporary storage unit, and whose output terminal is connected to the response analysis circuit module, and outputs an all-vector test completion signal pattern_complete, and the vector test completion signal pattern_complete is used to generate a test completion signal bist_done.

2. The memory built-in self-test system capable of rapid testing according to claim 1, characterized in that, The test vector selection signal temporary storage unit includes X groups of output sub-units, and the X groups of output sub-units are connected in sequence, and are used to test the test vectors in sequence according to the operation priority; the number of bits of each group of output sub-units corresponds to the number of bits of the temporary storage intermediate value psel_temp in sequence. When the nth output sub-unit finishes testing, the value of psel_temp[n - 1] is output as 0, where n is greater than or equal to 1 and less than or equal to X.

3. The memory built-in self-test system capable of rapid testing according to claim 1, characterized in that, The described test vector selection signal storage unit includes six D flip-flops, five AND gates, and five NOT gates. The D terminals of the six D flip-flops all receive the test vector selection signal pattern_sel, the clock terminals are all connected to the same clock signal, and the Q terminals all output the stored intermediate value psel_temp. The five AND gates and five NOT gates form five NAND gates, and the six D flip-flops are connected through the five NAND gates.

4. The memory built-in self-test system capable of rapid testing according to claim 1, characterized in that the test vector encoding signal generation unit includes X groups of encoding sub-units, which are connected in sequence and are used to calculate and output the test vector encoding signal pattern_id according to the stored intermediate value in sequence according to the operation priority; each group of encoding sub-units sequentially determines whether the number of bits of the stored intermediate value psel_temp is valid, and when the value of psel_temp[m] is 1, outputs the corresponding test vector encoding signal pattern_id.

5. The memory built-in self-test system capable of rapid testing according to claim 1, characterized in that the test vector encoding signal generation unit includes a D flip-flop, seven two-to-one multiplexers, four OR gates, five AND gates, and five NOT gates. The seven two-to-one multiplexers are connected in sequence, the two-to-one multiplexer with the highest priority is connected to the D terminal of the D flip-flop, the five AND gates and five NOT gates form five NAND gates, and the five two-to-one multiplexers with lower priority are connected to the output terminals of the five NAND gates. The output terminals of the four OR gates are respectively connected to the input terminals of the NAND gates of the four two-to-one multiplexers with lower priority. The NAND gates and OR gates all input the stored intermediate value psel_temp. The two-to-one multiplexer with the highest priority receives the test enable signal bist_en, and the Q terminal of the D flip-flop outputs the test vector encoding signal pattern_id.

6. The memory built-in self-test system capable of rapid testing according to claim 1, characterized in that the described test control circuit module controls the ascending and descending order of the address and the read and write of the memory.

7. The memory built-in self-test system capable of rapid testing according to claim 1, characterized in that the bit width of the test vector selection signal pattern_sel is X bits, and each bit width corresponds to a group of test vectors.

8. A method for realizing a memory built-in self-test capable of rapid testing by using the system according to claim 1, characterized in that the method includes the following steps: (1) Input the test vector selection signal pattern_sel; (2) Assign the stored intermediate value psel_temp equal to the test vector selection signal pattern_sel, the initial value of the test vector encoding signal pattern_id is 0, and the initial value of the internal signal n is 0; (3) Calculate pattern_complete = ~(|psel_temp), output pattern_complete, and determine whether pattern_complete is 1. If it is, proceed to step (5); otherwise, proceed to step (4). (4) Test the current test vector. (5) Output the signal indicating that all vector tests are completed: pattern_complete = 1.

9. The method for implementing memory built-in self-test that can be quickly tested according to claim 8, characterized in that the specific steps of step (4) include the following steps: (4.1) Output the signal indicating that all vector tests are completed: pattern_complete = 0. (4.2) Input the signal indicating that one algorithm is completed: fsm_complete. (4.3) Determine whether the signal indicating that one algorithm is completed: fsm_complete is equal to 1. If it is, proceed to step (4.6); otherwise, proceed to step (4.4); (4.4) Determine whether the temporarily stored intermediate value psel_temp[n] is equal to 1. If it is, proceed to step (4.5); otherwise, increment the value of n by 1 and proceed to step (4.4). (4.5) Assign pattern_id as n + 1, output the test vector encoding signal pattern_id at this moment, and proceed to step (4.2). (4.6) Assign psel_temp[n] as 0, increment n by 1, the current test vector test is completed, and proceed to step (3).

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