A power semiconductor device and a manufacturing process

Abstract

The present invention provides a power semiconductor device and a manufacturing method thereof. Through the method of low-temperature and low-pressure pre-sintering, good adhesion is formed between the various layer components of the power semiconductor device, avoiding the displacement of the positions of the components during the sintering process. A height balance film is arranged on the power chip to balance the height difference formed between the source electrode of the mounted copper foil and the gate electrode of the unmounted copper foil, so that during a single sintering process, the overall pressure on the power chip is uniform. The technical solution proposed by the present invention not only completely solves the influence of the height difference of the sintered product, but also realizes a single sintering scheme for the upper and lower surfaces of the chip by further optimizing the sintering process, and adopts the bonding method of copper wire and copper strip, improving the life of the module power cycle.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and particularly relates to a power semiconductor device and a manufacturing process thereof. Background Art

[0002] Due to its bandgap width three times that of silicon (Si), high critical breakdown electric field, thermal conductivity, and carrier saturation drift velocity, silicon carbide (SiC) material has become an excellent material for fabricating core power devices in the field of power electronics. At the same time, because of the high-power, high service temperature, high-voltage, and high-frequency working environment of SIC, higher requirements are put forward for packaging materials, processes, structures, thermal management, and reliability.

[0003] Such as Figure 1 The flow schematic diagram of the traditional silver sintering process shown; the traditional silver sintering process successively needs to go through the processes of sintering material picking and curing, chip sticking, first sintering on the lower surface of the chip, as shown in Figure 1 (a), removing the oxidation on the upper surface of the chip, sticking the copper frame, and second sintering on the upper surface of the chip, as shown in Figure 1 (b). Technical problems that may be brought about by traditional silver sintering: 1. The chip needs to withstand high temperature and high pressure twice (temperature above 200 degrees and pressure above 15 Mpa), which poses a great test to the chip performance and may cause damages such as chip cracking; 2. The deoxidation process generally selects plasma deoxidation, which will damage the polymide of the chip and affect the electrical performance of the chip; 3. The sintering molds for the lower surface and the upper surface of the chip are inconsistent, and two sets of sintering jigs need to be purchased; 4. During sintering, the equipment requires that the height difference of the product (after sticking the chip and after sticking the copper frame) does not exceed 0.1 mm, which requires high requirements for the previous processes; 5. The shape of the copper frame is restricted due to the limitations of the current chip mounter when sticking the copper frame.

[0004] Therefore, due to the limitations of high pressure and the design of the equipment, the traditional silver sintering process has great limitations on the height difference of the sintered product, making the full-silver sintering solution for the upper and lower surfaces of the chip have a complex process flow and many product limitation conditions. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a power semiconductor device and a manufacturing process thereof, aiming to solve the problems of complex process flow and many product limitation conditions in the silver sintering process of traditional power semiconductor devices.

[0006] To solve the above technical problem, the present invention is implemented as follows. In the first aspect of the present invention, a manufacturing process of a power semiconductor device is provided, and the manufacturing process includes:

[0007] Provide a substrate, and sequentially stack a first sintered material layer, a power chip, and a copper foil on the substrate by using a low-temperature and low-pressure mounting processing technique. A second sintered material layer is provided on a side of the copper foil close to the power chip. Among them, the copper foil is arranged corresponding to the source electrode of the power chip;

[0008] Mount a height balance film on the power chip, and the height balance film is arranged corresponding to the gate electrode of the power chip;

[0009] Perform a sintering process on the overall device after mounting to connect the power chip to the copper foil and connect the power chip to the substrate;

[0010] Bond and connect a copper strip to the copper foil to obtain a power semiconductor device.

[0011] Further, the mounting temperature in the low-temperature and low-pressure mounting processing technique is 130 - 170 °C, the mounting pressure is 0.3 - 1 Mpa, and the mounting time lasts for 0.5 - 3 s.

[0012] Further, the materials of the first sintered material layer and the second sintered material layer are both silver thin films. The thickness of the first sintered material layer is 55 - 65 μm, and the thickness of the second sintered material layer is 45 - 55 μm.

[0013] Further, a metal coating is provided on the surface of the power chip. The material of the metal coating is silver or gold, and the thickness of the metal coating is 180 - 220 nm.

[0014] Further, the material of the height balance film includes one of a Teflon film and silicone rubber.

[0015] Further, the sintering process includes: placing the overall device after mounting in a sintering mold and performing sintering by using a high-temperature and high-pressure sintering process.

[0016] Further, during the sintering process, the temperature of the sintering process is 230 - 270 °C, and the pressure is 15 - 25 Mpa.

[0017] Further, the power chip is one of a SiC chip, a GaN chip, and a GaAs chip.

[0018] Further, the substrate is a ceramic copper clad laminate.

[0019] In a second aspect of the present invention, a power semiconductor device is provided, and the power semiconductor device is obtained by using the preparation method described above.

[0020] A power semiconductor device and a manufacturing process provided in the present invention have the following beneficial effects compared with the prior art: The present invention adopts a new sintering method. Through low-temperature and low-pressure pre-sintering, good bonding is formed between the component layers of the power semiconductor device, avoiding the displacement of each component during the sintering process. A height balance film is provided on the power chip to balance the height difference formed between the source electrode of the mounted copper foil and the gate electrode of the unmounted copper foil, so that the overall pressure on the power chip is uniform during a single sintering process. The technical solution proposed by the present invention not only completely solves the influence of the height difference of sintered products, but also realizes a single sintering solution for the upper and lower surfaces of the chip by further optimizing the sintering process, and improves the life of the module power cycle by using the bonding method of copper wires and copper strips. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 FIG. 6 is a schematic diagram of the principle of the prior art using two sintering steps in an embodiment of the present invention, where (a) is the first sintering process; (b) is the second sintering process;

[0022] Figure 2 FIG. 10 is a schematic diagram of the manufacturing process flow of a power semiconductor device in an embodiment of the present invention;

[0023] Figure 3 FIG. 14 is a schematic diagram of the sintering principle of a power semiconductor device in an embodiment of the present invention, where (a) is sequentially stacking a first sintering material layer, a power chip, a second sintering material layer, and a copper foil on a substrate; (b) is adding a height balance film; (c) is performing sintering treatment using a sintering mold.

[0024] In the drawings, each reference numeral represents: 10 - substrate; 20 - first sintering material layer; 30 - power chip; 40 - second sintering material layer; 50 - copper foil; 60 - height balance film; 100 - sintering mold. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0026] Refer to Figure 2 - Figure 3 as shown in FIGs.

[0027] Step S101: Provide a substrate 10, and sequentially stack a first sintered material layer 20, a power chip 30, and a copper foil 50 on the substrate 10 by using a low-temperature and low-pressure mounting processing technique. A second sintered material layer 40 is disposed on a side of the copper foil 50 close to the power chip 30, wherein the copper foil 50 corresponds to the source electrode of the power chip 30.

[0028] The substrate 10 is a ceramic copper clad laminate, and the power chip 30 is a SiC chip. In other embodiments, the power chip 30 may also be other chips such as a GaN chip or a GaAs chip.

[0029] Step S101 is essentially a pre-mounting process of the substrate 10, the power chip 30, and the copper foil 50 by using a low-temperature and low-pressure mounting technique, so that the substrate 10, the power chip 30, and the copper foil 50 are preliminarily formed into an integral device through the sintered material, as shown in Figure 3 (a). Further, in the low-temperature and low-pressure mounting processing technique, the mounting temperature is 130 - 170 °C, the mounting pressure is 0.3 - 1 Mpa, and the mounting time lasts for 0.5 - 3 s. As one of the embodiments of the present invention, the low-temperature and low-pressure mounting processing technique specifically includes:

[0030] Mount the first sintered material layer 20 on the substrate 10 in an environmental state where the temperature is 130 °C and the pressure is 0.3 Mpa, and the mounting duration is 1.5 s;

[0031] Mount the power chip 30 on a side of the first sintered material layer 20 away from the substrate 10 in an environmental state where the temperature is 150 °C and the pressure is 0.8 Mpa, and the mounting duration is 0.1 s;

[0032] Mount the copper foil 50 on a side of the power chip 30 away from the first sintered material layer 20 in an environmental state where the temperature is 170 °C and the pressure range is 0.5 Mpa, and the mounting duration is 2 s; wherein a second sintered material layer 40 is pre-disposed on a side of the copper foil 50 corresponding to the power chip 30.

[0033] Through the above steps, the pre-connection of the substrate 10, the first sintered material layer 20, the power chip 30, the second sintered material layer 40, and the copper foil 50 is completed, and the basic positions among the components of the power semiconductor device are fixed, thereby avoiding the offset of each component and improving the stability during the sintering process of the power semiconductor device.

[0034] Preferably, the second sintered material layer 40 can be mounted on the copper foil 50 by using the low-temperature and low-pressure mounting processing technique proposed in this embodiment. In other embodiments, the second sintered material layer 40 can also be mounted on the power chip 30, and then the copper foil 50 is mounted. It can be understood that the purpose of step S101 is to form an integral device structure of each layer component of the mounted power semiconductor.

[0035] As one of the embodiments of the present invention, the first sintering material can be coated on the substrate 10 by screen printing technology, and / or the second sintering material can also be coated on the copper foil 50 by screen printing technology. After baking in an oven at about 120 °C, the first sintering material layer 20 and / or the second sintering material layer 40 are formed.

[0036] Both the first sintering material layer 20 and the second sintering material layer 40 are made of silver thin film. Specifically, the silver thin film is a solid sintered layer formed by pure silver, containing almost no organic components, which greatly reduces the porosity. Among them, the thickness of the first sintering material layer 20 is 55 - 65 μm, and the thickness of the second sintering material layer 40 is 45 - 55 μm.

[0037] Furthermore, a metal coating is provided on the surface of the power chip 30. The material of the metal coating is silver or gold, and the thickness of the metal coating is 180 - 220 nm.

[0038] Step S102, mount the height balance film 60 on the power chip 30. The height balance film 60 is arranged corresponding to the gate of the power chip 30.

[0039] It should be noted that during the mounting process of the copper foil 50 and the power chip 30, the copper foil 50 is connected to the source electrode of the power chip 30. The area of the copper foil 50 corresponds to the size of the source electrode region of the power chip 30. Correspondingly, the second sintering material layer 40 corresponds to the area of the copper foil 50, resulting in the need for two separate sintering processes in the traditional sintering method: the first sintering to form the connection between the substrate 10 and the power chip 30, and the second sintering to form the connection between the power chip 30 and the copper foil 50, which brings about the problem of complicated sintering process. At the same time, in the traditional sintering method, a copper foil 50 is arranged corresponding to the source electrode region of the power chip 30, while no component is arranged in the gate region outside the source electrode region, resulting in a height difference between the source electrode with the copper foil 50 mounted and the gate electrode without the copper foil 50 mounted.

[0040] Compared with the traditional method of sintering in two steps, the present invention adopts a one-step sintering process to simultaneously complete the sintering between the power chip 30 and the substrate 10, and the sintering between the power chip 30 and the copper foil 50.

[0041] The present invention mounts the height balance film 60 on the power chip 30 to balance this height difference. Specifically, the height balance film 60 is arranged corresponding to the gate of the power chip 30. After adding the height balance film 60, the copper foil 50 on the source electrode of the power chip 30 and the height balance film 60 on the gate electrode of the power chip 30 are almost at the same horizontal height, as shown in Figure 3 (b).

[0042] Further, the height-balanced film 60 is made of Teflon film or silicone rubber and has a thickness of about 1 mm. When performing the sintering process, the sintering module can press down the power chip 30 through the height-balanced film 60, so that the power chip 30 is uniformly pressed, avoiding the problem of uneven stress in the area corresponding to the gate of the power chip 30 due to no direct force during a full sintering.

[0043] Step S103: Perform a sintering process on the assembled device to connect the power chip 30 to the copper foil 50 and connect the power chip 30 to the substrate 10.

[0044] The sintering process includes: using a high-temperature and high-pressure sintering process to cause the silver particles in the first sintering material layer 20 and the second sintering material layer 40 to migrate. At the same time, under high pressure, the gaps between the silver particles become smaller, resulting in particle coalescence. Finally, a connection body with few voids and high density is formed by the substrate 10, the power chip 30, and the copper foil 50, improving the heat dissipation and electrical conductivity of the connection layer. At the same time, high pressure promotes the accelerated movement between the silver particles through heat energy, which can shorten the sintering time and is beneficial to the large-scale mass production of power semiconductor devices.

[0045] In this embodiment, the sintering process is carried out in the sintering mold 100. Based on the traditional sintering method, the sintering mold 100 includes a first sintering mold 100 and a second sintering mold 100. The first sintering mold 100 is located above the whole formed by the substrate 10, the first sintering material layer 20, the power chip 30, the second sintering material layer 40, and the copper foil 50, and the second sintering mold 100 is located below the whole formed by the substrate 10, the first sintering material layer 20, the power chip 30, the second sintering material layer 40, and the copper foil 50. During sintering, the first sintering mold 100 and the second sintering mold 100 apply pressure and heat to the whole.

[0046] Since the height difference between the source region and the gate region of the power chip 30 is compensated by the height-balanced film 60 in the present invention, in the selection of the sintering mold 100, the size of the sintering mold 100 corresponds to the size of the power chip 30 and can be slightly larger than the power chip 30. During the pressing process of the sintering mold 100, it can completely cover the power chip 30 and make the power chip 30 uniformly pressed, as shown in Figure 3 (c).

[0047] It should be noted that the sintering mold 100 is provided with a sintering unit for positioning the whole. On the one hand, it provides the high temperature and high pressure requirements needed during the sintering process. On the other hand, it further prevents misalignment and offset between the components in the power semiconductor device. Preferably, the sintering mold 100 includes a plurality of corresponding sintering units, which can be used to sinter multiple wholes formed by the substrate 10, the first sintering material, the power chip 30, the second sintering material, and the copper foil 50 simultaneously, suitable for mass production. Specifically, during the sintering process, the sintering temperature is 230 - 270 °C, and the sintering pressure is 15 - 25 Mpa.

[0048] Step S104, bond a copper strip to the copper foil 50 to obtain a power semiconductor device.

[0049] Bonding with copper wire and copper strip eliminates the shape limitation of the copper frame of the mounter, makes the process more flexible, simplifies the design of the sintering mold 100, has operability, and improves the life of the module power cycle.

[0050] The second aspect of the present invention provides a power semiconductor device, which is obtained by using the preparation method described above.

[0051] In summary, based on the above technical solutions, the beneficial effects of the present invention are as follows:

[0052] This patent adopts a new silver sintering method. Through low-temperature and low-pressure pre-sintering, good bonding is formed between the layers of components in the power semiconductor device, avoiding the offset of the positions of each component during the sintering process. A height balance film is provided on the power chip to balance the height difference formed between the source of the mounted copper foil and the gate of the unmounted copper foil, so that the whole power chip is evenly stressed during a single sintering process. The technical solution proposed by the present invention not only completely solves the influence of the height difference of the sintered product, but also realizes a one-time full silver sintering solution for the upper and lower surfaces of the chip by further optimizing the silver sintering process. By using the bonding method of copper wire and copper strip, the life of the module power cycle is improved.

[0053] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A manufacturing process for a power semiconductor device, characterized in that, the manufacturing process includes: providing a substrate, and sequentially laminating a first sintered material layer, a power chip, and a copper foil on the substrate by using a low-temperature and low-pressure mounting treatment technique. A second sintered material layer is provided on a side of the copper foil close to the power chip. Among them, the copper foil is arranged corresponding to the source electrode of the power chip; mounting a height balance film on the power chip, and the height balance film is arranged corresponding to the gate electrode of the power chip; the height balance film is used to balance the height difference formed between the source electrode of the mounted copper foil and the gate electrode without the mounted copper foil; performing a first sintering treatment on the overall device after mounting is completed. At the same time, connecting the power chip to the copper foil and connecting the power chip to the substrate; bonding and connecting a copper strip to the copper foil to obtain a power semiconductor device; wherein, the material of the height balance film includes one of a Teflon film and silicone rubber; the sintering treatment includes: placing the overall device after mounting is completed in a sintering mold and performing sintering by using a high-temperature and high-pressure sintering process.

2. The manufacturing process for a power semiconductor device according to claim 1, characterized in that, the mounting temperature in the low-temperature and low-pressure mounting treatment technique is 130 - 170 °C, the mounting pressure is 0.3 - 1 Mpa, and the mounting time lasts for 0.5 - 3 s.

3. The manufacturing process for a power semiconductor device according to claim 1, characterized in that, the materials of both the first sintered material layer and the second sintered material layer are silver thin films. The thickness of the first sintered material layer is 55 - 65 μm, and the thickness of the second sintered material layer is 45 - 55 μm.

4. The manufacturing process for a power semiconductor device according to claim 1, characterized in that, a metal coating is provided on the surface of the power chip. The material of the metal coating is silver or gold, and the thickness of the metal coating is 180 - 220 nm.

5. The manufacturing process for a power semiconductor device according to claim 1, characterized in that, the temperature of the sintering treatment is 230 - 270 °C, and the pressure is 15 - 25 Mpa.

6. The manufacturing process for a power semiconductor device according to claim 1, characterized in that, the power chip is one of a SiC chip, a GaN chip, and a GaAs chip.

7. The manufacturing process for a power semiconductor device according to claim 1, characterized in that, the substrate is a ceramic copper clad laminate.

8. A power semiconductor device, characterized in that, the power semiconductor device is manufactured by using the manufacturing process according to any one of claims 1 - 7.

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