Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device, when a gap filling process is performed to fill a region between active patterns, a support pattern can be used to fix an upper portion of the active patterns, and thus, a possibility of the active patterns being bent or collapsed can be prevented or reduced. Accordingly, a failure of the semiconductor device can be reduced and / or reliability of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] Some example embodiments relate to a semiconductor device and / or a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor and / or a method of manufacturing a semiconductor device. BACKGROUND

[0002] A semiconductor device includes an integrated circuit including a metal oxide semiconductor field effect transistor (MOSFET). To meet an increasing demand for a semiconductor device having a small pattern size and a simplified design rule, the MOSFET is being scaled down. Scaling down of the MOSFET can cause deterioration in the working performance of the semiconductor device. Various studies are being conducted to overcome technical limitations related to scaling down of the semiconductor device and to implement a high-performance semiconductor device. SUMMARY

[0003] Some example embodiments of the inventive concept provide a semiconductor device having improved reliability and a method of manufacturing the same.

[0004] According to some example embodiments of the inventive concept, a semiconductor device can include a substrate having a plurality of trenches, an insulating pattern covering bottom surfaces of the plurality of trenches and inner side surfaces of the plurality of trenches, and an active pattern defined by the plurality of trenches. The active patterns are spaced apart from and parallel to each other in a first direction parallel to a top surface of the substrate, and at least one of opposite topmost ends of the active patterns has a stepped portion.

[0005] According to some example embodiments of the inventive concept, a semiconductor device can include a substrate having a plurality of trenches including first and second trenches having different widths from each other, an active pattern defined by the plurality of trenches, an oxide layer covering inner surfaces of each of the first and second trenches, and a nitride layer filling the second trench. At least one of opposite topmost ends of the active pattern has a stepped portion, the oxide layer is interposed between an inner side surface of the second trench and a side surface of the nitride layer, and the oxide layer is interposed between a bottom surface of the second trench and a bottom surface of the nitride layer.

[0006] According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device can include forming a plurality of trenches in a substrate, the plurality of trenches defining an active pattern between the plurality of trenches; forming a protective layer to conformally cover a top surface of the active pattern and to cover bottom surfaces of the plurality of trenches and inner side surfaces of the plurality of trenches; forming a sacrificial layer to fill a remaining portion of the plurality of trenches; forming a support pattern to cover a portion of the protective layer and to cover the sacrificial layer; forming a protective pattern between the support pattern and the active pattern; removing the sacrificial layer; filling a lower oxide layer to fill a portion of the plurality of trenches from which the sacrificial layer is removed; removing the support pattern; and forming an upper oxide layer to cover the protective pattern and the lower oxide layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Some example embodiments will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0008] FIG. 1A , FIG. 2A , FIG. 3A , FIG. 4A , FIG. 5A , FIG. 6A , FIG. 7A , FIG. 8A , FIG. 9A , FIG. 10A , FIG. 11A , FIG. 12A , FIG. 13A and FIG. 14A are plan views showing a portion of a semiconductor device according to some example embodiments of the inventive concepts, for describing a method of manufacturing a semiconductor device.

[0009] FIG. 1B , FIG. 2B , FIG. 3B , FIG. 4B , FIG. 5B , FIG. 6B , FIG. 7B , FIG. 8B , FIG. 9B , FIG. 10B , FIG. 11B , FIG. 12B , FIG. 13B and FIG. 14B are cross-sectional views taken along lines FIG. 1A , FIG. 2A , FIG. 3A , FIG. 4A , FIG. 5A , FIG. 6A , FIG. 7A , FIG. 8A , FIG. 9A , FIG. 10A , FIG. 11A , FIG. 12A, FIG. 13A and FIG. 14A are sectional views taken along the line I-I' of

[0010] FIG. 10C , FIG. 11C , FIG. 12C , FIG. 13C and FIG. 14C are sectional views taken along the line II-II' of FIG. 10A , FIG. 11A , FIG. 12A , FIG. 13A and FIG. 14A .

[0011] FIG. 15A , FIG. 16A , FIG. 17A , FIG. 18A and FIG. 19A are plan views showing a portion of a semiconductor device according to some example embodiments of the inventive concepts, for describing modified examples of a method of manufacturing a semiconductor device.

[0012] FIG. 15B , FIG. 16B , FIG. 17B , FIG. 18B and FIG. 19B are sectional views taken along the line I-I' of FIG. 15A , FIG. 16A , FIG. 17A , FIG. 18A and FIG. 19A .

[0013] FIG. 15C , FIG. 16C , FIG. 17C , FIG. 18C and FIG. 19C are sectional views taken along the line II-II' of FIG. 15A , FIG. 16A , FIG. 17A , FIG. 18A and FIG. 19A .

[0014] FIG. 20A , FIG. 21A , FIG. 22A and FIG. 23A are plan views showing a portion of a semiconductor device according to some example embodiments of the inventive concepts, for describing modified examples of a method of manufacturing a semiconductor device.

[0015] FIG. 20B , FIG. 21B , FIG. 22B and FIG. 23B are sectional views taken along the line I-I' of FIG. 20A , FIG. 21A , FIG. 22A andFIG. 23A cross-sectional view taken along the line I-I' of

[0016] FIG. 21C FIG. 22C and FIG. 23C are cross-sectional views taken along the line II-II' of FIG. 21A FIG. 22A and FIG. 23A

[0017] FIG. 24A FIG. 25A FIG. 26A and FIG. 27A are plan views showing a part of a semiconductor device according to some example embodiments of the inventive concept, for describing modified examples of a method of manufacturing a semiconductor device.

[0018] FIG. 24B FIG. 25B FIG. 26B and FIG. 27B are cross-sectional views taken along the line I-I' of FIG. 24A FIG. 25A FIG. 26A and FIG. 27A

[0019] FIG. 25C FIG. 26C and FIG. 27C are cross-sectional views taken along the line II-II' of FIG. 25A FIG. 26A and FIG. 27A

[0020] FIG. 28A is a plan view showing a semiconductor device according to some example embodiments of the inventive concept, wherein a substrate with an active pattern is provided.

[0021] FIG. 28B are cross-sectional views taken along the lines I1-I2 and I3-I4 of FIG. 28A for showing a semiconductor device, wherein a substrate with an active pattern is provided in the semiconductor device.

[0022] ​​​​​​​​​​​​​It should be noted that the drawings are intended to illustrate the general characteristics of methods, structures and / or materials used in certain example implementations, and the written description is not to be taken as limiting or restrictive in any way. The drawings are not necessarily drawn to scale and are intended for use in illustration of the principles of the present disclosure and / or the exemplary implementations described hereinbefore and hereinafter. For example, the relative thicknesses of the various layers, regions, and / or structural elements can be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various drawings is intended to indicate like or similar elements or features. DETAILED DESCRIPTION

[0023] Some embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0024] FIGS. 1A-14A is a plan view showing a portion of a semiconductor device according to some example embodiments of the inventive concepts, for describing a method of manufacturing a semiconductor device. FIGS. 1B-14B is a cross-sectional view taken along line I-I' of FIGS. 1A-14A . FIGS. 10C-14C is a cross-sectional view taken along line II-II' of FIGS. 10A-14A .

[0025] Referring to FIG. 1A and FIG. 1B , a substrate 100 can be provided. The substrate 100 can include a cell region in which a memory cell is to be formed. The substrate 100 can be or include a semiconductor substrate. For example, the substrate 100 can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 can be doped, for example, can be lightly doped with a P-type impurity such as boron. The substrate 100 can include a plurality of first trenches 110. The first trenches 110 can be formed to be spaced apart from each other in a first direction D1 parallel to a top surface of the substrate 100. The first trenches 110 can be formed by an etching process such as a reactive ion etching (RIE) process using a mask pattern such as a soft mask pattern including a photoresist and / or a hard mask pattern (not shown). An active pattern ACT can be defined between adjacent first trenches among the first trenches 110. The first trenches 110 can be formed to expose side surfaces of the active pattern ACT. The active pattern ACT can correspond to an island having a long first axis and a short second axis. The long first axis can extend at an angle (for example, at an angle between 45 degrees and 89 degrees, such as at an angle of 70 degrees) and intersect the first direction D1; however, example embodiments are not limited thereto. In some example embodiments, the active pattern ACT can correspond to an active pattern of a dynamic random access memory (DRAM) device; however, example embodiments are not limited thereto.

[0026] In some example embodiments, the etching process can include a photolithography process in which extreme ultraviolet (EUV) light is used. As used herein, extreme ultraviolet light can have a wavelength of 4 nm to 124 nm (particularly 4 nm to 20 nm, more particularly 13.5 nm). Extreme ultraviolet light can have an energy of 6.21 eV to 124 eV (particularly 90 eV to 95 eV). In particular, the EUV photolithography process can include an exposure step in which EUV light is irradiated onto a photoresist layer and a development step. The photoresist layer can be formed of or include a photosensitive compound and a synthetic resin, in which the photosensitive compound and the synthetic resin can be exposed and developed in the EUV photolithography process. The photoresist layer can be formed of or include a material having a high EUV absorption rate, and for example, can include at least one of an organometallic material, an organic solvent, an iodine-containing material, or a fluorine-containing material. The photoresist layer can be formed, for example, can be deposited (spin-coated) onto the substrate 100 to have a relatively small thickness. The photoresist pattern can be formed by developing the photoresist layer exposed by the EUV light. When viewed in a plan view, each photoresist pattern can be a linear pattern extending in a particular direction, or can have at least one of an island shape, a zigzag shape, a honeycomb shape, or a circular shape, but the inventive concept is not limited to these examples. According to some example embodiments of the inventive concept, the small-pitch active pattern ACT can be formed by performing the EUV photolithography process, and can not be formed by a multi-patterning technique (MPT) (e.g., a double patterning technique (DPT) and / or a quadruple patterning technique (QPT)). For example, in some example embodiments, the active pattern ACT can be formed to have a minimum pitch of 45 nm or less. By using the EUV photolithography process, the thickness of the photoresist layer can be reduced, and thus the active pattern ACT can be formed in a precise and / or fine manner.

[0027] Referring to FIG. 2A and FIG. 2B A protective layer 120 can be formed on the substrate 100 to cover the active pattern ACT. The protective layer 120 can be formed to conformally cover the top surface of the active pattern ACT. The protective layer 120 can also be formed to conformally cover the bottom surface and the inner side surface of each first trench 110. The protective layer 120 can be formed by, for example, a chemical vapor deposition process and / or an atomic layer deposition process. The protective layer 120 can be formed of or can include doped or undoped polysilicon.

[0028] Referring to FIG. 3A and FIG. 3BA first sacrificial layer 131 can be formed on the protective layer 120. The first sacrificial layer 131 can be formed to fill the remaining portions of the first trenches 110. The first sacrificial layer 131 can be formed by, for example, a chemical vapor deposition process and / or an atomic layer deposition process. The first sacrificial layer 131 can be formed of or include a carbon-containing material. For example, the first sacrificial layer 131 can include a spin-on hard mask (SOH) layer.

[0029] Referring to FIG. 4A and FIG. 4B The first sacrificial layer 131 can be etched, for example, at least partially etched, to form a first sacrificial pattern 132. The first sacrificial pattern 132 can be formed locally in each of the first trenches 110. The top surface and portions of the side surfaces of the protective layer 120 can be exposed due to the etching process of the first sacrificial layer 131. The first sacrificial pattern 132 can be formed by, for example, a back-etching process, such as a blanket back-etching process that exposes the entire top portion of the substrate 100 to an etching chemistry.

[0030] Referring to FIG. 5A and FIG. 5B A support layer 140 can be formed on the first sacrificial pattern 132 and the protective layer 120. The support layer 140 can be formed to cover the first sacrificial pattern 132 and the protective layer 120. The support layer 140 can be formed by, for example, a chemical vapor deposition process and / or an atomic layer deposition process. The support layer 140 can be formed of or include a silicon-containing material. For example, the support layer 140 can include a silicon nitride (SiN) layer.

[0031] Referring to FIG. 6A and FIG. 6B A second sacrificial layer 145 and a third sacrificial layer 146 can be sequentially stacked on the support layer 140. The second sacrificial layer 145 and the third sacrificial layer 146 can be formed by, for example, a chemical vapor deposition process and / or an atomic layer deposition process. The second sacrificial layer 145 can be formed of or include a carbon-containing material. For example, the second sacrificial layer 145 can include a spin-on hard mask (SOH) layer. The third sacrificial layer 146 can be formed of or include a silicon-containing material. For example, the third sacrificial layer 146 can be formed of or include silicon oxynitride (SiON) and / or plasma enhanced silicon oxynitride (PE-SiON).

[0032] Referring to FIG. 7A and FIG. 7BA mask pattern 147 can be formed on the third sacrificial layer 146. The mask pattern 147 can be formed to cover portions of the third sacrificial layer 146. Each mask pattern 147 can be a rectangular pattern when viewed in a plan view. The mask patterns 147 can be formed to be spaced apart from each other in a second direction D2 that is parallel to the top surface of the substrate 100 and perpendicular to the first direction D1. The mask pattern 147 can be formed of or include photoresist, and can be deposited (e.g., can be spin-coated) on the top surface of the sacrificial layer 146. Alternatively or additionally, the mask pattern 147 can be formed of or include a hard mask pattern, and can be formed with an ALD process and / or a CVD process.

[0033] Referring to FIG. 8A and FIG. 8B A support pattern 141 can be formed on the first sacrificial pattern 132 and the protective layer 120 by an etching process using the mask pattern 147. The formation of the support pattern 141 can include etching the second sacrificial layer 145, the third sacrificial layer 146, and the support layer 140 using the mask pattern 147 as an etching mask. The formation of the support pattern 141 can further include removing the remaining portions of the second sacrificial layer 145 and the remaining portions of the third sacrificial layer 146 after the etching process. The remaining portions of the second sacrificial layer 145 and the remaining portions of the third sacrificial layer 146 can be removed by an ashing process and / or a stripping process such as an O2 ashing process. The formation of the support pattern 141 can include performing a wet etching process using an etching solution (e.g., a solution containing an etchant such as, but not limited to, phosphoric acid). The support pattern 141 can be a plurality of rectangular patterns when viewed in a plan view. The support pattern 141 can be a rectangular pattern elongated in the first direction D1 when viewed in a plan view. The support pattern 141 can be formed to cover opposite edge portions of each active pattern ACT when viewed in a plan view. The support pattern 141 can be formed to fill the upper portion of the first trench 110.

[0034] Referring to FIG. 9A and FIG. 9B The first sacrificial pattern 132 can be removed. In some example embodiments, the first sacrificial pattern 132 can be removed by an ashing process and / or a stripping process such as a process using O2 flash stripping. The bottom surface of the protective layer 120 can be exposed during the removal of the first sacrificial pattern 132. Additionally or alternatively, the first sacrificial pattern 132 can be removed with a wet etching process.

[0035] Referring to FIG. 10A , 10BAnd 10C, in addition to the first trench 110, the substrate 100 can further include a second trench 111 having a larger width than the first trench 110. As an example, a second width W2 of a bottom surface of the second trench 111 in the first direction D1 can be larger than a first width W1 of a bottom surface of the first trench 110 in the first direction D1. The support pattern 141 can fill upper portions of the first trench 110 and the second trench 111 even when the first sacrificial pattern 132 is removed. The lower oxide layer 151 can be formed in the first trench 110 and the second trench 111. The protective layer 120 can be partially oxidized by an oxidation process performed to form the lower oxide layer 151. The protective layer 120 on the bottom surfaces and the inner side surfaces of the first trench 110 and the second trench 111 can be oxidized by the oxidation process, as a result, the first lower oxide layer 151a can be formed. The first lower oxide layer 151a can be formed by exposing polysilicon included in the protective layer 120 to oxygen (O2), causing a reaction (e.g., oxidation) of the polysilicon to form silicon oxide (SiO2). An unoxidized portion of the protective layer 120, which will be referred to as a protective pattern 121, can be left between the support pattern 141 and the active pattern ACT. The oxidation process can be an oxidation treatment process in which plasma is used. Alternatively or additionally, the oxidation process can include a thermal oxidation process in which plasma is not used. For example, the oxidation process can be or include an in-situ steam generation (ISSG) process and / or a low pressure chemical vapor deposition (LPCVD) process; however, example embodiments are not limited thereto. The support pattern 141 can not be oxidized by the oxidation treatment process. The protective pattern 121 covered by the support pattern 141 can also not be oxidized. For example, the protective pattern 121 covered by the support pattern 141 can not be exposed to oxygen or can be minimally exposed to oxygen, and can prevent oxidation or reduce the likelihood of oxidation.

[0036] Formation of the lower oxide layer 151 can further include forming a second lower oxide layer 151b to fill the remaining portion of the first trench 110 and portions of the second trench 111. Formation of the second lower oxide layer 151b can be associated with a model of secondary growth of oxidation given by the Deal-Grove model. The first lower oxide layer 151a and the second lower oxide layer 151b can be formed from, include, or consist of the same material. The first lower oxide layer 151a and the second lower oxide layer 151b can be referred to as the lower oxide layer 151. The lower oxide layer 151 can be formed to partially fill the second trench 111, which has a width in the first direction D1 that is greater than a width of the first trench 110 in the first direction D1. The lower oxide layer 151 can be formed to conformally cover the bottom surface and the inner side surfaces of the second trench 111. As the lower oxide layer 151 is formed to partially fill the second trench 111, the third trenches 112 can be formed in the second trench 111, respectively. Each of the third trenches 112 can be or correspond to an empty region formed in a respective one of the second trenches 111. The lower oxide layer 151 can be formed by, for example, at least one of a thermal oxidation process, a chemical vapor deposition process, or an atomic layer deposition process. The lower oxide layer 151 can be formed from or include an oxide material. For example, the lower oxide layer 151 can be formed from or include silicon oxide (SiO2).

[0037] Referring to FIG. 11A , FIG. 11B and FIG. 11C The support pattern 141 can be removed. Removal of the support pattern 141 can include performing a dry etching process and / or a wet etching process using an etching solution (e.g., phosphoric acid). The etching solution can have a high etching rate for a material of the support pattern 141 (e.g., silicon nitride) and a relatively lower etching rate for a material of the protection pattern 121 (e.g., polysilicon). As a result of removing the support pattern 141, the protection pattern 121 can be exposed.

[0038] Referring to FIG. 12A , FIG. 12B and FIG. 12CThe nitride layer 152 can be formed to fill the third trenches 112. The nitride layer 152 can be formed to completely fill the third trenches 112. The lower oxide layer 151 can be interposed between the inner side surfaces of the second trenches 111 and the side surfaces of the nitride layer 152 and between the bottom surfaces of the second trenches 111 and the bottom surfaces of the nitride layer 152. The nitride layer 152 can be formed by, for example, a chemical vapor deposition process and / or an atomic layer deposition process. The nitride layer 152 can be formed of, include, or consist of a material different from the lower oxide layer 151. The nitride layer 152 can be formed of or include a nitride-containing material. For example, the nitride layer 152 can include a silicon nitride layer (SiN). The nitride layer 152 can initially fill all of the third trenches 112, and then can be etched and / or recessed; however, example embodiments are not limited thereto.

[0039] Referring to FIG. 13A , FIG. 13B and FIG. 13C The upper oxide layer 153 can be formed on the protective pattern 121, the lower oxide layer 151, and the nitride layer 152. The upper oxide layer 153 can be formed to cover the protective pattern 121, the oxide layer 151, and the nitride layer 152. The upper oxide layer 153 can be formed by, for example, at least one of a thermal oxidation process, a chemical vapor deposition process, or an atomic layer deposition process. The upper oxide layer 153 can be formed of, include, or consist of the same material as the lower oxide layer 151. The upper oxide layer 153 can be formed of or include an oxide material. For example, the upper oxide layer 153 can be formed of or include a silicon oxide (SiO2). The lower oxide layer 151 and the upper oxide layer 153 can be referred to as an oxide layer 154. The oxide layer 154 and the nitride layer 152 can be referred to, for example, together as an insulating pattern.

[0040] Referring to FIG. 14A , FIG. 14B and FIG. 14CA stepped portion 10 can be formed partially at the opposite topmost end of the active pattern ACT. The formation of the stepped portion 10 can include oxidizing the protection pattern 121. As a result of forming the oxide layer 154, the protection pattern 121 adjacent to the oxide layer 154 can be oxidized or fully oxidized, for example, can be fully converted from polysilicon to silicon oxide (SiO2). Hereinafter, the oxide layer 154 can include the protection pattern 121 oxidized by this process. Since the protection pattern 121 is oxidized / fully oxidized, the opposite topmost end of the active pattern ACT adjacent to the oxide layer 154 can also be oxidized. Accordingly, the stepped portion 10 can be formed to have a shape that is recessed or indented toward the inside of each active pattern ACT, compared to the side surface 11 of each active pattern ACT. The distance T1 between the topmost surface 12 of the active pattern ACT and the bottom surface 13 of the first trench 110 can be greater than the distance T2 between the bottom step or bottom surface 10a of the stepped portion 10 and the bottom surface 13 of the first trench 110.

[0041] According to some example embodiments of the inventive concept, when performing a gap fill process to fill the area between the active patterns, the support pattern 141 can be used to fix the upper portion of the active pattern and prevent or reduce the possibility of the active pattern bending or collapsing. Thus, the failure of the semiconductor device can be reduced and / or the reliability of the semiconductor device can be improved.

[0042] FIGS. 15A-19A is a plan view showing a portion of a semiconductor device according to some example embodiments of the inventive concept, for describing a modified example of a method of manufacturing a semiconductor device. FIGS. 15B-19B is a cross-sectional view taken along the line I-I’ of FIGS. 15A-19A . FIGS. 15C-19C is a cross-sectional view taken along the line II-II’ of FIGS. 15A-19A .

[0043] In the process of manufacturing a semiconductor device according to some example embodiments of the inventive concept, reference is made to FIGS. 1A-9A and FIGS. 1B-9B described above can be performed in substantially the same manner. For the sake of a concise description, features different from the manufacturing method described with reference to FIGS. 10A-14A , FIGS. 10B-14B and FIGS. 10C-14C will be mainly explained in the following description.

[0044] Reference is made to FIG. 15A , FIG. 15B and FIG. 15CThe lower oxide layer 151 can be formed in the first trench 110 and the second trench 111. The protective layer 120 can be fully oxidized by an oxidation process performed to form the lower oxide layer 151. The protective layer 120 on the bottom surface and the inner side surface of the first trench 110 and the second trench 111 can be oxidized by the oxidation process, as a result, the first lower oxide layer 151a can be formed. The support pattern 141 can be formed of or include a material susceptible to oxidation, such as polysilicon, and can also be oxidized by the oxidation process. As the support pattern 141 is oxidized, the remaining portion of the protective layer 120 between the support pattern 141 and the active pattern 142 can be oxidized to form an oxide pattern, which will be referred to as a protective oxide pattern 122. The oxidation process can be or include a thermal oxidation process, such as an ISSG process and / or an LPCVD process, and / or an oxidation treatment process in which plasma is used. The support pattern 141 can be formed of or include a silicon-containing material. For example, the support pattern 141 can be formed of or include doped or undoped polysilicon. Thus, the support pattern 141 can be suitable for oxidation. The protective oxide pattern 122 can be formed of or include an oxide material. For example, the protective oxide pattern 122 can be formed of or include silicon oxide (SiO2).

[0045] The formation of the lower oxide layer 151 can further include forming a second lower oxide layer 151b to fill the remaining portion of the first trench 110 and the portion of the second trench 111. The first lower oxide layer 151a and the second lower oxide layer 151b can be formed of, include, or consist of the same material. The first lower oxide layer 151a and the second lower oxide layer 151b can be referred to as (e.g., collectively referred to as) the lower oxide layer 151. The lower oxide layer 151 can be formed to partially fill the second trench 111, the second trench 111 having a width in the first direction D1 that is greater than a width of the first trench 110 in the first direction D1. The lower oxide layer 151 can be formed to conformally cover the bottom surface and the inner side surface of the second trench 111. As the lower oxide layer 151 is formed to partially fill the second trench 111, the third trench 112 can be formed in the second trench 111, respectively. Each third trench 112 can be or correspond to an empty region formed in a respective one of the second trenches 111. The lower oxide layer 151 can be formed of, include, or consist of the same material as the protective oxide pattern 122.

[0046] Reference is made to FIG. 16A , FIG. 16B and FIG. 16CThe support pattern 141 can be removed. As a result of removing the support pattern 141, the protective oxide pattern 122 can be exposed.

[0047] Referring to FIG. 17A , FIG. 17B and FIG. 17C , the nitride layer 152 can be formed to fill the remaining portion of the second trench 111. The nitride layer 152 can be formed to completely fill the third trench 112. The nitride layer 152 can initially overfill the third trench 112, and can be recessed to completely fill the third trench 112 without overflowing; however, example embodiments are not limited thereto. The lower oxide layer 151 can be interposed between the inner side surface of the second trench 111 and the side surface of the nitride layer 152 and between the bottom surface of the second trench 111 and the bottom surface of the nitride layer 152.

[0048] Referring to FIG. 18A , FIG. 18B and FIG. 18C , the upper oxide layer 153 can be formed on the protective oxide pattern 122, the lower oxide layer 151, and the nitride layer 152. The upper oxide layer 153 can be formed to cover the protective oxide pattern 122, the oxide layer 151, and the nitride layer 152. The upper oxide layer 153 can be formed of, include, or consist of the same material as the protective oxide pattern 122. The protective oxide pattern 122, the lower oxide layer 151, and the upper oxide layer 153 can be collectively referred to as an oxide layer 154.

[0049] Referring to FIG. 19A , FIG. 19B and FIG. 19C , the oxide layer 154 can be formed to completely cover the active pattern ACT. Unlike the active pattern ACT described with reference to FIG. 14A , FIG. 14B and FIG. 14C , a stepped portion can not be formed at the opposite topmost end of the active pattern ACT.

[0050] FIGS. 20A-23A is a plan view showing a portion of a semiconductor device according to some example embodiments of the inventive concepts, for describing a modified example of a method of manufacturing a semiconductor device. FIGS. 20B-23B are cross-sectional views taken along lines I-I' and II-II' of FIGS. 20A-23A , respectively. FIGS. 21C-23C are cross-sectional views taken along lines I-I' and II-II' of FIGS. 21A-23A , respectively.

[0051] In the process of manufacturing a semiconductor device according to the present embodiment of the inventive concepts, reference is made to FIGS. 1A-8A and FIGS. 1B-8BThe manufacturing processes described can be performed in substantially the same manner. For the sake of a concise description, features different from the manufacturing methods described with reference to FIGS. 9A-14A , FIGS. 9B-14B and FIGS. 10C-14C will be mainly explained in the following description.

[0052] With reference to FIG. 24A , FIG. 24B , the support pattern 141 can be a plurality of circular and / or elliptical patterns when viewed in plan view. The support pattern 141 can be formed to cover opposite edge portions of the active pattern ACT when viewed in plan view.

[0053] With reference to FIG. 25A , FIG. 25B and FIG. 25C , a lower oxide layer 151 can be formed in the first trench 110 and the second trench 111. The protective layer 120 can be partially oxidized by an oxidation process performed to form the lower oxide layer 151. The protective layer 120 on the bottom surface and the inner side surface of the first trench 110 and the second trench 111 can be oxidized by the oxidation process, as a result, the first lower oxide layer 151a can be formed. An unoxidized portion of the protective layer 120, which will be referred to as a protective pattern 121, can be left between the support pattern 141 and the active pattern ACT. The oxidation process can be or include a thermal oxidation process, such as an ISSG process and / or an LPCVD process, and / or an oxidation treatment process in which plasma is used. The support pattern 141 can not be oxidized by the oxidation treatment process. The protective pattern 121 covered by the support pattern 141 can also not be oxidized.

[0054] The formation of the lower oxide layer 151 can further include forming a second lower oxide layer 151b to fill a remaining portion of the first trench 110 and a portion of the second trench 111. The lower oxide layer 151 can be formed to cover the exposed top surface of the active pattern ACT. A top surface of the lower oxide layer 151 on the exposed top surface of the active pattern ACT can be located at a lower level than a top surface of the support pattern 141. The lower oxide layer 151 can be formed to partially fill the second trench 111, the second trench 111 having a width in the first direction D1 greater than a width of the first trench 110 in the first direction D1. The lower oxide layer 151 can be formed to conformally cover the bottom surface and the inner side surface of the second trench 111. As the lower oxide layer 151 is formed to partially fill the second trench 111, a third trench 112 can be formed in the second trench 111, respectively. Each third trench 112 can be or include an empty region formed in a respective one of the second trenches 111.

[0055] With reference to FIG. 26A , FIG. 26B and FIG. 26CThe support pattern 141 can be removed. The removal of the support pattern 141 can include performing a wet etching process using an etching solution (e.g., phosphoric acid). The etching solution can selectively etch the support pattern 141 and can not etch or only minimally etch the protection pattern 121. As a result of the removal of the support pattern 141, the protection pattern 121 can be exposed.

[0056] Referring to FIG. 27A , FIG. 27B and FIG. 27C A nitride layer 152 can be formed to fill the remaining portion of the second trench 111. The nitride layer 152 can be formed to completely fill the third trench 112. The lower oxide layer 151 can be interposed between the inner side surface of the second trench 111 and the side surface of the nitride layer 152 and between the bottom surface of the second trench 111 and the bottom surface of the nitride layer 152.

[0057] An oxide layer 154 can be formed to cover the protection pattern 121, the lower oxide layer 151, and the nitride layer 152. The oxide layer 154 can be formed to completely cover the first trench 110. The oxide layer 154 can be interposed between the inner side surface of the second trench 111 and the side surface of the nitride layer 152 and between the bottom surface of the second trench 111 and the bottom surface of the nitride layer 152. The oxide layer 154 can be formed by at least one of, for example, a thermal oxidation process, a chemical vapor deposition process, or an atomic layer deposition process. The oxide layer 154 can be formed of or include an oxide material. For example, the oxide layer 154 can be formed of or include silicon oxide (SiO2).

[0058] The stepped portion 10 can be partially formed at the opposite topmost end of the active pattern ACT. The formation of the stepped portion 10 can include oxidizing the protection pattern 121. The protection pattern 121 adjacent to the oxide layer 154 can be oxidized due to the formation of the oxide layer 154. Hereinafter, the oxide layer 154 can include the protection pattern 121 oxidized by this process. Since the protection pattern 121 is oxidized, the opposite topmost end of the active pattern ACT adjacent to the oxide layer 154 can also be oxidized. Accordingly, the stepped portion 10 can be formed to have a shape that is recessed or indented toward the inside of each active pattern ACT, as compared to the side surface 11 of each active pattern ACT. The distance T1 between the topmost surface 12 of the active pattern ACT and the bottom surface 13 of the first trench 110 can be greater than the distance T2 between the bottom surface 10a of the stepped portion 10 and the bottom surface 13 of the first trench 110.

[0059] ​ is a plan view showing a portion of a semiconductor device according to some example embodiments of the inventive concepts, for describing modified examples of a method of manufacturing a semiconductor device.​ are cross-sectional views taken along lines I-I' and II-II' of ​ ​ are cross-sectional views taken along lines I-I' and II-II' of ​

[0060] In the process of manufacturing a semiconductor device according to the present embodiment, the manufacturing process described with reference to ​ and ​ can be performed in substantially the same manner. For the sake of a concise description, features different from the manufacturing method described with reference to ​ , ​ and ​ will mainly be explained in the following description.

[0061] With reference to ​ and ​ , the support pattern 141 can be a plurality of rectangular patterns when viewed in plan view. The support pattern 141 can be a rectangular pattern elongated in the third direction D3, which is obtuse to the first direction D1 and acute to the second direction D2 when viewed in plan view. The support pattern 141 can be formed to cover opposite edge portions of the active pattern ACT when viewed in plan view.

[0062] With reference to ​ , ​ and ​ , the lower oxide layer 151 can be formed in the first trench 110 and the second trench 111. The protective layer 120 can be partially oxidized by an oxidation process performed to form the lower oxide layer 151. The protective layer 120 on the bottom surface and the inner side surface of the first trench 110 and the second trench 111 can be oxidized by the oxidation process, as a result, the first lower oxide layer 151a can be formed. The unoxidized portion of the protective layer 120, which will be referred to as the protective pattern 121, can be left between the support pattern 141 and the active pattern ACT. The oxidation process can be or include a thermal oxidation process, such as an ISSG process and / or an LPCVD process, and / or an oxidation treatment process in which plasma is used. The support pattern 141 can not be oxidized by the oxidation treatment process. The protective pattern 121 covered by the support pattern 141 can also not be oxidized.

[0063] ​​The forming of the lower oxide layer 151 can further include forming a second lower oxide layer 151b to fill the remaining portion of the first trench 110 and a portion of the second trench 111. The lower oxide layer 151 can be formed to cover the exposed top surface of the active pattern ACT. A top surface of the lower oxide layer 151 on the exposed top surface of the active pattern ACT can be located at a lower level than a top surface of the support pattern 141. The lower oxide layer 151 can be formed to partially fill the second trench 111, the second trench 111 having a width in the first direction D1 greater than a width of the first trench 110 in the first direction D1. The lower oxide layer 151 can be formed to conformally cover a bottom surface and an inner side surface of the second trench 111. As the lower oxide layer 151 is formed to partially fill the second trench 111, the third trench 112 can be formed in the respective one of the second trenches 111, respectively. Each of the third trenches 112 can be an empty region formed in the respective one of the second trenches 111.

[0064] Referring to ​ , ​ and ​ , the support pattern 141 can be removed. The removal of the support pattern 141 can include performing a wet etching process using an etching solution (e.g., phosphoric acid). As a result of the removal of the support pattern 141, the protection pattern 121 can be exposed.

[0065] Referring to ​ , ​ and ​ , a nitride layer 152 can be formed to fill the remaining portion of the second trench 111. The nitride layer 152 can be formed to completely fill the third trench 112. The lower oxide layer 151 can be interposed between the inner side surface of the second trench 111 and the side surface of the nitride layer 152 and between the bottom surface of the second trench 111 and the bottom surface of the nitride layer 152.

[0066] An oxide layer 154 can be formed to cover the protection pattern 121, the lower oxide layer 151, and the nitride layer 152. The oxide layer 154 can be formed to completely cover the first trench 110. The oxide layer 154 can be interposed between the inner side surface of the second trench 111 and the side surface of the nitride layer 152 and between the bottom surface of the second trench 111 and the bottom surface of the nitride layer 152. The oxide layer 154 can be formed by, for example, a chemical vapor deposition process or an atomic layer deposition process. The oxide layer 154 can be formed of or include an oxide material. For example, the oxide layer 154 can be formed of or include silicon oxide (SiO2).

[0067] The stepped portion 10 can be partially formed at the opposite topmost end of the active pattern ACT. The formation of the stepped portion 10 can include oxidizing the protection pattern 121. The protection pattern 121 adjacent to the oxide layer 154 can be oxidized due to the formation of the oxide layer 154. Hereinafter, the oxide layer 154 can include the protection pattern 121 oxidized by this process. Since the protection pattern 121 is oxidized, the opposite topmost end of the active pattern ACT adjacent to the oxide layer 154 can also be oxidized. Accordingly, the stepped portion 10 can be formed to have a shape that is recessed and / or indented toward the inside of each active pattern ACT, compared to the side surface 11 of each active pattern ACT. The distance T1 between the topmost surface 12 of the active pattern ACT and the bottom surface 13 of the first trench 110 can be greater than the distance T2 between the bottom surface 10a of the stepped portion 10 and the bottom surface 13 of the first trench 110.

[0068] Figure 28A is a plan view showing a semiconductor device according to some example embodiments of the inventive concepts, in which a substrate having active patterns is provided. Figure 28B is a cross-sectional view taken along lines I1-I2 and I3-I4 of Figure 28A , for illustrating a semiconductor device in which a substrate having active patterns is provided. Hereinafter, the oxide layer 154 and the nitride layer 152 can be referred to as an insulating pattern.

[0069] Referring to Figure 28A and Figure 28B , the insulating pattern can be partially etched to form a device isolation layer 150. The etching of the insulating pattern can be performed to expose a top surface of the active pattern ACT. Accordingly, the device isolation layer 150 can be locally formed in the first trench 110 and the second trench 111. The active pattern ACT defined by the device isolation layer 150 can be provided in a cell region CELL of the substrate 100, and word lines WL can be provided on the cell region CELL of the substrate 100. The word lines WL can be spaced apart from each other in the second direction D2, and can extend in the first direction D1. The word lines WL can be buried in or within the substrate 100. A gate insulating layer 307 can be provided under the word lines WL.

[0070] The first doped region 312a can be provided in the active pattern ACT between a pair of word lines WL, and a pair of second doped regions 312b can be provided in opposite edge portions of each active pattern ACT. The first doped region 312a and the second doped region 312b can be doped with impurities (e.g., n-type impurities such as phosphorus and / or arsenic). The first doped region 312a can correspond to a common drain region, and the second doped region 312b can correspond to a source region. The word line WL and the first doped region 312a and the second doped region 312b adjacent thereto can constitute or correspond to a transistor, e.g., an access transistor in a DRAM device.

[0071] The word line cover pattern 310 can be provided on the word line WL, respectively. The word line cover pattern 310 can be a linear pattern extending in a length direction of the word line WL. The interlayer insulating layer 305 can be provided on the substrate 100. The interlayer insulating layer 305 can include a plurality of island-shaped patterns spaced apart from each other when viewed in a plan view. The word line cover pattern 310 can be formed of or include a nitride such as silicon nitride.

[0072] The bit line BL can be provided on the interlayer insulating layer 305. The bit line BL can be provided to cross the word line cover pattern 310 and the word line WL. The bit line BL can be arranged to be spaced apart from each other in a first direction D1 and can extend in a second direction D2. The bit line BL can include a bit line polysilicon pattern 330, a bit line ohmic pattern 331, and a bit line metal-containing pattern 332 sequentially stacked. A bit line cover pattern 337 can be provided on the bit line BL, respectively. The bit line cover pattern 337 can be formed of or include an insulating material (e.g., silicon nitride).

[0073] The bit line contact DC can be provided between adjacent word lines WL and can be partially buried in the substrate 100. The bit line contact DC can electrically connect the first doped region 312a to the bit line BL. The lower insulating gap fill layer 341 can be provided on a side surface of the bit line contact DC.

[0074] Storage node contacts BC can be provided between adjacent pairs in the bit lines BL. The storage node contacts BC can be spaced apart from each other. The storage node contacts BC can be formed of or include doped or undoped polysilicon, and / or can be formed of or include a metal such as tungsten. Bit line spacers SP can be interposed between the bit lines BL and the storage node contacts BC. The bit line spacers SP can include first sub-spacers 321 and second sub-spacers 325 that are spaced apart from each other by an air gap AG. The first sub-spacers 321 can cover side surfaces of the bit lines BL and side surfaces of a bit line cover pattern 337. The second sub-spacers 325 can be adjacent to the storage node contacts BC. The first sub-spacers 321 and the second sub-spacers 325 can be formed of, include, or consist of the same material, e.g., silicon nitride.

[0075] A storage node ohmic layer 309 can be provided on the storage node contacts BC. The storage node ohmic layer 309 can be formed of or include at least one metal silicide material. The storage node ohmic layer 309, the first sub-spacers 321 and the second sub-spacers 325, and the bit line cover pattern 337 can be conformally covered by a diffusion prevention pattern 311a. The diffusion prevention pattern 311a can be formed of or include at least one metal nitride, e.g., titanium nitride or tantalum nitride. Landing pads LP can be provided on the diffusion prevention pattern 311a. The landing pads LP can be formed of or include a metal-containing material, e.g., tungsten. The landing pads LP can include an upper portion having a width that is greater than a width of the storage node contacts BC. A center of the landing pads LP can be offset from or offset relative to a center of the storage node contacts BC. First cover patterns 358a and second cover patterns 360a can be provided between adjacent ones of the landing pads LP. Each of the first cover patterns 358a and the second cover patterns 360a can include at least one of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a porous layer. The first cover patterns 358a can have a higher porosity than the second cover patterns 360a.

[0076] The air gap AG between the first sub-spacers 321 and the second sub-spacers 325 can extend into an area between the landing pads LP. The first cover patterns 358a, the bit line cover pattern 337, and the landing pads LP can be partially exposed by the air gap AG. The air gap AG can include air, such as clean, dry air, and / or can be under vacuum, e.g., can have a pressure that is less than atmospheric pressure.

[0077] A bottom electrode BE can be disposed on the landing pad LP, respectively. The bottom electrode BE can be formed of or include at least one of doped polysilicon, metal nitride (e.g., titanium nitride), or metal (e.g., tungsten, aluminum, and / or copper). The bottom electrode BE can have a cylindrical shape, a hollow cylindrical shape, and / or a cup shape, such as a wine glass shape. Upper side surfaces of adjacent ones of the bottom electrodes BE can be connected to each other by a support pattern 374a. The support pattern 374a can be formed of or include at least one insulating material (e.g., silicon nitride, silicon oxide, and silicon oxynitride).

[0078] Between the bottom electrodes BE, the first and second cover patterns 358a and 360a can be covered by an etch stop layer 370. The etch stop layer 370 can be formed of or include at least one insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride). Surfaces of the bottom electrodes BE and the support pattern 374a can be covered with a dielectric layer DL. The dielectric layer DL can be covered by a top electrode TE. The top electrode TE can include at least one of a doped polysilicon layer, a doped silicon germanium layer, a metal nitride layer (e.g., a titanium nitride layer), or a metal layer (e.g., a tungsten, aluminum, and / or copper layer). The bottom electrode BE, the dielectric layer DL, and the top electrode TE can constitute or correspond to a capacitor CAP, e.g., a capacitor CAP used in a dynamic random access memory (DRAM) device.

[0079] In a semiconductor device according to some example embodiments of the inventive concepts, when a gap fill process is performed to fill a region between active patterns, a support pattern can be used to fix an upper portion of the active patterns, and thus, a possibility that the active patterns are bent or collapsed can be prevented or reduced. Accordingly, a failure of the semiconductor device can be reduced and a reliability of the semiconductor device can be improved.

[0080] While example embodiments of the inventive concepts have been particularly shown and described, ordinary skilled in the art will understand that changes can be made in form and detail without departing from the spirit and scope of the appended claims.

[0081] This U.S. non-provisional patent application claims priority to Korean Patent Application No. 10-2020-0099387, filed on August 7, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device comprising: a substrate having a plurality of trenches; an insulating pattern covering bottom surfaces of the plurality of trenches and inner side surfaces of the plurality of trenches; and an active pattern defined by the plurality of trenches, wherein the active pattern are spaced apart from each other and parallel to each other in a first direction parallel to a top surface of the substrate, and at least one of opposite topmost ends of the active pattern has a stepped portion, wherein the stepped portion includes a bottom surface and a side surface, and the bottom surface is parallel to a top surface of the active pattern, the insulating pattern is in continuous contact with the bottom surfaces, the top surfaces, and the inner side surfaces of the plurality of trenches and the bottom surface and the side surface of the stepped portion, the insulating pattern covers the top surface of the active pattern and the top surfaces of the plurality of trenches, and the insulating pattern has a flat top surface.

2. The semiconductor device of claim 1, wherein a distance from a topmost surface of the active pattern to the bottom surfaces of the plurality of trenches is greater than a distance from a bottom step of the stepped portion to the bottom surfaces of the plurality of trenches.

3. The semiconductor device of claim 1, wherein the stepped portion has a shape that is concave or indented toward an inner portion of each active pattern compared to a side surface of each active pattern.

4. The semiconductor device of claim 1, wherein the plurality of trenches include a first trench and a second trench, and a width of a bottom surface of the second trench in the first direction is greater than a width of a bottom surface of the first trench in the first direction.

5. The semiconductor device of claim 4, wherein the insulating pattern includes a lower oxide layer and a nitride layer, the lower oxide layer fills the first trench, and the lower oxide layer conformally covers the bottom surface of the second trench and the inner side surface of the second trench.

6. The semiconductor device of claim 5, wherein the nitride layer fills a remaining portion of the second trench.

7. The semiconductor device of claim 6, wherein the insulating pattern further includes an upper oxide layer, and the upper oxide layer covers a top surface of the lower oxide layer, covers the nitride layer, and covers the active pattern.

8. The semiconductor device of claim 7, wherein the upper oxide layer includes a same material as the lower oxide layer, and the nitride layer includes a different material than the lower oxide layer and a different material than the upper oxide layer.

9. A semiconductor device comprising: a substrate having a plurality of trenches including a first trench and a second trench having different widths from each other; an active pattern defined by the plurality of trenches; an oxide layer covering inner surfaces of each of the first trench and the second trench; and a nitride layer filling the second trench, wherein at least one of opposite topmost ends of the active pattern has a stepped portion, the stepped portion includes a bottom surface and a side surface, and the bottom surface is parallel to a top surface of the active pattern, ​ ​ the oxide layer is interposed between a bottom surface of the second trench and a bottom surface of the nitride layer, the oxide layer is interposed between a bottom surface of the second trench and a bottom surface of the nitride layer, the oxide layer and the nitride layer form an insulation pattern, the insulation pattern completely covers bottom surfaces, top surfaces, and inner side surfaces of the plurality of trenches such that it is in continuous contact with the bottom surfaces, the top surfaces, and the inner side surfaces of the plurality of trenches and the bottom surface and the side surfaces of the stepped portion, and the insulation pattern has a flat top surface that covers top surfaces of the active patterns and the plurality of trenches.

10. The semiconductor device of claim 9, wherein the active patterns are parallel to each other and spaced apart from each other in a first direction that is parallel to a top surface of the substrate, and a distance between a topmost surface of the active patterns and the bottom surfaces of the plurality of trenches is greater than a distance between a bottom step of the stepped portion and the bottom surfaces of the plurality of trenches.

11. The semiconductor device of claim 10, wherein a width of the bottom surface of the second trench in the first direction is greater than a width of a bottom surface of the first trench in the first direction.

12. The semiconductor device of claim 9, wherein the stepped portion has a shape that is recessed or indented toward an interior of each active pattern compared to a side surface of each active pattern.

13. A method of manufacturing a semiconductor device, comprising: forming a plurality of trenches in a substrate, the plurality of trenches defining active patterns between the plurality of trenches; forming a protection layer to conformally cover top surfaces of the active patterns and to cover bottom surfaces of the plurality of trenches and inner side surfaces of the plurality of trenches; forming a sacrificial layer to fill remaining portions of the plurality of trenches; forming a support pattern to cover a portion of the protection layer and to cover the sacrificial layer; forming a protection pattern between the support pattern and the active patterns; removing the sacrificial layer; filling a lower oxide layer to fill portions of the plurality of trenches from which the sacrificial layer was removed; removing the support pattern; and forming an upper oxide layer to cover the protection pattern and the lower oxide layer.

14. The method of claim 13, wherein the forming of the upper oxide layer includes oxidizing opposite topmost ends of the active patterns adjacent to the protection pattern to form a stepped portion in at least one of the opposite topmost ends of the active patterns.

15. The method of claim 13, wherein the support pattern is formed to cover opposite edge portions of the active patterns when viewed in a plan view, and each of the support patterns has a rectangular or circular structure when viewed in a plan view.

16. The method of claim 13, wherein the forming of the protection pattern includes oxidizing a portion of the protection layer and leaving the protection pattern, the protection pattern being a remaining portion of the protection layer that is not oxidized, the remaining portion being between the support pattern and the active patterns.

17. The method of claim 13, wherein ​ forming the protective pattern includes oxidizing the support pattern, during the oxidizing of the support pattern, a portion of the protective pattern is oxidized to form a protective oxide pattern, and the protective oxide pattern includes the same material as the lower oxide layer.

18. The method of claim 13, wherein the forming the lower oxide layer includes: oxidizing the protective layer exposed on the bottom surfaces of the plurality of trenches and on the inner side surfaces of the plurality of trenches to form a first lower oxide layer; and forming a second lower oxide layer to fill remaining portions of the plurality of trenches.

19. The method of claim 13, wherein the protective pattern includes a material different from the lower oxide layer, and the protective pattern includes polysilicon.

20. The method of claim 13, wherein the plurality of trenches includes a first trench and a second trench, the lower oxide layer conformally covers a bottom surface of the second trench and an inner side surface of the second trench, and the method further includes forming a nitride layer to fill remaining portions of the second trench. ​

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