Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a base, a gate structure on the base, source / drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on the side of the gate structure and covering the source / drain doped layers; forming a dielectric layer on the gate structure and the interlayer dielectric layer; etching the dielectric layer and the interlayer dielectric layer to form a first opening exposing the source / drain doped layers; forming a first plug in the first opening; forming a pattern definition layer on the dielectric layer, the pattern definition layer having a first groove corresponding to the gate structure; etching the dielectric layer exposed by the first groove to form a second opening exposing the gate structure in the dielectric layer; wherein the dielectric layer is more easily etched than the first plug, the first plug is less likely to be damaged during the formation of the second opening, the second opening is less likely to expose the substrate at the bottom of the source / drain doped layers, and the second plug formed in the second opening is less likely to connect with the substrate, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the device.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a gate structure located on the substrate, source / drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on the side of the gate structure and covering the source / drain doped layers; forming a dielectric layer on the gate structure and the interlayer dielectric layer; etching the dielectric layer and the interlayer dielectric layer to form a first opening exposing the source / drain doped layers; forming a first plug in the first opening; after forming the first opening, forming a pattern definition layer on the dielectric layer, the pattern definition layer having a first groove corresponding to the gate structure; after forming the first plug, etching the dielectric layer exposed by the first groove to form a second opening exposing the gate structure in the dielectric layer; and forming a second plug in the second opening.

[0006] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate, the substrate including a base, a gate structure located on the base, source and drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on the side of the gate structure and covering the source and drain doped layers; a dielectric layer located on the substrate; a first plug penetrating the dielectric layer and the interlayer dielectric layer, and the source and drain doped layers being connected; and a pattern definition layer located on the dielectric layer, the pattern definition layer having a first groove corresponding to the gate structure.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure formation method provided by the present invention, a first opening is formed in the dielectric layer to expose the source / drain doped layer, a first plug is formed in the first opening, the first plug is connected to the source / drain doped layer, a pattern definition layer is formed on the dielectric layer, the pattern definition layer has a first groove corresponding to the gate structure, the dielectric layer exposed by the first groove is etched, and a second opening is formed in the dielectric layer to expose the gate structure. In the step of forming the second opening, the etching difficulty of the dielectric layer is usually less than that of the first plug, so the first plug is not easily damaged, the second opening is not easily exposed to the source / drain doped layer corresponding to the first plug, and correspondingly the second opening is not easily exposed to the substrate at the bottom of the source / drain doped layer. Therefore, the second plug formed in the second opening is not easily connected to the substrate, which is beneficial to improving the electrical performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 5 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0011] The devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0012] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] like Figure 1As shown, a substrate is provided, the substrate including a substrate 1, a gate structure 2 located on the substrate 1, source and drain doped layers 3 located on both sides of the gate structure 2, and an interlayer dielectric layer 4 located on the side of the gate structure 2 and covering the source and drain doped layers 3; a dielectric layer 5 is formed on the gate structure 2 and the interlayer dielectric layer 4; the dielectric layer 5 is etched to form a first opening 6 in the dielectric layer 5 that exposes the source and drain doped layers 3.

[0014] like Figure 2 As shown, after the first opening 6 is formed, an anti-reflective coating 7 is formed in the first opening 6 and on the dielectric layer 5, and a mask layer 8 is formed on the anti-reflective coating 7. The mask layer 8 has a groove 9 corresponding to the gate structure 2.

[0015] like Figure 3 As shown, the dielectric layer 5 is etched using the mask layer 8 as a mask to form a second opening 10 that exposes the gate structure 2.

[0016] like Figure 4 As shown, a contact plug 11 is formed in the second opening 10, which is connected to the gate structure 2 and the source / drain doped layer 3.

[0017] In the step of forming the mask layer 8, the mask layer 8 exposes the anti-reflection coating 7 directly above the gate structure 2 and part of the source / drain doped layer 3. In the step of etching the dielectric layer 5 using the mask layer 8 as a mask, while the anti-reflection coating 7 directly above the source / drain doped layer 3 is removed, the dielectric layer 5 directly above the gate structure 2 is etched to a certain thickness. The etching of the dielectric layer 5 directly above the gate structure 2 continues until the gate structure 2 is exposed. During the removal of the dielectric layer 5 directly above the gate structure 2, the source / drain doped layer 3 is easily etched away, and the second opening 10 easily exposes the substrate 1. Correspondingly, during the formation of the contact plug 11 in the second opening 10, the contact plug 11 contacts the substrate 1. When the semiconductor structure is working, leakage is likely between the contact plug 11 and the substrate 1, resulting in poor electrical performance of the semiconductor structure.

[0018] Furthermore, it should be noted that the substrate includes a dense pattern region and a sparse pattern region. The pattern density of the first opening 6 in the dense pattern region is greater than that in the sparse pattern region. During the formation of the anti-reflective coating 7 and the mask layer 8, the total thickness of the anti-reflective coating 7 and the mask layer 8 in the dense pattern region is less than that in the sparse pattern region. This also increases the probability that the source / drain doped layer 3 will be etched away during the formation of the second opening 10, and increases the leakage current between the contact plug 11 and the substrate 1.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, a gate structure located on the substrate, source / drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on the side of the gate structure and covering the source / drain doped layers; forming a dielectric layer on the gate structure and the interlayer dielectric layer; etching the dielectric layer and the interlayer dielectric layer to form a first opening exposing the source / drain doped layers; forming a first plug in the first opening; after forming the first opening, forming a pattern definition layer on the dielectric layer, the pattern definition layer having a first groove corresponding to the gate structure; after forming the first plug, etching the dielectric layer exposed by the first groove to form a second opening exposing the gate structure in the dielectric layer; and forming a second plug in the second opening.

[0020] In the semiconductor structure formation method provided by the present invention, a first opening is formed in the dielectric layer to expose the source / drain doped layer, a first plug is formed in the first opening, the first plug is connected to the source / drain doped layer, a pattern definition layer is formed on the dielectric layer, the pattern definition layer has a first groove corresponding to the gate structure, the dielectric layer exposed by the first groove is etched, and a second opening is formed in the dielectric layer to expose the gate structure. In the step of forming the second opening, the etching difficulty of the dielectric layer is usually less than that of the first plug, so the first plug is not easily damaged, the second opening is not easily exposed to the source / drain doped layer corresponding to the first plug, and correspondingly the second opening is not easily exposed to the substrate at the bottom of the source / drain doped layer. Therefore, the second plug formed in the second opening is not easily connected to the substrate, which is beneficial to improving the electrical performance of the semiconductor structure.

[0021] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figures 5 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0023] like Figure 5 As shown, a substrate is provided, the substrate including a substrate 100, a gate structure 101 located on the substrate 100, source and drain doped layers 102 located on both sides of the gate structure 101, and an interlayer dielectric layer 103 located on the side of the gate structure 101 and covering the source and drain doped layers 102.

[0024] The substrate provides a process platform for the subsequent formation of semiconductors.

[0025] This embodiment uses a FinFET (Fin Field-Effect Transistor) semiconductor structure as an example. Accordingly, the substrate includes a substrate 100 and fins 104 located on the substrate 100. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0026] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0027] When the subsequently formed semiconductor structure is in operation, the fin 104 at the bottom of the gate structure 101 is used as a channel region.

[0028] In this embodiment, the fin 104 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0029] The gate structure 101 spans the fin 104 and covers part of the top wall and part of the side wall of the fin 104.

[0030] The gate structure 101 is used to turn the channel on or off when the semiconductor structure is in operation.

[0031] Specifically, the material of the gate structure 101 includes metal.

[0032] In this embodiment, the gate structure 101 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0033] When a semiconductor structure is in operation, the work function layer is used to regulate the threshold voltage of the transistor.

[0034] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru, and W.

[0035] When the semiconductor structure is in operation, the source and drain doped layers 102 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0036] In this embodiment, the semiconductor structure is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the source / drain doped layer 102 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, by doping silicon carbide or silicon phosphide with N-type ions, the N-type ions replace the positions of silicon atoms in the crystal lattice. The more N-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. In this embodiment, the N-type ions include phosphorus, arsenic, or antimony.

[0037] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are silicon germanide doped with P-type ions. In this embodiment, by doping silicon germanide with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. In this embodiment, the P-type ions include boron, gallium, or indium.

[0038] Interlayer dielectric layer 103 is used for electrical isolation of adjacent devices.

[0039] In this embodiment, the material of the interlayer dielectric layer 103 is an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 103.

[0040] It should be noted that, in the step of providing the substrate, a gate cap layer 105 is formed on the gate structure 101.

[0041] During the subsequent formation of the semiconductor structure, the gate cap layer 105 is used to protect the top of the gate structure 101 from damage.

[0042] In this embodiment, the gate capping layer 105 is also formed on the interlayer dielectric layer 103. In other embodiments, the gate capping layer may be formed only on top of the gate structure 101.

[0043] In this embodiment, the material of the gate cap layer 105 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron nitride silicon carbide.

[0044] In the step of providing the substrate, an isolation layer is formed on the substrate 100 exposed by the fin 104, the isolation layer covering a portion of the sidewall of the fin 104.

[0045] The isolation layer is used to achieve electrical isolation between the individual fins 104.

[0046] In this embodiment, the material of the isolation layer is a dielectric material. Specifically, the material of the isolation layer includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer.

[0047] refer to Figure 6 A dielectric layer 106 is formed on the gate structure 101 and the interlayer dielectric layer 103.

[0048] The dielectric layer 106 is used for electrical isolation of the first and second plugs subsequently formed.

[0049] In this embodiment, the dielectric layer 106 is made of an insulating material. Specifically, the dielectric layer 106 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the dielectric layer.

[0050] In this embodiment, the dielectric layer 106 is formed using a flowable chemical vapor deposition (FCVD) process. The FCVD process has excellent filling capabilities and is suitable for filling openings with high aspect ratios, which helps reduce the probability of voids and other defects forming within the dielectric layer 106, thereby improving the film quality of the dielectric layer 106.

[0051] Combination Figure 6 refer to Figure 7 and Figure 8 Etching the dielectric layer 106 and the interlayer dielectric layer 103 forms a first opening 112 exposing the source / drain doped layer 102 (e.g., ...). Figure 8 (As shown).

[0052] The first opening 112 provides process space for the subsequent formation of the first plug.

[0053] In this embodiment, a dry etching process is used to etch the dielectric layer 106 and the interlayer dielectric layer 103 to form a first opening 112 exposing the source / drain doped layer 102. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps ensure that the morphology of the first opening 112 meets process requirements. This makes it less likely that the first opening 112 will expose the gate structure 101 adjacent to the source / drain doped layer 102, thus making it less likely that the first plug subsequently formed in the first opening 112 will connect with the gate structure 101. This ensures that the current characteristics meet process requirements and improves the electrical performance of the semiconductor structure. During the formation of the first opening 112 using the dry etching process, the top of the source / drain doped layer 102 can be used as the etching stop position, reducing damage to other film structures.

[0054] Specifically, the step of etching the dielectric layer 106 and the interlayer dielectric layer 103 to form a first opening 112 exposing the source / drain doped layer 102 includes:

[0055] like Figure 6 A patterned layer 107 is formed on the dielectric layer 106.

[0056] A second groove is subsequently formed in the graphic layer 107. The graphic layer 107 with the second groove serves as a mask for forming the first opening. The graphic layer 107 is prepared for the subsequent formation of the graphic definition layer.

[0057] Specifically, the material of the patterned layer 107 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron silicon carbide. In this embodiment, the material of the patterned layer 107 includes silicon nitride. Silicon nitride is a commonly used material in manufacturing processes, and its formation process is simple, which helps to reduce the manufacturing cost of semiconductor structures.

[0058] In this embodiment, the patterned layer 107 is formed using chemical vapor deposition (CVD). CVD is a method for generating a thin film by chemically reacting one or more gaseous compounds or elements containing thin film elements. It has good step coverage and allows for precise control of the thickness of the patterned layer 107.

[0059] It should be noted that during the formation of the pattern layer 107, the pattern layer 107 should not be too thick or too thin. If the pattern layer 107 is too thick, it will require excessive processing time to form, and the subsequent patterning of the pattern layer 107 and the formation of the pattern definition layer will also take too long, resulting in low semiconductor structure formation efficiency. In the subsequent patterning of the pattern layer 107, a second groove is formed in the pattern layer 107, and the dielectric layer 106 exposed by the second groove is etched to form a first opening in the dielectric layer 106. If the pattern layer 107 is too thin, during the formation of the first opening, the pattern layer 107 with the second groove is easily consumed prematurely, and the pattern layer 107 will not effectively act as a mask, resulting in poor formation quality of the first opening. Consequently, the first plug subsequently formed in the first opening cannot effectively connect the source / drain doped layer to the subsequent metal, leading to poor electrical performance of the semiconductor structure. In this embodiment, in the step of providing the pattern layer 107, the thickness of the pattern layer 107 is 40 nanometers to 50 nanometers.

[0060] like Figure 7 As shown, the graphic layer 107 is graphically represented, and a second groove 109 is formed in the graphic layer 107.

[0061] Subsequently, using the patterned layer 107 as a mask, the dielectric layer 106 exposed by the second groove 109 is etched, and a first opening is formed in the dielectric layer 106 to expose the source / drain doped layer 102.

[0062] In this embodiment, an anisotropic dry etching process is used to pattern the pattern layer 107, forming a second groove 109 in the pattern layer 107. The anisotropic dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps ensure that the morphology of the second groove 109 meets process requirements. It also helps improve the material removal efficiency of the pattern layer 107, consequently ensuring that the morphology of the first opening formed by the subsequent etching of the dielectric layer 106 exposed by the second groove 109 meets process requirements.

[0063] The steps of patterning the pattern layer 107 include: forming a first anti-reflective material layer on the pattern layer 107; forming a first photoresist layer 111 on the first anti-reflective material layer; etching the first anti-reflective material layer using the first photoresist layer 111 as a mask to form a first anti-reflective coating 110; and etching the pattern layer 107 using the first anti-reflective coating 110 and the first photoresist layer 111 as a mask to form a second groove 109 in the pattern layer 107.

[0064] It should be noted that the method for forming the semiconductor structure includes: after forming the second groove 109, removing the first anti-reflective coating 110 and the first photoresist layer 111.

[0065] Removing the first anti-reflective coating 110 and the first photoresist layer 111 prepares for the subsequent etching of the pattern layer 107 to form the pattern definition layer. It also makes the first anti-reflective coating and the first photoresist layer less likely to contaminate the equipment, thereby improving the formation quality of the semiconductor structure.

[0066] It should be noted that, Figure 7 Three interlayer dielectric layers 103 are shown. Figure 7 The second groove 109 in the middle corresponds to only two interlayer dielectric layers 103, and the second groove 109 corresponding to the other interlayer dielectric layer 103 is in other cross sections.

[0067] like Figure 8 As shown, the dielectric layer 106 exposed by the second groove 109 is etched to form the first opening 112.

[0068] Specifically, the dielectric layer 106 is etched using a dry etching process with the patterned layer 107 having the second groove 109 as a mask, forming a first opening 112 in the dielectric layer 106 that exposes the source / drain doped layer 102.

[0069] It should be noted that, in the step of forming the first opening 112, the gate cap layer 105 is also etched.

[0070] refer to Figures 9 to 13A first plug 114 is formed in the first opening 112 (e.g., Figure 13 (as shown); after forming the first opening 112, a pattern definition layer 113 is formed on the dielectric layer 106 (as shown). Figure 10 As shown), the pattern definition layer 113 has a first recess 117 corresponding to the gate structure 101 (as shown). Figure 10 (As shown).

[0071] The first plug 114 is used to connect the source / drain doped layer 102 to the subsequent metal.

[0072] Specifically, the material of the first plug 114 includes one or more of Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the first plug 114 includes Cu. Copper has low resistivity, which is beneficial for improving the signal delay of the subsequent RC circuit and increasing the processing speed of the semiconductor structure. At the same time, it is also beneficial for reducing the resistance of the first plug 114, thereby reducing power consumption.

[0073] The pattern definition layer 113 serves as an etching mask for the subsequent etching of the dielectric layer 106, forming the second opening.

[0074] Specifically, the steps for forming the first plug 114 and the graphics definition layer 113 include:

[0075] like Figure 9 and Figure 10 As shown, after the first opening 112 is formed, the graphics layer 107 is graphically formed to form the graphics definition layer 113.

[0076] The steps of patterning the pattern layer 107 to form the pattern definition layer 113 include: forming an anti-reflective material layer in the first opening 112 and on the pattern layer 107; forming a photoresist layer on the anti-reflective material layer; etching the anti-reflective material layer using the photoresist layer as a mask to form an anti-reflective coating (not shown in the figure); etching the pattern layer 107 using the anti-reflective coating and the photoresist layer as a mask to form a first groove 117 in the pattern layer 107, and the remaining pattern layer 107 serving as the pattern definition layer 113.

[0077] Specifically, in the step of forming the graphic definition layer 113, the anti-reflective material layer is a second anti-reflective material layer 115 (e.g., Figure 9 As shown), the photoresist layer is the second photoresist layer 116 (as shown). Figure 9 (As shown).

[0078] It should be noted that during the step of forming the first groove 117, a portion of the first opening 112 is exposed in the first groove 117. That is, during the process of forming the first groove 117, a portion of the sidewall of the second groove 109 is etched.

[0079] The first groove 117 exposes the first opening 112, providing process space for the subsequent formation of the first plug in the first opening 112.

[0080] The method for forming the semiconductor structure further includes: patterning the pattern layer 107, forming the pattern definition layer 113, and then removing the second anti-reflective coating and the second photoresist layer 116.

[0081] Removing the second anti-reflective coating and the second photoresist layer 116 prepares for the subsequent formation of the first plug in the first opening 112, and also makes the second anti-reflective coating and the second photoresist layer 116 less likely to contaminate the machine, thereby improving the formation quality of the semiconductor structure.

[0082] like Figures 11 to 13 As shown, the step of forming the first plug 114 in the first opening 112 includes: forming a first conductive material layer 118 on the first groove 117, the second groove 109, the first opening 112 and the pattern definition layer 113; removing the first conductive material layer 118 above the pattern definition layer 113; removing the first conductive material layer 118 in the first groove 117 and the second groove 109, and the remaining first conductive material layer 118 located in the first opening 112 serves as the first plug 114.

[0083] In this embodiment, the first conductive material layer 118 is formed by an electrochemical electroplating process. The electrochemical electroplating process has the advantages of simple operation, fast deposition speed, and low price.

[0084] In this embodiment, a planarization process is used to remove the first conductive material layer 118 that is higher than the pattern definition layer 113.

[0085] Specifically, the planarization process includes chemical mechanical planarization (CMP), a surface planarization technique, in which the top of the pattern definition layer 113 can be used as the planarization stop position during the step of removing the first conductive material layer 118 above the pattern definition layer 113.

[0086] In this embodiment, a dry etching process is used to remove the first conductive material layer 118 in the first groove 117 and the second groove 109. During the dry etching process to remove the first conductive material layer 118 in the first groove 117 and the second groove 109, the removal rate of the first conductive material layer 118 is greater than the removal rate of the pattern definition layer 113.

[0087] It should be noted that, Figure 13 Four gate structures 101 are shown. Figure 13 The first groove 117 in the middle corresponds to only two gate structures 101, while the first groove 117 corresponding to the other two gate structures 101 is in other cross sections.

[0088] refer to Figure 14 After forming the first plug 114, the dielectric layer 106 exposed by the first groove 117 is etched, and a second opening 119 is formed in the dielectric layer 106 to expose the gate structure 101.

[0089] A first opening 112 is formed in the dielectric layer 106 to expose the source / drain doped layer 102. A first plug 114 is formed in the first opening 112 and is connected to the source / drain doped layer 102. A pattern definition layer 113 is formed on the dielectric layer 106. The pattern definition layer 113 has a first groove 117 corresponding to the gate structure 101. The dielectric layer 106 exposed by the first groove 117 is etched. A second opening 119 is formed in the dielectric layer 106 to expose the gate structure 101. In the step of the second opening 119, the dielectric layer 106 is less difficult to etch than the first plug 114. Therefore, the first plug 114 is not easily damaged, and the second opening 119 is less likely to expose the source / drain doped layer 102 corresponding to the first plug 114. Correspondingly, the second opening is less likely to expose the substrate at the bottom of the source / drain doped layer 102. Therefore, after the second plug is formed in the second opening 119, neither the first plug 114 nor the second plug is easily connected to the substrate 100, which is beneficial to improving the electrical performance of the semiconductor structure.

[0090] The second opening 119 provides process space for the subsequent formation of the second plug.

[0091] In this embodiment, a dry etching process is used to etch the dielectric layer 106 exposed in the first groove 117, forming a second opening 119 in the dielectric layer 106 that exposes the gate structure 101. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps to ensure that the morphology of the second opening 119 meets process requirements and also improves the removal efficiency of the dielectric layer 106 and the gate cap layer 105. In the step of forming the second opening 119 using the dry etching process, the top of the gate structure 101 can be used as the etching stop position, reducing damage to other film structures. Furthermore, by changing the etching gas, the dielectric layer 106 and the gate cap layer 105 can be etched in the same etching equipment, simplifying the process steps.

[0092] It should be noted that the first plug 114 is made of metal, and the dielectric layer 106 is made of silicon oxide. During the formation of the second opening 119, the etching rate of the dielectric layer 106 is greater than the etching rate of the first plug 114.

[0093] Specifically, the etching gas used in forming the second opening 119 includes hydrogen fluoride.

[0094] It should be noted that, in the step of forming the second opening 119, the gate cap layer 105 is also etched.

[0095] The method for forming the semiconductor structure further includes: removing the pattern definition layer 113 after forming the second opening 119 and before forming the second plug.

[0096] Removing the graphic definition layer 113 helps to expand the formation process window of the second plug and improve the formation quality of the second plug.

[0097] In this embodiment, a wet etching process is used to remove the pattern definition layer 113. The wet etching process has a high etching rate, is simple to operate, and has low processing costs.

[0098] Specifically, the material of the pattern definition layer 113 is silicon nitride, and correspondingly, the etching solution includes a phosphoric acid solution.

[0099] refer to Figure 15 and Figure 16 A second plug 120 is formed in the second opening 119.

[0100] When the semiconductor structure is in operation, the second plug 120 is used to connect the gate structure 101 to the downstream metal.

[0101] The step of forming a second plug 120 in the second opening 119 includes: forming a second conductive material layer 121 in the second opening 119 and on the dielectric layer 106; removing the portion of the second conductive material layer 121 above the dielectric layer 106, and using the remaining portion of the second conductive material layer 121 in the second opening 119 as the second plug 120.

[0102] In this embodiment, the second conductive material layer 121 is formed by an electrochemical electroplating process. The electrochemical electroplating process has the advantages of simple operation, fast deposition speed, and low price.

[0103] In this embodiment, a planarization process is used to remove the second conductive material layer 121 that is higher than the pattern definition layer 113.

[0104] Specifically, the planarization process includes chemical mechanical planarization (CMP), a global surface planarization technique that, in the step of removing the second conductive material layer 121 above the pattern definition layer 113, can use the top of the dielectric layer 106 as the planarization stop position.

[0105] The present invention also provides a second embodiment of a method for forming a semiconductor structure. The similarities between the second embodiment and the first embodiment will not be repeated here. The differences between the second embodiment and the first embodiment are as follows:

[0106] The method for forming the semiconductor structure further includes: forming a mask layer on the dielectric layer before etching the dielectric layer; patterning the mask layer and forming a second groove in the mask layer; in the step of forming the first opening, etching the dielectric layer exposed by the second groove to form the first opening; the method for forming the semiconductor structure further includes: removing the mask layer after forming the first opening; forming a first plug in the first opening after removing the mask layer; forming the first plug and forming a pattern definition layer on the dielectric layer, wherein the pattern definition layer has a first groove corresponding to the gate structure.

[0107] In this embodiment of the invention, the mask layer is a mask for etching the dielectric layer to form a first opening, and the pattern definition layer is a mask for etching the dielectric layer to form a second opening. The pattern definition layer is formed after removing the mask layer. Therefore, the pattern definition layer does not have a second groove. Thus, in the step of using the pattern definition layer as a mask to etch the dielectric layer exposed by the first groove and forming a second opening in the dielectric layer to expose the gate structure, the first plug is protected by the pattern definition layer, making the first plug less susceptible to damage. The second opening is less likely to expose the source / drain doped layer corresponding to the first plug, and correspondingly, the second opening is less likely to expose the substrate at the bottom of the source / drain doped layer. Therefore, after forming the second plug in the second opening, neither the first plug nor the second plug is easily connected to the substrate, which is beneficial for improving the electrical performance of the semiconductor structure.

[0108] Accordingly, embodiments of the present invention also provide a semiconductor structure. (See reference...) Figure 13 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0109] The semiconductor structure includes: a substrate, the substrate including a substrate 100, a gate structure 101 located on the substrate 100, source / drain doped layers 102 located on both sides of the gate structure 101, and an interlayer dielectric layer 103 located on the side of the gate structure 101 and covering the source / drain doped layers 102; a dielectric layer 106 located on the substrate; a first plug 114 penetrating the dielectric layer 106 and the interlayer dielectric layer 103, and connected to the source / drain doped layers 102; and a pattern definition layer 113 located on the dielectric layer 106, and the pattern definition layer 113 having a first groove 117 corresponding to the gate structure 101.

[0110] In the semiconductor structure provided by this embodiment of the invention, a first plug 114 penetrates the dielectric layer 106 and the interlayer dielectric layer 103, and is connected to the source / drain doped layer 102. The pattern definition layer 113 has a first groove 117 corresponding to the gate structure 101. In the subsequent step of etching the dielectric layer 106 exposed by the first groove 117 to form a second opening in the dielectric layer 106 to expose the gate structure 101, the etching difficulty of the dielectric layer 106 is less than that of the first plug 114. Therefore, the first plug 114 is not easily damaged, and the second opening is not easily exposed to the source / drain doped layer 102 corresponding to the first plug 114. Correspondingly, the second opening is not easily exposed to the substrate 100 at the bottom of the source / drain doped layer 102. Therefore, after the second plug is formed in the second opening, neither the first plug 114 nor the second plug is easily connected to the substrate 100, which is beneficial to improving the electrical performance of the semiconductor structure.

[0111] This embodiment uses a FinFET (Fin Field-Effect Transistor) semiconductor structure as an example. Accordingly, the substrate includes a substrate 100 and fins 104 located on the substrate 100. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0112] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0113] When the subsequently formed semiconductor structure is in operation, the fin 104 at the bottom of the gate structure 101 is used as a channel region.

[0114] In this embodiment, the fin 104 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0115] The gate structure 101 spans the fin 104 and covers part of the top wall and part of the side wall of the fin 104.

[0116] The gate structure 101 is used to turn the channel on or off when the semiconductor structure is in operation.

[0117] Specifically, the material of the gate structure 101 includes metal.

[0118] In this embodiment, the gate structure 101 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0119] When a semiconductor structure is in operation, the work function layer is used to regulate the threshold voltage of the transistor.

[0120] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru, and W.

[0121] When the semiconductor structure is in operation, the source and drain doped layers 102 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0122] In this embodiment, the semiconductor structure is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the source / drain doped layer 102 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, by doping silicon carbide or silicon phosphide with N-type ions, the N-type ions replace the positions of silicon atoms in the crystal lattice. The more N-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. In this embodiment, the N-type ions include phosphorus, arsenic, or antimony.

[0123] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are silicon germanide doped with P-type ions. In this embodiment, by doping silicon germanide with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. In this embodiment, the P-type ions include boron, gallium, or indium.

[0124] Interlayer dielectric layer 103 is used for electrical isolation of adjacent devices.

[0125] In this embodiment, the material of the interlayer dielectric layer 103 is an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the interlayer dielectric layer 103.

[0126] It should be noted that a gate cap layer 105 is formed between the gate structure 101 and the dielectric layer 106.

[0127] The gate cap layer 105 is used to protect the top of the gate structure 101 from damage.

[0128] In this embodiment, the gate cap layer 105 is also located on the interlayer dielectric layer 103. In other embodiments, the gate cap layer may be located only on top of the gate structure 101.

[0129] In this embodiment, the material of the gate cap layer 105 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron nitride silicon carbide.

[0130] In the step of providing the substrate, an isolation layer is formed on the substrate 100 exposed by the fin 104, and the isolation layer covers part of the sidewall of the fin 104.

[0131] The isolation layer is used to achieve electrical isolation between the individual fins 104.

[0132] In this embodiment, the material of the isolation layer is a dielectric material. Specifically, the material of the isolation layer includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer.

[0133] The dielectric layer 106 is used to electrically isolate the first plug 114 and the subsequently formed second plug.

[0134] In this embodiment, the dielectric layer 106 is made of an insulating material. Specifically, the dielectric layer 106 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the difficulty and cost of forming the dielectric layer.

[0135] The first plug 114 is used to connect the source / drain doped layer 102 to the subsequent metal.

[0136] Specifically, the material of the first plug 114 includes one or more of Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the first plug 114 includes Cu. Copper has low resistivity, which is beneficial for improving the signal delay of the subsequent RC circuit and increasing the processing speed of the semiconductor structure. At the same time, it is also beneficial for reducing the resistance of the first plug 114, thereby reducing power consumption.

[0137] It should be noted that the first plug 114 also penetrates the gate cap layer 105.

[0138] It should be noted that, Figure 13 Three source / drain doped layers 102 are shown. Figure 13 The first plug 114 in the middle is only connected to two source / drain doped layers 102, and the first plug 114 corresponding to the other source / drain doped layer 102 is in other cross sections.

[0139] The pattern definition layer 113 serves as an etching mask for the subsequent etching of the dielectric layer 106, forming the second opening.

[0140] Specifically, the material of the pattern definition layer 113 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron silicon carbide. In this embodiment, the material of the pattern definition layer 113 includes silicon nitride. Silicon nitride is a commonly used material in manufacturing processes, and its formation process is simple, which helps to reduce the manufacturing cost of semiconductor structures.

[0141] It should be noted that the pattern definition layer 113 should not be too thick or too thin. If the pattern definition layer 113 is too thick, it will require excessive processing time to form, resulting in low semiconductor structure formation efficiency. If the pattern definition layer 113 is too thin, during the subsequent etching of the dielectric layer 106 using the pattern definition layer 113 as a mask to form the second opening, the pattern definition layer 113 is easily consumed prematurely, failing to effectively function as a mask. This leads to poor formation quality of the second opening, and consequently, the second plug formed in the second opening cannot effectively connect the gate structure 101 to the subsequent metal, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the pattern definition layer 113 is 40 nanometers to 50 nanometers.

[0142] It should be noted that in this embodiment, the first groove 117 exposes the first plug 114. In the subsequent step of etching the dielectric layer 106 using the pattern definition layer 113 as a mask, the first plug 114 is more difficult to etch than the dielectric layer 106, therefore the damage to the first plug 114 is smaller.

[0143] It should be noted that, Figure 13 Four gate structures 101 are shown. Figure 13 The first groove 117 in the middle corresponds to only two gate structures 101, while the first groove 117 corresponding to the other two gate structures 101 is in other cross sections.

[0144] It should be noted that, in this embodiment, a second groove 109 is also formed in the graphic definition layer 113. The second groove 109 exposes the first plug 114.

[0145] In other embodiments, the pattern definition layer may also cover the first plug, thereby forming the second opening by etching the dielectric layer with the pattern definition layer as a mask. In this step, the first plug is protected by the pattern definition layer, making it less susceptible to etching. The source / drain doped layer and substrate at the bottom of the first plug are also less susceptible to etching, making it less likely that the second opening will expose the source / drain doped layer and substrate. Consequently, the second plug formed in the second opening is less likely to connect with the substrate, which is beneficial for improving the electrical performance of the semiconductor structure.

[0146] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0147] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a gate structure on the substrate, source and drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on the side of the gate structure and covering the source and drain doped layers; A dielectric layer is formed on the gate structure and the interlayer dielectric layer; The dielectric layer and the interlayer dielectric layer are etched to form a first opening exposing the source and drain doped layers; A first plug is formed in the first opening; After the first opening is formed, a pattern definition layer is formed on the dielectric layer, and the pattern definition layer has a first groove corresponding to the gate structure. After the first plug is formed, the dielectric layer exposed by the first groove is etched, and a second opening exposing the gate structure is formed in the dielectric layer; A second plug is formed in the second opening; The step of etching the dielectric layer to form a first opening in the dielectric layer that exposes the source / drain doped layer includes: forming a patterned layer on the dielectric layer; patterning the patterned layer to form a second groove in the patterned layer; and etching the dielectric layer exposed by the second groove to form the first opening. After the first opening is formed, the graphics layer is graphically represented to form the graphics definition layer; The step of forming the first plug in the first opening includes: forming a first conductive material layer on the first groove, the second groove, the first opening and the pattern definition layer; Remove the first conductive material layer that is above the graphic definition layer; The first conductive material layer in the first groove and the second groove is removed, and the remaining first conductive material layer in the first opening is used as the first plug.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the first groove, the first groove exposes a portion of the first opening.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the graphic definition layer includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron nitride silicon carbon.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the graphic definition layer is 40 nanometers to 50 nanometers.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The patterned layer is formed using a chemical vapor deposition process.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for forming the graphics definition layer include: An anti-reflective material layer is formed in the first opening and on the patterned layer; A photoresist layer is formed on the anti-reflective material layer; The antireflective material layer is etched using the photoresist layer as a mask to form an antireflective coating. The pattern layer is etched using the photoresist layer and the anti-reflective coating as a mask to form the first groove in the pattern layer, and the remaining pattern layer serves as the pattern definition layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dielectric layer and interlayer dielectric layer exposed by the second groove are etched using a dry etching process to form a first opening that exposes the source and drain doped layers.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first conductive material layer in the second groove and the first groove is removed by a dry etching process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dielectric layer exposed by the first groove is etched using a dry etching process, forming a second opening in the dielectric layer that exposes the gate structure.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second plug in the second opening includes: forming a second conductive material layer in the second opening and on the dielectric layer; removing the second conductive material layer above the dielectric layer, and using the remaining second conductive material layer in the second opening as the second plug.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: removing the pattern definition layer after forming the second opening and before forming the second plug.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The pattern definition layer is removed using a wet etching process.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: forming a mask layer on the dielectric layer before etching the dielectric layer; patterning the mask layer and forming a second groove in the mask layer; In the step of forming the first opening, the dielectric layer exposed by the second groove is etched to form the first opening; The method for forming the semiconductor structure further includes: after forming the first opening, removing the mask layer; After removing the mask layer, a first plug is formed in the first opening; After the first plug is formed, the pattern definition layer having the first groove is formed on the dielectric layer.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a gate cap layer is formed on the gate structure; In the step of forming the second opening, the gate cap layer is also etched.

15. A semiconductor structure, characterized in that, include: The substrate includes a substrate, a gate structure on the substrate, source and drain doped layers on both sides of the gate structure, and an interlayer dielectric layer on the side of the gate structure that covers the source and drain doped layers. A dielectric layer is located on the substrate; The first plug penetrates the dielectric layer and the interlayer dielectric layer, and the source and drain doped layers are connected; A pattern definition layer is located on the dielectric layer, and the pattern definition layer has a first groove corresponding to the gate structure; A second plug extends through the dielectric layer and contacts the gate structure. The second plug is formed after the pattern definition layer is removed, and the second plug is electrically isolated from the first plug based on the dielectric layer.

16. The semiconductor structure as claimed in claim 15, characterized in that, The material of the graphic definition layer includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and boron nitride silicon carbon.

17. The semiconductor structure as claimed in claim 15, characterized in that, The thickness of the graphic definition layer is 40 nanometers to 50 nanometers.

18. The semiconductor structure as claimed in claim 15, characterized in that, The first groove exposes a portion of the first plug.

19. The semiconductor structure as described in claim 15, characterized in that, A gate cap layer is formed between the gate structure and the dielectric layer.

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