Semiconductor element and method for producing the same

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a pad layer, a filling layer, and a barrier layer. The second die is disposed on the first die. The pad layer is disposed in the first die. The filling layer includes an upper portion and a recessed portion. The barrier layer is disposed between the second die and the upper portion of the filling layer, between the first die and the upper portion of the filling layer, and between the pad layer and the recessed portion of the filling layer. The upper portion of the filling layer is disposed along the second die and the first die, and the recessed portion of the filling layer extends from the upper portion and is disposed in the pad layer.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 16 / 945,096, filed July 31, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having a bonding pad layer and a method for fabricating the same. Background Technology

[0003] Semiconductor components are indispensable for many modern applications. For example, they are widely used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Furthermore, with advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously providing better functionality and incorporating a larger number of integrated circuits. However, as semiconductor components shrink proportionally, the spacing between adjacent conductive elements gradually decreases, reducing the process window for interconnect structures. Therefore, fabricating interconnect structures within semiconductor components becomes increasingly difficult. Consequently, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a first die, a second die, a pad layer, a fill layer, and a barrier layer. The second die is disposed on the first die. The pad layer is disposed in the first die. The fill layer includes an upper portion and a recessed portion. The barrier layer is disposed between the second die and the upper portion of the fill layer, between the first die and the upper portion of the fill layer, and between the pad layer and the recessed portion of the fill layer. The upper portion of the fill layer is disposed along the second die and the first die, and the recessed portion of the fill layer extends from the upper portion and is disposed in the pad layer.

[0006] In one embodiment, the depth of the recess in the filler layer is greater than half the thickness of the pad layer and less than the thickness of the pad layer.

[0007] In one embodiment, a horizontal distance between the upper sidewall of the filler layer and the sidewall of the recess of the filler layer is equal to or less than the depth of the recess of the filler layer.

[0008] In one embodiment, the sidewalls of the recess in the filling layer are curved.

[0009] In one embodiment, the bottom surface of the recess in the filling layer is curved.

[0010] In one embodiment, the semiconductor device includes an isolation layer disposed between the second die and the upper portion of the filling layer, and disposed between the first die and the upper portion of the filling layer.

[0011] In one embodiment, the semiconductor device includes a passivation layer disposed on the second grain, and the upper portion of the filling layer is disposed along the passivation layer, the second grain, and the first grain. The passivation layer is formed of silicon nitride, silicon oxynitride, silicon oxide, silicon nitride oxide, epoxy resin, polyimide, benzocyclobutene, or polybenzoxazole.

[0012] In one embodiment, the semiconductor device includes an adhesion layer disposed between the fill layer and the barrier layer. The adhesion layer is formed of titanium, tantalum, titanium-tungsten, or manganese nitride.

[0013] In one embodiment, the semiconductor device includes a seed layer disposed between the attachment layer and the fill layer. The thickness of the seed layer is in the range of about 10 nm to about 40 nm.

[0014] In one embodiment, the semiconductor device includes a pad barrier layer disposed on and under the pad layer, respectively.

[0015] In one embodiment, the interface between the passivation layer and the upper part of the filler layer is tapered.

[0016] In one embodiment, the angle between a top surface of the passivation layer and an interface is in the range of approximately 120 to 135 degrees, wherein the interface is between the passivation layer and the upper portion of the filler layer.

[0017] In one embodiment, the filler layer is formed of polycrystalline silicon, tungsten, copper, carbon nanotubes, or a solder alloy.

[0018] In one embodiment, the isolation layer is formed of silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate (TEOS).

[0019] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, comprising: performing a bonding process to bond a second die to a first die having a pad layer; forming a through-substrate opening along the second die extending into the first die of the pad layer; conformally forming an isolation layer in the through-substrate opening; performing a punching etching process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer; performing an isotropic etching process to form a recessed space extending from the through-substrate opening into the pad layer; conformally forming a barrier layer in the through-substrate opening and the recessed space; and forming a barrier layer in the through-substrate opening and the recessed space.

[0020] In one embodiment, the directional etching has an etch rate ratio between the pad layer and the isolation layer, which is in the range of approximately 100:1 to approximately 1.05:1.

[0021] In one embodiment, the isolation layer is formed of silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate.

[0022] In one embodiment, the filler layer is formed of polycrystalline silicon, tungsten, copper, carbon nanotubes, or a solder alloy.

[0023] In one embodiment, the fabrication method includes the step of forming a passivation layer on the second grain. The through-substrate opening along the passivation layer and the second grain is the pad layer formed and extending into the first grain.

[0024] In one embodiment, the passivation layer is formed of silicon nitride, silicon oxynitride, silicon oxide, silicon oxynitride, epoxy resin, polyimide, phenylcyclobutene, or polybenzoxazole.

[0025] Due to the design of the semiconductor device disclosed herein, the upper portion of the fill layer increases the contact surface between the fill layer and the barrier layer, thereby reducing the contact resistance of the barrier layer. Therefore, the reliability of the semiconductor device can be improved. Furthermore, due to the geometry of the protective layer, the fill layer can be formed without any gaps. Therefore, the manufacturing yield of the semiconductor device can be improved.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0029] Figures 2 to 10 This is a cross-sectional schematic diagram of the fabrication process of the semiconductor device according to some embodiments of the present disclosure.

[0030] Figures 11 to 14 This is a cross-sectional schematic diagram of the fabrication process of a semiconductor device according to another embodiment of the present disclosure.

[0031] Figures 15 to 17 This is a cross-sectional schematic diagram of the fabrication process of a semiconductor device according to another embodiment of the present disclosure.

[0032] Figure 18 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure.

[0033] The reference numerals in the attached figures are explained as follows:

[0034] 1A: Semiconductor components

[0035] 1B: Semiconductor components

[0036] 1C: Semiconductor components

[0037] 10: Preparation method

[0038] 100: First grain

[0039] 101: First basement

[0040] 103: First dielectric layer

[0041] 105: First bonding layer

[0042] 107: First component

[0043] 109: First dummy conductive layer

[0044] 200: Second grain

[0045] 201: Second basement

[0046] 201TS: Top Surface

[0047] 203: Second dielectric layer

[0048] 205: Second bonding layer

[0049] 207: Second component

[0050] 209: Second dummy conductive layer

[0051] 301TS: Top surface

[0052] 301: Passivation layer

[0053] 303: Weld pad layer

[0054] 305: Solder pad barrier layer

[0055] 307: Solder pad barrier layer

[0056] 309: Protective layer

[0057] 401: Isolation Layer

[0058] 401S: Sidewall

[0059] 401TP: The highest point

[0060] 403: Barrier layer

[0061] 403C: Covering section

[0062] 403R: concave part

[0063] 403U: upper part

[0064] 405: Filler layer

[0065] 405R: Recessed portion

[0066] 405RS: Sidewall of the recessed portion

[0067] 405U: upper part

[0068] 501: Through-substrate opening

[0069] 503: Recessed Space

[0070] 503BS: Bottom surface

[0071] 503S: Sidewall

[0072] 505: Conductive material

[0073] D1: Depth

[0074] D2: Depth

[0075] D3: Depth

[0076] H1: Horizontal distance

[0077] H2: Horizontal distance

[0078] IF01: Interface

[0079] S11: Steps

[0080] S13: Steps

[0081] S15: Steps

[0082] S17: Steps

[0083] S19: Steps

[0084] S21: Steps

[0085] S23: Steps

[0086] S25: Steps

[0087] T1: Thickness

[0088] W1: Width

[0089] α: Angle Detailed Implementation

[0090] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0091] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0092] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0093] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the apparatus. Furthermore, the description of a first feature being formed "on" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at different scales. In the drawings, some layers / features may be omitted for simplicity.

[0094] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the elements during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0095] Figure 1 This is a schematic flowchart of a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figures 2 to 10 This is a cross-sectional schematic diagram of the fabrication process of semiconductor element 1A according to some embodiments of the present disclosure.

[0096] refer to Figure 1 and Figure 2 In step S11 of preparation method 10, a bonding process can be performed to bond a second grain 200 to a first grain 100 having a pad layer 303.

[0097] refer to Figure 2 The first die 100 and the second die 200 can be fabricated independently, but this disclosure is not limited thereto. The first die 100 and the second die 200 can have different functionalities. For example, the first die 100 can provide a logic function, while the second die 200 can provide a memory function. In some embodiments, the first die 100 and the second die 200 can have the same functionality.

[0098] refer to Figure 2The first die 100 may include a first substrate 101, a first dielectric layer 103, a first bonding layer 105, a first element component 107, and a first dummy conductive layer 109.

[0099] Please refer to the following: Figure 2 In some embodiments, the first substrate 101 is a bulk semiconductor substrate wholly composed of at least one semiconductor material. The material of the bulk semiconductor substrate may include any material or stack of materials having semiconductor properties, including but not limited to silicon, germanium, silicon-germanium alloys, III-V compound semiconductors, or II-VI compound semiconductors. III-V compound semiconductors are materials comprising at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. II-VI compound semiconductors are materials comprising at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0100] Please refer to the following: Figure 2 In some embodiments, the first substrate 101 may include a silicon-on-insulator (SOI) structure, which, from bottom to top, comprises a processing substrate, an insulating layer, and a topmost semiconductor material layer. The processing substrate and the topmost semiconductor material layer may be formed using the same material as the bulk semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or nitride. For example, the insulating layer may be a dielectric oxide that can oxidize silicon. As another example, the insulating layer may be a dielectric nitride of silicon nitride or boron nitride. As yet another example, the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride arranged in any order. The insulating layer may have a thickness in the range of about 10 nm to 200 nm.

[0101] In some embodiments, the SOI structure can be formed by wafer bonding. In some embodiments, the SOI structure can be formed by an implantation process, such as a separation by implantation of oxygen (SIMOX) process. In some embodiments, the top semiconductor material layer of the SOI structure is formed by a thermal mixing process or a thermal condensation process. The thermal mixing process may include annealing in an inert environment (helium and / or argon), while the thermal condensation process may include annealing in an oxidizing environment (air, oxygen, ozone, and / or NO2). The annealing temperatures of the thermal mixing process and the thermal condensation process can be in the range of about 600°C to about 1200°C.

[0102] Please refer to the following: Figure 2A first dielectric layer 103 may be formed on a first substrate 101. The first dielectric layer 103 may be a stacked layer structure. The first dielectric layer 103 may include a plurality of first insulator layers. Each of the plurality of first insulator layers may have a thickness ranging from about 0.5 micrometers to about 3.0 micrometers.

[0103] The plurality of first insulator layers may be formed of materials such as silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, similar materials, or combinations thereof. The plurality of first insulator layers may be formed of different materials, but this disclosure is not limited thereto. The low-k dielectric material may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant of less than 2.0.

[0104] The first dielectric layer 103 can be formed by a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. A planarization process can be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps. A first element component 107, a conductive component (not shown), a solder pad layer 303, and solder pad barrier layers 305, 307 can be formed during the formation of the first dielectric layer 103.

[0105] Please refer to the following: Figure 2 The solder pad layer 303 may be formed in the first dielectric layer 103. Solder pad barrier layers 305 and 307 may be formed correspondingly on and under the solder pad layer 303, respectively. In some embodiments, the top surface of the solder pad barrier layer 307 may be substantially coplanar with the top surface of the first dielectric layer 103. The top surface of the first bonding layer 105 may be referred to as the top surface of the first grain 100. The solder pad layer 303 may be formed of, for example, aluminum, copper, aluminum-copper alloys, aluminum alloys, copper alloys, or other suitable conductive materials. The solder pad barrier layers 305 and 307 may be formed of, for example, titanium, titanium nitride, tantalum nitride, or a titanium / titanium nitride bilayer material. The solder pad layer 303 and the barrier layers 305 and 307 may be patterned by, for example, a chemical vapor deposition, a physical vapor deposition, a vapor deposition, or a sputtering deposition process followed by a photolithography-etching process.

[0106] Please refer to the following: Figure 2The first bonding layer 105 may be formed on the first dielectric layer 103. In some embodiments, the first bonding layer 105 may be formed of an organic material, such as a material selected from undoped silicate glass, silicon nitride, silicon oxynitride, silicon oxide, silicon oxynitride, and combinations thereof. In some embodiments, the first bonding layer 105 may be formed of a polymer, such as epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, or similar materials. The first bonding layer 105 may be formed by a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating.

[0107] It should be understood that, in this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride refers to a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0108] Please refer to the following: Figure 2 The first dummy conductive layer 109 can be formed in the first bonding layer 105 through a damascene process. The top surface of the first dummy conductive layer 109 is substantially coplanar with the top surface of the first bonding layer 105. The first dummy conductive layer 109 can be made of the following materials: for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum carbide, magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0109] It should be understood that, in the description of this disclosure, referring to an element as a “virtual” element means that when semiconductor element 1A is in operation, no external voltage or current is applied to the element.

[0110] Please refer to the side. Figure 2 A second die 200 may have a structure similar to that of the first die 100. The second die 200 may include a second substrate 201, a second dielectric layer 203, a second bonding layer 205, components of a second element 207, and a second dummy conductive layer 209. Similar reference numerals between the first die 100 and the second die 200 may be formed from the same material and through similar processes, but this disclosure is not limited thereto. For example, the second substrate 201 may be formed from the same material as the first substrate 101.

[0111] Please refer to the following: Figure 2The second die 200 can be placed in an opposite orientation during the bonding process. That is, the first die 100 and the second die 200 can be bonded face-to-face. Specifically, during the bonding process, a second bonding layer 205 can be placed on the first die 100. The second dielectric layer 203 can be on the second bonding layer 205. The second substrate 201 can be on the second dielectric layer 203. The second dummy conductive layer 209 can be in the second bonding layer 205. The bottom surface of the second dummy conductive layer 209 is substantially coplanar with the bottom surface of the second bonding layer 205. In some embodiments, the second die 200 and the first die 100 are bonded back-to-back.

[0112] In some embodiments, a heat treatment may be performed during the bonding process to achieve hybrid bonding between the elements of the second die 200 and the first die 100. The temperature of the bonding process may be in the range of about 300°C to about 450°C. The hybrid bonding may include dielectric-to-dielectric bonding and / or metal-to-metal bonding. The dielectric-to-dielectric bonding may begin with bonding between the second bonding layer 205 and the first bonding layer 105. The metal-to-metal bonding may begin with bonding between the second dummy conductive layer 209 and the first dummy conductive layer 109. That is, the first dummy conductive layer 109 and the second dummy conductive layer 209 may facilitate bonding between the first die 100 and the second die 200 during the bonding process. In addition, the first dummy conductive layer 109 and the second dummy conductive layer 209 may respectively increase the mechanical strength of the first die 100 and the second die 200.

[0113] refer to Figure 1 and Figure 3 In step S13, a passivation layer 301 may be formed on the second grain 200.

[0114] refer to Figure 3 A thinning process can be performed on the second substrate 201 to reduce the thickness of the second substrate 201. The thinning process uses an etching process, a chemical polishing process, or a grinding process.

[0115] Please refer to the following: Figure 3The passivation layer 301 can be formed by a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, the passivation layer 301 can be formed of an organic material, such as a material selected from silicon nitride, silicon oxynitride, silicon oxide, silicon oxynitride, and combinations thereof. In some embodiments, the passivation layer 301 can be formed of a polymer, such as epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, or similar materials. In some embodiments, the passivation layer 301 can be formed of a material that has etch selectivity for the second grain 200 of the second substrate 201. In some embodiments, the passivation layer 301 can serve as a high vapor barrier to prevent moisture from entering from above. In some embodiments, the passivation layer 301 can serve as a hard masking layer during the formation of the opening through the substrate, the process of which will be described in detail later. In some embodiments, the passivation layer 301 can serve as a buffer layer to prevent metal-to-silicon leakage during the formation of a filler layer, the process of which will be described in detail later.

[0116] refer to Figure 1 and Figure 4 In step S15, a through-substrate opening 501 can be formed along the passivation layer 301 and the second grain 200 and extending to the top surface of the pad barrier layer 307.

[0117] refer to Figure 4 The through-substrate opening 501 can be formed using one or more etching processes, milling, electroforming techniques, or similar processes. A portion of the top surface of the solder pad barrier layer 307 can be exposed through the through-substrate opening 501. In some embodiments, the width W1 of the through-substrate opening 501 can range from approximately 5 μm to approximately 15 μm. In some embodiments, the through-substrate opening 501 can have a depth D1 ranging from approximately 20 μm to approximately 160 μm. Specifically, the depth D1 of the through-substrate opening 501 can range from approximately 50 μm to approximately 130 μm. In some embodiments, the through-substrate opening 501 can have an aspect ratio ranging from approximately 1:2 to approximately 1:35. Specifically, the aspect ratio of the through-substrate opening 501 can range from approximately 1:10 to approximately 1:25.

[0118] refer to Figure 1 and Figure 5 In step S17, an isolation layer 401 is conformally formed in the through-substrate opening 501.

[0119] refer to Figure 5Specifically, the isolation layer 401 may be conformally formed in the through-substrate opening 501 and may be conformally formed on the top surface of the passivation layer 301. In some embodiments, the isolation layer 401 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate, or combinations thereof. The isolation layer 401 may have a thickness in the range of about 50 nm to about 200 nm. The isolation layer 401 may be formed by, for example, chemical vapor deposition or plasma-enhanced chemical vapor deposition. In some embodiments, the isolation layer 401 may be formed of, for example, parylene, epoxy resin, or parylene. The isolation layer 401 may have a thickness in the range of about 1 μm to about 5 μm. The isolation layer 401 may be formed by a spin-coating process having a coating and subsequent curing.

[0120] refer to Figure 1 and Figure 6 In step 19, a punching etching process may be performed to expose a portion of the top surface of the pad layer 303.

[0121] refer to Figure 6 In this punching and etching process, the isolation layer 401 formed on the top surface of the solder pad barrier layer 307 can be removed, and the portion of the solder pad barrier layer 307 exposed after the isolation layer 401 formed on the top surface of the solder pad layer 303 is removed can be removed. As a result, a portion of the top surface of the solder pad layer 303 can be exposed.

[0122] The punching etching process can be an anisotropic etching process, such as an anisotropic dry etching process, so that the through-substrate opening 501 formed on the sidewall of the isolation layer 401 can remain intact. After the punching etching process, the isolation layer 401 can be divided into multiple parts. In some embodiments, the etching rate of the punching etching process of the isolation layer 401 can be faster than the etching rate of the punching etching process of the passivation layer 301 to avoid damage to the silicon / hard mask layer interface. In some embodiments, the etching rate of the punching etching process of the pad barrier layer 307 can be faster than the etching rate of the punching etching process of the pad layer 303. The isolation layer 401 can electrically isolate a filler layer (to be formed later) formed in the passivation layer 301, the second grain 200, and the first bonding layer 105. In some embodiments, the isolation layer 401 formed on the top surface of the passivation layer 301 can also be removed during the punching etching process. Figure 6 (Not shown in the image).

[0123] refer to Figure 1 and Figure 7 In step S21, an isotropic etching process can be performed to form a recessed space 503 in the pad layer 303.

[0124] refer to Figure 7In some embodiments, the etch rate of isotropic etching of the solder pad layer 303 may be faster than the etch rate of isotropic etching of the isolation layer 401. For example, during isotropic etching, the etch rate ratio of the solder pad layer 303 to the isolation layer 401 may be in the range of approximately 100:1 to approximately 1.05:1. As another example, during isotropic etching, the etch rate ratio of the solder pad layer 303 to the isolation layer 401 may be in the range of approximately 20:1 to approximately 10:1.

[0125] Please refer to the following: Figure 7 A recessed space 503 can be formed by extending downward from the through-base opening 501. A depth D2 of the recessed space 503 is the vertical distance between the bottom surface of the solder pad barrier layer 307 and a bottom surface 503BS of the recessed space 503. The depth D2 can be greater than half the thickness T1 of the solder pad layer 303 and less than the thickness T1 of the solder pad layer 303. A horizontal distance H1 between a sidewall 401S of the isolation layer 401 and a sidewall 503S of the recessed space 503 can be equal to or less than the depth D2 of the recessed space 503. In some embodiments, the bottom surface 503BS and the sidewall 503S of the recessed space 503 are flat surfaces. In some embodiments, the bottom surface 503BS and the sidewall 503S of the recessed space 503 are curved surfaces. In some embodiments, the intersection point of the bottom surface 503BS and the sidewall 503S of the recessed space 503 is curved. The intersection point is a bend, which can avoid the corner effect.

[0126] refer to Figure 1 and Figure 8 In step 23, a barrier layer 403 is conventionally formed in the through-base opening 501 and the recessed space 50.

[0127] refer to Figure 8 The barrier layer 307 can be formed on the top surface of the isolation layer 401, the sidewall 401S of the isolation layer 401, the sidewall of the solder pad barrier layer 307, the sidewall 503S of the recessed space 503, and the bottom surface 503BS of the recessed space 503. The barrier layer 403 formed on the top surface of the recessed space 503 of the isolation layer 401 can be referred to as the cover portion 403C of the barrier layer 403. The barrier layer 403 formed on the sidewall 401S of the isolation layer 401 and the sidewall of the solder pad barrier layer 307 can be referred to as the upper portion 403U of the barrier layer 403. The barrier layer 403 formed on the sidewall 503S of the recessed space 503 and the bottom surface 503BS of the recessed space 503 can be referred to as the recess 403R of the barrier layer 403.

[0128] For example, the barrier layer 403 may be formed of tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum bilayer material. The barrier layer 403 may be formed by a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering. The barrier layer 403 may inhibit the diffusion of conductive material from a filler layer (to be fabricated later) into the passivation layer 301, the second grain 200, and the first bonding layer 105. Furthermore, the recesses 403R of the barrier layer 403 may increase the contact surface between the barrier layer 403 and the pad layer 303. Therefore, the contact resistance of the barrier layer 403 may be reduced. Thus, the reliability of the semiconductor device 1A may be improved.

[0129] Conversely, if the recessed space 503 is not formed, the barrier layer 403 is formed directly on the exposed portion of the solder pad layer 303 in the through-substrate opening 501. In this case, the contact surface between the barrier layer 403 and the solder pad layer 303 is smaller than the contact surface between the recessed portion 403R of the barrier layer 403 and the solder pad layer 303. Therefore, the contact resistance of the barrier layer 403 is higher, and reliability-related issues will be amplified.

[0130] Please refer to the following: Figure 8 An adhesion layer (not shown for clarity) may be conformally formed on the barrier layer 403 and in the through-substrate opening 501 and recess 503. This adhesion layer may be made of a material such as titanium, tantalum, titanium-tungsten, or manganese nitride. The adhesion layer may be formed by a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering. The adhesion layer may improve the bonding between a sublayer (described in detail later) and the barrier layer 403.

[0131] Please refer to the following: Figure 8 A seed layer (not shown for clarity) can be conventionally formed on the adhesion layer and in the through-substrate opening 501 and recessed space 503. The seed layer can have a thickness ranging from approximately 10 nm to approximately 40 nm. The seed layer can be formed, for example, from copper. The seed layer can be formed by a deposition process, such as a physical vapor deposition process, an atomic layer deposition process, a chemical vapor deposition process, or a sputtering process. The seed layer can reduce the resistivity of the through-substrate opening 501 and recessed space 503 during the formation of a fill layer.

[0132] refer to Figure 1 , Figure 9 and Figure 10 In step 25, a filling layer 405 may be formed in the through-substrate opening 501 and recessed space 50.

[0133] refer to Figure 9A layer of conductive material 505 can be formed to completely fill the through-substrate opening 501 and recessed space 503 and cover the cover portion 403C of the barrier layer 403. The conductive material 505 can be formed from, for example, polycrystalline silicon, tungsten, copper, carbon nanotubes, or tin alloy. This layer of conductive material 505 can be formed by an electroplating process, a physical vapor deposition process, a chemical vapor deposition process, or a sputtering process.

[0134] For example, a layer of conductive material 505 can be formed in the through-substrate opening 501 and recessed space 503 by electroplating in an acid bath containing copper sulfate, sulfuric acid, sodium chloride, inhibitor, accelerator, and leveling agent. The inhibitor interacts with chloride ions to inhibit copper deposition. The accelerator can be adsorbed onto the electrode surface, where it gradually replaces the inhibitor, thus enabling copper electroplating. The leveling agent can be used to improve filling efficiency, reduce surface roughness, and prevent copper deposition on the upper part of the through-substrate opening 501. The inhibitor can be, for example, a polymer of polyethylene glycol. The accelerator and leveling agent can be, for example, 3-mercapto-1-propanesulfonate, (3-sulfopropylpropyl) disulfide, or 3,3-thiobis(1-propanesulfonate).

[0135] In some embodiments, it may be possible Figure 9 An annealing process is performed on the intermediate semiconductor device shown. This annealing process can reduce the adverse effects of copper-pumping during subsequent semiconductor processes, improve the adhesion between the conductive material 505 layer and the isolation layer 401, and stabilize the microstructure of the conductive material 505 layer.

[0136] refer to Figure 10 A planarization process, such as chemical mechanical polishing or grinding, may be performed until the insulating layer 401 is exposed to remove excess material, providing a substantially flat surface for subsequent processing steps, and simultaneously transforming the layer of conductive material 505 into a filler layer 405. In some embodiments, a planarization process may be performed until the passivation layer 301 is exposed. In some embodiments, the planarization process may be performed until the second substrate 201 is exposed.

[0137] Please refer to the following: Figure 10 The filler layer 405 formed in the through-substrate opening 501 can be referred to as the upper portion 405U of the filler layer 405. The filler layer 405 formed in the recessed space 503 can be referred to as the recessed portion 405R of the filler layer 405. A depth D3 of the recessed portion 405R can be greater than half the thickness T1 of the solder pad layer 303 and less than the thickness T1 of the solder pad layer 303. A horizontal distance H2 between a sidewall 405US of the upper portion 405U and a sidewall 405RS of the recessed portion 405R can be equal to or less than the depth D3 of the upper portion 405U.

[0138] It should be understood that the same or similar reference numerals used throughout the drawings are used to indicate the same or similar features, elements or structures, therefore, detailed descriptions of the same or similar features, elements or structures in each drawing will not be repeated.

[0139] Figures 11 to 14 This is a cross-sectional schematic diagram of the fabrication process of a semiconductor element 1B according to another embodiment of the present disclosure.

[0140] refer to Figure 11 An intermediate semiconductor device can be made from Figures 2 to 4 The process shown is used to fabricate the structure. An extended etching process can be performed to extend the through-substrate opening 501 in the passivation layer 301. During the extended etching process, the etch rate ratio of the passivation layer 301 to the second substrate 201 of the second grain 200 can be in the range of approximately 100:1 to approximately 1.05:1. In some embodiments, the extended etching process is a wet etching process using a wet etching solution. The wet etching solution is a hydrofluoric acid solution that may have a 6:1 buffered oxide etchant and includes 7% w / w (mass percentage) hydrofluoric acid, 34% w / w ammonium fluoride, and 59% w / w water. In some embodiments, the extended etching process is a dry etching process using a gas selected from the group consisting of CH2F2, CHF3, and C4F8.

[0141] Following this extended etching process, the width of the through-substrate opening 501 in the passivation layer 301 can be increased, while the width of the through-substrate opening 501 in the second grain 200 or the first grain 100 can remain unchanged. As a result, after the extended etching process, the sidewalls of the through-substrate opening 501 in the passivation layer 301 can gradually taper. The increased through-substrate opening 501 in the passivation layer 301 provides an improved tolerance range for void-free filling layer formation, wherein this improved tolerance range eliminates the adverse effects of the faster deposition rate from the through-substrate opening 501 in the passivation layer 301 by providing additional space.

[0142] refer to Figure 12 The isolation layer 401 can be conformally formed in the through-substrate opening 501 and can also be conformally formed on the top surface of the passivation layer 301. The interface IF01 between the passivation layer 301 and the isolation layer 401 is conical. The sidewall 401S of the isolation layer 401 in the passivation layer 301 is also conical. The isolation layer 401 can be made using a similar... Figure 5 The process shown is formed. The angle α between the top surface 301TS of the passivation layer 301 and the interface IF01 (between the passivation layer 301 and the isolation layer 401) can be in the range of approximately 120 degrees to 135 degrees.

[0143] refer to Figure 13The punching and etching process can be performed to expose a portion of the top surface of the pad layer 303. Since the isolation layer 401 is formed on the interface IF01 (between the passivation layer 301 and the isolation layer 401) and on the top surface of the passivation layer 301, it can have a greater thickness compared to the thickness of the isolation layer 401 formed on the top surface of the pad barrier layer 307. Therefore, the isolation layer 401 formed on the interface IF01 (between the passivation layer 301 and the isolation layer 401) and on the top surface of the passivation layer 301 can be thinned only after the punching and etching process.

[0144] refer to Figure 14 The barrier layer 403, the attachment layer, the seed layer, and the filler layer 405 can be seen from Figure 7. Figure 10 The process shown is similar to that of manufacturing.

[0145] Figures 15 to 17 This is a cross-sectional schematic diagram of the fabrication process of a semiconductor device 1C according to another embodiment of the present disclosure.

[0146] refer to Figure 15 It can provide Figure 12 An intermediate semiconductor device as described herein is capable of undergoing a punch-etch process. After this punch-etch process, a portion of the top surface of the pad layer 303 is exposed, and the isolation layer 401 formed on the interface IF01 (between the passivation layer 301 and the isolation layer 401) and the isolation layer 401 formed on the top surface of the passivation layer 301 can be removed. The highest point 401TP of the isolation layer 401 may be at a vertical height equal to or lower than the top surface 201TS of the second substrate 201. The vertical height of the highest point 401TP of the isolation layer 401 is lower than the vertical height of the top surface 201TS of the second substrate 201. During the formation of the fill layer 405, metal-to-silicon leakage may occur.

[0147] refer to Figure 16 A protective layer 309 can be formed to cover the upper part of the isolation layer 401. The protective layer 309 can be formed by a deposition process, such as atomic layer deposition, which precisely controls the amount of the first precursor of the atomic layer deposition process. For example, the protective layer 309 can be formed of, for example, alumina, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

[0148] In some embodiments, when the protective layer 309 is formed of alumina, the first precursor of the atomic layer deposition method is trimethylaluminum, and the second precursor of the atomic layer deposition method is water or ozone.

[0149] In some embodiments, when the protective layer 309 is formed of hafnium oxide, the first precursor of the atomic layer deposition method is hafnium tetrachloride, hafnium tert-butoxide, hafnium diformamide, hafnium ethylformamide, hafnium diacetamide, or hafnium methoxytert-butoxide, and the second precursor of the atomic layer deposition method is water or ozone.

[0150] In some embodiments, when the protective layer 309 is formed of zirconium oxide, the first precursor of the atomic layer deposition method is zirconium tetrachloride, and the second precursor of the atomic layer deposition method is water or ozone.

[0151] In some embodiments, when the protective layer 309 is formed of titanium oxide, the first precursor of the atomic layer deposition method may be titanium tetrachloride, tetraethyl titanate or titanium isopropoxide, and the second precursor of the atomic layer deposition method may be water or ozone.

[0152] In some embodiments, when the protective layer 309 is formed of titanium nitride, the first precursor of the atomic layer deposition method is titanium tetrachloride and ammonia.

[0153] In some embodiments, when the protective layer 309 is formed of tungsten nitride, the first precursor of the atomic layer deposition method is tungsten hexafluoride and ammonia.

[0154] In some embodiments, when the protective layer 309 is formed of silicon nitride, the first precursor of the atomic layer deposition method is methylene silane, chlorine, ammonia and / or dinitrogen tetrahydrofuran.

[0155] In some embodiments, when the protective layer 309 is formed of silicon oxide, the first precursor of the atomic layer deposition method is tetraisocyanate or CH3OSi(NCO)3, and the second precursor of the atomic layer deposition method is hydrogen or ozone.

[0156] Because of the tapered sidewalls of the passivation layer 301 that penetrate the substrate opening 501, the sidewalls 309S of the protective layer 309 can be substantially vertical. The protective layer 309 can provide additional protection to the passivation layer 301 and the second die 200 during subsequent semiconductor processing. Therefore, metal-to-silicon leakage can be avoided during the formation of the fill layer 405. Consequently, the performance / yield of the semiconductor device 1C can be improved.

[0157] It should be understood that in the description of this disclosure, if there is a vertical plane, then the surface (or sidewall) is "vertical" and the deviation of the surface from the vertical plane does not exceed three times the square root of the surface roughness.

[0158] refer to Figure 17 The barrier layer 403, the attachment layer, the seed layer, and the filler layer 405 can be seen from Figure 7. Figure 10 The process is similar to that shown. In some embodiments, such as Figure 10 The planarization process shown can be performed until the protective layer 309 is exposed. In some embodiments, such as Figure 10 The planarization process shown can be performed until the passivation layer 301 is exposed. In some embodiments, such as Figure 10 The planarization process shown can be performed until the second substrate 201 is exposed.

[0159] Furthermore, the presence of the protective layer 309 reduces the deposition rate of the conductive material 505 on the sidewalls of the through-substrate opening 501. Therefore, the deposition rate of the conductive material 505 on the sidewalls of the conductive material layer 505 can be close to the deposition rate of the conductive material 505 in the recessed space 503. Thus, the through-substrate opening 501 and the recessed space 503 can be filled without any voids forming, improving the yield of the semiconductor device 1C.

[0160] Figure 18 This is a cross-sectional schematic diagram of a semiconductor device 1D according to another embodiment of the present disclosure.

[0161] refer to Figure 18 Semiconductor element 1D can be connected to... Figures 2 to 10 The process shown is formed as follows. The main difference is that the pad layer 303 and the pad barrier layers 305 and 307 are formed in the first bonding layer 105 of the first die 100, instead of forming the pad layer 303 and the pad barrier layer 305 in the first dielectric layer 103 of the first die 100. The top surface of the pad barrier layer 307 may be substantially coplanar with the top surface of the first bonding layer 105.

[0162] One embodiment of this disclosure provides a semiconductor device including a first die, a second die, a pad layer, a fill layer, and a barrier layer. The second die is disposed on the first die. The pad layer is disposed in the first die. The fill layer includes an upper portion and a recessed portion. The barrier layer is disposed between the second die and the upper portion of the fill layer, between the first die and the upper portion of the fill layer, and between the pad layer and the recessed portion of the fill layer. The upper portion of the fill layer is disposed along the second die and the first die, and the recessed portion of the fill layer extends from the upper portion and is disposed in the pad layer.

[0163] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, comprising: performing a bonding process to bond a second die to a first die having a pad layer; forming a through-substrate opening along the second die extending into the first die of the pad layer; conformally forming an isolation layer in the through-substrate opening; performing a punching etching process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer; performing an isotropic etching process to form a recessed space extending from the through-substrate opening into the pad layer; conformally forming a barrier layer in the through-substrate opening and the recessed space; and forming a barrier layer in the through-substrate opening and the recessed space.

[0164] Due to the design of the semiconductor device disclosed herein, the upper portion 405U of the fill layer 405 can increase the contact surface between the fill layer 405 and the barrier layer 403, thereby reducing the contact resistance of the barrier layer 403. Therefore, the reliability of the semiconductor device 1A can be improved. Furthermore, due to the geometry of the protective layer 309, a fill layer 405 without any gaps can be formed. Therefore, the manufacturing yield of the semiconductor device 1C can be improved.

[0165] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0166] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: a first die; a second die disposed on the first die; a pad layer disposed in the first die; a fill layer including an upper portion and a recessed portion, wherein the upper portion of the fill layer is disposed along the second die and the first die, and the recessed portion of the fill layer extends from the upper portion and is disposed in the pad layer; and a barrier layer disposed between the second die and the upper portion of the fill layer, and between the first die and the upper portion of the fill layer, and between the pad layer and the recessed portion of the fill layer, the semiconductor device further comprising an isolation layer disposed between the second die and the upper portion of the fill layer, and between the first die and the upper portion of the fill layer, the semiconductor device further comprising a protective layer to cover an upper portion of the isolation layer, wherein a shape of the fill layer narrows at the protective layer.

2. The semiconductor device of claim 1, wherein a depth of the recessed portion of the fill layer is greater than half a thickness of the pad layer and less than the thickness of the pad layer.

3. The semiconductor device of claim 2, wherein a horizontal distance between a sidewall of the upper portion of the fill layer and a sidewall of the recessed portion of the fill layer is equal to or less than the depth of the recessed portion of the fill layer.

4. The semiconductor device of claim 3, wherein the sidewall of the recessed portion of the fill layer is curved.

5. The semiconductor device of claim 3, wherein a bottom surface of the recessed portion of the fill layer is curved.

6. The semiconductor device of claim 1, further comprising a passivation layer disposed on the second die, and the upper portion of the fill layer is disposed along the passivation layer, the second die, and the first die, wherein the passivation layer is formed of silicon nitride, silicon oxynitride, silicon oxide, silicon oxynitride, epoxy, polyimide, benzocyclobutene, or polybenzoxazole.

7. The semiconductor device of claim 6, further comprising an adhesion layer disposed between the fill layer and the barrier layer, wherein the adhesion layer is formed of titanium, tantalum, titanium tungsten, or manganese nitride.

8. The semiconductor device of claim 7, further comprising a seed layer disposed between the adhesion layer and the fill layer, wherein a thickness of the seed layer is in a range of about 10 nm to about 40 nm.

9. The semiconductor device of claim 8, further comprising a pad barrier layer disposed on and under the pad layer, respectively.

10. The semiconductor device of claim 9, wherein an interface between the passivation layer and the upper portion of the fill layer is tapered.

11. The semiconductor device of claim 10, wherein an angle between a top surface of the passivation layer and an interface is in a range of about 120 degrees to 135 degrees, wherein the interface is between the passivation layer and the upper portion of the fill layer.

12. The semiconductor device of claim 11, wherein the fill layer is formed of polysilicon, tungsten, copper, carbon nanotube, or solder alloy.

13. The semiconductor device of claim 12, wherein the isolation layer is formed of silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate. ​ ​ ​ ​ ​ ​ ​ ​ 14. A method for fabricating a semiconductor device, comprising: performing a bonding process to bond a second die to a first die having a pad layer; forming a through-substrate opening along the second die extending into the pad layer of the first die; conformally forming an isolation layer in the through-substrate opening; performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer; performing an isotropic etch process to form a recessed space extending from the through-substrate opening and in the pad layer; conformally forming a barrier layer in the through-substrate opening and in the recessed space; and forming a barrier layer in the through-substrate opening and in the recessed space, forming a protective layer to cover an upper portion of the isolation layer, forming a fill layer including an upper portion and a recessed portion, wherein the upper portion of the fill layer is disposed along the second die and the first die, and the recessed portion of the fill layer extends from the upper portion and is disposed in the pad layer, wherein a shape of the fill layer narrows at the protective layer.

15. The method of claim 14, wherein the isotropic etch has an etch rate ratio of the pad layer to the isolation layer in a range of about 100: 1 to about 1.05:

1.

16. The method of claim 15, wherein the isolation layer is formed of silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate.

17. The method of claim 15, wherein the fill layer is formed of polysilicon, tungsten, copper, carbon nanotube, or solder alloy.

18. The method of claim 17, further comprising a step of forming a passivation layer on the second die, wherein the through-substrate opening is formed along the passivation layer and the second die and extends into the pad layer of the first die.

19. The method of claim 18, wherein the passivation layer is formed of silicon nitride, silicon oxynitride, silicon oxide, silicon oxynitride, epoxy, polyimide, benzocyclobutene, or polybenzoxazole.

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