Three-node access device for vertical three-dimensional (3d) memory

Abstract

This disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access means and vertically oriented access lines, comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack, wherein a first portion of the sacrificial material is located in a first region of the vertical stack in which first and second source / drain regions laterally separated by channel regions are formed; forming a first vertical opening using an etchant process to expose a vertical sidewall in the vertical stack adjacent to the first portion of the sacrificial material; selectively etching the first portion of the sacrificial material to form a first horizontal opening, thereby removing sacrificial material in the first region at a first horizontal distance backward from the first vertical opening; and depositing first and second source / drain materials and channel material in the first horizontal opening to form a three-node access means for memory cells in the array of vertically stacked memory cells.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more particularly to the formation and structure of a three-node access device for a vertical three-dimensional (3D) memory. Background Technology

[0002] Memory is typically implemented in electronic systems such as computers, mobile phones, and handheld devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is applied and can include NAND flash memory, NOR flash memory, Nnitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), etc.

[0003] With the shrinking of design rules, the semiconductor space available for manufacturing memory (including DRAM arrays) has decreased. Individual memory cells for DRAM may contain access means, such as transistors, of first and second source / drain regions separated by a channel region. A gate may be opposite to the channel region and may be separated from it by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell may contain memory nodes, such as capacitor cells, coupled to the digit lines via access means. Access means may be activated (e.g., to select a cell) via access lines coupled to access transistors. Capacitors may store charge corresponding to the data values ​​(e.g., logic "1" or "0") of the individual cells. Summary of the Invention

[0004] In one aspect, this disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack, wherein a first portion of the sacrificial material is located in a first region of the vertical stack in which a first source / drain region and a second source / drain region are formed, which are laterally separated by a channel region; forming a first vertical opening using an etchant process to expose a vertical sidewall in the vertical stack adjacent to the first portion of the sacrificial material; selectively etching the first portion of the sacrificial material to form a first horizontal opening, thereby removing the sacrificial material in the first region at a first horizontal distance backward from the first vertical opening; and depositing a first source / drain material, a channel material, and a second source / drain material in the first horizontal opening to form a three-node access device for the memory cells in the array of vertically stacked memory cells.

[0005] In another aspect, this disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access means and vertically oriented access lines, the method comprising: depositing alternating layers of dielectric material and sacrificial material in repeated iterations to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack and primarily in the second horizontal direction to form elongated vertical pillars with sidewalls in the vertical stack; conformally depositing a first conductive material on the gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical pillars; and forming vertical stacks that primarily extend in the first horizontal direction and expose the vertical stack. A second vertical opening is formed in the stack of the vertically stacked memory cells. The first region of the sacrificial material is selectively etched to form a first horizontal opening, thereby removing the sacrificial material a first horizontal distance backward from the second vertical opening. A first source / drain region, a channel region, and a second source / drain region are sequentially formed in the first horizontal opening to form a three-node access device for the memory cells in the array of vertically stacked memory cells without body contact. A third vertical opening is formed through the vertical stack to expose the sidewall of the vertical stack adjacent to the second region of the sacrificial material. The second region of the sacrificial material is selectively etched to form a second horizontal opening in which a memory node electrically coupled to the first source / drain region is formed.

[0006] In a further aspect, this disclosure relates to a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising: depositing alternating layers of dielectric material and sacrificial material to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack to a substrate and primarily in the second horizontal direction, using a first etchant process to form elongated vertical pillars with sidewalls in the vertical stack; conformally depositing a first conductive material on the gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical pillars; and forming through the vertical stack using a second etchant process. The second vertical opening extends primarily in the first horizontal direction to expose a second sidewall adjacent to a first region of the sacrificial material; the first region is selectively removed to form a first horizontal opening in which a first source / drain region, a channel region, and a second source / drain region are sequentially formed, thereby forming a three-node access device for memory cells in an array of vertically stacked memory cells; a third vertical opening is formed through the vertical stack and extends primarily in the first horizontal direction using a third etchant process to expose a third sidewall in the vertical stack adjacent to a second region of the sacrificial material; and the second region is selectively removed to form a second horizontal opening in which memory nodes are formed before the formation of the first source / drain region, the channel region, and the second source / drain region.

[0007] In a further aspect, this disclosure relates to a memory device having horizontally oriented access means and vertically oriented access lines, the device comprising: an array of vertically stacked memory cells, the array of vertically stacked memory cells comprising: a horizontally oriented three-node access means having a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite to the channel region and separated from it by a gate dielectric, the three-node access means having no direct electrical body contact with the body region of the three-node access means or the channel region; vertically oriented access lines coupled to the gate and separated from the channel region by the gate dielectric; horizontally oriented memory nodes electrically coupled to the first source / drain region of the three-node access means; and horizontally oriented digit lines electrically coupled to the second source / drain region of the three-node access means. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0009] Figure 2 This is a perspective view showing a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to several embodiments of the present disclosure.

[0010] Figure 3 This is a perspective view showing a portion of a three-node access device in a vertical three-dimensional (3D) memory cell according to various embodiments of the present disclosure.

[0011] Figure 4 An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in a stage of a semiconductor manufacturing process to form a three-node access device.

[0012] Figures 5A to 5B An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having a three-node horizontally oriented access device.

[0013] Figures 6A to 6E An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having three horizontally oriented access devices and vertically oriented access lines.

[0014] Figures 7A to 7E An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having three horizontally oriented access devices and vertically oriented access lines.

[0015] Figures 8A to 8E An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having three horizontally oriented access devices and vertically oriented access lines.

[0016] Figures 9A to 9E An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having three horizontally oriented access devices and vertically oriented access lines.

[0017] Figure 10 Examples of three-node horizontally oriented access devices according to various embodiments of the present disclosure are shown, the three-node horizontally oriented access devices being coupled to horizontally oriented memory nodes and to vertically oriented access lines and horizontally oriented digital lines.

[0018] Figure 11 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure describe a three-node access device for a vertical three-dimensional (3D) memory. The three-node horizontal access device is formed without body region contacts. As used herein, three-node is intended to refer to an access device comprising: (1) a first source / drain region and (2) a second source / drain region separated by a channel region, and (3) one or more gates opposite the channel regions. In the three-node access device, there are no direct electrical contacts from the body contact line to the body region and / or channel of the access device to control the body region or channel of the access device. As a result, semiconductor manufacturing overhead is reduced because such body contacts do not need to be formed. The three-node horizontal access device is integrated with vertical access lines and with horizontal digit lines. According to embodiments, the three-node horizontal access device can be configured such that the channel region has fewer minority carriers, for example, it can operate without minority carriers, thereby eliminating the need to control the body potential of the body region of the access device. The advantages of the structure and process described herein may include: reduced access device cutoff current (Ioff) compared to silicon-based (Si-based) access devices; and / or reduced access device gate / drain leakage (GIDL).

[0020] In some embodiments, channel and / or source / drain region replacement manufacturing steps can be performed after the capacitor cell formation process, thereby reducing the thermal budget. Since there is no body contact with the body region of the access device, integration of the digit lines can be more easily achieved during manufacturing. Additionally, due to the shorter channel length and lower source / drain semiconductor manufacturing process overhead, the embodiments described herein can achieve a better lateral scaling path than that achieved with channel regions based on doped polysilicon. A further advantage is the avoidance (e.g., no use) of gas phase doping (GPD) in the formation of the source / drain regions.

[0021] The figures in this document follow the following numbering conventions, where the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. For example, figure numeral 104 can refer to... Figure 1 The element "04" in the text, and similar elements can be found in the text. Figure 2 Reference 204 is used in the figure. Multiple similar elements in a figure can be referenced using a figure number followed by a hyphen and another number or letter. For example, 302-1 can be referenced... Figure 3Component 302-1 can be referenced as 302-2, while 302-2 can refer to component 302-2, which may be similar to component 302-1. Such similar components can generally be referenced without hyphens and additional numbers or letters. For example, components 302-1 and 302-2, or other similar components, can generally be referenced as 302.

[0022] Figure 1 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 1 A circuit diagram showing a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure is shown. Figure 1 The diagram illustrates that a cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each sub-cell array, for example, sub-cell array 101-2, can contain multiple access lines 103-1, 103-2, ..., 103-Q (also referred to as word lines). Furthermore, each sub-cell array, for example, sub-cell array 101-2, can contain multiple bit lines 107-1, 107-2, ..., 107-P (also referred to as bit lines, data lines, or read lines). Figure 1 The diagram illustrates digital lines 107-1, 107-2, ..., 107-P extending in a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal plane (“XY”). The third direction (D3) 111 can be considered to be in a vertical plane (“Z”). Therefore, according to the embodiment described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0023] Memory cells, such as 110, may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 103-1, 103-2, ..., 103-Q and each digit line 107-1, 107-2, ..., 107-P. Memory cells can be written to or read from using access lines 103-1, 103-2, ..., 103-Q and digit lines 107-1, 107-2, ..., 107-P. Digital lines 107-1, 107-2, ..., 107-P can electrically interconnect memory cells along the horizontal columns of each sub-cell array 101-1, 101-2, ..., 101-N, and access lines 103-1, 103-2, ..., 103-Q can electrically interconnect memory cells along the vertical rows of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell, such as 110, can be located between one access line (e.g., 103-2) and one digital line (e.g., 107-2). Each memory cell can be uniquely addressed through the combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-P.

[0024] The digit lines 107-1, 107-2, ..., 107-P can be or may include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. The digit lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. The digit lines 107-1, 107-2, ..., 107-P in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., a third direction (D3) 111).

[0025] Access lines 103-1, 103-2, ..., 103-Q may be or may include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., on a third direction (D3) 111) relative to the substrate. Access lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0026] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line, such as 103-2, and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a digit line, such as 107-2. Each of the memory cells (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to "first" and "second" source / drain regions are used herein to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have any unique meaning. Rather, it simply means that one of the source / drain regions is connected to a digit line, such as 107-2, while the other may be connected to a storage node.

[0027] Figure 2 Perspective views of a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure are shown, for example, Figure 1 A portion of the sub-cell array 101-2 shown is a vertically oriented stack of memory cells in the array. Figure 3 The display shows Figure 2 The unit cell of the 3D semiconductor memory device shown (e.g., Figure 1 A perspective view of the memory cell 110 shown.

[0028] like Figure 2 As shown, a bonding can be formed on the substrate 200. Figure 1 One of the described arrays of sub-cells, such as 101-2. For example, substrate 200 may be or may comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0029] like Figure 2 As shown in the example embodiment, a memory cell (e.g.,) may be fabricated on the substrate 200. Figure 1 A vertically oriented stack of memory cells 110, the stack extending in a vertical direction (e.g., third direction (D3) 111). According to some embodiments, the vertically oriented stack of memory cells can be manufactured such that each memory cell (e.g., Figure 1 The memory cells 110 are formed on multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3). Repeating vertical levels L1, L2, and L3 can be arranged vertically (e.g., ...). Figure 1The third-order (D3) 111 arrangement shown is, for example, “stacked”. Each of the repeating vertical hierarchies L1, L2, and L3 may include multiple discrete components (e.g., regions) of the access device 230 (e.g., transistors) with a lateral orientation, and memory nodes (e.g., capacitors), including access lines 103-1, 103-2, ..., 103-Q connections and digit lines 107-1, 107-2, ..., 107-P connections. The horizontally oriented three-node access device (e.g., Figure 1 Multiple discrete components of transistor 110 can be formed within each level during multiple iterative vertical repeating layers, as shown in the following combination. Figure 4 More detailed descriptions are available, and can be found in similar formats. Figure 1 The second direction (D2)105 shown extends horizontally on the second direction (D2)205.

[0030] A plurality of discrete components of a horizontally oriented three-node access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225, both extending laterally in a second direction (D2) 205. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first and second source / drain regions 221 and 223 may comprise n-type doped regions (e.g., semiconductor materials) formed adjacent to p-type doped channel regions (e.g., semiconductor materials) of the access device to form n-type conductive transistors. In some embodiments, the first and second source / drain regions 221 and 223 may comprise p-type conductive portions (e.g., doped semiconductor materials) formed adjacent to n-type conductive channel regions (e.g., doped semiconductor materials) of the access device to form p-type conductive transistors. By way of example, and not limitation, the n-type dopant may comprise phosphorus (P) atoms, while the p-type dopant may comprise boron (B) atoms formed in a relatively doped bulk region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0031] Storage node 227, such as a capacitor, can be connected to a corresponding terminal of the access device. Figure 2 As shown, storage node 227, such as a capacitor, can be connected to the second source / drain region 223 of the access device. A storage node can be or may contain a memory element capable of storing data. Each of the storage nodes can be a memory element using one of the following: a capacitor, a magnetic tunnel connection pattern, and / or a variable resistivity comprising a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1The memory node associated with each access device of the memory cell 110 in the second direction (D2) 205 can be similarly located in the second direction (D2) 205 (similar to Figure 1 It extends in the second direction (D2)105 shown.

[0032] like Figure 2 As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extend along the first direction (D1) 209, similar to... Figure 1 The first direction (D1) is 109. Multiple horizontally oriented digit lines 207-1, 207-2, ..., 207-P can be connected with... Figure 1 Similar to 107-1, 107-2, ..., 107-P shown. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P can be arranged along a third direction (D3) 211, for example, "stacked". Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P can contain conductive materials. For example, the conductive material can contain one or more of doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0033] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-M, the horizontally oriented memory cells (e.g., Figure 1 The memory cells 110 in the memory can be horizontally spaced apart from each other in the first direction (D1) 209. However, as combined below Figure 4As described in more detail, a plurality of discrete components (e.g., a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225) extending laterally in the second direction (D2) 205 can be formed in different vertical layers within each level of the laterally oriented access device 230, and a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in the first direction (D1) 209. For example, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in the first direction (D1) 209 can be disposed on and electrically contacted on the top surface of the first source / drain region 221, and orthogonal to the laterally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 are formed in a vertical layer at a higher level (e.g., layer (L1)) than the layer forming discrete components (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225). In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be directly connected to the top surface of the first source / drain region 221 and / or connected via additional contacts comprising metal silicide.

[0034] like Figure 2 As shown in the example embodiment, access lines 203-1, 203-2, ..., 203-Q extend vertically relative to substrate 200 (e.g., on third-direction (D3) 211). Further, as... Figure 2 As shown, a sub-cell array (e.g., Figure 1 Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 101-2 can be spaced apart from each other in the first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be provided that extend vertically relative to the substrate 200 in the third direction (D3) 211 between a pair of horizontally oriented three-node access devices 230 (e.g., transistors) extending laterally in the second direction (D2) 205, but are adjacent to each other in the first direction (D1) 209 at a certain level (e.g., the first level (L1)). Each of the access lines 203-1, 203-2, ..., 203-Q can extend vertically in the third direction (D3) on the sidewall of a corresponding one of a plurality of vertically stacked horizontally oriented three-node access devices 230 (e.g., transistors).

[0035] For example, such as Figure 3 As shown in more detail, the first of the vertically extending access lines (e.g., 203-1) can make the sidewall of the channel region 225 adjacent to the sidewall of the first of the horizontally oriented three-node access devices 230 (e.g., transistors) in the first level (L1) 213-1, the sidewall of the first of the horizontally oriented three-node access devices 230 (e.g., transistors) in the second level (L2) 213-2, and the sidewall of the first of the horizontally oriented three-node access devices 230 (e.g., transistors) in the third level (L3) 213-M. Similarly, the second vertically extending access line (e.g., 203-2) may have its sidewall adjacent to the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the first level (L1) 213-1, and spaced apart from the first horizontally oriented three-node access device 230 (e.g., transistor) in the first direction (D1) 209. Furthermore, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the second level (L2) 213-2 and the sidewall of the channel region 225 of the second horizontally oriented three-node access device 230 (e.g., transistor) in the third level (L3) 213-M. The embodiments are not limited to a specific number of levels.

[0036] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain conductive materials, such as, for example, doped semiconductor materials, conductive metal nitrides, metals and / or metal semiconductor compounds. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) of the description.

[0037] like Figure 2 As shown in the example embodiment, the insulating layer dielectric (ILD) 250 can be formed such that, in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-M above the substrate 200, the end face of the horizontally oriented three-node access device 230 (e.g., a transistor) extends along a first direction (D1) 209. The ILD 250 can isolate and separate vertically stacked memory cells (e.g., ...) along a second direction (D2) 205. Figure 1An array of 101-1, 101-2, ..., 101-N. The ILD 250 may contain insulating materials, such as dielectric materials, such as one of oxide materials, silicon oxide (SiO2) materials, silicon nitride (SiN) materials, silicon oxynitride materials, and / or combinations thereof, etc.

[0038] Although not in Figure 2 As shown, however, the insulating material may fill other spaces in the array of vertically stacked memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0039] Figure 3 Examples of some embodiments according to this disclosure are shown in more detail. Figure 1 The unit cell of the vertically stacked array of memory cells within the sub-cell array 101-2, for example... Figure 1 Memory unit 110 in the middle. For example... Figure 3 As shown, the first and second source / drain regions 321 and 323 can be impurity-doped regions of a horizontally oriented three-node access device 330 (e.g., a transistor). The first and second source / drain regions 321 and 323 may also comprise metals, and / or metal composites containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂-xSn) formed using atomic layer deposition processes. x At least one of O3), etc. However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor materials are intended to refer to semiconductor materials such as polycrystalline silicon containing highly doped dopants that have significant interactions with each other, such as phosphorus (P), boron (B), etc. In contrast, non-degenerate semiconductor materials contain moderate doping, wherein the dopant atoms are well separated from each other in the semiconductor host lattice and the interactions are negligible. The first and second source / drain regions 321 and 323 can be similar to Figure 2 The first and second source / drain regions 221 and 223 are shown in the diagram.

[0040] The first and second source / drain regions can be separated by a channel 325 (e.g., a channel region) of a horizontally oriented three-node access device 330 (e.g., a transistor). The channel 325 can be a lightly doped (p-) polycrystalline silicon material. In some embodiments, the channel 325 can be a lightly doped (p-) polygermanium (Ge) material. In some embodiments, the channel 325 can be a lightly doped (p-) polycrystalline silicon-germanium (poly-SiGe) material. However, in some embodiments, the channel 325 can be made of a semiconductor oxide (also referred to herein as “oxide semiconductor” or “oxide semiconductor material”). The semiconductor oxide can include any suitable composition; and in some embodiments can include one or more of indium, zinc, tin, and gallium. Examples of oxide semiconductor materials and / or compositions comprising one or more of indium, zinc, tin, and gallium, as used herein, can include materials such as ZnO. x InO x SnO2, Zn x O y N, Mg x Zn y O z In x Zn y O z In x Zn y O z In x Ga y Zn z O a In x Ga y Si z O a Zr x In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O b Si x In y Zn z O a Zn x Sn y O z Alx Zn y Sn z O a Ga x Zn y Sn z O a and Zr x Zn y Sn z O a .

[0041] In another embodiment, the channel 325 may be made of a two-dimensional (2D) material. The 2D material may include any suitable composition; and in some embodiments, it may include one or more of transition metal disulfides (including molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten sulfide (WS2), and tungsten selenide (WSe2). However, the embodiments are not limited to these examples.

[0042] In some embodiments, channel 325 may comprise a composite material, such as indium gallium zinc oxide (In2Ga2ZnO7) material (also referred to herein as “IGZO”). In some embodiments, the IGZO composite material is a multilayer I2G2ZnO7 channel, which is enriched in indium (In) in the first layer closest to the channel surface opposite the gate dielectric relative to the plurality of layers. In some embodiments, the IGZO composite material is a multilayer I2G2ZnO7 channel, which is enriched in gallium (Ga) in the outermost layer of the multilayer channel farthest from the channel surface opposite the gate dielectric relative to the multilayer. And, in some embodiments, the IGZO composite material is a multilayer I2G2ZnO7 channel, which is enriched in zinc (Zn) in the outermost layer of the multilayer channel farthest from the channel surface opposite the gate dielectric relative to the multilayer, and so on. However, the embodiments are not limited to these examples.

[0043] Digit lines (e.g., 307-1, similar to) Figure 2 The digit lines 207-1, 207-2, ..., 207-P in the text are... Figure 1 The 107-1, 107-2, ..., 107-P shown can be formed to make electrical contact with the first source / drain region 321. For example... Figure 3 As shown in the example embodiment, the access line (e.g., 303-1, similar to...) Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1The 103-1, 103-2, ..., 103-Q) can be adjacent to the sidewall of the channel region 325 of the horizontally oriented three-node access device 330 (e.g., a transistor that conducts horizontally between the first and second source / drain regions 321 and 323 along the second direction (D2) 305) and extend vertically in the third direction (D3) 311. A gate dielectric material 304 can be inserted between the access line 303-1 (a portion of which forms the gate of the horizontally oriented three-node access device 330, e.g., a transistor) and the channel region 325. The gate dielectric material 304 can comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof. The embodiments are not limited thereto. For example, in the example of high-k dielectric materials, the gate dielectric material 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobium iron ore, etc.

[0044] Figure 4 An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in a stage of a semiconductor manufacturing process, the array having, for example, Figure 1-3 The image shows a horizontally oriented access device and a vertically oriented access line. In Figure 4 In the example embodiments shown in the examples, the method includes depositing alternating layers of dielectric materials 430-1, 430-2, ..., 430-N (also referred to herein individually and / or collectively as "430") and sacrificial materials 432-1, 432-2, ..., 432-N (also referred to herein individually and / or collectively as "432") in repeated iterations to form a vertical stack 401 on the working surface of the semiconductor substrate 400. In one embodiment, the dielectric material 430 may be deposited having a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third direction (D3). In one embodiment, the sacrificial material 432 may be deposited having a thickness in the range of twenty (20) nm to one hundred (100) nm, for example, a vertical height. However, the embodiments are not limited to these examples.

[0045] In one example, the sacrificial materials 432-1, 432-2, ..., 432-N may include sacrificial semiconductor materials, such as polycrystalline silicon (Si), silicon nitride (SiN), or even oxide-based semiconductor compositions. While the discussion herein will refer to examples of sacrificial semiconductor materials, the embodiments are not limited to this example. It is contemplated that the sacrificial materials may be selectively etched relative to alternating layers 430-1, 430-2, ..., 430-N of dielectric material.

[0046] like Figure 4 As shown, the vertical direction 411 is represented as a third direction (D3), for example, the direction z in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) is shown among the first, second, and third directions. Figure 4 The example shows four levels of repeated iterations of the vertical stack 401, numbered 1, 2, 3, and 4. However, the embodiment is not limited to this example and may include more or fewer repeated iterations. A photolithographic hard mask (HM) layer 435 may be deposited as the top layer on the repeated iterations of the vertical stack 401.

[0047] In some embodiments, dielectric materials 430-1, 430-2, ..., 430-N may be interlayer dielectrics (ILDs). By way of example and not limitation, dielectric materials 430-1, 430-2, ..., 430-N may include silicon dioxide (SiO2) material. In another example, dielectric materials 430-1, 430-2, ..., 430-N may include silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another example, dielectric materials 430-1, 430-2, ..., 430-N may include silicon oxycarbide (SiO2) material. x C y The material (also referred to herein as "SiOC"). In another example, dielectric materials 430-1, 430-2, ..., 430-N may comprise silicon oxynitride (SiO2). x N y The materials used are silicon (Si) materials (also referred to herein as "SiON") and / or combinations thereof. Embodiments are not limited to these examples. In some embodiments, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise polycrystalline and / or amorphous silicon (Si) materials. In another example, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon nitride (SiN) materials. However, embodiments are not limited to these examples.

[0048] Alternating layers of dielectric materials 430-1, 430-2, ..., 430-N and sacrificial semiconductor materials 432-1, 432-2, ..., 432-N can be deposited in a semiconductor manufacturing apparatus using a semiconductor manufacturing process, such as chemical vapor deposition (CVD). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of dielectric materials 430-1, 430-2, ..., 430-N and sacrificial semiconductor materials 432-1, 432-2, ..., 432-N in repeated iterations to form a vertical stack 401, such as... Figure 4 As shown.

[0049] Figure 5A An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having, for example, Figure 1-3 The image shows a horizontally oriented access device and a vertically oriented access line. Figure 5A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 5A In the example embodiment shown in the example, the method includes forming a plurality of first vertical openings 500 having a first horizontal orientation (D1) 509 and a second horizontal orientation (D2) 505, extending through a vertical stack to the substrate. In one example, as Figure 5A As shown, a plurality of first vertical openings 500 extend primarily in the second horizontal direction (D2) 505 and can form elongated vertical pillars 513 with sidewalls 514 in the vertical stack. The plurality of first vertical openings 500 can be formed using photolithography to pattern a photomask 535 on the vertical stack, for example, to form a hard mask (HM), prior to etching the plurality of first vertical openings 500.

[0050] Figure 5B It is along Figure 5A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific point in the semiconductor manufacturing process. Figure 5BThe illustration shows conductive materials 540-1, 540-2, ..., 540-4 formed on a gate dielectric material 538 within a plurality of first vertical openings 500. By way of example, and not limitation, the gate dielectric material 538 can be conformally deposited in the plurality of first vertical openings 500 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 can be deposited to a specific thickness (t1) suitable for a particular design rule, for example, a gate dielectric thickness of approximately 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example, and not limitation, the gate dielectric 538 can include, as shown Figure 3 The aforementioned silicon dioxide (SiO2) material, alumina (Al2O3) material, high dielectric constant (k) (e.g., high k) dielectric material, and / or combinations thereof.

[0051] Furthermore, such as Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited in a plurality of first vertical openings 500 on the surface of the gate dielectric material 538. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited in the plurality of first vertical openings 500 on the surface of the gate dielectric material 538 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings on the gate dielectric 538. Conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a specific thickness (t2) to form vertically oriented access lines, such as, as in Figure 1 The displays shown, and applicable to specific design rules, are access lines 103-1, 103-2, ..., 103-Q (also referred to as word lines). For example, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 may include, as shown... Figure 3 The metals such as tungsten (W), metal compositions, titanium nitride (TiN), doped polycrystalline silicon, and / or some other combinations thereof described herein.

[0052] like Figure 5BAs shown, conductive materials 540-1, 540-2, ..., 540-4 can be recessed backward so that they are recessed only along the slender vertical pillars (now in...). Figure 5B The vertical sidewalls (shown as 542-1, 542-2, and 542-3 in the cross-sectional views) are preserved. They can be preserved from the first vertical opening (e.g., using a suitable selective anisotropic etchant process). Figure 5A In step 500), conductive materials 540-1, 540-2, ..., 540-4 are removed from the bottom surface, causing the conductive materials 540-1, 540-2, ..., 540-4 to be recessed backward, exposing the gate dielectric 538 on the bottom surface, thereby forming individual conductive materials 540-1, 540-2, ..., 540-4. For example... Figure 5B As shown, a dielectric material 539 (such as an oxide or other suitable spin-on dielectric (SOD)) can then be deposited into the first vertical opening 500 using a process such as CVD to fill the first vertical opening 500. The dielectric can be planarized to a vertical semiconductor stack (e.g., as shown) using chemical mechanical planarization (CMP) or other suitable semiconductor fabrication techniques. Figure 4 The top surface of the hard mask 535 (shown as 401). Subsequent photolithographic material 536 (e.g., the hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical opening 500 above the conductive materials 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0053] Figure 6A An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having, for example, Figure 1-3 The image shows a horizontally oriented access device and a vertically oriented access line. Figure 6A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 6A In an example embodiment, the method includes using a photolithography process to... Figure 5B The photolithography masks 636 and 536 in the middle are patterned. Figure 6A The method further illustrates the use of a selective isotropic etchant process to remove portions of the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z( Figure 5BIn the 540), to separate and individually form multiple separate vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, for example, Figure 1 Access lines 103-1, 103-2, ..., 103-Q in the diagram. Therefore, along the sidewall of a slender vertical column, for example, along... Figure 5B The sidewalls of the slender vertical columns 542-1, 542-2 and 542-3 in the cross-sectional view show multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z.

[0054] like Figure 6A As shown in the example, the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be back-removed into the gate dielectric material 638 in the first vertical opening using a suitable selective isotropic etchant process, for example... Figure 5A 500 in the middle. For example... Figure 6A As shown, a subsequent dielectric material 641, such as an oxide or other suitable spin-on dielectric (SOD), can then be deposited to fill the remaining openings from which the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z has been removed using a process such as CVD or other suitable techniques. The dielectric material 641 can be planarized to a vertical semiconductor stack (e.g., as shown) using a process such as CMP or other suitable techniques. Figure 4 The top surface of the hard mask 635 (shown as 401). In some embodiments, the subsequent photolithography material 537 (e.g., the hard mask) can be deposited using CVD and planarized using CMP to cover and enclose the vertical semiconductor stack ( Figure 4 Multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z on the working surface of 401) are provided to protect the multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z along the sidewall of the slender vertical column. However, the embodiments are not limited to these process examples.

[0055] Figure 6B It shows along Figure 6AThe cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6B The cross-sectional view shown is away from multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and shows repeated iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N on the semiconductor substrate 400 to form a vertical stack, for example, as... Figure 4 As shown in Figure 401. Figure 6B As shown, the vertical direction 611 is represented as a third direction (D3), for example, direction z in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) 111 is shown among the first, second, and third directions. The plane of the drawing extends left and right along the first direction (D1) 609. Figure 6B In the example embodiment, dielectric material 641 is shown filling the vertical opening on the residual gate dielectric 638 deposition. The aforementioned hard mask 637 covers the structure shown.

[0056] Figure 6C It shows along Figure 6A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6C The cross-sectional view shown is illustrated as an axis extending in a second direction (D2) 605 along the repeating iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, along the sacrificial semiconductor materials. Horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) can be formed within the layers of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, adjacent opposing vertical access lines 640-3 are shown by dashed lines, which indicate the positions set inward from the plane and orientation of the drawing.

[0057] Figure 6D It shows along Figure 6A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6DThe cross-sectional view shown is illustrated as extending in a second direction (D2) 605 outside the region of horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) formed within layers of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, along the axis of repeated iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-(N+1). Figure 6C In the drawing, dielectric material 641 is shown filling the space between horizontally oriented access devices and horizontally oriented memory nodes, which can be separated along a first direction (D1) extending into and out of the drawing plane of the three-dimensional array of vertically oriented memory cells. At the left end of the drawing, a repeating iteration of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N is shown, which can be integrated at said location. Figure 1 The horizontally oriented digital lines shown in the figure (e.g., digital lines 107-1, 107-2, ..., 107-P) form an electrical contact with the second source / drain, as described in more detail below.

[0058] Figure 6E It shows along Figure 6A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6E The cross-sectional view shown is presented from right to left on the drawing plane. It extends along the axis of repeated iterations of alternating layers of dielectric materials 630-1, 630-2, ..., 630-N and sacrificial semiconductor materials 632-1, 632-2, ..., 632-N in a first direction (D1) 609, intersecting with multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and intersecting with regions of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, in which channel regions separated by gate dielectric 638 from multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1). Figure 6EIn the diagram, the first dielectric filling material 639 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which can be formed to extend into and out of the drawing plane (as described in more detail below) and can be spaced apart along the first direction (D1) 609 and vertically stacked in an array extending in the third direction (D3) 611 in the three-dimensional (3D) memory.

[0059] Figure 7A An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having, for example, Figure 1-3 The image shows a horizontally oriented access device and a vertically oriented access line. Figure 7A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 7A In an example embodiment, the method includes using a photolithography process to process photolithographic masks 735, 736, and / or 737 (e.g., Figures 6A-6E Patterning is performed on 635, 636 and / or 637. Figure 7A The method further illustrates the use of one or more etchant processes in the memory node region 750 (in Figure 7A and 7C A vertical opening 751 is formed in the middle (744) through the vertical stack and extending primarily in the first horizontal direction (D1) 709. One or more etchant processes form the vertical opening 751 to expose the vertical stack adjacent to a second region of the sacrificial semiconductor material (in...). Figures 7B-7E The diagram shows the third sidewall of a repeating iterative layer of alternating layers of dielectric materials 730-1, 730-2, ..., 730-N and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N. Other numbered components can be similarly combined. Figures 6A to 6E Those shown and discussed.

[0060] According to embodiments, a second region of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N can be removed in a vertically stacked manner through repeated iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-N and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N to form a memory node. In some embodiments, this process is performed before the access device regions (e.g., transistor regions) in which the first source / drain regions, channel regions, and second source / drain regions of horizontally oriented access devices are formed, are selectively removed from the sacrificial semiconductor materials. In other embodiments, this process is performed after the access device regions in which the first source / drain regions, channel regions, and second source / drain regions of horizontally oriented access devices are selectively removed from the sacrificial semiconductor materials. Figures 7B-7E In the example embodiment shown, the method includes selectively etching second regions of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N to form a second horizontal opening a second horizontal distance backward from the vertical opening 751 in the vertical stack. In some embodiments, such as Figures 7B-7E As shown, the method includes forming a capacitor cell as a storage node in a second horizontal opening. By way of example, and not limitation, forming the capacitor includes using an atomic layer deposition (ALD) process to sequentially deposit a first electrode 761 and a second electrode 756 separated by a cell dielectric 763 in the second horizontal opening. Other suitable semiconductor fabrication techniques and / or storage node structures may be used.

[0061] Figure 7B It shows along Figure 7A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7B The cross-sectional view shown is away from multiple individual vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1) and shows repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1) separated by horizontally oriented capacitor cells on a semiconductor substrate 700 to form a vertical stack, wherein the capacitor cells have a first electrode 761 (e.g., a bottom cell contact electrode), a cell dielectric 763, and a second electrode 756 (e.g., a top common node electrode). Figure 7B As shown, the vertical direction 711 is represented as a third direction (D3), for example, direction z in the xyz coordinate system, similar to... Figure 1-3The third direction (D3) 111 is shown among the first, second, and third directions. The plane of the drawing extends left and right along the first direction (D1) 709. Figure 7B In an example embodiment, the first electrode 761 (e.g., the bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 756 are shown separated by a cell dielectric material 763 that extends into and out of the drawing plane in a second direction (D2) and along the orientation axis of the horizontal access device and horizontal access node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0062] Figure 7C It shows along Figure 7A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7C The cross-sectional view shown is illustrated as extending along a second direction (D2) 705 along the left-right direction of the drawing plane, along an axis of repeated iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N, along the sacrificial semiconductor material. Horizontally oriented access devices and horizontally oriented storage nodes, such as capacitor cells, can be formed within the layers of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N. Figure 7C In the example embodiment, horizontally oriented memory nodes (e.g., capacitor cells) are shown as having been formed in this semiconductor manufacturing process, and a first electrode 761 (e.g., a bottom electrode to be coupled to the source / drain regions of the horizontal access device) and a second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane such as a ground plane) separated by a cell dielectric 763 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 761 (e.g., a bottom electrode to be coupled to the source / drain regions of the horizontal access device) and the second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane such as a ground plane) separated by a cell dielectric 763 may be formed after the first source / drain regions, channel regions, and second source / drain regions are formed in the regions of the sacrificial semiconductor materials 732-1, 732-2, ..., 732-N, for positioning, such as arrangement, of the horizontally oriented access device, which will be described below.

[0063] exist Figure 7CIn an example embodiment, a horizontally oriented memory node is shown having a first electrode 761 (e.g., a bottom electrode to be coupled to a source / drain region of a horizontal access device) and a second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane such as a ground plane). The horizontally oriented memory node is formed in a second horizontal opening along the orientation axis of the horizontal access device and the horizontal memory node in an array of vertically stacked memory cells of a three-dimensional (3D) memory. This second horizontal opening extends a second distance in a second direction (D2) (left-right of the drawing plane) relative to a vertical opening formed on the vertical stack. Figure 7C In the drawing, adjacent opposing vertical access lines 740-3 are shown by dashed lines, which indicate the positions set inward from the plane and orientation of the drawing.

[0064] Figure 7D It shows along Figure 7A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7D The cross-sectional view shown is depicted as extending in a second direction (D2) 705 (left and right of the drawing plane) outside the region of horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) formed within layers of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N, along the axis of repeated iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-N, 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N. Figure 7C In the diagram, dielectric material 741 is shown filling the space between horizontally oriented access devices, which are separated along a first direction (D1) extending into and out of the drawing plane of a three-dimensional array of vertically oriented memory cells. However, in Figure 7D In the cross-sectional view, the second electrode 756 (e.g., the top common electrode of the capacitor cell structure) is further shown as existing in the space between horizontally adjacent devices. At the left end of the drawing, a repeating iteration of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N is shown, which can be integrated at said location. Figure 1 The horizontally oriented digital lines shown in the figure (e.g., digital lines 107-1, 107-2, ..., 107-P) form an electrical contact with the second source / drain, as described in more detail below.

[0065] Figure 7E It shows along Figure 7AThe cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7E The cross-sectional view shown (from right to left in the drawing plane) illustrates an axis extending in a first direction (D1) 709 along the repeating iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, ..., 732-N. This axis intersects with multiple individual vertical access lines 740-1, 740-2, ..., 740-4 and with regions of sacrificial semiconductor materials 732-1, 732-2, ..., 732-N, where channel regions separated by gate dielectric 738 from the multiple individual vertical access lines 740-1, 740-2, ..., 740-4 can be formed. Figure 7E In the diagram, the first dielectric filling material 739 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which can be formed to extend into and out of the drawing plane (as described in more detail below) and can be spaced apart along the first direction (D1) 709 and vertically stacked in an array extending in the third direction (D3) 711 in the three-dimensional (3D) memory.

[0066] Figure 8A An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having, for example, Figure 1-3 The image shows a horizontally oriented access device and a vertically oriented access line. Figure 8A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 8A In an example embodiment, the method includes patterning photomasks 835, 836, and / or 837 using a photolithography process, such as... Figures 6A to 6E As described in 7A to 7E. Figure 8A The method further illustrates the use of one or more etchant processes in access device regions (e.g., for replacing channel and source / drain transistor regions). Figure 7C 742 and Figure 8C Vertical openings 871-1 and 871-2 are formed through the vertical stack (842). Vertical openings 871-1 and 871-2 are shown extending primarily in the first horizontal direction (D1) 709. One or more etchant processes form the vertical openings 871-1 and 871-2 to expose the vertical stack adjacent to a first region of the sacrificial semiconductor material (in...). Figures 8B-8EThe third sidewall is shown in the repeated iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and sacrificial semiconductor materials 832-1, 832-2, ..., 832-N. Other numbered components can be similarly combined. Figures 6A to 6E And those shown and discussed in 7A to 7E.

[0067] According to an embodiment, the access device regions of the sacrificial semiconductor materials 832-1, 832-2, ..., 832-N are... Figure 8A and 8C The 842 region (e.g., a transistor region) can be removed from alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) and sacrificial semiconductor material 832-1, 832-2, ..., 832-N in a vertically stacked array to form an access device, such as a transistor. In some embodiments, this process is performed before the selective removal of the sacrificial semiconductor material in the memory node region where capacitor cells are formed. In other embodiments, this process is performed after the selective removal of the sacrificial semiconductor material in the memory node region where capacitor cells are formed. Figures 8B-8E The example embodiment shown includes selectively etching access device regions of sacrificial semiconductor materials 832-1, 832-2, ..., 832-N to form a first horizontal opening in a vertical stack, extending a first horizontal distance backward from vertical openings 871-1 and 871-2. In some embodiments, such as Figures 8B-8E As shown, the method includes forming a transistor as an access device having a first source / drain region, a channel region, and a second source / drain region in a first horizontal opening. By way of example, and not limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first horizontal opening, the first source / drain region, the channel region, and the second source / drain region using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or memory node structures may be used.

[0068] Figure 8B It shows along Figure 8A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8BThe cross-sectional view shown is away from multiple individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1) and illustrates the repeated iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) separated by capacitor cells on a semiconductor substrate 800 to form a vertical stack, wherein the capacitor cells have a first electrode 861 (e.g., a bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., a top common node electrode). Figure 8B As shown, the vertical direction 811 is represented as a third direction (D3), for example, the direction z in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) 111 is shown among the first, second, and third directions. The plane of the drawing extends left and right along the first direction (D1) 809. Figure 8B In an example embodiment, the first electrode 861 (e.g., the bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 856 are shown separated by a cell dielectric material 863 that extends into and out of the drawing plane in a second direction (D2) and along the orientation axis of the horizontal access device and horizontal access node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0069] Figure 8C It shows along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8C The cross-sectional view shown is depicted as an axial extension along the repeating iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) in a second direction (D2) 805 along the plane of the drawing. However, it is now shown that sacrificial semiconductor material has been removed from the access device region 842 of the vertically stacked alternating layers to form horizontal openings 833-1, 833-2, ..., 833-N, where horizontally oriented access devices with a first source / drain region, a channel region, and a second source / drain region can be formed between the vertically alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1). Figure 8CIn an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown as having been formed in memory node region 844 during this semiconductor manufacturing process, and a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane such as a ground plane) separated by a cell dielectric 863 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane such as a ground plane) separated by a cell dielectric 863 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in the regions of the sacrificial semiconductor material 832-1, 832-2, ..., 832-N.

[0070] exist Figure 8C In an example embodiment, horizontal openings 830-1, 830-2, ..., 830-N, having a first source / drain region, a channel region, and a second source / drain region, are shown extending along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory, at a certain distance from the vertical openings 871-1 and 871-2 formed on the vertical stack in a second direction 805 (D2) to the left and right of the drawing plane. Figure 8C In the drawing, adjacent opposing vertical access lines 840-3 are shown by dashed lines, which indicate the positions set inward from the plane and orientation of the drawing.

[0071] Figure 8D It shows along Figure 8A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8D The cross-sectional view shown is depicted as an axis extending along a second direction (D2) 805, horizontally to the left and right of the drawing plane, outside the area where horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed, along the repeating iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-N, 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N. Figure 8D In the diagram, dielectric material 841 is shown filling the space between horizontally oriented access devices, which are separated along a first direction (D1) extending into and out of the drawing plane of a three-dimensional array of vertically oriented memory cells. However, in Figure 8DIn the cross-sectional view, the second electrode 856 (e.g., the top common electrode of the capacitor cell structure) is further shown as existing in the space between horizontally adjacent devices. At the left end of the drawing is shown a repeating iteration of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N, which can be integrated at said locations. Figure 1 The horizontally oriented digital lines shown in the figure (e.g., digital lines 107-1, 107-2, ..., 107-P) form an electrical contact with the second source / drain region of the formed horizontal access device.

[0072] Figure 8E It shows along Figure 8A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8E The cross-sectional view shown is illustrated as (from right to left in the drawing plane) an axis extending in a first direction (D1) 809 along the repeating iterations of alternating layers of dielectric materials 830-1, 830-2, ..., 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N, where a channel region separated by a gate dielectric 838 and multiple individual vertical access lines 840-1, 840-2, ..., 840-4 will be formed. Figure 8E In the diagram, the first dielectric filling material 839 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which can be formed to extend into and out of the drawing plane (as described in more detail below) and can be spaced apart along the first direction (D1) 809 and vertically stacked in an array extending in the third direction (D3) 811 in the three-dimensional (3D) memory.

[0073] Figure 9A An example method is shown according to several embodiments of the present disclosure for forming an array of vertically stacked memory cells in another stage of a semiconductor manufacturing process, the array having, for example, Figure 1-3 The image shows a horizontally oriented access device and a vertically oriented access line. Figure 9A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 9A In the example embodiments, there are still Figures 8A-8E The vertical openings 971-1 and 971-2. However, in Figures 9A-9E In the middle, there is a first source / drain region, a channel region, and a second source / drain region (in Figure 9CThe horizontal access devices 998-1, 998-2, ..., 998-N (displayed as 998-1A, 998-1B, and 998-1C respectively) have been installed. Figure 8C and 8D The horizontal openings 833-1, 833-2, ..., 833-N shown are formed. Horizontal access devices 998-1, 998-2, 998-N are formed to extend in the second direction 905 (D2) within the vertically stacked horizontal access device region 942. Additionally, horizontal digit lines 999-1, 999-2, 999-N have been formed and integrated to contact the second source / drain region (e.g., 998-1C), as shown. Figure 9C and 9D As shown in the diagram. Other numbered components can be combined in a similar manner. Figures 6A to 6E Those shown and discussed in 7A to 7E and 8A to 8E.

[0074] According to an embodiment, in Figures 8A-8E In the access device region 942 (e.g., transistor region), sacrificial semiconductor materials 832-1, 832-2, ..., 832-N have been removed to... Figures 8A to 8E The process involves repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) and horizontal openings 833-1, 833-2, ..., 833-N in a vertically stacked array to form an access device, such as a transistor. In some embodiments, this process is performed before the selective removal of sacrificial semiconductor material from the storage node region 944 in which capacitor cells are formed. In other embodiments, this process is performed after the selective removal of sacrificial semiconductor material from the storage node region 944 in which capacitor cells are formed. According to an example embodiment, such as... Figure 9B-9E As shown, the method includes using atomic layer deposition (ALD) processes or other suitable deposition techniques, in Figures 8A-8E In each of the horizontal openings 833-1, 833-2, ..., 833-N, a first source / drain region 938-1A, a channel region 938-1B, and a second source / drain region 938-1C are deposited. By way of example, and not limitation, forming the first source / drain region, the channel region, and the second source / drain region includes: sequentially depositing the first horizontal opening, the first source / drain region, the channel region, and the second source / drain region using an atomic layer deposition (ALD) process according to the process and techniques described in co-filed, co-pending U.S. Patent Application No. _______________, entitled “_________________”, which has at least one co-inventor. Other suitable semiconductor manufacturing techniques and / or memory node structures may be used.

[0075] Figure 9B It shows along Figure 9A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9B The cross-sectional view shown is away from multiple individual vertical access lines 940-1, 940-2, ..., 940-N, 940-(N+1), ..., 940-(Z-1) and illustrates the repeated iterations of alternating layers of dielectric materials 930-1, 930-2, ..., 930-(N+1) separated by capacitor cells on a semiconductor substrate 900 to form a vertical stack, wherein the capacitor cells have a first electrode 961 (e.g., a bottom cell contact electrode), a cell dielectric 963, and a second electrode 956 (e.g., a top common node electrode). Figure 9B As shown, the vertical direction 911 is represented as a third direction (D3), for example, the direction z in the xyz coordinate system, similar to... Figure 1-3 The third direction (D3) 111 is shown among the first, second, and third directions. The plane of the drawing extends left and right along the first direction (D1) 909. Figure 9B In an example embodiment, the first electrode 961 (e.g., the bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 956 are shown separated by a cell dielectric material 963 that extends into and out of the drawing plane in a second direction (D2) and along the orientation axis of the horizontal access device and horizontal access node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0076] Figure 9C It shows along Figure 9A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9C The cross-sectional view shown is depicted as an axial extension along the alternating layers of dielectric materials 930-1, 930-2, ..., 930-(N+1) in a second direction (D2) 905 along the left-right axis of the drawing plane. However, what is shown now is the first source / drain region material, the channel region material, and the second source / drain region materials 998-1, 998-2, ..., 998-N that have been deposited on... Figures 8A-8EThe horizontal openings 833-1, 833-2, ..., 833-N extend in the second direction 905 (D2). As an example, the first source / drain region material 998-1, channel regions 998-1B and 998-1C are shown in different ways. Further, the horizontal digital lines 999-1, 999-2, ..., 999-N are integrated with the second source / drain region (e.g., 998-1C) which extends in the first direction (D1), for example, together with the dielectric materials 930-1, 930-2, ..., 930-(N+1), vertically extending into and out of the drawing plane in the alternating layers in direction (D3) 911.

[0077] Therefore, three-node horizontal access devices 938-1, 938-2, ..., 938-N have been formed and integrated into vertical access lines 940-1, 940-2, ..., 940-(Z+1) and digit lines 999-1, 999-2, ..., 999-N without body contact. Advantages of the structure and process described herein may include: reduced access device cutoff current (Ioff) compared to silicon-based (Si-based) access devices. The channel region (e.g., 938-1B) may be free of minority carriers for the access device, thus eliminating the need for volume potential control of the access device's body region and / or reducing gate / drain extreme leakage (GIDL) of the access device. In some embodiments, channel and / or source / drain region replacement manufacturing steps can be performed after the capacitor cell formation process, thereby reducing the thermal budget. Since there is no body contact with the access device's body region, integration of the digit lines can be more easily achieved during manufacturing. Furthermore, due to the shorter channel length and lower source / drain semiconductor manufacturing process overhead, the embodiments described herein can achieve a better lateral scaling path than that achieved by channel regions based on doped polysilicon.

[0078] Furthermore, the first source / drain regions, channel regions, and second source / drain regions of the horizontal access devices 998-1, 998-2, ..., 998-N, and the horizontal digit lines 999-1, 999-2, ..., 999-N, can be integrated according to the processes and techniques described in co-filed, co-pending U.S. patent applications (Micron file numbers 2020-0692 and 2020-0693) with at least one co-inventor and entitled “__________________”. A further advantage, according to the various embodiments, is the avoidance (e.g., non-use) of gas phase doping (GPD) in the formation of the source / drain regions. Other suitable semiconductor manufacturing techniques and / or memory node structures can be used.

[0079] exist Figure 9C In an example embodiment, a horizontal access device having a first source / drain region, a channel region, and second source / drain regions 998-1, 998-2, ..., 989-N is shown as extending along the orientation axis of the horizontal access device and horizontal memory node in a second direction 905 (D2) to the left and right of the drawing plane, at a certain distance from the vertical openings 971-1 and 971-2 formed on the vertical stack, and along the vertical stacked memory cell array of the three-dimensional (3D) memory. Figure 10 As shown, dielectric material can be deposited to fill the vertical openings 971-1 and 971-3. Figure 9C In the drawing, adjacent opposing vertical access lines 940-3 are shown by dashed lines, which indicate the positions set inward from the plane and orientation of the drawing.

[0080] Figure 9D It shows along Figure 9A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9D The cross-sectional view shown is depicted as follows: outside the regions forming horizontally oriented access devices 938-1, 938-2, ..., 938-N and horizontally oriented storage nodes (e.g., capacitor cells) in the access device region 942 and the storage node region 944, in a second direction (D2) 905 extending left and right along the drawing plane, along the axis of repeated iterations of alternating layers of dielectric materials 930-1, 930-2, ..., 930-N, 930-(N+1) and horizontal digit lines 999-1, 999-2, ..., 999-N, extending into and out of the drawing plane in the first direction (D1). Figure 9D In the diagram, dielectric material 941 is shown filling the space between horizontally oriented access devices, which are separated along a first direction (D1) extending into and out of the drawing plane of a three-dimensional array of vertically oriented memory cells. However, in Figure 9D In the cross-sectional view, the second electrode 956 (e.g., the top common electrode of the capacitor cell structure) is further shown as existing in the space between horizontally adjacent devices. At the left end of the drawing are shown dielectric materials 930-1, 930-2, ..., 930-(N+1) and horizontal digit lines 999-1, 999-2, ..., 999-N (e.g., ...). Figure 1 Repeated iterative integration of the digital lines 107-1, 107-2, ..., 107-P shown in the figure to form an electrical contact with the second source / drain region (e.g., 938-1C) of the formed horizontal access device.

[0081] Figure 9E It shows along Figure 9A The cross-sectional view taken by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9E The cross-sectional view shown is illustrated (from right to left in the drawing plane) as an axis of repeated iterations along the alternating layers of the dielectric materials 930-1, 930-2, ..., 930-(N+1) and the horizontal access devices 998-1, 998-2, ..., 998-N, extending in a first direction (D1) 909, separated by the gate dielectric 938 from multiple individual vertical access lines 940-1, 940-2, ..., 940-4. Figure 9E In the diagram, the first dielectric filling material 939 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which can be formed to extend into and out of the drawing plane (as described in more detail below) and can be spaced apart along the first direction (D1) 909 and vertically stacked in an array extending in the third direction (D3) 911 in the three-dimensional (3D) memory.

[0082] Figure 10 A three-node horizontally oriented access device 1042 is shown, according to an embodiment of the present disclosure, coupled to a horizontally oriented storage node 1044 of a vertical three-dimensional (3D) memory. Figure 10 In the diagram, a three-node horizontally oriented access device 1042 is shown extending in a second direction (D2) 1005 on the left-right axis of the drawing plane. The horizontally oriented access device 1042 is shown having a first source / drain region 1098-1A, which is in electrical contact with a first electrode 1061 (e.g., bottom electrode) of a horizontally oriented storage node 1044 (e.g., a capacitor cell). The storage node 1044 is further shown having a dielectric material 1063 that separates the first electrode 1061 from a second electrode 1056 (e.g., the top common node electrode of a capacitor cell).

[0083] Channel region 1098-1B is shown as electrically contacting the first source / drain region 1098-1A. Vertically oriented access lines 1040-3 are opposite channel region 1098-1B and separated from it by a gate dielectric. Vertically oriented access lines 1040-2 are shown by dashed lines, indicating that the vertically oriented access lines are configured to enter and / or exit the drawing plane. Depending on specific design rules, vertically oriented access lines 1040 may extend in a second direction (D2) 1005 in a manner longer and / or shorter than the channel region, for example, with source / drain overlay and / or underlay.

[0084] The second source / drain region 1098-1C is shown as electrically contacting the channel region 1098-1B and electrically contacting and integrating with the horizontally oriented digital line 1099 extending into and out of the drawing plane. (As shown) Figure 10 As shown, the horizontally oriented access device 1042 and the horizontally oriented memory node 1044 can be horizontally spaced from the adjacent memory cells along the second direction (D2) 1005 via the interlayer dielectric material 1080, and can be vertically spaced from the adjacent cells stacked in the three-dimensional (3D) memory via the dielectric layers 1030-1 and 1030-2.

[0085] Figure 11 This is a block diagram of a device in the form of a computing system 1100 including a memory device 1103, according to several embodiments of the present disclosure. As used herein, for example, the memory device 1103, memory array 1110, and / or host 1102 may also be considered as "devices". According to an embodiment, the memory device 1102 may include at least one memory array 1110 having three-node access means for vertical three-dimensional (3D) memory, as already described herein.

[0086] In this example, system 1100 includes a host 1102 coupled to memory device 103 via interface 1104. Among various other types of systems, computing system 1100 can also be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device. Host 1102 may include multiple processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 1103. System 1100 may include a separate integrated circuit, or host 1102 and memory device 1103 may both reside on the same integrated circuit. For example, host 1102 may be a system controller for a memory system including multiple memory devices 1103, wherein system controller 1105 provides access to the individual memory devices 1103 via another processing resource (such as a central processing unit (CPU)).

[0087] exist Figure 1In the example shown, host 1102 is responsible for executing the operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., from memory device 1103 via controller 1105). The OS and / or the various applications can be loaded from memory device 1103 by providing access commands from host 1102 to memory device 1103 for accessing data including the OS and / or the various applications. Host 1102 can also access data used by the OS and / or the various applications by providing access commands to memory device 1103 for retrieving the data used in executing the OS and / or the various applications.

[0088] For clarity, system 1100 has been simplified to focus on features particularly relevant to this disclosure. Memory array 1110 may be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash memory array, and / or NOR flash memory array including at least one three-node access device for three-dimensional (3D) memory. For example, memory array 1110 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1110 may include memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via bit lines (which may be referred to herein as sense lines or data lines). Although in Figure 1 A single array 1110 is shown, but the embodiments are not limited thereto. For example, the memory device 1103 may include multiple arrays 1110 (e.g., multiple groups of DRAM cells).

[0089] Memory device 1103 includes an address circuitry 1106 for latching address signals provided via interface 1104. The interface may include, for example, a physical interface employing an appropriate protocol (e.g., a data bus, address bus, and command bus, or a combination of data / address / command buses). Such a protocol may be custom or proprietary, or interface 1104 may employ a standardized protocol such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, etc. Address signals are received and decoded via row decoder 1108 and column decoder 1112 to access memory array 1110. Data can be read from memory array 1110 by sensing voltage and / or current changes on a sensing line using sensing circuitry 111. Sensing circuitry 1111 may include, for example, a sensing amplifier capable of reading and latching data pages (e.g., rows) from memory array 1110. I / O circuitry 1107 can be used for bidirectional data communication with host 1102 via interface 1104. The read / write circuitry 1113 system is used to write data to or read data from the memory array 1110. As an example, the circuitry 1113 may include various drivers, latch circuits, etc.

[0090] The control circuitry system 1105 decodes signals provided by the host 1102. These signals may be commands provided by the host 1102. These signals may include chip enable signals, write enable signals, and address latch signals, which are used to control operations performed on the memory array 1110, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry system 1105 is responsible for executing instructions from the host 1102. The control circuitry system 1105 may include a state machine, a sequencer, and / or some other type of control circuitry system that may be implemented in hardware, firmware, or software, or any combination thereof. In some examples, the host 1102 may be a controller external to the memory device 103. For example, the host 1102 may be a memory controller coupled to the processing resources of a computing device.

[0091] The term "semiconductor" can refer to, for example, a material, wafer, or substrate, and includes any basic semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a basic semiconductor structure, and other semiconductor structures. Furthermore, when referring to semiconductors in the preceding description, prior process steps may have been used to form regions / junctions in the basic semiconductor structure, and the term "semiconductor" may include the underlying material containing such regions / junctions.

[0092] The accompanying drawings follow a numbering convention, wherein the first one or more numbers correspond to the drawing number, and the remaining numbers identify elements or components in the drawing. Similar elements or components between different drawings may be identified by using similar (e.g., identical) numbers. It will be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide multiple additional embodiments of this disclosure. Furthermore, it will be understood that the scales and relative dimensions of the elements provided in the drawings are intended to illustrate embodiments of this disclosure and should not be considered limiting.

[0093] As used herein, “several” or “some” can refer to one or more such things. For example, “several or some” memory cells can refer to one or more memory cells. “Multiple” is intended to mean two or more. As used herein, multiple actions performed simultaneously refer to actions that at least partially overlap during a specific time period. As used herein, the term “coupling” can include electrical coupling without intermediate elements, direct coupling and / or direct connection (e.g., through direct physical contact), indirect coupling and / or connection with intermediate elements, or wireless coupling. The term “coupling” can further include two or more elements that cooperate or interact with each other (e.g., causality). An element coupled between two elements can be located between and coupled to each of the two elements.

[0094] It should be recognized that, due to variations in routine manufacturing, measurement, and / or assembly, the term "vertical" encompasses variations in "complete" verticality, and the meaning of the term "vertical" will be understood by those skilled in the art. For example, vertical can correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above or to the side of the other element, and / or may be in direct physical contact with the other element. For example, lateral can refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0095] Although specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements that yield the same results through calculation can replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of the various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon reading the above description. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, the method comprising: In repeated iterations, alternating layers of dielectric material (430, 630, 730, 830, 930) and sacrificial material (432, 632, 732, 832) are deposited to form a vertical stack (401), wherein a first portion of the sacrificial material (432, 632, 732, 832) is located in the vertical stack (401) in which a first source / drain region (221, 321, 998-1A, 1098-1A) and a second source / drain region (223, 323, 998-1C, 1098-1C) are formed, which are laterally separated by channel regions (225, 325, 998-1B, 1098-1B); An etchant process is used to form a first vertical opening (500), thereby exposing the vertical sidewalls of the vertical stack (432, 632, 732, 832) adjacent to the first portion of the sacrificial material (432, 632, 732, 832). Selectively etching the first portion of the sacrificial material (432, 632, 732, 832) to form a first horizontal opening, thereby removing the sacrificial material (432, 632, 732, 832) in the first region at a first horizontal distance backward from the first vertical opening (500); and First source / drain materials (221, 321, 998-1A, 1098-1A), channel materials (225, 325, 998-1B, 1098-1B), and second source / drain materials (223, 323, 998-1C, 1098-1C) are deposited in the first horizontal opening to form a three-node access device (230, 330) for the memory cell (110) in the array (101, 1110) of the vertically stacked memory cells.

2. The method according to claim 1, further comprising: Integrate horizontally oriented digital lines (107, 207, 999, 1099) to form electrical contact with the material of the second source / drain region; and Vertically oriented access lines (103, 203, 303, 640, 740, 840, 940, 1040) are integrated to form the three-node access device for the memory cell without body contact, the access lines being opposite to the channel material separated from them by a gate dielectric (304, 538, 638, 738, 838, 938).

3. The method according to claim 1, further comprising: The first source / drain material, the channel material, and the second source / drain material are sequentially deposited in the first horizontal opening.

4. The method according to claim 1, further comprising: The first source / drain material, the channel material, and the second source / drain material are deposited in the first horizontal opening using an atomic layer deposition process.

5. The method according to any one of claims 1 to 4, further comprising: Deposit multilayer channel materials.

6. The method according to any one of claims 1 to 4, further comprising: Before depositing the first source / drain material, the channel material, and the second source / drain material, a second portion of the sacrificial material located in the second region of the vertical stack is selectively etched to form the memory nodes (227, 327) of the memory cell.

7. The method according to any one of claims 1 to 4, further comprising: The second portion of the sacrificial material located in the second region of the vertical stack is selectively etched to form a second horizontal opening, thereby removing the sacrificial material in the second region from the second vertical opening in the vertical stack at a second horizontal distance backward.

8. The method according to any one of claims 1 to 4, further comprising: Polycrystalline silicon (poly-Si) material is deposited as the sacrificial material; and The deposited oxide material serves as the dielectric material.

9. The method of claim 8, further comprising: Before forming a first vertical opening using a first etchant process to expose the vertical sidewalls in the vertical stack, a hard mask selective for both the polysilicon material and the oxide material is deposited.

10. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, the method comprising: Alternating layers of dielectric material (430, 630, 730, 830, 930) and sacrificial material (432, 632, 732, 832) are deposited in repeated iterations to form a vertical stack (401); A plurality of first vertical openings (500) are formed having a first horizontal direction (509, 609, 709, 809, 909) and a second horizontal direction (505, 605, 705, 805, 905), passing through the vertical stack (401) and extending in the second horizontal direction (505, 605, 705, 805, 905) to form an elongated vertical column with sidewalls in the vertical stack (401); A first conductive material (540, 640) is conformally deposited on the gate dielectric material (304, 538, 638, 738, 838, 938) in the first vertical opening (500); Remove a portion of the first conductive material (540, 640) to form a plurality of individual vertical access lines (103, 203, 303, 640, 740, 840, 940, 1040) along the sidewall of the elongated vertical column; A second vertical opening is formed in the first horizontal direction (509, 609, 709, 809, 909) and exposes a sidewall adjacent to a first region of the sacrificial material (432, 632, 732, 832) in the vertical stack. The first region of the sacrificial material (432, 632, 732, 832) is selectively etched to form a first horizontal opening, thereby removing the sacrificial material (432, 632, 732, 832) a first horizontal distance backward from the second vertical opening; A first source / drain region (221, 321, 998-1A, 1098-1A), a channel region (225, 325, 998-1B, 1098-1B), and a second source / drain region (223, 323, 998-1C, 1098-1C) are sequentially formed in the first horizontal opening to form a three-node access device (230, 330) for the memory cell (110) in the array (101, 1110) of the vertically stacked memory cells without body contact. A third vertical opening is formed through the vertical stack (401), thereby exposing the sidewalls in the vertical stack (401) adjacent to the second region of the sacrificial material (432, 632, 732, 832); as well as The second region of the sacrificial material (432, 632, 732, 832) is selectively etched to form a second horizontal opening in which a memory node (227, 327) electrically coupled to the first source / drain region (221, 321, 998-1A, 1098-1A) is formed.

11. The method of claim 10, further comprising: Before sequentially forming the first source / drain region, the channel region, and the second source / drain region, the second region of the sacrificial material is selectively etched to form the memory node of the memory cell.

12. The method of claim 10, further comprising: The second region of the sacrificial material is selectively etched from the third vertical opening on the vertical stack to a second horizontal distance backward.

13. The method of claim 10, further comprising: A capacitor cell is formed in the second horizontal opening using an atomic layer deposition process as the storage node, and a first electrode (761, 861, 961, 1061) and a second electrode (756, 856, 956, 1056) separated by cell dielectrics (763, 863, 963, 1063) are sequentially deposited in the second horizontal opening.

14. The method according to any one of claims 10 to 13, further comprising: Integrate horizontally oriented digital lines (107, 207, 999, 1099) to form an electrical contact with the second source / drain region.

15. A method for forming an array of vertically stacked memory cells, the array having horizontally oriented access means and vertically oriented access lines, the method comprising: Alternating layers of deposited dielectric materials (430, 630, 730, 830, 930) and sacrificial materials (432, 632, 732, 832) are formed to form a vertical stack (401); A first etchant process is used to form a plurality of first vertical openings (500) having a first horizontal direction (509, 609, 709, 809, 909) and a second horizontal direction (505, 605, 705, 805, 905), extending through the vertical stack (401) to the substrate and extending in the second horizontal direction (505, 605, 705, 805, 905) to form an elongated vertical pillar with sidewalls in the vertical stack (401); A first conductive material (540, 640) is conformally deposited on the gate dielectric material (304, 538, 638, 738, 838, 938) in the first vertical opening (500); Remove a portion of the first conductive material (540, 640) to form a plurality of individual vertical access lines (103, 203, 303, 640, 740, 840, 940, 1040) along the sidewall of the elongated vertical column; A second vertical opening is formed through the vertical stack (401) and extending in the first horizontal direction (509, 609, 709, 809, 909) using a second etchant process to expose a second sidewall adjacent to a first region of the sacrificial material (432, 632, 732, 832). The first region is selectively removed to form a first horizontal opening in which a first source / drain region (221, 321, 998-1A, 1098-1A), a channel region (225, 325, 998-1B, 1098-1B), and a second source / drain region (223, 323, 998-1C, 1098-1C) are sequentially formed, thereby forming a three-node access device (230, 330) for the memory cell (110) in the array (101, 1110) of vertically stacked memory cells; A third vertical opening is formed through the vertical stack (401) and extending in the first horizontal direction (509, 609, 709, 809, 909) using a third etchant process to expose a third sidewall in the vertical stack (401) adjacent to a second region of the sacrificial material (432, 632, 732, 832). as well as The second region is selectively removed to form a second horizontal opening in which storage nodes (227, 327) are formed before the formation of the first source / drain regions (221, 321, 998-1A, 1098-1A), the channel regions (225, 325, 998-1B, 1098-1B), and the second source / drain regions (223, 323, 998-1C, 1098-1C).

16. The method of claim 15, further comprising: Indium gallium zinc oxide (IGZO) channel regions were deposited in the first horizontal opening using atomic layer deposition.

17. The method of claim 16, further comprising: A gradient IGZO channel region with decreasing indium (In) concentration is deposited in a direction away from the gate dielectric material, the gate dielectric material separating the channel region from the vertical access line of the three-node device for the memory cell.

18. The method of claim 15, further comprising: Deposit the channel region such that its width W is greater than the thickness t of the channel region.

19. A memory device having horizontally oriented access means and vertically oriented access lines, comprising: An array of vertically stacked memory cells (110), the array of vertically stacked memory cells (110) comprising: A horizontally oriented three-node access device (230, 330) having a first source / drain region (221, 321, 998-1A, 1098-1A) and a second source / drain region (223, 323, 998-1C, 1098-1C) separated by a channel region (225, 325, 998-1B, 1098-1B), and a connection to the channel region (225, 325, 998-1B).

5. The gates of the three-node access devices (230, 330) are separated from each other by the gate dielectric (304, 538, 638, 738, 838, 938), and the three-node access devices (230, 330) have no direct electrical contact with the body region of the three-node access devices (230, 330) or the channel region (225, 325, 998-1B, 1098-1B); Vertically oriented access lines (103, 203, 303, 640, 740, 840, 940, 1040), said vertically oriented access lines are coupled to the gate and separated from the channel region (225, 325, 998-1B, 1098-1B) by the gate dielectric (304, 538, 638, 738, 838, 938); Horizontally oriented storage nodes (227, 327), said horizontally oriented storage nodes being electrically coupled to the first source / drain regions (221, 321, 998-1A, 1098-1A) of the three-node access device (230, 330); and Horizontally oriented digital lines (107, 207, 999, 1099), said horizontally oriented digital lines being electrically coupled to the second source / drain region (223, 323, 998-1C, 1098-1C) of the three-node access device (230, 330).

20. The memory device of claim 19, wherein the three-node access device has three nodes without direct electrical contact, the three nodes including the first source / drain region (1), the second source / drain region (2) and the gate (3).

21. The memory device of claim 19, wherein the channel region comprises an oxide semiconductor having at least one of an indium material, a zinc material, or a gallium material.

22. The memory device according to any one of claims 19 to 21, wherein the channel region comprises a two-dimensional material, the two-dimensional material comprising one or more transition metal dichalcogenides.

23. The memory device according to any one of claims 19 to 21, wherein the vertically oriented access line has a horizontal width W greater than the horizontal length L of the channel region and horizontally overlaps with both the first and second source / drain regions.

24. The memory device according to any one of claims 19 to 21, wherein the vertically oriented access line has a horizontal width W less than the horizontal length L of the channel region and horizontally overlaps with both the first and second source / drain regions.

25. The memory device according to any one of claims 19 to 21, wherein the horizontally oriented memory node includes a capacitor cell having a first horizontally oriented electrode (761, 861, 961, 1061) electrically coupled to the first source / drain region of the three-node access device and a second electrode (756, 856, 956, 1056) separated from the first horizontally oriented electrode by a cell dielectric (763, 863, 963, 1063).

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