Semiconductor memory device and its manufacturing method

Abstract

This invention discloses a semiconductor memory device and its formation method. The semiconductor memory device includes a substrate, multiple bit lines, bit line contacts, multiple plugs, multiple memory node pads, and spacers. The bit lines and plugs are disposed on the substrate, and are arranged alternately and separately. The bit line contacts extend into the substrate and directly contact the underlying substrate, and are integrally formed with the semiconductor layer of the bit lines. The memory node pads are disposed above the plugs and bit lines and directly contact the plugs. Isolation sidewalls are disposed on the sidewalls of the memory node pads and directly contact the top surface of the plugs. This avoids short circuits caused by inappropriate electrical connections between memory node pads, thereby improving device performance.

Description

Technical Field

[0001] This invention relates to a semiconductor memory device and a method for forming the same, particularly a semiconductor memory device including a dynamic random access memory and a method for forming the same. Background Technology

[0002] As electronic products trend towards miniaturization, the design of semiconductor memory devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage current caused by capacitor structure. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structure.

[0003] Generally, dynamic random access memory (DRAM) with a recessed gate structure consists of a large number of memory cells arranged in an array to store information. Each memory cell can be composed of a transistor assembly and a capacitor assembly connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array must continue to increase, leading to increasing difficulties and complexity in related manufacturing processes and designs. Therefore, existing technologies require further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0004] One objective of this invention is to provide a semiconductor memory device and a method for forming the same, which involves a two-stage etching process for a metal layer and a barrier layer, and / or additionally forming isolation sidewalls on two opposite sidewalls of the memory node pads. This effectively mitigates short-circuit problems caused by residues from the etching process of the metal layer, and the isolation sidewalls isolate adjacent memory node pads, preventing them from conducting to each other. Consequently, short circuits caused by inappropriate electrical connections between memory node pads are avoided, thereby improving device performance.

[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor memory device, including a substrate, multiple bit lines, bit line contacts, multiple plugs, memory node pads, and isolation sidewalls. The bit lines are disposed on the substrate, and the plugs are also disposed on the substrate, alternating with and spaced apart from the bit lines. The bit line contacts extend into the substrate and directly contact the substrate below, and are integrally formed with the semiconductor layer of the bit lines. The memory node pads are disposed above the plugs and the bit lines and directly contact the plugs. The isolation sidewalls are disposed on the sidewalls of the memory node pads and directly contact the top surface of the plugs.

[0006] To achieve the above objectives, another embodiment of the present invention provides a method for forming a semiconductor memory device, comprising the following steps: First, a substrate is provided, and a plurality of bit lines are formed on the substrate. Next, a plurality of plugs are formed on the substrate, the plugs being alternately and spaced from the bit lines. Then, a plurality of memory node pads are formed above the plugs and the bit lines, directly contacting the plugs. Subsequently, isolation sidewalls are formed on the sidewalls of the memory node pads, the isolation sidewalls directly contacting the top surface of the plugs. Attached Figure Description

[0007] Figures 1 to 5 This is a schematic diagram of the steps in the method for forming a semiconductor memory device according to the first embodiment of the present invention, wherein:

[0008] Figure 1 This is a top view of a semiconductor memory device after bit lines have been formed.

[0009] Figure 2 for Figure 1 A cross-sectional view along the tangent line A-A';

[0010] Figure 3 This is a schematic cross-sectional view of a semiconductor memory device after a patterned mask has been formed.

[0011] Figure 4 This is a schematic cross-sectional view of a semiconductor memory device after an etching process; and

[0012] Figure 5 This is a schematic cross-sectional view of a semiconductor memory device after the formation of an insulating layer.

[0013] Figures 6 to 10 This is a schematic diagram of the steps in the method for forming a semiconductor memory device according to the second embodiment of the present invention, wherein:

[0014] Figure 6 This is a cross-sectional view of a semiconductor memory device after an etching process.

[0015] Figure 7 This is a schematic cross-sectional view of a semiconductor memory device after the formation of the insulating layer 230;

[0016] Figure 8 This is a schematic cross-sectional view of a semiconductor memory device after another etching process.

[0017] Figure 9 This is a schematic cross-sectional view of a semiconductor memory device after the formation of an insulating material layer; and

[0018] Figure 10 This is a cross-sectional view of a semiconductor memory device after an etch-back fabrication process.

[0019] Figure 11 This is a cross-sectional schematic diagram of a semiconductor memory device according to the third embodiment of the present invention.

[0020] The reference numerals in the attached figures are explained as follows:

[0021] 300, 400, 500 semiconductor memory devices

[0022] 100 substrate

[0023] 101 Insulation Zone

[0024] 103 Active Zone

[0025] 130 dielectric layer

[0026] 131 Oxide Layer

[0027] 133 Nitride layer

[0028] 135 oxide layer

[0029] 140 Embedded Gate

[0030] 160 bit line

[0031] 160a bit line contact

[0032] 161 Semiconductor Layer

[0033] 163 Barrier Layer

[0034] 165 conductive layer

[0035] 167, 167a cap layer

[0036] 170 gap wall structure

[0037] 171 First spacer wall

[0038] 173 Second spacer wall

[0039] 175 Third spacer wall

[0040] 180 plug

[0041] 190 Barrier Layer

[0042] Patterned barrier layers 191, 193

[0043] 200 metal layers

[0044] 201 Storage Node Pads

[0045] Residues of 203, 205, 205a, and 207

[0046] 203a U-shaped structure

[0047] 210 Patterned Mask

[0048] 211 Storage node pads

[0049] 220, 261 Insulation Layer

[0050] 230, 231, 233 Insulation Layers

[0051] 240, 240a Isolation sidewalls

[0052] 250 Oxygen Interface Layer

[0053] 260 Insulation Material Layer

[0054] D1 First Direction Detailed Implementation

[0055] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0056] Please refer to Figures 1 to 5 The illustration shows the steps of a method for forming a semiconductor memory device 300 according to the first embodiment of the present invention. First, as... Figure 1 and Figure 2As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate, etc. At least one insulating region 101, such as a shallow trench isolation (STI), is formed within the substrate 100, and a plurality of active areas (AA) 103 are defined on the substrate 100. Preferably, the active areas 103 extend parallel to each other and spaced apart from each other along a first direction D1, and are alternately arranged, wherein the first direction D1, for example, intersects and is not perpendicular to the y-direction or x-direction, such as... Figure 1 As shown. In one embodiment, the insulating region 101 is formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 using an etching method, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but is not limited thereto.

[0057] Multiple buried gates 140 may also be formed within the substrate 100. These buried gates 140 extend parallel to each other along a direction (e.g., the y-direction) and cross the active region 103, serving as buried word lines (BWLs) of the semiconductor memory device 300. Multiple bit lines 160 and multiple plugs 180 may be formed above the substrate 100. Each bit line 160 extends, for example, in another direction perpendicular to the aforementioned direction (e.g., the x-direction) and intersects with the active region 103. The plugs 180 are spaced apart on the substrate 100 and alternate with each bit line 160 in the aforementioned direction (e.g., the y-direction). Figure 1 As shown. Those skilled in the art will readily understand that, in a projection direction (not shown), the bit line 160 extending in the x direction should be perpendicular to the buried gate 140 extending in the y direction, such that the bit line 160 can simultaneously intersect the active region 103 and the buried gate 140 in the projection direction.

[0058] In detail, such as Figure 2As shown, each bit line 160 is disposed on the substrate 100 with spacing between them and includes a semiconductor layer (e.g., polysilicon) 161, a barrier layer 163 (e.g., titanium and / or titanium nitride), a conductive layer 165 (e.g., a low-resistivity metal such as tungsten, aluminum, or copper), and a capping layer 167 (e.g., silicon oxide, silicon nitride, or silicon oxynitride), but is not limited thereto. It should be noted that a portion of the bit lines 160 are formed on the dielectric layer 130 above the substrate 100, wherein the dielectric layer 130 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure comprising an oxide layer 131-nitride layer 133-oxide layer 135; the other portion of the bit lines 160 further forms bit line contacts (BLC) 160a below them, extending into the substrate 100 and directly contacting the substrate 100 below (active region 103). Furthermore, the bit line contact 160a is integrally formed with the semiconductor layer 161 of the other part of the bit line 160. On the other hand, each plug 180 is disposed between adjacent bit lines 160 and can directly contact the underlying substrate 100 (including the active region 103 and the insulating region 101) to serve as a storage node contact (SNC) of the semiconductor memory device 300. In one embodiment, the plug 180 is made of a low-resistivity metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and each plug 180 is insulated from each bit line 160 through a spacer structure 170. In one embodiment, the spacer structure 170 may selectively have a single-layer structure or a layered structure. Figure 2 The composite layer structure shown includes, for example, a first spacer 171 (e.g., containing silicon nitride), a second spacer 173 (e.g., containing silicon oxide), and a third spacer 175 (e.g., containing silicon nitride) stacked sequentially on the sidewall of bit line 160, but is not limited thereto.

[0059] Next, a plurality of storage node pads (SN pads) 201 are formed on the substrate 100. The storage node pads 201 are formed, for example, through a self-aligned double patterning (SADP) fabrication process or a self-aligned reverse patterning (SARP) fabrication process, but are not limited thereto. Please refer to [reference needed]. Figure 3 as well as Figure 4As shown, a barrier layer 190 and a metal layer 200 are first formed sequentially above the plug 180 and bit line 160, integrally covering the plug 180 and bit line 160 below. Next, a patterning process is performed to form multiple patterned masks 210 on the metal layer 200 (e.g., ...). Figure 3 As shown), an etching process is performed on the lower plug 180, and then an etching process is performed using a patterned mask 210 as an etching mask to pattern the lower metal layer 200 and barrier layer 190, exposing the lower bit line 160 and further removing part of the capping layer 167 of the bit line 160 (as shown). Figure 4 (As shown). Thus, the storage node pad 201 and the patterned barrier layer 191 can be formed. In one embodiment, the metal layer 200 and the storage node pad 201 contain, for example, a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, and preferably contain a metal material different from that of the plug 180, such as tungsten, while the barrier layer 190 and the patterned barrier layer 191 contain, for example, titanium / titanium nitride (TiN) or tantalum / titanium nitride (TaN), but are not limited thereto.

[0060] It should be noted that during the etching process of metal layer 200, residue 203 may be generated after etching. This residue may include, for example, tungsten-containing materials such as tungsten polymers or tungsten elements, but is not limited to these. After subsequent cleaning processes, the residue 203 may remain on the exposed surfaces of the patterned barrier layer 191 and the dielectric layer (including capping layer 167a and third spacer 175) (such as the sidewalls of patterned barrier layer 191, the sidewalls of third spacer 175, and the top surface of capping layer 167a), thus forming a continuous ( Figure 4 (Rightmost) or discontinuous membrane structures, such as Figure 4 As shown. Then, as Figure 5 As shown, an insulating layer 220 is formed to fill the space between each memory node pad 201 and each patterned barrier layer 191, and is located above the plug 180 and bit line 160 to completely cover the residue 203. The insulating layer 220 may be made of materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, which can effectively isolate each memory node pad 201 and the residue 203 generated therefrom, and prevent the residue 203 from containing conductive elements (such as tungsten) from causing mutual conductivity between adjacent memory node pads 201.

[0061] Thus, the semiconductor memory device 300 of the first embodiment of the present invention is completed. According to the formation method of this embodiment, the memory node pads 201 and the patterned barrier layer 191 are formed through a self-aligned double patterning process or a self-aligned reverse patterning process, so that the memory node pads 201 can be electrically connected to the underlying memory node plugs (i.e., plugs 180) and electrically connected to the transistor components (not shown) of the semiconductor memory device 300. Furthermore, an insulating layer 220 is formed between each memory node pad 201, which surrounds the outside of each memory node pad 201 to act as a storage node isolation layer, isolating adjacent memory nodes (not shown) and preventing adjacent memory node pads 201 from conducting to each other. This avoids short circuits, allowing the semiconductor memory device 300 of this embodiment to achieve optimized device performance.

[0062] However, in some cases, the residue 203 may also form a continuous film structure on the exposed surfaces (such as the top surface and sidewalls) of the patterned barrier layer 191 and the dielectric layer (including the capping layer 167a and the third spacer wall 175), such as... Figure 5 The U-shaped structure 203a shown on the far right, even when covered by the subsequently formed insulating layer 220, may still cause short circuits due to interconnection between adjacent memory node pads 201. Therefore, to meet actual product requirements, this invention provides other forms of semiconductor memory devices and their formation methods to further improve the short circuit problem caused by the residue 203 generated during the etching process of the metal layer 200. Other embodiments or variations of the semiconductor memory device method of this invention will be further described below. For simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0063] Please refer to Figures 6 to 10 The diagram illustrates the steps of a method for forming a semiconductor memory device 400 according to a second embodiment of the present invention. The steps for forming the front end of the semiconductor memory device 400 in this embodiment are generally the same as those for forming the front end of the semiconductor memory device 300 in the first embodiment described above, such as... Figures 1 to 3 As shown, further details are omitted here. The main difference between this embodiment and the first embodiment described above is the additional formation of an isolation sidewall 240.

[0064] In detail, the forming method of this embodiment is based on forming such Figure 3Following the structure shown, an etching process is performed using the capping layer 167 of bit line 160 as an etch stop layer to pattern the underlying metal layer 200 and barrier layer 190, exposing the underlying bit line 160 and forming the memory node pads 201 and the patterned barrier layer 191. It should be noted that, under this operation, the residue 205 generated after etching the metal layer 200 will remain on the sidewalls of the patterned barrier layer 191, the top surface of the capping layer 167, and the top surface of the third spacer wall 175, even after subsequent cleaning processes, forming continuous or discontinuous film structures, such as... Figure 6 As shown. Next, as Figure 7 As shown, a first deposition process, preferably atomic layer deposition, is performed to form an isolation layer 230 on the substrate 100, which integrally covers the underlying memory node pads 201, patterned barrier layer 191, residue 205, and capping layer 167. In one embodiment, the isolation layer 230 may be made of materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, preferably silicon nitride, but is not limited thereto.

[0065] Then, a first etching process is performed to partially remove the isolation layer 230 and a portion of the remaining material 205 below it, forming an isolation sidewall 240 located on opposite sides of the memory node pad 201 and the patterned barrier layer 191. Next, using the isolation sidewall 240 and the memory node pad 201 as an etching mask, another etching process is performed to remove a portion of the capping layer 167 of the bit line 160, such as... Figure 8 As shown. It should be noted that the isolation sidewall 240 is disposed on the spacer wall structure 170 (e.g., the third spacer wall 175) and includes an upper half and a lower half stacked in sequence. The upper half includes the isolation layer 231 after the first etching process, which may be made of materials such as silicon nitride. The lower half includes the isolation layer 231 and the residue 205a after the first etching process. The residue 205a may include tungsten polymer, tungsten element, or other tungsten-containing materials, but is not limited thereto. In this way, the continuous film structure that the residue 205 may form can be cut off through the first etching process, especially the residue 205 remaining on the horizontal surface (such as the top surface of the capping layer 167 and the third gap wall 175), cutting off the conductive path formed by the residue 205 between adjacent memory node pads 201, and the isolation sidewall 240 is used to initially isolate adjacent memory node pads 201 and the remaining residue 205a, so as to prevent adjacent memory node pads 201 from conducting to each other.

[0066] Subsequently, a cleaning process can be performed first, followed by the formation of an insulating layer 261, which is then filled into the spaces between each memory node pad 201 and each patterned barrier layer 191, and positioned above the plug 180 and bit line 160. Please refer to... Figure 9as well as Figure 10 As shown, the cleaning process includes, for example, an oxygen treatment process, in which a chemical agent (not shown) is first introduced to clean the etched surfaces of the insulating layer 231 and the capping layer 167a. The chemical agent can react with the exposed surfaces of the dielectric layer (including the insulating sidewall 240, the third spacer wall 175, and the capping layer 167a) to form a U-shaped oxygen interface layer 250 (e.g., ...). Figure 9 (As shown), then, a second deposition process is performed to integrally form an insulating material layer 260 on the substrate 110, filling the space between the isolation sidewalls 240 and each patterned barrier layer 191, the capping layer 167a that directly contacts the bit line 160, and further covering the top surface of the memory node pad 201 (as shown). Figure 9 As shown), then a second etching process is performed to partially remove the insulating material layer 260, forming the insulating layer 261 (as shown). Figure 10 (As shown). It should be noted that the oxygen interface layer 250 is formed on the exposed surfaces of the isolation sidewall 240, the third spacer wall 175, and the capping layer 167a, with its bottom surface directly contacting the top surface of the capping layer 167a, as shown. Figure 9 As shown; the insulating layer 261 fills the space between each storage node pad 201 and each patterned barrier layer 191, and is entirely surrounded by the oxygen interface layer 250. Thus, a portion of the oxygen interface layer 250 may be located between the isolation sidewall 240 and the insulating layer 261, and another portion of the oxygen interface layer 250 may extend below the isolation sidewall 240, directly contacting a portion of the sidewall of the third spacer wall 175 and the top surface of the capping layer 167a, as shown. Figure 10 As shown.

[0067] Thus, adjacent memory node pads 201 can be isolated from each other by the sequentially arranged isolation sidewalls 240, oxygen interface layer 250, and insulating layer 261, thereby effectively preventing conductive connections between adjacent memory node pads 201. In one embodiment, the insulating material layer 260 and the insulating layer 261 include materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, preferably including the same material as the isolation layer 230. For example, both the isolation layer 230 and the insulating layer 261 (insulating material layer 260) may include silicon nitride, but they can be formed through different fabrication processes (such as atomic layer deposition and deposition processes) to achieve different densities, but this is not a limitation.

[0068] Thus, the semiconductor memory device 400 of the second embodiment of the present invention is completed. According to the formation method of this embodiment, an isolation layer 230 is additionally formed and its etch-back fabrication process is performed. In this way, the residue 205 generated after etching the metal layer 200 can be etched along with the isolation layer 230 during the subsequent etch-back fabrication process, breaking its continuous film structure. Under this operation, not only can the short-circuit problem caused by the residue generated by the etching process of the metal layer 200 be effectively improved, but the residue 205a after the etch-back fabrication process and the isolation layer 231 can together form an isolation sidewall 240, located on both opposite sides of the memory node pads 201, helping to isolate adjacent memory node pads 201 and prevent them from conducting to each other. Therefore, the semiconductor memory device 400 of this embodiment can achieve more optimized device performance.

[0069] Please refer to Figure 11 The diagram illustrates a cross-sectional view of the semiconductor memory device 500 in the third embodiment of the present invention. The formation steps of the semiconductor memory device 500 in this embodiment are generally the same as those of the semiconductor memory device 400 in the aforementioned second embodiment, and will not be repeated here. The main difference between this embodiment and the aforementioned second embodiment lies in the staged etching process of the metal layer 200 and the barrier layer 190.

[0070] In detail, the forming method of this embodiment is based on forming such Figure 3 Following the structure shown, an etching process is performed using the barrier layer 190 as an etch stop layer, while only the underlying metal layer 200 is patterned to form the memory node pad 201. It should be noted that in this operation, the residue (not shown) generated after etching the metal layer 200 will only remain on the top surface of the barrier layer 190. This residue will then be etched and cut off during the back etch process of the isolation layer 230, forming residue 207, located on both opposite sides of the memory node pad 201 and below the etched isolation layer 233. Figure 11 As shown. Next, the lower barrier layer 190 is patterned to form a patterned barrier layer 193, and an insulating layer 261 is formed, filling the space between the isolation sidewalls 240a and the patterned barrier layers 193. Thus, the isolation layer 233 and the remaining material 207 can also jointly form the isolation sidewalls 240a, located on opposite sides of the storage node pads 201, and positioned above the patterned barrier layers 193, as shown. Figure 11 As shown. Under this configuration, adjacent memory node pads 201 can be isolated from each other by the isolation sidewalls 240a and the insulating layer 261 arranged therebetween, thereby effectively preventing adjacent memory node pads 201 from conducting.

[0071] Thus, the semiconductor memory device 500 of the third embodiment of the present invention is completed. According to the formation method of this embodiment, an etching process is first performed on the metal layer 200, followed by the formation of an isolation layer 230 and its etch-back process, and then an etching process is performed on the barrier layer 190. In this way, the residue generated after etching the metal layer 200 remains only on the top surface of the barrier layer 190, and is etched together with the subsequent etch-back process of the isolation layer 230, severing its continuous film structure and forming residue 207. This operation not only effectively improves the short-circuit problem caused by the residue generated by the etching process of the metal layer 200, but the residue 207 after the etch-back process and the isolation layer 233 can jointly form an isolation sidewall 240a, located on both opposite sides of the memory node pads 201, to help isolate adjacent memory node pads 201 and prevent them from conducting to each other. Therefore, the semiconductor memory device 500 of this embodiment can also achieve more optimized device performance.

[0072] In general, this invention involves providing an insulating layer, an oxygen interface layer, and / or an isolation sidewall (including an isolation layer) between adjacent memory node pads to isolate the memory node pads, prevent conductivity, and thereby optimize the device performance of the semiconductor memory device. The isolation layer may include materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride to effectively mitigate short-circuit problems caused by residues from the etching process of the metal layer. The insulating layer and the insulating layer preferably comprise the same dielectric material but have different densities. For example, both the insulating layer and the insulating layer may comprise silicon nitride, but can be formed using different fabrication processes (such as atomic layer deposition and deposition processes) to achieve different densities, but this is not a limitation.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that, include: Substrate; Multiple bit lines are disposed on the substrate; Bit line contacts extend into the substrate and directly contact the substrate below, wherein the bit line contacts are integrally formed with the semiconductor layer of the bit line; Multiple plugs are disposed on the substrate and are alternately and spaced apart from the bit lines; The gap wall structure located between the plug and the bit line; Multiple memory node pads are disposed above the plug and the bit line and in direct contact with the plug; and An isolation sidewall is disposed on the sidewall of the storage node pad, the isolation sidewall comprising an upper half and a lower half made of different materials; and the upper half and the lower half are stacked sequentially on the spacer wall structure.

2. The semiconductor memory device according to claim 1, characterized in that, It also includes an insulating layer disposed above the plug and the bit line, and located between adjacent memory node pads.

3. The semiconductor memory device according to claim 2, characterized in that, It also includes an oxygen interface layer surrounding the insulating layer.

4. The semiconductor memory device according to claim 3, characterized in that, The oxygen interface layer is partially disposed below the isolation sidewall.

5. The semiconductor memory device according to claim 3, characterized in that, The oxygen interface layer is partially disposed between the isolation sidewall and the insulating layer.

6. The semiconductor memory device according to claim 1, characterized in that, The lower half contains a tungsten polymer.

7. The semiconductor memory device according to claim 2, characterized in that, The upper part and the insulating layer contain the same dielectric material, but have different densities.

8. A method for forming a semiconductor memory device, characterized in that... include: Provide substrate; Multiple bit lines are formed on the substrate; A plurality of plugs are formed on the substrate, the plugs being alternately and spaced from the bit lines; Multiple memory node pads are formed above the plug and the bit line, directly contacting the plug; A gap wall structure is formed between the plug and the bit line; as well as An isolation sidewall is formed on the sidewall of the storage node pad, the isolation sidewall comprising an upper half and a lower half of different materials; and the upper half and the lower half are stacked sequentially on the gap wall structure.

9. A method for forming a semiconductor memory device according to claim 8, characterized in that, Also includes: A metal layer is formed above the plug and the bit line; The metal layer is patterned to form the memory node pads; as well as After the isolation sidewall is formed, an insulating layer is formed between the storage node pads.

10. A method for forming a semiconductor memory device according to claim 9, characterized in that, Also includes: A barrier layer is formed above the plug and the bit line, located below the metal layer; as well as The barrier layer is patterned simultaneously with the metal layer to form a patterned barrier layer, wherein the isolation sidewalls are formed on the storage node pads and the two opposite sidewalls of the patterned barrier layer.

11. A method for forming a semiconductor memory device according to claim 9, characterized in that, Also includes: The first deposition process is performed to form an isolation layer on the substrate; The first etching process is performed to form the isolation sidewall; A second deposition process is performed to form an insulating material layer on the substrate. The insulating layer and the insulating material layer contain the same dielectric material but have different densities. as well as A second etching process is performed to form the insulating layer.

12. A method for forming a semiconductor memory device according to claim 11, characterized in that, The first deposition process is atomic layer deposition.

13. A method for forming a semiconductor memory device according to claim 11, characterized in that, After patterning the metal layer, the first deposition process is performed.

14. The method for forming a semiconductor memory device according to claim 11, characterized in that, Also includes: After the first etching process, the exposed bit lines are partially removed, and the insulating material layer directly contacts the bit lines.

15. A method for forming a semiconductor memory device according to claim 14, characterized in that, Also includes: An oxygen treatment process is performed to form an oxygen interface layer between the isolation sidewall and the insulating layer.

16. A method for forming a semiconductor memory device according to claim 15, characterized in that, The oxygen treatment process is performed before the second deposition process.

17. A method for forming a semiconductor memory device according to claim 15, characterized in that, A portion of the oxygen interface layer extends below the isolation sidewall, and another portion is disposed between the isolation sidewall and the insulating layer.

18. A method for forming a semiconductor memory device according to claim 11, characterized in that, Also includes: A barrier layer is formed above the plug and the bit line, located below the metal layer; as well as After the first etching process, the barrier layer is patterned to form a patterned barrier layer, wherein the isolation sidewall is located above the patterned barrier layer.

19. A method for forming a semiconductor memory device according to claim 8, characterized in that, The lower half contains a tungsten polymer.

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