Semiconductor package

Abstract

Semiconductor packages including redistribution substrates including insulating layers and redistribution patterns in the insulating layers can be provided. Each redistribution pattern can include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion can be connected to each other to form a single object. A horizontal level of a bottom surface of the pad portion can be lower than a horizontal level of a bottom surface of the line portion. A width of the line portion can have a maximum value at a horizontal level between a top surface of the line portion and the bottom surface of the line portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application Nos. 10-2020-0096176 and 10-2021-0006217, filed with the Korean Intellectual Property Office on July 31, 2020 and January 15, 2021, respectively, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor packages, and more particularly to semiconductor packages that include a redistributed substrate and have increased integration density and improved reliability. Background Technology

[0004] Semiconductor packages are configured to easily incorporate semiconductor chips as part of electronic products. Typically, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and electrically connected to it via bonding wires or bumps. With the development of the electronics industry, numerous studies are underway to improve the reliability and reduce the size of semiconductor packages. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide semiconductor packages with increased integration density and improved reliability.

[0006] According to an exemplary embodiment of the present invention, a semiconductor package may include a redistributed substrate comprising an insulating layer and a redistributed pattern therein. Each redistributed pattern may include a via portion, a pad portion perpendicularly overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. The horizontal level of the bottom surface of the pad portion may be lower than the horizontal level of the bottom surface of the line portion, and the width of the line portion may have a maximum value at a horizontal level between the top surface and the bottom surface of the line portion.

[0007] According to an exemplary embodiment of the present invention, a semiconductor package may include a redistributed substrate comprising an insulating layer and a redistributed pattern therein. Each redistributed pattern may include a via portion, a pad portion, and a line portion connected to each other to form a single object. The pad portion may overlap perpendicularly with the via portion, and the line portion may extend from the pad portion. The horizontal level of the bottom surface of the pad portion may be lower than the horizontal level of the bottom surface of the line portion. The side surfaces of the via portion may have a linear shape, and the side surfaces of the pad portion may have an arcuate shape.

[0008] According to an exemplary embodiment of the present invention, a semiconductor package may include: a lower redistribution substrate including an insulating layer and a first redistribution pattern therein; a first semiconductor chip located on the lower redistribution substrate and including chip pads; a first connection terminal located between the lower redistribution substrate and the chip pads of the first semiconductor chip, and connecting the lower redistribution substrate and the chip pads of the first semiconductor chip; a molding layer located on the lower redistribution substrate to cover the first semiconductor chip; metal pillars disposed around the first semiconductor chip, penetrating the molding layer, and connected to the lower redistribution substrate; and an upper redistribution substrate located on the molding layer. The upper redistribution substrate may include an upper insulating layer and an upper redistribution pattern therein. Each of the first redistribution patterns may include a first passage portion, a first pad portion, and a first line portion connected to each other to form a single object. The first pad portion may overlap perpendicularly with the first passage portion, and the first line portion may extend from the first pad portion. The horizontal height of the bottom surface of the first line portion can decrease as the distance from the center portion of the first line portion in the outward direction increases. Attached Figure Description

[0009] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0010] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 10 , Figure 11 , Figure 12 and Figure 13 The cross-sectional view illustrates a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0011] Figure 8 This is a top view illustrating, exemplarily, a first redistribution pattern and a second redistribution pattern of a redistribution substrate according to an exemplary embodiment of the concept of the present invention.

[0012] Figure 9A , Figure 9B and Figure 9C They are shown separately. Figure 7 Enlarged cross-sectional views of parts aa, bb, and cc.

[0013] Figure 14This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0014] Figure 15 It is shown Figure 14 A magnified cross-sectional view of part of dd.

[0015] Figure 16 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0016] Figure 17 It is shown Figure 16 A magnified cross-sectional view of part of ee.

[0017] Figure 18 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0018] Figure 19 This is a schematic top view illustrating an example embodiment of a semiconductor package according to the concept of the present invention.

[0019] Figure 20 It is along Figure 19 A cross-sectional view taken along line I-I' to illustrate a semiconductor package according to an exemplary embodiment of the concept of the present invention.

[0020] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as defining or limiting the range of values ​​or properties contained in the exemplary embodiments. For example, the relative thickness and location of molecules, layers, regions, and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0021] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which some exemplary embodiments are shown.

[0022] While the terms “same,” “equal,” or “identical” are used in the description of the exemplary embodiments, it should be understood that some imprecisions may exist. Therefore, when an element is described as being the same as another element, it should be understood that one element is the same as the other element within a desired range of manufacturing or operational tolerances (e.g., ±10%). Similarly, when the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) around the listed value. Furthermore, when the words “generally” and “substantially” are used in conjunction with geometry, it is intended that no precision of the geometry is required, but the dimensions of the shape are within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “approximately” or “substantially,” it should be understood that these numerical values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the listed value or shape.

[0023] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 10 , Figure 11 , Figure 12 and Figure 13 The cross-sectional view illustrates a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0024] Reference Figure 1 An adhesive layer ADL can be formed on a carrier substrate CR. The carrier substrate CR can be a glass substrate. The adhesive layer ADL can be formed of, for example, an insulating material or a polymer tape including an insulating material. In an example embodiment, a metal layer can be formed prior to forming the adhesive layer ADL to protect the carrier substrate CR.

[0025] A first insulating layer 10 may be formed on the adhesive layer AD1. The formation of the first insulating layer 10 may include performing a coating process (e.g., spin coating or slot coating) and a curing process. The first insulating layer 10 may be formed of or include at least one photoimageable dielectric material. The first insulating layer 10 may include, for example, a photoimageable polymer. The photoimageable polymer may include at least one of, for example, photoimageable polyimide, polybenzoxazole, phenolic polymer, or benzocyclobutene polymer.

[0026] A first hard mask layer HM1 may be formed on the first insulating layer 10. The first hard mask layer HM1 may be formed of or comprise a material selected to have etch selectivity relative to the first insulating layer 10. The first hard mask layer HM1 may be formed of or comprise at least one metallic material (e.g., titanium, titanium nitride, tantalum, tantalum nitride, or tungsten). For example, the first hard mask layer HM1 may be formed of or comprise titanium.

[0027] A first photoresist pattern PR1 can be formed on a first hard mask layer HM1. The formation of the first photoresist pattern PR1 may include forming a photoresist layer on the first hard mask layer HM1, and performing exposure and development processes on the photoresist layer.

[0028] Reference Figure 1 and Figure 2 The first hard mask layer HM1 can be patterned using a first photoresist pattern PR1 as an etching mask. Subsequently, the patterned first hard mask layer HM1 can be used as an etching mask to pattern the first insulating layer 10. The patterning process can include, for example, a dry etching process. As a result of the patterning process, multiple openings OP can be formed to penetrate the first insulating layer 10.

[0029] After the patterning process of the first insulating layer 10 and the first hard mask layer HM1, the first photoresist pattern PR1 and the remaining portion of the first hard mask layer HM1 can be removed. In an example embodiment, the remaining portion of the first hard mask layer HM1 can be removed by a wet etching process.

[0030] Next, a seed / barrier layer 11 can be formed on the first insulating layer 10 and the adhesive layer ADL. The seed / barrier layer 11 can be formed of or include at least one conductive material (e.g., copper / titanium (Cu / Ti)). A metal layer 13 can be formed on the seed / barrier layer 11 to fill the opening OP in the first insulating layer 10. The metal layer 13 can be formed of or include at least one metallic material (e.g., copper) and can extend to a region on the top surface of the first insulating layer 10. The metal layer 13 can be formed by an electroplating process using the seed / barrier layer 11 as an electrode.

[0031] Reference Figure 3A planarization process can be performed on the seed / barrier layer 11 and the metal layer 13 to form an under-bump pattern (UBM). The UBM may include a seed / barrier pattern (BP) and a metal pattern (MP). As a result of the planarization process, the seed / barrier layer 11 and the metal layer 13 can be formed as a seed / barrier pattern (BP) and a metal pattern (MP), respectively. The seed / barrier pattern (BP) can be disposed in the first insulating layer 10, and can be disposed between the bottom surface of the metal pattern (MP) and the first insulating layer 10, and between the side surface of the metal pattern (MP) and the first insulating layer 10.

[0032] In an example embodiment, a chemical mechanical polishing process can be used to perform the planarization process. The planarization process can be performed until the top surface of the first insulating layer 10 is exposed.

[0033] Reference Figure 4 A second insulating layer 20, including a preliminary via PVH, can be formed on the first insulating layer 10. The second insulating layer 20 may include the same or similar photoimageable dielectric material as the first insulating layer 10. The preliminary via PVH can be formed as part of an exposed under-bump pattern (UBM). The preliminary via PVH can be formed by performing an exposure and development process on the second insulating layer 20. Thereafter, a curing process can be performed on the second insulating layer 20.

[0034] A second hard mask layer HM2 can be formed on the second insulating layer 20, on which the initial via PVH is provided. The second hard mask layer HM2 can conformally cover the inner surface of the initial via PVH and the top surface of the second insulating layer 20. The second hard mask layer HM2 can cover the top surface of the under-bump pattern UBM exposed through the initial via PVH.

[0035] A second photoresist pattern PR2 can be formed on the second hard mask layer HM2. The second photoresist pattern PR2 can be formed by forming a photoresist layer on the second hard mask layer HM2 and performing exposure and development processes on the photoresist layer.

[0036] The second photoresist pattern PR2 can be formed with an opening that exposes a portion of the second hard mask layer HM2. The second photoresist pattern PR2 may include a first opening region R1, a second opening region R2, a third opening region R3, and a fourth opening region R4.

[0037] The first opening region R1 may define the area in which the first trench will be formed. The second opening region R2 may define the area in which the second trench will be formed. The third opening region R3 may define the area in which the third trench will be formed. The fourth opening region R4 may define the area in which the fourth trench will be formed. The first opening region R1 may overlap perpendicularly with the initial through-hole PVH.

[0038] Reference Figure 4 and Figure 5 The second photoresist pattern PR2 can be used as an etching mask to perform an anisotropic etching process on the second hard mask layer HM2. Therefore, a hard mask pattern HMP can be formed on the second insulating layer 20. The anisotropic etching process on the second hard mask layer HM2 can be performed using at least one of the following processes: reactive ion etching (RIE), magnetically enhanced reactive ion etching (MERIE), inductively coupled plasma (ICP) etching, transformer coupled plasma (TCP) etching, hollow anode plasma etching, or spiral resonator plasma etching.

[0039] Next, an anisotropic etching process can be performed on the second insulating layer 20 using a hard mask pattern (HMP) as an etching mask.

[0040] Therefore, first to fourth trenches T1, T2, T3, and T4 can be formed in the second insulating layer 20, and through-holes VH can be formed to expose the pattern UBM under the bump. The first trench T1, second trench T2, third trench T3, and through-hole VH can be connected to each other. When viewed in a top view, both the first trench T1 and the third trench T3 can be shaped as, for example, circular holes. The second trench T2 can be a linear region extending in the first direction D1 and / or the second direction D2. The fourth trench T4 can be a linear region extending in the first direction D1 and / or the second direction D2. Figure 5 In the figure, the portion of the second groove T2 extending in the first direction D1 is indicated by reference numeral T2a, and the portion of the second groove T2 extending linearly in the second direction D2 is indicated by reference numeral T2b. The portion of the fourth groove T4 extending in the second direction D2 is shown as an example. The width of each of the first groove T1, the third groove T3, and the fourth groove T4 may be greater than the width of the second groove T2.

[0041] Due to the loading effect that may occur during the formation of the first trench T1 and the second trench T2 with different widths, the second trench T2 may have a depth different from that of the first trench T1. In an example embodiment, the depth of the first trench T1 may be greater than the depth of the second trench T2. The widths of the third trench T3 and the fourth trench T4 may be greater than the width of the second trench T2. The depths of the third trench T3 and the fourth trench T4 may be greater than the depth of the second trench T2.

[0042] Because the first trench T1 is being formed Figure 4Since the initial via PVH is formed after the anisotropic etching of the second insulating layer 20, the corner portion where the initial via PVH and the first trench T1 connect to each other can have an arcuate surface or a sloping surface. The corner portion can have a varying profile that defines a width in the D1 direction that varies along the vertical direction (e.g., along the D3 direction).

[0043] Furthermore, the lower corner of the second groove T2 can be arc-shaped, and the horizontal height of the central portion of the bottom surface of each second groove T2 can be higher than the horizontal height of the edge portion of its bottom surface.

[0044] Furthermore, due to the booming effect that may occur during the etching process forming the first trench T1 to the fourth trench T4, the first trench T1 to the fourth trench T4 may have curved side surfaces. For example, the first trench T1 to the fourth trench T4 may have laterally convex side surfaces.

[0045] Reference Figure 6 The second photoresist pattern PR2 and the hard mask pattern HMP can be removed. The second photoresist pattern PR2 can be removed using a stripping process. The hard mask pattern HMP can be removed using a wet etching process.

[0046] Subsequently, a seed / barrier layer 11 and a metal layer 13 can be formed sequentially to fill the via VH and the first trench T1 to the fourth trench T4.

[0047] The seed / barrier layer 11 can be deposited on the second insulating layer 20, which has vias VH and first trenches T1 to fourth trenches T4, to have a substantially uniform thickness. In other words, the seed / barrier layer 11 can be configured to conformally cover the inner surface of the via VH, the inner surfaces of the first trenches T1 to fourth trenches T4, and the top surface of the second insulating layer 20. The seed / barrier layer 11 can be formed by PVD, CVD, or ALD processes.

[0048] The metal layer 13 can be formed to completely fill the via VH and the first trench T1 to the fourth trench T4 where the seed / barrier layer 11 is provided. The metal layer 13 can also be formed on the top surface of the second insulating layer 20. The metal layer 13 can be formed by an electroplating process.

[0049] Reference Figure 7 A planarization process can be performed on the metal layer 13 and the seed / barrier layer 11 to expose the top surface of the second insulating layer 20. The planarization process can be performed using a chemical mechanical polishing (CMP) process. Through the planarization process, a first redistribution pattern RDL1 and a second redistribution pattern RDL2, separated from each other, can be formed. Both the first redistribution pattern RDL1 and the second redistribution pattern RDL2 can include a seed / barrier pattern BP and a metal pattern MP.

[0050] The first redistribution pattern RDL1 can be a line used to transmit signals, and the second redistribution pattern RDL2 can be a dummy line or a power line connected to a power source.

[0051] The first redistribution pattern RDL1 and the second redistribution pattern RDL2 may have substantially flat or smooth top surfaces. Furthermore, the top surface of the second redistribution pattern RDL2 may be substantially coplanar with the top surface of the second insulating layer 20.

[0052] Figure 8 It is a top view schematically showing the first and second redistribution patterns.

[0053] Reference Figure 7 and Figure 8 The first redistribution pattern RDL1 may include a first pass pad portion VP1, a first line portion L1, and a first connection pad portion CP1. A first pass portion V1 penetrating the second insulating layer 20 may be provided. The first pass pad portion VP1 may be connected to the first pass portion V1 and may be disposed within the second insulating layer 20. The first connection pad portion CP1 may be connected to an end of the first line portion L1 and may be disposed within the second insulating layer 20. The first line portions L1 may extend in a first direction D1 and / or a second direction D2 and may be spaced apart from each other.

[0054] The first redistribution pattern RDL1 may have a minimum width (hereinafter, first width W1) at the first line portion L1, and the first width W1 may be from approximately 0.5 μm to approximately 2.0 μm. The first line portions L1 may be spaced apart from each other by a first distance S1. The first distance S1 and the first width W1 may be substantially equal to each other.

[0055] In an example embodiment, the second redistribution pattern RDL2 may have a shape similar to the first redistribution pattern RDL1, except that the second redistribution pattern RDL2 has a wider width than the first redistribution pattern RDL1. The second redistribution pattern RDL2 may include a second pass pad portion VP2, a second line portion L2, and a second connection pad portion CP2. A second pass portion V2 penetrating the second insulating layer 20 may be provided. The second pass pad portion VP2 may be connected to the second pass portion V2 and may be disposed within the second insulating layer 20. The second connection pad portion CP2 may be connected to the end of the second line portion L2 and may be disposed within the second insulating layer 20. The second redistribution pattern RDL2 may have a minimum width (hereinafter, the second width W2) at the second line portion L2, and the second width W2 may be from approximately 3.0 μm to approximately 10.0 μm.

[0056] Figure 9A , Figure 9B and Figure 9C They are shown separately. Figure 7 Enlarged cross-sectional views of parts aa, bb, and cc.

[0057] Reference Figure 7 and Figure 9A Each of the first redistribution patterns RDL1 may include a seed / block pattern BP and a metal pattern MP. The seed / block pattern BP may be provided to cover the side and bottom surfaces of the metal pattern MP.

[0058] The first thickness H1 of the first path pad portion VP1 of the first redistribution pattern RDL1 can be greater than the second thickness H2 of the first line portion L1. The first thickness H1 can be approximately 3.0 μm to 4.3 μm, and the second thickness H2 can be 2.7 μm to 3.5 μm. The bottom surface B1 of the first path pad portion VP1 can be located at a horizontal height lower than the bottom surface B2 of the first line portion L1. The horizontal height difference LV1 between the bottom surface B1 of the first path pad portion VP1 and the bottom surface B2 of the first line portion L1 can be approximately 0.3 μm to 0.8 μm.

[0059] In the first redistribution pattern RDL1, the first path pad portion VP1 and the first line portion L1 may have a top surface that is substantially coplanar with the top surface of the second insulating layer 20. The first path pad portion VP1 and the first line portion L1 may each have arcuate side surfaces VPS and LS, respectively. The side surface VPS of the first path pad portion VP1 and the side surface LS of the first line portion L1 may be laterally convex. The side surface VS of the first path portion V1 may have a relatively linear shape.

[0060] The angle between the side surface VS of the first channel portion V1 and the bottom surface B3 of the first channel portion V1 can be greater than 95°. According to an exemplary embodiment of the present invention, the side surface VS of the first channel portion V1 can have a linear shape, while the side surface VPS of the first channel pad portion VP1 can have an arcuate shape. This is because, as referenced... Figure 4 and Figure 5 The via VH is formed by optical patterning, and the first trench T1 is formed by etching.

[0061] The edge portion EG where the side surface VPS of the first pad portion VP1 and the side surface VS of the first channel portion V1 connect to each other can have an arc shape. In other words, the bottom surface of the first pad portion VP1 and the side surface of the first channel portion V1 are connected to form an edge portion with an arc shape. See reference. Figure 5During the anisotropic etching of the hard mask pattern HMP, the corner portion where the via VH and the first trench T1 connect to each other can be etched more easily, thus having a sloping surface. The corner portion can define a width in the D1 direction that varies along the vertical direction (e.g., along the D3 direction).

[0062] The metal pattern MP may have a groove portion GP near the seed / blocking pattern BP or near the edge of the top surface of the first line portion L1. The groove portion GP may have a depth greater than 0 nm and less than 300 nm.

[0063] This may be because Figure 7 During the chemical mechanical planarization process, the etching rate of the metal pattern MP is relatively high at the interface between the metal pattern MP and the seed / block pattern BP.

[0064] The diameter CPW of the first path pad portion VP1 can be 1.5 times or more than the first width W1 of the first line portion L1. The diameter CPW of the first path pad portion VP1 has a maximum value at the horizontal height between the top surface and the bottom surface of the first path pad portion VP1.

[0065] Reference Figure 8 and Figure 9B The side surface VS of the first passage portion V1 may include a lower sidewall portion VSB with a first slope and an upper sidewall portion VSU with a second slope. The inflection point N1 of the slope change may exist between the lower sidewall portion VSB and the upper sidewall portion VSU. The absolute value of the first slope may be greater than the absolute value of the second slope. For example, the angle of the first slope may be less than 90°.

[0066] The upper sidewall portion VSU can be connected to the bottom surface B3 of the first pass pad portion VP1 via the lower sidewall portion VSB. The lower sidewall portion VSB and the upper sidewall portion VSU can have substantially linear shapes.

[0067] For reference Figure 5 During the anisotropic etching of the hard mask pattern HMP, the corner portion where the via VH and the first trench T1 connect to each other can be etched more easily, so the upper sidewall portion VSU can be formed with a smaller slope than the lower sidewall portion VSB. The corner portion can define a width in the D1 direction that varies along the vertical direction (e.g., along the D3 direction).

[0068] Reference Figure 8 and Figure 9C The first line portion L1 of the first redistribution pattern RDL1 and the second line portion L2 of the second redistribution pattern RDL2 can be laterally raised.

[0069] For example, the first line portion L1 of the first redistribution pattern RDL1 may have a minimum width (hereinafter, the first width W1) at the horizontal height of the top or bottom surface of the first line portion L1. Furthermore, the first line portion L1 of the first redistribution pattern RDL1 may have a maximum width P1 at the horizontal height between its top and bottom surfaces. In the first line portion L1 of the first redistribution pattern RDL1, the difference between the maximum width P1 and the minimum width W1 (e.g., the width of the top surface of the first line portion L1 and / or the width of the bottom surface of the first line portion L1) may be greater than 0 nm and less than or equal to 300 nm.

[0070] The second line portion L2 of the second redistribution pattern RDL2 may also have a minimum width (hereinafter, the second width W2) at the horizontal height of the top or bottom surface of the second line portion L2.

[0071] The difference LV2 between the horizontal height of the bottom surface B2 of the first line portion L1 of the first redistribution pattern RDL1 and the horizontal height of the bottom surface B4 of the second line portion L2 of the second redistribution pattern RDL2 can be greater than 0 μm and less than 0.5 μm.

[0072] The horizontal height of the bottom surface of the first line portion L1 of the first redistribution pattern RDL1 can decrease as the distance from the center portion of the first line portion L1 in the outward direction increases. In other words, the horizontal height of the bottom surface of the first line portion L1 of the first redistribution pattern RDL1 can be highest at the center portion of the first line portion L1. The difference in horizontal height between the center portion and the edge portion of the bottom surface of the first line portion L1 can be greater than 0 nm and less than 300 nm.

[0073] This may be because of the use Figure 4 and Figure 5 In the process of HMP etching the second insulating layer 20 using a hard mask pattern, the exposed edge portions of the second insulating layer 20 are etched more.

[0074] The edge portion of the bottom surface of the first line portion L1 of the first redistribution pattern RDL1 may have an arc shape. As an example, the edge portion of the bottom surface of the first line portion L1 of the first redistribution pattern RDL1 may have a radius of curvature RA of 0.3 μm or greater.

[0075] According to an exemplary embodiment of the present invention, as described above, the first redistribution pattern RDL1 may include a seed / block pattern BP and a metal pattern MP, and the seed / block pattern BP may be disposed between the metal pattern MP and the second insulating layer 20 to mitigate or prevent material reaction between the metal pattern MP and the second insulating layer 20, thereby mitigating or preventing oxidation of the metal pattern MP. Therefore, for fine lines used to transmit signals (e.g., the first redistribution pattern RDL1), the mitigation or prevention of oxidation can make it possible to improve the reliability of the device.

[0076] Reference Figure 10 A third insulating layer 30 can be formed on the second insulating layer 20 to cover the top surfaces of the first redistribution pattern RDL1 and the second redistribution pattern RDL2.

[0077] The third insulating layer 30 may be formed of or comprise at least one photoimageable dielectric material. As an example, the third insulating layer 30 may be formed of or comprise the same polymer material as the second insulating layer 20.

[0078] Next, a via VH can be formed in the third insulating layer 30 to expose a portion of the first redistribution pattern RDL1. In the case where the third insulating layer 30 comprises a photoimageable polymer, the via VH can be formed by performing an exposure and development process on a portion of the third insulating layer 30. After forming the via VH, a curing process can be performed on the third insulating layer 30.

[0079] Similar to the first redistribution pattern RDL1 and the second redistribution pattern RDL2 formed on the second insulating layer 20, the first redistribution pattern RDL1 and the second redistribution pattern RDL2 can be formed on the third insulating layer 30.

[0080] Reference Figure 11 A fourth insulating layer 40 may be formed on the third insulating layer 30. The fourth insulating layer 40 may be formed of or include at least one photoimageable polymer.

[0081] By performing an exposure and development process on a portion of the fourth insulating layer 40, a via VH can be formed to expose a portion of the first redistribution pattern RDL1 and the second redistribution pattern RDL2 disposed in the third insulating layer 30.

[0082] Subsequently, a seed / barrier layer 11 can be formed to conformally cover the surfaces of the fourth insulating layer 40 and the via VH. A third photoresist pattern PR3 with multiple openings can be formed on the seed / barrier layer 11. The openings of the third photoresist pattern PR3 can overlap with the via VH of the fourth insulating layer 40.

[0083] Reference Figure 11 An electroplating process can be performed to form a first bonding pad pattern 44 and a second bonding pad pattern 46 in the openings of the third photoresist pattern PR3. In an example embodiment, the first bonding pad pattern 44 may be formed of or comprise copper, and the second bonding pad pattern 46 may be formed of or comprise at least one metal (e.g., nickel (Ni) and gold (Au)) or an alloy thereof, or may have a multilayer structure comprising at least one metal (e.g., nickel (Ni) and gold (Au)).

[0084] Reference Figure 12 The third photoresist pattern PR3 can be removed using a stripping process. Next, a wet etching process can be used to etch the seed / barrier layer 11 on the top surface of the fourth insulating layer 40. Thus, a bonding pad 48 comprising the seed / barrier pattern BP, the first bonding pad pattern 44, and the second bonding pad pattern 46 can be formed.

[0085] Subsequently, connection terminals 150 can be attached to bonding pads 48 to connect semiconductor chip 100 to redistribution substrate 300.

[0086] Reference Figure 13 The carrier substrate CR and adhesive layer ADL can be removed. Next, the seed / block pattern BP on the bottom surface of the metal pattern MP can be removed to expose the bottom surface of the metal pattern MP disposed in the first insulating layer 10. The seed / block pattern BP can be selectively located between the first insulating layer 10 and the metal pattern MP, and the redistribution substrate 300 can be formed by attaching external connection terminals 390 to the exposed bottom surface of the metal pattern MP.

[0087] The semiconductor package may include a redistribution substrate 300 and a semiconductor chip 100 disposed on the redistribution substrate 300. In an example embodiment, data signals and control signals may be provided to a first redistribution pattern RDL1, the line portions of which each have a minimum width (e.g., a first width W1) at their top or bottom surface.

[0088] The power supply voltage and the ground voltage can be provided to the second redistribution pattern RDL2, the line portions of the second redistribution pattern RDL2 each having a minimum width at their top or bottom surface (e.g., a second width W2 greater than the first width W1).

[0089] Figure 14 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention. Figure 15 It is shown Figure 14 A magnified cross-sectional view of part of dd.

[0090] For the sake of brevity, elements and features similar to those previously shown and described will not be described in further detail in this example.

[0091] Reference Figure 14 and Figure 15 According to this example embodiment, the semiconductor package 1 may include a first semiconductor package PK1 and a second semiconductor package PK2 disposed on the first semiconductor package PK1.

[0092] The first semiconductor package PK1 may include a lower redistribution substrate 300L and an upper redistribution substrate 300U, a first semiconductor chip 100, a metal pillar 306 and a molding layer 370.

[0093] As an example, refer to Figure 16 The redistribution substrate 300L may include first to sixth insulating layers 310, 320, 330, 340, 350, and 360 stacked in sequence. In an example embodiment, the first to sixth insulating layers 310, 320, 330, 340, 350, and 360 may be considered as a single insulating layer.

[0094] The aforementioned bump pattern UBM can be disposed in the first insulating layer 310. The aforementioned first redistribution pattern RDL1 and second redistribution pattern RDL2 can both be disposed in the second insulating layers 320 to the fifth insulating layers 350. A lower bonding pad 48, identical or substantially similar to the aforementioned bonding pad 48, can be provided in the sixth insulating layer 360. The lower bonding pad 48 can correspond to the aforementioned bonding pad 48. The lower bonding pad 48 may include a first lower bonding pad 48a and a second lower bonding pad 48b. In other words, the first redistribution pattern RDL1 and the second redistribution pattern RDL2 can be configured to have the same characteristics as the above-mentioned references. Figure 7 , Figure 8 and Figures 9A to 9C Features that are described as identical or substantially similar.

[0095] Return to reference Figure 14A first semiconductor chip 100 can be disposed on a lower redistribution substrate 300L. When viewed in a top view, the first semiconductor chip 100 can be disposed in the central region of the lower redistribution substrate 300L. A plurality of chip pads 111 can be disposed on the bottom surface of the first semiconductor chip 100. The first semiconductor chip 100 can be disposed such that its bottom surface faces the top surface of the lower redistribution substrate 300L. A first connection terminal 150 can be disposed between the chip pads 111 of the first semiconductor chip 100 and the uppermost redistribution patterns RDL1 and RDL2 of the lower redistribution substrate 300L, and attached to the chip pads 111 of the first semiconductor chip 100 and the uppermost redistribution patterns RDL1 and RDL2 of the lower redistribution substrate 300L. The chip pads 111 of the first semiconductor chip 100 can be connected to a second lower bonding pad 48b and the redistribution patterns RDL1 and RDL2 of the lower redistribution substrate 300L via the first connection terminal 150.

[0096] Metal pillars 306 may be disposed around the first semiconductor chip 100 and may electrically connect the lower redistribution substrate 300L to the upper redistribution substrate 300U. Metal pillars 306 may be configured to penetrate the molding layer 370 and may have a top surface coplanar with the top surface of the molding layer 370. The bottom surface of the metal pillars 306 may be in direct contact with the second lower bonding pad 48b.

[0097] A molding layer 370 may be disposed between a lower redistribution substrate 300L and an upper redistribution substrate 300U to cover the first semiconductor chip 100. The molding layer 370 may be disposed on the top surface of the lower redistribution substrate 300L to cover the side and top surfaces of the first semiconductor chip 100. The molding layer 370 may fill the space between the metal pillars 306, and the thickness of the molding layer 370 may be substantially equal to the length of the metal pillars 306. The molding layer 370 may be formed of or comprise at least one insulating polymer (e.g., epoxy molding compound).

[0098] The second connection terminal 390 can be attached to the UBM pattern under the bump. The second connection terminal 390 can be a solder ball formed of tin, lead, copper, etc.

[0099] The second semiconductor package PK2 may be disposed on the upper redistribution substrate 300U. In an example embodiment, similar to the lower redistribution substrate 300L, the upper redistribution substrate 300U may include upper insulating layers 310U, 320U and 330U, an upper redistribution pattern RDL and an upper bonding pad 49.

[0100] The second semiconductor package PK2 may include a package substrate 710, a second semiconductor chip 200, and an upper molding layer 730. The package substrate 710 may include a printed circuit board. In an example embodiment, a redistribution substrate may be used as the package substrate 710. A lower conductive pad 705 may be disposed on the bottom surface of the package substrate 710.

[0101] The second semiconductor chip 200 may be disposed on the packaging substrate 710. The second semiconductor chip 200 may include an integrated circuit, and in an example embodiment, the integrated circuit may include a memory circuit, a logic circuit, or a combination thereof. The chip pads 221 of the second semiconductor chip 200 may be electrically connected to an upper conductive pad 703 disposed on the top surface of the packaging substrate 710 via wire bonding. The upper conductive pad 703 on the top surface of the packaging substrate 710 may be electrically connected to a lower conductive pad 705 via internal wiring in the packaging substrate 710.

[0102] The upper molding layer 730 may be disposed on the packaging substrate 710 to cover the second semiconductor chip 200. The upper molding layer 730 may be formed of or comprise an insulating polymer (e.g., an epoxy polymer).

[0103] The third connection terminal 750 may be disposed between the lower conductive pad 705 and the upper bonding pad 49 of the package substrate 710. The third connection terminal 750 may be formed of or include at least one tin-containing metal with a low melting temperature (e.g., soldering material), but the inventive concept is not limited to this example.

[0104] Figure 16 This is a cross-sectional view showing an example embodiment of a semiconductor package 2 according to the present invention. Figure 17 It is shown Figure 16 A magnified cross-sectional view of part ee. For the sake of brevity, elements and features similar to those previously shown and described will not be described in further detail.

[0105] Reference Figure 16 and Figure 17 In the semiconductor package 2 according to this embodiment, and Figure 14 and Figure 15 Unlike the example embodiments, the first semiconductor chip 100 can be disposed such that its active surface contacts the top surface of the lower redistribution substrate 300L.

[0106] The lower redistribution substrate 300L may include first to fourth insulating layers 310, 320, 330, and 340 sequentially stacked on the chip pads 111 of the first semiconductor chip 100. A first redistribution pattern RDL1 and a second redistribution pattern RDL2 may be disposed in the first to third insulating layers 310, 320, and 330.

[0107] The path portion V1 of the first redistribution pattern RDL1 can be connected to the chip pad 111 of the first semiconductor chip 100. Although not shown, the path portion of the second redistribution pattern RDL2 can be connected to the chip pad 111 of the first semiconductor chip 100. The first redistribution pattern RDL1 and the second redistribution pattern RDL2 can be configured to have the same characteristics as the reference pattern. Figure 7 , Figure 8 and Figures 9A to 9C Features that are described as identical or substantially similar.

[0108] Figure 18 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention. (Refer to...) Figure 18 According to this example embodiment, the semiconductor package 3 may include a first semiconductor package PK1 and a second semiconductor package PK2 disposed on the first semiconductor package PK1.

[0109] The first semiconductor package PK1 may include a redistribution substrate 300, a connection substrate 400 disposed on the redistribution substrate 300, a first semiconductor chip 100, and a molding layer 450.

[0110] As described above, the redistribution substrate 300 may include insulating layers 310 to 340 and redistribution patterns RDL1 and RDL2.

[0111] The connecting substrate 400 may have an opening formed to expose the top surface of the redistribution substrate 300, and the first semiconductor chip 100 may be disposed in the opening of the connecting substrate 400. The connecting substrate 400 may be provided before or after the first semiconductor chip 100 is provided. As an example, the connecting substrate 400 may be manufactured by forming holes in a printed circuit board. When viewed in top view, the first semiconductor chip 100 may be positioned to overlap with the central portion of the redistribution substrate 300.

[0112] The connecting substrate 400 may include a base layer 410 and a conductive structure 420. The base layer 410 may be formed of or include at least one insulating material. For example, the base layer 410 may be formed of or include at least one of a carbon-based material, a ceramic material, or a polymer material. The conductive structure 420 may include interconnect patterns and interconnect pathways connecting the interconnect patterns. The conductive structure 420 of the connecting substrate 400 may be connected to a first redistribution pattern RDL1 and a second redistribution pattern RDL2 of the redistribution substrate 300. The conductive structure 420 may be formed of or include at least one metallic material. The conductive structure 420 may be formed of or include at least one of, for example, copper, aluminum, gold, lead, stainless steel, silver, iron, or alloys thereof.

[0113] A molding layer 450 may be formed on the first semiconductor chip 100 and the interconnect substrate 400. The molding layer 450 may extend into the gap between the first semiconductor chip 100 and the interconnect substrate 400 to fill the gap. The molding layer 450 may be formed of or comprise at least one insulating polymer (e.g., an epoxy polymer). The molding layer 450 may expose a portion of the conductive structure 420 of the interconnect substrate 400.

[0114] The second semiconductor package PK2 may include a package substrate 710, a second semiconductor chip 200, and an upper molding layer 730. The package substrate 710 may be a printed circuit board. In an example embodiment, a substrate similar to the redistribution substrate 300 may be used as the package substrate 710. A lower conductive pad 705 may be disposed on the bottom surface of the package substrate 710.

[0115] The second semiconductor chip 200 may be disposed on the packaging substrate 710. The second semiconductor chip 200 may include an integrated circuit, and the integrated circuit may include memory circuits, logic circuits, or a combination thereof. The chip pads 221 of the second semiconductor chip 200 may be electrically connected to the lower conductive pads 705 via internal lines 715 disposed in the packaging substrate 710. An upper molding layer 730 may be disposed on the packaging substrate 710 to cover the second semiconductor chip 200. The upper molding layer 730 may be formed of or include at least one insulating polymer (e.g., an epoxy polymer).

[0116] The third connection terminal 750 can be disposed in the upper hole of the molding layer 450. The third connection terminal 750 can contact the conductive structure 420 and the lower conductive pad 705.

[0117] Figure 19This is a schematic top view illustrating an example embodiment of a semiconductor package according to the concept of the present invention. Figure 20 It is along Figure 19 A cross-sectional view taken along line I-I' to illustrate a semiconductor package according to an exemplary embodiment of the concept of the present invention.

[0118] Reference Figure 19 and Figure 20 The semiconductor package 4 according to this example embodiment may include a first semiconductor chip 100 and a second semiconductor chip 200, a redistribution substrate 300, a packaging substrate 500 and a heat dissipation structure 600.

[0119] The first semiconductor chip 100 and the second semiconductor chip 200 can be disposed on the top surface of the redistribution substrate 300.

[0120] The first semiconductor chip 100 may include chip pads 111 disposed on its bottom surface. The first semiconductor chip 100 may be a microelectromechanical system (MEMS) device, an optoelectronic device, or a logic chip including a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a mobile application chip, or a digital signal processor (DSP)). The first semiconductor chip 100 may have a thickness ranging from approximately 700 μm to approximately 775 μm.

[0121] A second semiconductor chip 200 may be disposed on a redistribution substrate 300, spaced apart from the first semiconductor chip 100. Each second semiconductor chip 200 may include a plurality of vertically stacked memory chips 210. The memory chips 210 may be connected to each other via upper chip pads 221 and lower chip pads 223, chip penetration paths 225, and connection bumps 230. The memory chips 210 may be stacked on the redistribution substrate 300 with their side surfaces aligned with each other. An adhesive layer 235 may be disposed between the memory chips 210. In an example embodiment, the adhesive layer 235 may be formed of an insulating material or a polymer tape including an insulating material. The adhesive layer 235 may be interposed between the connection bumps 230 to mitigate or prevent short circuits from forming between the connection bumps 230.

[0122] The first semiconductor chip 100 and the second semiconductor chip 200 can be connected to the redistribution substrate 300 via a first connection terminal 150. The first connection terminal 150 can be attached to the chip pad 111 of the first semiconductor chip 100 and the chip pad 221 of the second semiconductor chip 200. Each first connection terminal 150 can be at least one of a solder ball, a conductive bump, or a conductive pillar.

[0123] A molding layer 370 may be disposed on a redistribution substrate 300 to cover the first semiconductor chip 100 and the second semiconductor chip 200. The side surfaces of the molding layer 370 may be aligned with the side surfaces of the redistribution substrate 300. The top surface of the molding layer 370 may be substantially coplanar with the top surfaces of the first semiconductor chip 100 and the second semiconductor chip 200. The molding layer 370 may be formed of or comprise at least one insulating polymer (e.g., epoxy molding compound).

[0124] The bottom filler layer UF may be located between the first semiconductor chip 100 and the redistribution substrate 300, and between the second semiconductor chip 200 and the redistribution substrate 300. The bottom filler layer UF may be provided to fill the space between the first connection terminals 150. The bottom filler layer UF may include, for example, a thermosetting resin or a photocurable resin. In some example embodiments, the bottom filler layer UF may be omitted, and the space between the bottom surfaces of the first semiconductor chip 100 and the second semiconductor chip 200 and the redistribution substrate 300 may be filled with a molding layer 370.

[0125] The redistribution substrate 300 can be disposed on the packaging substrate 500 and can be connected to the packaging substrate 500 via the second connection terminal 390.

[0126] The redistribution substrate 300 may include a plurality of sequentially stacked insulating layers 310, 320, 330, 340, and 350, and redistribution patterns respectively disposed in the insulating layers 310, 320, 330, 340, and 350. A second connection terminal 390 may be attached to the under-bump pattern UBM. The second connection terminal 390 may be a solder ball formed of tin, lead, copper, etc. The second connection terminal 390 may have a thickness of approximately 40 μm to 80 μm.

[0127] The packaging substrate 500 can be, for example, a printed circuit board, a flexible substrate, a strip substrate, etc. In an example embodiment, the packaging substrate 500 can be one of a flexible printed circuit board, a rigid printed circuit board, or a combination thereof in which internal circuitry 521 is disposed.

[0128] The package substrate 500 may have a top surface and a bottom surface opposite to each other, and may include a top coupling pad 511, an external coupling pad 513, and internal wiring 521. The top coupling pad 511 may be disposed on the top surface of the package substrate 500, and the external coupling pad 513 may be disposed on the bottom surface of the package substrate 500. The top coupling pad 511 may be electrically connected to the external coupling pad 513 via the internal wiring 521. An external coupling terminal 550 may be connected to the external coupling pad 513. A ball grid array (BGA) may be provided as the external coupling terminal 550.

[0129] The heat dissipation structure 600 may be formed of or include at least one thermally conductive material. The thermally conductive material may include metallic materials (e.g., copper and / or aluminum) or carbon-containing materials (e.g., graphene, graphite, and / or carbon nanotubes). The heat dissipation structure 600 may have a relatively high thermal conductivity. As an example, a single metal layer or multiple stacked metal layers may be used as the heat dissipation structure 600. As another example, the heat dissipation structure 600 may include a radiator or heat pipe. As yet another example, the heat dissipation structure 600 may be configured using a water-cooling method.

[0130] A thermally conductive layer 650 may be situated between the first semiconductor chip 100, the second semiconductor chip 200, and the heat dissipation structure 600. The thermally conductive layer 650 may be in contact with the top surface of the semiconductor package and the bottom surface of the heat dissipation structure 600. The thermally conductive layer 650 may be formed of or comprise a thermal interface material (TIM). The thermal interface material may include, for example, a polymer and thermally conductive particles. The thermally conductive particles may be dispersed in the polymer. During operation of the semiconductor package, heat generated within the semiconductor package can be transferred to the heat dissipation structure 600 through the thermally conductive layer 650.

[0131] According to an exemplary embodiment of the present invention, the redistribution substrate may include a fine-width redistribution pattern, and the redistribution pattern may include a metal pattern disposed in an insulating layer, and seed / block patterns disposed between the bottom surface of the metal pattern and the insulating layer, and between the side surface of the metal pattern and the insulating layer. Because the seed / block patterns are located between the side surface of the metal pattern and the insulating layer, contact between the metal pattern and the insulating layer can be reduced or prevented, thereby reducing or preventing accidental oxidation of the metal pattern. Therefore, the integration density and reliability of the redistribution substrate can be improved.

[0132] While some exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: A redistributed substrate, the redistributed substrate comprising an insulating layer and a redistributed pattern located within the insulating layer. Each of the redistribution patterns includes a pathway portion, a pad portion perpendicularly overlapping the pathway portion, and a line portion extending from the pad portion. The pathway portion, the pad portion, and the line portion are connected to each other to form a single object. The bottom surface of the pad portion is at a lower level than the bottom surface of the line portion, and In a direction perpendicular to the extension direction of the line portion and parallel to the top surface of the line portion, the width of the line portion at a horizontal height between the top surface and the bottom surface of the line portion is greater than the width of the line portion at the top surface of the line portion and greater than the width of the line portion at the bottom surface of the line portion.

2. The semiconductor package according to claim 1, wherein, The difference in horizontal height between the bottom surface of the pad portion and the bottom surface of the line portion is 0.2 μm to 0.5 μm.

3. The semiconductor package according to claim 1, wherein, The diameter of the pad portion has its maximum value at a horizontal height between the top surface and the bottom surface of the pad portion.

4. The semiconductor package according to claim 1, wherein, The difference between the maximum width of the line portion and the width of the top surface of the line portion is greater than 0 nm and less than 300 nm.

5. The semiconductor package according to claim 1, wherein, Each of the redistribution patterns includes: Metal pattern, the metal pattern being located within the insulating layer; and A seed / blocking pattern is located between the bottom surface of the metal pattern and the insulating layer, and between the side surface of the metal pattern and the insulating layer.

6. The semiconductor package according to claim 5, wherein, The upper part of the metal pattern has a grooved portion near the seed / blocking pattern.

7. The semiconductor package according to claim 6, wherein, The groove portion has a depth greater than 0 nm and less than 300 nm.

8. The semiconductor package according to claim 1, wherein, The diameter of the pad portion is 1.5 times the width of the line portion.

9. The semiconductor package according to claim 1, wherein, Each of the redistribution patterns further includes a second pad portion connected to the end of the line portion, such that the second pad portion and the line portion form a single object, and The bottom surface of the second pad portion is at a lower level than the bottom surface of the line portion.

10. A semiconductor package, comprising: A redistributed substrate, the redistributed substrate comprising an insulating layer and a redistributed pattern located within the insulating layer. Each of the redistributed patterns includes a pathway portion, a pad portion, and a line portion that are connected to each other to form a single object. The pad portion overlaps perpendicularly with the passage portion. The line portion extends from the pad portion. The bottom surface of the pad portion is at a lower level than the bottom surface of the line portion. The side surface of the passage portion has a linear shape, and The side surface of the pad portion has an arc shape. In a direction perpendicular to the extension direction of the line portion and parallel to the top surface of the line portion, the width of the line portion at a horizontal height between the top surface and the bottom surface of the line portion is greater than the width of the line portion at the top surface of the line portion and greater than the width of the line portion at the bottom surface of the line portion.

11. The semiconductor package of claim 10, wherein, The side surface of the passage portion includes: The lower sidewall portion has a first slope; and The upper sidewall portion has a second slope. The upper sidewall portion is connected to the bottom surface of the pad portion, and The absolute value of the first slope is greater than the absolute value of the second slope.

12. The semiconductor package of claim 11, wherein, The angle of the first slope is less than 90°.

13. The semiconductor package of claim 10, wherein, The bottom surface of the pad portion and the side surface of the passage portion are connected to form an edge portion with an arc shape.

14. The semiconductor package of claim 10, wherein, Each of the redistribution patterns includes: Metal pattern, the metal pattern being located within the insulating layer; and A seed / blocking pattern is located between the bottom surface of the metal pattern and the insulating layer, and between the side surface of the metal pattern and the insulating layer.

15. The semiconductor package of claim 10, wherein, The angle between the side surface of the passage portion and the bottom surface of the passage portion is greater than 95°.

16. A semiconductor package, comprising: A lower redistribution substrate, the lower redistribution substrate comprising an insulating layer and a first redistribution pattern located in the insulating layer; A first semiconductor chip, located on the lower redistribution substrate, and including chip pads; A first connection terminal is located between the lower redistribution substrate and the chip pad of the first semiconductor chip, and connects the lower redistribution substrate and the chip pad of the first semiconductor chip. A molding layer is located on the lower redistribution substrate to cover the first semiconductor chip; Metal pillars are disposed around the first semiconductor chip, penetrate the molding layer, and are connected to the lower redistribution substrate; as well as An upper redistribution substrate, the upper redistribution substrate being located on the molding layer, and including an upper insulating layer and an upper redistribution pattern located in the upper insulating layer, Each of the first redistribution patterns includes a first pathway portion, a first pad portion, and a first line portion that are connected to each other to form a single object. The first pad portion overlaps perpendicularly with the first channel portion. The first line portion extends from the first pad portion, and The horizontal height of the bottom surface of the first line portion decreases as the distance from the center portion of the first line portion increases in the outward direction. In a direction perpendicular to the extension direction of the first line portion and parallel to the top surface of the first line portion, the width of the first line portion at a horizontal height between the top surface and the bottom surface of the first line portion is greater than the width of the first line portion at the top surface and greater than the width of the first line portion at the bottom surface.

17. The semiconductor package of claim 16, wherein, The first line portion has an arc-shaped edge portion between its bottom surface and its side surface, and The arc-shaped edge portion has a radius of curvature of 0.3 μm or greater.

18. The semiconductor package of claim 16, wherein, The difference between the horizontal height of the central portion of the bottom surface of the first line portion and the horizontal height of the edge portion of the bottom surface of the first line portion is greater than 0 nm and less than 300 nm.

19. The semiconductor package of claim 16, wherein, The lower redistribution substrate further includes a second redistribution pattern located in the insulating layer. Each of the first redistribution patterns has a minimum width of a first value at its top or bottom surface. The second redistribution pattern each has a minimum width of a second value at its top or bottom surface. The second value is greater than the first value. The second redistribution pattern includes a second line portion, and The bottom surface of the second line portion is at a lower level than the bottom surface of the first line portion.

20. The semiconductor package of claim 19, wherein, The top surfaces of the first line portion and the second line portion are at the same horizontal height.

Images