Semiconductor device package including sidewalls connected to semiconductor die contact pads

Abstract

A semiconductor device package (100) comprises: a printed circuit board (10) comprising a first central region, a second lateral region and a third lateral region; a semiconductor die (20) comprising a first main face, a second main face opposite the first main face, a first contact pad (20A) disposed on the first main face and a second contact pad (20B) disposed on the second main face, the semiconductor die (20) disposed in the first central region of the printed circuit board (10); a first metal sidewall (30) of the semiconductor device package disposed in the second lateral region of the printed circuit board (10); a second metal sidewall (40) of the semiconductor device package disposed in the third lateral region of the printed circuit board (10); wherein at least one of the first metal sidewall (30) and the second metal sidewall (40) is electrically connected to one of the first contact pad (20A) and the second contact pad (20B) of the semiconductor die (20).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a method for manufacturing the semiconductor device package. Background Technology

[0002] Chip embedding is a solution in which active or passive components are positioned between at least two layers of a printed circuit board. Currently, it is commonly used in low-voltage signal processing systems, with initial attempts to apply embedding to low-voltage (<100V) power circuits. However, for high-voltage circuits, specific challenges related to high electric fields are anticipated. The motivations for this are multifaceted, including increased power density, extremely low parasitic inductance, better EMI shielding, and high reliability and power cycle robustness. Furthermore, chip embedding typically employs chemically plated, and especially electroplated, electrical interconnect structures, which are superior to other types of electrical interconnect structures.

[0003] Another solution for manufacturing embedded high-voltage semiconductor devices is to place the die on a leadframe, isolate the die on the leadframe, and then embed the component. One risk of this embedding technique is the interaction between the device and the carrier material used, where a primary mechanism is voltage and the resulting electric field. In the worst case, this can lead to component damage, for example, due to copper migration. Another threat is exposed copper metallization on the die. Oxidation of this metallization must be specially treated during the embedding process. After component placement, connections to the outer layers are made via vias. The channels from the vias to the chip metallization are particularly critical points for cracking. Furthermore, there is a strong interaction between the embedding encapsulation material and the manufacturing process and the high-voltage device and the resulting electric field, leading to chemical degradation of the encapsulation material (e.g., pentode, reversible drift), voltage drift of the device due to ions in the encapsulation material, and corrosion of the device. The embedding material is also sensitive to humidity, and the density of the covered chip cannot be guaranteed, which accelerates the negative effects described above. To prevent delamination of the surrounding layers, cavities are used in the leadframe, and the die is then placed within these cavities. Using this method, a dedicated cavity must be made for each bare wafer.

[0004] This disclosure is necessary for these and other reasons. Summary of the Invention

[0005] A first aspect of this disclosure relates to a semiconductor device package, comprising: a printed circuit board including a first central region, a second lateral region, and a third lateral region; a semiconductor die including a first main surface, a second main surface opposite to the first main surface, a first contact pad disposed on the first main surface, and a second contact pad disposed on the second main surface, the semiconductor die being disposed in the first central region of the printed circuit board; a first metal sidewall of the semiconductor device package disposed in the second lateral region of the printed circuit board; and a second metal sidewall of the semiconductor device package disposed in the third lateral region of the printed circuit board; wherein at least one of the first metal sidewall and the second metal sidewall is electrically connected to one of the first contact pad and the second contact pad of the semiconductor die.

[0006] A second aspect of this disclosure relates to a method for manufacturing a semiconductor device package, the method comprising: providing a printed circuit board including a first central region, a second lateral region, and a third lateral region, wherein a semiconductor die including contact pads is disposed in the first central region, a first metal sidewall is disposed in the second lateral region, and a second metal sidewall is disposed in the third lateral region; electrically connecting at least one of the first and second metal sidewalls to one of the contact pads of the semiconductor die; and completing the semiconductor device package such that the first and second metal sidewalls are exposed to the outside and define respective sidewalls of the semiconductor device package.

[0007] A third aspect of this disclosure relates to a semiconductor device package, comprising: a printed circuit board including a first central region; a semiconductor die including a first main surface, a second main surface opposite to the first main surface, a first contact pad disposed on the first main surface, and a second contact pad disposed on the second main surface, the semiconductor die being disposed in the first central region of the printed circuit board; a first metal via strip disposed on the first contact pad of the semiconductor die, the first metal via strip having a thickness of at least 100 μm; and a second metal via strip disposed on the second contact pad of the semiconductor die, the second metal via strip having a thickness of at least 100 μm.

[0008] A fourth aspect of this disclosure relates to a method for manufacturing a semiconductor device package, the method comprising: providing a printed circuit board including a first central opening, wherein a semiconductor die is disposed in the first central opening, the semiconductor die including a first main surface, a second main surface opposite to the first main surface, a first contact pad disposed on the first main surface, and a second contact pad disposed on the second main surface; disposing a first metal via strip on the first contact pad of the semiconductor die, the first metal via strip having a thickness of at least 100 μm; and disposing a second metal via strip on the second contact pad of the semiconductor die, the second metal via strip having a thickness of at least 100 μm. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate several embodiments and, together with the description, serve to explain the principles of the embodiments. Other embodiments and many anticipated advantages of the embodiments will be readily understood as they become better understood by referring to the following detailed description.

[0010] The elements in the accompanying drawings are not necessarily proportional to each other. Similar or identical reference numerals indicate corresponding similar or identical parts.

[0011] Figure 1 A schematic side sectional view of a semiconductor device package according to an example is shown, wherein the semiconductor device package includes metal sidewalls and via strips on contact pads of a semiconductor die.

[0012] Figure 2 A flowchart of a method for manufacturing a semiconductor device package according to the second aspect is shown.

[0013] Figure 3 A flowchart of a method for manufacturing a semiconductor device package according to the fourth aspect is shown.

[0014] Figures 4.1 to 4.33 A schematic side sectional view is shown to illustrate the manufacture of, for example, Figure 1 The method for packaging semiconductor devices shown.

[0015] Figure 5 A schematic side sectional view of a semiconductor device package according to an example is shown, wherein, with Figure 1 In contrast, the core layer is formed in a different way. Detailed Implementation

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification, in which specific embodiments of the present disclosure may be practiced by way of illustration. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “leading,” “tail,” etc., are used with reference to the orientation of the described drawings. Because components of the embodiments can be positioned in a number of different orientations, the directional terms are for illustrative purposes and are not intended to be limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of the present disclosure is defined by the appended claims.

[0017] It should be understood that, unless otherwise specifically indicated, the features of the various exemplary embodiments described herein can be combined with each other.

[0018] As used herein, the terms “joining,” “attachment,” “connection,” “coupling,” and / or “electrical connection / electrical coupling” do not imply that the corresponding elements or layers must be in direct contact with each other; rather, an intermediary element or layer may be provided between the elements that are “joined,” “attached,” “connected,” “coupled,” and / or “electrically connected / electrically coupled.” However, according to this disclosure, the foregoing terms may optionally also have the specific meaning of elements or layers being in direct contact with each other, i.e., no intermediary element or layer is provided between the elements that are “joined,” “attached,” “connected,” “coupled,” and / or “electrically connected / electrically coupled.”

[0019] Furthermore, the term "above" as used herein with respect to components, elements, or material layers formed or located "above" a surface may be used to indicate that the component, element, or material layer is "indirectly" positioned (e.g., placed, formed, deposited, etc.) on the surface such that one or more additional components, elements, or layers are arranged between the surface and the component, element, or material layer. However, the term "above" as used with respect to components, elements, or material layers formed or located "above" a surface may also optionally have a specific meaning: that the component, element, or material layer is "directly" positioned (e.g., placed, formed, deposited, etc.) on the surface, for example, in direct contact with the surface.

[0020] Detailed description

[0021] Figure 1 A schematic side sectional view of a semiconductor device package is shown. The semiconductor device package 100 includes a printed circuit board 10 containing a first central region, a semiconductor die 20 including a first main surface and a second main surface opposite to the first main surface, a first contact pad 20A disposed on the first main surface and a second contact pad 20B disposed on the second main surface, the semiconductor die 20 being disposed in the first central region of the printed circuit board 10.

[0022] The printed circuit board 10 is part of the core layer, and the layer above the core layer can be called the top building layer, and the layer below the core layer can be called the bottom building layer.

[0023] Figure 1 The semiconductor device package 100 may further include a second lateral region and a third lateral region, a first metal sidewall 30 of the semiconductor device package disposed in the second lateral region of the printed circuit board 10, and a second metal sidewall 40 of the semiconductor device package disposed in the third lateral region of the printed circuit board 10, wherein one or both of the first metal sidewall 30 and the second metal sidewall 40 are electrically connected to one of the first contact pads 20A and 20B of the semiconductor die 20. Such a semiconductor device package represents a semiconductor device package according to a first aspect of the present disclosure.

[0024] Figure 1 The semiconductor device package 100 may alternatively or additionally include: a first metal via strip 50 disposed on a first contact pad 20A of the semiconductor die 20, the first metal via strip 50 having a thickness of at least 100 μm; and a second metal via strip 60 disposed on a second contact pad 20B of the semiconductor die 20, the second metal via strip 60 having a thickness of at least 100 μm. Such a semiconductor device package represents a semiconductor device package according to a second aspect of this disclosure.

[0025] The thickness of one or both of the first and second metal via strips 50 and 60 can be in the range of 100 μm to 250 μm, wherein the lower limit can be 110 μm, 120 μm, 130 μm, 140 μm or 150 μm, and the upper limit can be 240 μm, 230 μm, 220 μm, 210 μm or 200 μm.

[0026] in other words, Figure 1 A semiconductor device package 100 is shown, wherein the basic features of the semiconductor device package of the first and second aspects of this disclosure are shown together.

[0027] exist Figure 1 In the semiconductor device package 100 shown, a first metal sidewall 30 is electrically connected to a first contact pad 20A of the semiconductor die 20, and a second metal sidewall 40 is electrically connected to a second contact pad 20B of the semiconductor die 20. However, it is also possible for only one of the first metal sidewall 30 and the second metal sidewall 40 to be electrically connected to either the first contact pad 20A or the second contact pad 20B of the semiconductor die 20.

[0028] According to one example of the semiconductor device package 100, a first metal via strip 50 is connected between a first contact pad 20A of the semiconductor die 20 and a first metal sidewall 30, and a second metal via strip 60 is connected between a second contact pad 20B of the semiconductor die 20 and a second metal sidewall 40.

[0029] According to one example, the semiconductor device package 100 further includes a first upper main surface and a second lower main surface of the semiconductor device package, wherein at least one of the first metal sidewall 30 and the second metal sidewall 40 is exposed at the first upper main surface and / or the second lower main surface of the semiconductor device package 100. According to one example of the semiconductor device package 100, the first metal sidewall 30 and the second metal sidewall 40 are exposed at the first upper main surface and / or the second lower main surface of the semiconductor device package 100.

[0030] According to one example of the semiconductor device package 100, at least one of the outer vertical end faces of the first metal sidewall 30 and the second metal sidewall 40 is exposed to the outside.

[0031] The thickness of one or both of the first and second metal sidewalls 30 and 40 can be in the range of 100 μm to 250 μm, wherein the lower limit can be 110 μm, 120 μm, 130 μm, 140 μm or 150 μm, and the upper limit can be 240 μm, 230 μm, 220 μm, 210 μm or 200 μm.

[0032] According to one example, the semiconductor device package 100 also includes an isolation distance (arrow A) between a second contact pad 20B and a metal region connected to a first metal sidewall 30, the isolation distance being in the range of 100 μm to 300 μm, wherein the lower limit of the range may also be 110 μm, 120 μm, 130 μm, 140 μm or 150 μm, and the upper limit of the range may also be 290 μm, 280 μm, 270 μm, 260 μm or 250 μm.

[0033] According to one example, the semiconductor device package 100 also includes a polymer layer 70 disposed on a printed circuit board. Figure 1 The upper portion of the polymer layer 70 is used to electrically isolate the first metal via strip 50 from the second metal sidewall 40, and the lower portion of the polymer layer 70 is used to electrically isolate the second metal via strip 60 from the first metal sidewall 30. The polymer layer 70 can be formed by lamination, as shown later.

[0034] according to Figure 1 In one example of a semiconductor device package 100, a semiconductor die 20 may be embedded in a polymer film 25. The polymer film 25 is surrounded by a polymer layer 80, particularly an FR4 prepreg layer.

[0035] according to Figure 1 In one example of a semiconductor device package 100, solder resist layers 90 and 95 are formed in the upper and lower surfaces of the semiconductor device package 100, such that they are disposed on portions of the polymer layer 70. Therefore, the first and second metal sidewalls 30 and 40 can be electrically connected by soldering to external devices in any desired manner.

[0036] Figure 2 A flowchart of a method for manufacturing a semiconductor device package according to the second aspect is shown.

[0037] according to Figure 2Method 200 includes providing a printed circuit board including: a first central opening, a second lateral opening, and a third lateral opening, wherein a semiconductor die including contact pads is disposed in the first central opening, a first metal sidewall is disposed in the second lateral opening, and a second metal sidewall is disposed in the third lateral opening (210); electrically connecting at least one of the first and second metal sidewalls to one of the contact pads of the semiconductor die (220); and completing the fabrication of a semiconductor device package such that the first and second metal sidewalls are exposed to the outside and define respective sidewalls of the semiconductor device package (230).

[0038] Method 200 is specifically designed to manufacture a semiconductor device package according to the first aspect.

[0039] Each of steps 210-230 can include multiple sub-steps. Therefore, Figures 4.1-4.33 This will show in more detail how method 200 can actually be performed.

[0040] According to one example of method 200, the method further includes: electrically connecting one of the first metal sidewall and the second metal sidewall to a first contact pad of the semiconductor die; and electrically connecting the other of the first metal sidewall and the second metal sidewall to a second contact pad of the semiconductor die. According to another example, the electrical connection is implemented such that both the first metal sidewall and the second metal sidewall are exposed at at least one of a first upper main surface and a second lower main surface of the semiconductor device package.

[0041] According to one example of method 200, the method further includes providing an isolation layer over at least the semiconductor die. In fact, in Figures 4.1 to 4.33 As will be seen, isolation layers can be applied not only to semiconductor dies. Isolation layers can include, for example, polymer layers or laminated material layers.

[0042] According to an example of method 200, the electrical connection includes electroplating.

[0043] Figure 3 A flowchart of a method for manufacturing a semiconductor device package according to the fourth aspect is shown.

[0044] according to Figure 3Method 300 includes: providing a printed circuit board including a first central opening, wherein a semiconductor die is disposed in the first central opening, the semiconductor die including a first main surface, a second main surface opposite to the first main surface, a first contact pad disposed on the first main surface, and a second contact pad disposed on the second main surface (310); disposing a first metal via strip on the first contact pad of the semiconductor die, the first metal via strip having a thickness of at least 100 μm (320); and disposing a second metal via strip on the second contact pad of the semiconductor die, the second metal via strip having a thickness of at least 100 μm (330).

[0045] Method 300 is specifically designed to manufacture a semiconductor device package according to a third aspect.

[0046] Each of steps 310-330 can include multiple sub-steps. Therefore, Figures 4.1-4.33 This will show in more detail how method 300 can actually be performed.

[0047] According to one example of method 300, the printed circuit board further includes a second lateral opening and a third lateral opening, wherein a first metal sidewall is disposed in the second lateral opening of the printed circuit board, and a second metal sidewall is disposed in the third lateral opening of the printed circuit board. Method 300 further includes electrically connecting a first metal via strip to the first metal sidewall and electrically connecting a second metal via strip to the second metal sidewall.

[0048] According to one example of method 300, setting a first metal via strip and a second metal via strip and electrically connecting the first metal via strip and the second metal via strip to a first metal sidewall and a second metal sidewall includes electroplating.

[0049] Figures 4.1 to 4.30 A schematic side sectional view is shown to illustrate the manufacture of, for example, Figure 1 The method for packaging semiconductor devices shown.

[0050] Figures 4.1 to 4.13 The fabrication of the core layer of a semiconductor device package to be manufactured is shown.

[0051] according to Figure 4_1 The FR4 layer 400 includes a first main surface and a second main surface, as well as two Cu foils 401 and 402. Each Cu foil includes a stack consisting of two Cu sublayers, namely a thin seed layer and a thick release layer. The two sublayers can be easily separated from each other.

[0052] according to Figure 4_2 Each of Cu foils 401 and 402 is applied with its release layer to a corresponding one of the first and second main surfaces of FR4 layer 400.

[0053] according to Figure 4_3 The photolithography process is performed by applying photoresist layers 403 and 404 onto copper foils 401 and 402, respectively, followed by removing multiple portions of the photoresist layers 403 and 404 to create corresponding openings 403_1, 403_2 and 404_1, 404_2, respectively, extending downwards to the Cu foils 401 and 402. Openings 403_2 and 404_2 are formed in continuous rings.

[0054] according to Figure 4_4 The opening is filled with Cu through electroplating. The resulting outer Cu region 403_3 is Figure 1 The precursors are the first and second metal sidewalls 30 and 40, while the inner Cu regions 403_4 and 404_4 are continuous annular regions and can be used as cavity opening rings, which will be explained below.

[0055] according to Figure 4_5 The photoresist layers 403 and 404 were removed.

[0056] according to Figure 4_6 It provides two polymer layers 405 and 406, specifically two FR4 prepreg layers. Polymer layer 405 is... Figure 1 The precursor of polymer layer 80.

[0057] according to Figure 4_7 FR4 prepreg layers 405 and 406 are respectively laminated onto the upper Cu regions 403_3, 403_4 and the lower Cu regions 404_3, 404_4.

[0058] according to Figure 4_8 Grinding was performed to expose the outer surfaces of Cu regions 403_3, 403_4, 404_3 and 404_4.

[0059] according to Figure 4_9 The grinding process is completed, exposing the outer surfaces of Cu regions 403_3, 403_4, 404_3, and 404_4 to the outside.

[0060] according to Figure 4_10 By separating the seed layer and release layer of the two copper foils 401 and 402 respectively, the FR4 prepreg layers 405 and 406 with incorporated Cu regions 403_3, 403_4, 404_3, 404_4 are separated from the FR4 layer 400 (see large arrow).

[0061] according to Figure 4_11 The following figures illustrate only the further processing of one of the two prepreg layers, namely prepreg layer 405. Figure 4_11 The FR4 prepreg layer 405 is shown after the seed layer of the previous two copper foil layers 401 has been removed.

[0062] according to Figure 4_12 The photolithography process is performed by applying photoresist layers 408 and 409 to the upper and lower surfaces of the FR4 prepreg layer 405, wherein no photoresist layer is applied to the inner portion including the annular Cu region 403_4. The photoresist layers 408 and 409 are intended to mask the outer regions of the upper and lower main surfaces of layer 405.

[0063] according to Figure 4_13 The annular Cu region 403_4 and the region of the FR4 prepreg layer 405 surrounded by the annular Cu region 403_4 are removed by etching, thereby leaving a central opening 410 intended to accommodate a semiconductor die later.

[0064] according to Figure 4_14 The photoresist layers 408 and 409 were removed.

[0065] Figures 4.15 to 4.21 The placement of the semiconductor die and subsequent embedding are illustrated.

[0066] according to Figure 4_15 The bonding strip 411 is attached to the back surface of the FR4 prepreg layer 405.

[0067] according to Figure 4_16 The semiconductor die 412 is placed in the opening 410 by attaching it to the upper surface of the bonding strip 411. The semiconductor die 412 includes a first upper surface on which contact pads 412A are disposed, and a second lower surface on which contact pads 412B and 412C are disposed. Contact pads 412A, 412B, and 412C can be the drain pad, source pad, and gate pad of an IGBT die.

[0068] according to Figure 4_17 Polymer layer 413 is laminated onto FR4 prepreg layer 405 and semiconductor die 412, wherein polymer film 413 also flows into opening 410, thereby encapsulating semiconductor die 412. Polymer film 413 is... Figure 1 The precursor of polymer 25.

[0069] according to Figure 4_18 The joint tape 411 was removed.

[0070] Figures 4.19 to 4.21 The portion of polymer layer 413 above contact pad 412A is shown after removal.

[0071] according to Figure 4_19 The upper part of the portion is removed by laser drilling.

[0072] according to Figure 4_20 The removal of the upper part is complete.

[0073] according to Figure 4_21 The remainder of the polymer layer 413 is removed by plasma etching. Thus, only the portion of the polymer layer 413 surrounding the semiconductor die 412 is retained.

[0074] Figures 4.22 to 4.3 Figure 5 shows the final processing operations for PCBs and semiconductor device packages.

[0075] according to Figure 4_22 Seed layer 414 is deposited on the upper and lower surfaces of the structure. Seed layer 414 can be deposited by sputtering and the material can be Cu. Before sputtering Cu, a Ti or TiW barrier layer can be sputtered first.

[0076] according to Figure 4_23 Photoresist layers 415 and 416 are deposited on the upper and lower surfaces of the structure respectively, so as to mask specific portions of the upper and lower surfaces during subsequent plating processes.

[0077] according to Figure 4_24 Cu layers 417 and 418 are electroplated onto the upper and lower unmasked surfaces. The first copper layer 417 covers the drain pad 412A and electrically connects it to the left metal sidewall 403_3, and the second copper layer 418 covers the source pad 412B and electrically connects it to the right metal sidewall 403_3. The second copper layer 418 also covers the gate pad 412C.

[0078] according to Figure 4_25 Additional photoresist layers 419 and 420 are deposited on top of the previous photoresist layers 415 and 416 in preparation for subsequent plating processes.

[0079] according to Figure 4_26 Further electroplating of Cu is performed to create an upper Cu layer 421 and a lower Cu layer 422. The additional Cu layers 421 and 422 are deposited only on top of the previous Cu layers that connect the drain and source pads to their respective sidewalls. The gate pads are not covered by the additional Cu layer 422 but are instead routed to different locations. Photolithography and plating processes are performed to ensure that the Cu layers on the drain pad 412A and source pad 412B are at least 100 μm thick.

[0080] according to Figure 4_27 Photoresist layers 419 and 420 were removed.

[0081] according to Figure 4_28 Polymer layers 423 and 424 are laminated to the upper and lower surfaces of the structure. Polymer layers 423 and 424 are Figure 1 The precursor of polymer layer 70 shown.

[0082] according to Figure 4_29The polymer layers 423 and 424 are thinned, exposing the upper surface of the Cu layer's connecting portion to the outside. Thinning can be achieved through grinding, plasma etching, or similar methods.

[0083] according to Figure 4_30 Through-holes 425 and 426 are formed in the device. From Figure 4_30 As can be seen from the upper part, through holes 425 and 426 extend downwards from the upper main surface of the device to the lower main surface. From Figure 4_30 As can be seen in the lower part, the through holes 425 and 426 are in the form of strips, and the left through hole 425 is positioned along the interface between the left sidewall 403_3 and the adjacent FR4 layer 405 and polymer layers 423 and 424. Similarly, the right through hole 426 is positioned along the interface between the right sidewall 403_3 and the adjacent FR4 layer 405 and polymer layers 423 and 424.

[0084] according to Figure 4_31 Cu layers 427 and 428 are formed on the upper and lower main surfaces of the structure. Cu layers 427 and 428 are formed by a series of steps including sputtering or depositing a seed layer, photolithography, Cu plating, photoresist stripping, and etching.

[0085] according to Figure 4_32 Solder resist layers 429 and 430 are deposited on the upper and lower main surfaces of the structure. Solder resist layers 429 and 430 are formed in the recesses of Cu layers 427 and 428 and are also partially formed on adjacent portions of the Cu layers. In addition, surface finishing is performed on the copper sidewalls.

[0086] according to Figure 4_33 The structure is diced along dicing path 431 as shown in the following section to obtain the final semiconductor device shown in the above section. A feature of the final semiconductor device is that the outer sidewalls are exposed to the outside.

[0087] Figure 5 A schematic side sectional view of a semiconductor device package according to an example is shown, wherein, with Figure 1 In contrast, the core layer is formed in a different way.

[0088] More specifically, Figure 5 The semiconductor device package 500 includes: a printed circuit board 110; a semiconductor die 120 including a first contact pad 120A and a second contact pad 120B (drain pad and source pad, gate pad not visible here); a polymer layer 125 embedding the semiconductor die 120; a first metal sidewall 130; a second metal sidewall 140; a first via strip 150; a second via strip 160; a polymer layer 170; a polymer layer 180; and solder mask layers 190 and 195. All these components are connected to... Figure 1The corresponding comparable elements of the semiconductor device package 100 have similar characteristics and are manufactured in a similar manner.

[0089] and Figure 1 One difference in the semiconductor device package 100 is the structure of the polymer layers 170 and 180. In the semiconductor device package 500, both polymer layers 170 and 180 are included... Figure 1 The portions located at the outer left and outer right ends of the device that are not present in the semiconductor device package 100.

[0090] and Figure 1 Another difference in the semiconductor device package 100 is that the first contact pad 120A of the semiconductor die 120 is electrically connected to the second metal sidewall 140, and the second contact pad 120B of the semiconductor die 120 is electrically connected to the first metal sidewall 130.

[0091] Example 1 is a semiconductor device package, comprising: a printed circuit board including a first central region, a second lateral region, and a third lateral region; a semiconductor die including a first main surface and a second main surface opposite to the first main surface, a first contact pad disposed on the first main surface, and a second contact pad disposed on the second main surface, the semiconductor die being disposed in the first central region of the printed circuit board; a first metal sidewall of the semiconductor device package disposed in the second lateral region of the printed circuit board; and a second metal sidewall of the semiconductor device package disposed in the third lateral region of the printed circuit board; wherein at least one of the first metal sidewall and the second metal sidewall is electrically connected to one of the first contact pad and the second contact pad of the semiconductor die.

[0092] Example 2 is a semiconductor device package according to Example 1, wherein one of the first metal sidewall and the second metal sidewall is electrically connected to a first contact pad of the semiconductor die, and the other of the first metal sidewall and the second metal sidewall is electrically connected to a second contact pad of the semiconductor die.

[0093] Example 3 is a semiconductor device package according to Example 2, the semiconductor device package further comprising a first metal via strip connected between a first contact pad and a first metal sidewall of a semiconductor die and a second metal via strip connected between a second contact pad and a second metal sidewall of a semiconductor die.

[0094] Example 4 is a semiconductor device package according to any of the foregoing examples, the semiconductor device package further comprising: a first upper main surface of the semiconductor device package and a second lower main surface of the semiconductor device package, wherein at least one of the first metal sidewall and the second metal sidewall is exposed at the first upper main surface and / or the second lower main surface of the semiconductor device package.

[0095] Example 5 is a semiconductor device package according to any of Examples 2-4, wherein a first metal sidewall and a second metal sidewall are exposed at a first upper main surface and / or a second lower main surface of the semiconductor device package.

[0096] Example 6 is a semiconductor device package according to any of the foregoing examples, wherein the isolation distance between the second contact pad and a metal sidewall connected to the first contact pad is in the range of 100 μm to 300 μm, wherein the lower limit of the range may also be 110 μm, 120 μm, 130 μm, 140 μm or 150 μm, and the upper limit of the range may also be 290 μm, 280 μm, 270 μm, 260 μm or 250 μm.

[0097] Example 7 is a semiconductor device package according to any of the preceding examples, wherein the semiconductor device package further includes a laminated material layer disposed on a printed circuit board, wherein a first metal sidewall, a second metal sidewall, a first metal via strip, and a second metal via strip are disposed within the region of the laminated material layer.

[0098] Example 8 is a method for manufacturing a semiconductor device package, the method comprising: providing a printed circuit board including a first central region, a second lateral region, and a third lateral region, wherein a semiconductor die including contact pads is disposed in the first central region, a first metal sidewall is disposed in the second lateral region, and a second metal sidewall is disposed in the third lateral region; electrically connecting at least one of the first and second metal sidewalls to one of the contact pads of the semiconductor die; and completing the semiconductor device package such that the first and second metal sidewalls are exposed to the outside and define respective sidewalls of the semiconductor device package.

[0099] Example 9 is a method according to Example 8, the method further comprising: electrically connecting one of the first metal sidewall and the second metal sidewall to a first contact pad of the semiconductor die; and electrically connecting the other of the first metal sidewall and the second metal sidewall to a second contact pad of the semiconductor die.

[0100] Example 10 is the method according to Example 9, wherein an electrical connection is implemented such that both the first metal sidewall and the second metal sidewall are exposed at at least one of the first upper main surface and the second lower main surface of the semiconductor device package.

[0101] Example 11 is based on any of Examples 8-10, the method further comprising: after electrical connection, providing an isolation layer on at least a semiconductor die.

[0102] Example 12 is based on any of the methods in Examples 8-11, wherein the electrical connection includes electroplating.

[0103] Example 13 is a semiconductor device package comprising: a printed circuit board including a first central region; a semiconductor die including a first main surface and a second main surface opposite to the first main surface, a first contact pad disposed on the first main surface and a second contact pad disposed on the second main surface, the semiconductor die being disposed in a first region of the printed circuit board; a first metal via strip disposed on the first contact pad of the semiconductor die, the first metal via strip having a thickness of at least 100 μm; and a second metal via strip disposed on the second contact pad of the semiconductor die, the second metal via strip having a thickness of at least 100 μm.

[0104] Example 14 is a semiconductor device package according to Example 13, wherein the thickness of each of the first metal via strip and the second metal via strip is in the range of 100 μm to 300 μm, wherein the lower limit of the range may also be 110 μm, 120 μm, 130 μm, 140 μm or 150 μm, and the upper limit of the range may also be 290 μm, 280 μm, 270 μm, 260 μm or 250 μm.

[0105] Example 15 is a semiconductor device package according to Example 13 or 14, the semiconductor device package further comprising: a printed circuit board including a second lateral region and a third lateral region; a first metal sidewall of the semiconductor device package disposed in the second lateral region of the printed circuit board; a second metal sidewall of the semiconductor device package disposed in the third lateral region of the printed circuit board; wherein at least one of the first metal sidewall and the second metal sidewall is electrically connected to one of the first die pads or the second die pads of the semiconductor die.

[0106] Example 16 is a semiconductor device package according to Example 15, wherein a first metal via strip is connected between a first contact pad and a first metal sidewall of a semiconductor die, and a second metal via strip is connected between a second contact pad and a second metal sidewall of a semiconductor die.

[0107] Example 17 is a semiconductor device package according to any one of Examples 13-16, the semiconductor device package further comprising a laminated material layer disposed on a printed circuit board, wherein a first metal sidewall, a second metal sidewall, a first metal via strip, and a second metal via strip are disposed within the region of the laminated material layer.

[0108] Example 18 is a method for manufacturing a semiconductor device package, the method comprising: providing a printed circuit board including a first central opening, wherein a semiconductor die is disposed in the first central opening, the semiconductor die including a first main surface, a second main surface opposite to the first main surface, a first contact pad disposed on the first main surface, and a second contact pad disposed on the second main surface; disposing a first metal via strip on the first contact pad of the semiconductor die, the first metal via strip having a thickness of at least 100 μm; and disposing a second metal via strip on the second contact pad of the semiconductor die, the second metal via strip having a thickness of at least 100 μm.

[0109] Example 19 is a method according to Example 18, the method further comprising: making the printed circuit board further include a second lateral opening and a third lateral opening, wherein a first metal sidewall is disposed in the second lateral opening of the printed circuit board and a second metal sidewall is disposed in the third lateral opening of the printed circuit board; electrically connecting a first metal via strip to the first metal sidewall; and electrically connecting a second metal via strip to the second metal sidewall.

[0110] Example 20 is the method according to Example 19, wherein setting a first metal via strip and a second metal via strip and electrically connecting the first metal via strip and the second metal via strip to a first metal sidewall and a second metal sidewall includes electroplating.

[0111] Furthermore, while specific features or aspects of embodiments of this disclosure may be disclosed in combination with only one of several embodiments, such features or aspects may be combined with one or more other features or aspects of other embodiments, provided that this is desirable and advantageous for any given or particular application. Additionally, with regard to the use of the terms “comprising,” “having,” “with,” or other variations thereof in the Detailed Description section or claims, these terms are intended to be open-ended in a manner similar to the term “comprising.” Furthermore, it should be understood that embodiments of this disclosure may be implemented as discrete circuits, partially integrated circuits, or fully integrated circuits or programmable means. Moreover, the term “exemplary” is meant only as an example and not as the best or optimal. It should also be understood that, for purposes of simplicity and ease of understanding, features and / or elements depicted herein are shown in specific dimensions relative to each other, and actual dimensions may differ significantly from those shown herein.

[0112] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be used instead of the specific embodiments shown and described without departing from the scope of this disclosure. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, this disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor device package (100), comprising: - a printed circuit board (10) comprising a first central region, a second lateral region and a third lateral region; - a semiconductor die (20) comprising a first main face, a second main face opposite to the first main face, a first contact pad (20A) provided on the first main face and a second contact pad (20B) provided on the second main face, the semiconductor die (20) being provided in the first central region of the printed circuit board (10); - a first metal side wall (30) of the semiconductor device package provided in the second lateral region of the printed circuit board (10); - a second metal side wall (40) of the semiconductor device package provided in the third lateral region of the printed circuit board (10); - a first metal via strip (50) connected between the first contact pad (20A) of the semiconductor die (20) and the first metal side wall (30); and - a second metal via strip (60) connected between the second contact pad (20B) of the semiconductor die (20) and the second metal side wall (40), wherein at least one of the first metal side wall (30) and the second metal side wall (40) is electrically connected to one of the first contact pad (20A) and the second contact pad (20B) of the semiconductor die (20), characterized in that the semiconductor device package (100) further comprises: - a layer of lamination material (70) provided on the printed circuit board, wherein the first metal side wall (30), the second metal side wall (40), the first metal via strip (50) and the second metal via strip (60) are provided within a region of the layer of lamination material (70).

2. The semiconductor device package (100) according to claim 1, wherein one of the first metal side wall (30) and the second metal side wall (40) is electrically connected to the first contact pad (20A) of the semiconductor die (20), and the other one of the first metal side wall (30) and the second metal side wall (40) is electrically connected to the second contact pad (20B) of the semiconductor die (20). the semiconductor device package (100) further comprises:

3. The semiconductor device package (100) according to claim 1 or 2, wherein a first upper main face of the semiconductor device package and a second lower main face of the semiconductor device package, wherein at least one of the first metal side wall (30) and the second metal side wall (40) is exposed at the first upper main face and / or at the second lower main face of the semiconductor device package (100).

4. The semiconductor device package (100) according to claim 3, wherein the first metal side wall (30) and the second metal side wall (40) are exposed at the first upper main face and / or at the second lower main face of the semiconductor device package (100).

5. The semiconductor device package (100) according to any one of claims 1, 2, 4, wherein an isolation distance between the second contact pad (20B) and the first or second metal side wall connected to the first contact pad (20A) is in a range between 100 pm and 300 pm.

6. A method (200) for manufacturing a semiconductor device package, the method comprising: ​ - providing a printed circuit board comprising a first central region, a second lateral region, and a third lateral region, wherein a semiconductor die comprising contact pads is disposed in the first central region, a first metal sidewall is disposed in the second lateral region, and a second metal sidewall is disposed in the third lateral region (210); - electrically connecting at least one of the first and second metal sidewalls to one of the contact pads of the semiconductor die (220); and - completing the semiconductor device package such that the first and second metal sidewalls are exposed to the exterior and define respective sidewalls of the semiconductor device package (230).

7. The method of claim 6, wherein, The method further comprises: electrically connecting one of the first and second metal sidewalls to a first contact pad of the semiconductor die; and electrically connecting the other of the first and second metal sidewalls to a second contact pad of the semiconductor die.

8. The method of claim 7, wherein the electrically connecting is performed such that both the first and second metal sidewalls are exposed at at least one of the first upper major face and the second lower major face of the semiconductor device package.

9. The method of any one of claims 6-8, wherein, The method further comprises: disposing an isolation layer over at least the semiconductor die after the electrically connecting.

10. The method of any one of claims 6-8, wherein the electrically connecting comprises electroplating.

11. A method (300) for manufacturing a semiconductor device package, the method comprising: - providing a printed circuit board comprising a first central opening, wherein a semiconductor die is disposed in the first central opening, the semiconductor die comprising a first major face, a second major face opposite the first major face, a first contact pad disposed on the first major face, and a second contact pad disposed on the second major face (310); - disposing a first metal via strip on the first contact pad of the semiconductor die, the first metal via strip having a thickness of at least 100 pm (320); and - disposing a second metal via strip on the second contact pad of the semiconductor die, the second metal via strip having a thickness of at least 100 pm (330), wherein - the printed circuit board further comprises a second lateral opening and a third lateral opening, wherein a first metal sidewall is disposed in the second lateral opening of the printed circuit board and a second metal sidewall is disposed in the third lateral opening of the printed circuit board; the method (300) further comprising: - electrically connecting the first metal via strip to the first metal sidewall, and - electrically connecting the second metal via strip to the second metal sidewall.

12. The method (300) of claim 11, wherein the disposing of the first and second metal via strips and the electrically connecting of the first and second metal via strips to the first and second metal sidewalls comprises electroplating.

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