Semiconductor Components and Their Fabrication Methods

Abstract

This disclosure provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device has a substrate, a channel region, a plurality of first impurity regions, a gate dielectric layer, a lower gate conductive layer, a plurality of first contacts, a plurality of programmable isolation layers, and an upper conductive layer; the channel region is located in the substrate; the impurity regions are located in the substrate and are respectively located at both ends of the channel region; the gate dielectric layer is located on the channel region; the lower gate conductive layer is located on the gate dielectric layer; the first contacts are respectively located on the first impurity regions; the programmable isolation layers are respectively located on the first contacts; the upper conductive layer is located on the programmable isolation layer and is electrically connected to the lower gate conductive layer.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 16 / 984,911, filed August 4, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of fabricating the semiconductor device. In particular, the present disclosure relates to a semiconductor device having programmable features and a method of fabricating the semiconductor device having the programmable features. BACKGROUND

[0003] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually decreasing to meet the increasing demand for computing power. However, different problems are increased during the process of size reduction, and such problems continue to increase in number and complexity. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above “background” description is for the purpose of generally presenting the context of the disclosure. The above “background” description is not to be taken as an admission of prior art nor as constraining the overall scope of the disclosure, and is not to admit that any of the material presented “” is prior art or that any of the material is part of the prior art base or sum of the prior art at the priority date of the application as it exists naturally in that form, but that it may be a product of a prior application. The prior application, if it exists, could have been published in whole or in part in this disclosure. SUMMARY

[0005] One embodiment of the present disclosure provides a semiconductor device having a substrate; a channel region in the substrate; a plurality of first impurity regions in the substrate and respectively on two ends of the channel region; a gate dielectric layer on the channel region; a gate-under conductive layer on the gate dielectric layer; a plurality of first contact points respectively on the first impurity regions; the programmable isolation layer respectively on the first contact points; and an upper conductive layer on the programmable isolation layer and electrically connected to the gate-under conductive layer.

[0006] In some embodiments of the present disclosure, the thickness of the programmable isolation layer is different from a thickness of the gate dielectric layer.

[0007] In some embodiments of the present disclosure, the gate dielectric layer has a same thickness as the programmable isolation layer.

[0008] In some embodiments of the disclosure, the semiconductor element further comprises a gate upper conductive layer on the gate lower conductive layer and electrically connected to the upper conductive layer, wherein the gate upper conductive layer is made of titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0009] In some embodiments of the disclosure, a thickness of the gate upper conductive layer is between about 2 nm and about 20 nm.

[0010] In some embodiments of the disclosure, the semiconductor element further comprises a plurality of first gate gap sub-structures on sidewalls of the gate dielectric layer and on sidewalls of the gate lower conductive layer.

[0011] In some embodiments of the disclosure, the semiconductor element further comprises a plurality of second gate gap sub-structures on sidewalls of the first gate gap sub-structures.

[0012] In some embodiments of the disclosure, the semiconductor element further comprises a high peak portion having a triangular cross-sectional profile and between the channel region and the gate dielectric layer, wherein the gate dielectric layer comprises a cap portion on the high peak portion and a plurality of flat portions respectively connected to two ends of the cap portion and on the channel region.

[0013] In some embodiments of the disclosure, a thickness of the cap portion is equal to or less than a thickness of the flat portions.

[0014] In some embodiments of the disclosure, the high peak portion comprises a first faceted plane and a second faceted plane both contacting the cap portion, and an angle between the first faceted plane and the second faceted plane is between about 50 degrees and about 60 degrees.

[0015] In some embodiments of the disclosure, the semiconductor element further comprises a gate via between the upper conductive layer and the gate upper conductive layer, wherein the upper conductive layer and the gate upper conductive layer are electrically connected via the gate via.

[0016] In some embodiments of the disclosure, the semiconductor element further comprises a cover layer covering the first impurity regions, the first gate gap sub-structures, and the gate upper conductive layer, wherein the first contact points are respectively disposed along the cover layer and on the first impurity regions, and the gate via is disposed along the cover layer and on the gate upper conductive layer.

[0017] In some embodiments of the disclosure, the semiconductor element further comprises a second impurity region disposed in the substrate and away from the first impurity region, wherein the second impurity region has a different electrical type from the first impurity region, and wherein a first contact point is electrically connected to the second impurity region.

[0018] Another embodiment of the disclosure provides a semiconductor element having a substrate; a channel region disposed in the substrate; a plurality of first impurity regions disposed in the substrate and respectively disposed on two ends of the channel region; a gate dielectric layer disposed on the channel region; a gate lower conductive layer disposed on the gate dielectric layer; a gate via disposed on the gate lower conductive layer; a plurality of first contact points respectively disposed on the first impurity regions; a plurality of programmable isolation layers respectively disposed on the first contact points; and a plurality of upper conductive layers respectively disposed on the programmable isolation layers and the gate via.

[0019] Another embodiment of the disclosure provides a method of manufacturing a semiconductor element. The method comprises: providing a substrate; forming a channel region in the substrate; forming a gate dielectric layer on the channel region; forming a gate lower conductive layer on the gate dielectric layer; forming a plurality of first impurity regions on two ends of the channel region; forming a plurality of first contact points on the first impurity regions; forming a plurality of programmable isolation layers on the contact points; forming a gate via on the gate lower conductive layer; and forming an upper conductive layer on the gate via and the programmable isolation layers.

[0020] In some embodiments of the disclosure, the method of manufacturing a semiconductor element further comprises a step of: forming a plurality of first gate gap sub-regions on sidewalls of the gate lower conductive layer and on sidewalls of the gate dielectric layer.

[0021] In some embodiments of the disclosure, the method of manufacturing a semiconductor element further comprises a step of: forming a gate upper conductive layer between the gate via and the gate lower conductive layer.

[0022] In some embodiments of the disclosure, the gate upper conductive layer is made of titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0023] In some embodiments of the disclosure, a dopant concentration of the channel region is less than a dopant concentration of the first impurity regions.

[0024] In some embodiments of the disclosure, the channel region and the substrate have different electrical types.

[0025] Due to the design of the semiconductor element of the present disclosure, the gate dielectric layer and / or the programmable isolation layer can be broken when a programming voltage is applied. Therefore, the semiconductor element can be used as a programmable element and can be used in a repair system of a chip to improve the yield of the chip. In addition, due to the presence of the peak portion, the reliability of programming the semiconductor element can be improved.

[0026] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that those who are skilled in the art can, in light of the disclosure, make the best determination of the full scope and potential application of the disclosure. Other technical features and advantages of the present disclosure will be described in the detailed description of the disclosure that follows. Those skilled in the art will readily appreciate that the concept disclosed can be readily utilized as the basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art will also readily appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0027] The disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which like reference symbols refer to like elements throughout the several views.

[0028] Figure 1 A cross-sectional view of a semiconductor element according to an embodiment of the present disclosure.

[0029] Figure 2 A circuit architecture diagram having the semiconductor element according to an embodiment of the present disclosure.

[0030] Figures 3 to 7 Cross-sectional views of semiconductor elements according to an embodiment of the present disclosure.

[0031] Figure 8 A flowchart of a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0032] Figures 9 to 19 A cross-sectional view of a flow of a method of manufacturing the semiconductor element according to an embodiment of the present disclosure.

[0033] In the drawings, the following reference numerals are used:

[0034] 1A: Semiconductor element

[0035] 1B: Semiconductor element

[0036] 1C: Semiconductor element

[0037] 1D: semiconductor element

[0038] 1E: semiconductor element

[0039] 1F: semiconductor element

[0040] 101: base

[0041] 103: insulating layer

[0042] 105: first isolation layer

[0043] 107: second isolation layer

[0044] 109: upper conductive layer

[0045] 109-1: upper conductive layer

[0046] 109-3: upper conductive layer

[0047] 109-5: upper conductive layer

[0048] 111: peak

[0049] 113: cover layer

[0050] 201: gate structure

[0051] 203: gate dielectric layer

[0052] 203-1: cap portion

[0053] 203-3: flat portion

[0054] 205: gate lower conductive layer

[0055] 207: first gate gap sub

[0056] 209: gate upper conductive layer

[0057] 211: gate via

[0058] 213: second gate gap sub

[0059] 301: channel region

[0060] 303: first impurity region

[0061] 305: first impurity region

[0062] 307: first conductive layer

[0063] 309: first conductive layer

[0064] 311: first contact

[0065] 313: first contact

[0066] 315: programmable isolation layer

[0067] 317: programmable isolation layer

[0068] 401: second impurity region

[0069] 403: second conductive layer

[0070] 405: third conductive layer

[0071] 501: first active region

[0072] 503: second active region

[0073] 601: recess

[0074] INIB: pulse signal

[0075] Na: first node

[0076] NW1: high-voltage blocking switch

[0077] NW2: current-limiting switch

[0078] PP: programming portion

[0079] SENS: sensing transistor

[0080] SP: sensing portion

[0081] Vbias: bias voltage

[0082] Vprog: programming voltage

[0083] Vsel: selection voltage

[0084] W1: width

[0085] W2: width

[0086] a: angle

[0087] Z: direction

[0088] 10: production method

[0089] S11: step

[0090] S13: step

[0091] S15: step

[0092] S17: step

[0093] S19: step

[0094] S21: step

[0095] S23: step

[0096] S25: step

[0097] S27: step DETAILED DESCRIPTION

[0098] The following description describes specific examples of components and configurations to simplify the present disclosure. These examples are merely intended to facilitate description of the disclosure and are in no way limiting. For example, in the description below, a first component forming over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where additional components form between the first and second components such that the first and second components are not in direct contact. Additionally, embodiments of the present disclosure can repeat reference numerals and / or letters in various examples. This repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not necessarily imply a common purpose or function of such reference numerals and / or letters unless specifically identified as such.

[0099] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0100] It will be understood that, when a component is referred to as being "on", "connected to", or "coupled to" another component, it can be directly on, connected, or coupled to the other component, or electrically connected to the other component by way of (or on) an intervening component.

[0101] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0102] Unless otherwise indicated herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean an exact, identical orientation, layout, location, shape, size, amount, or other measure, but rather mean within acceptable variation, which can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to express this meaning. For example, substantially the same, substantially equal, or substantially planar can mean exactly the same, equal, or planar, or can mean the same, equal, or planar within acceptable variation, which can occur, for example, due to manufacturing processes.

[0103] In the present disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor elements.

[0104] It should be understood that in the description of the present disclosure, above (or up) is the direction corresponding to the Z-direction arrow, and below (or down) is the opposite direction corresponding to the Z-direction arrow.

[0105] It should be understood that in the description of this disclosure, a “depth” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view, measured from an upper surface to a lower surface of the element; a “width” refers to a size of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view, measured from one side surface of the element to an opposite surface. Where indicated, the term “thickness” may be used in place of “width” and / or “depth”.

[0106] It should be understood that, in the description of this disclosure, a surface of an element (or feature) located at its highest vertical level along the Z direction is represented as an upper surface of the element (or feature). A surface of an element (or feature) located at its lowest vertical level along the Z direction is represented as a lower surface of the element (or feature).

[0107] Figure 1 This is a cross-sectional schematic diagram of a semiconductor element 1A according to an embodiment of the present disclosure.

[0108] Please refer to Figure 1 The semiconductor device 1A may have a substrate 101, an insulating layer 103, a first isolation layer 105, a second isolation layer 107, an upper conductive layer 109, a gate structure 201, a plurality of first gate spacers 207, a gate upper conductive layer 209, a gate via 211, a channel region 301, a plurality of first impurity regions 303 and 305, a plurality of first conductive layers 307 and 309, a plurality of first contact points 311 and 313, and a plurality of programmable isolation layers 315 and 317.

[0109] Please refer to Figure 1In some embodiments, the substrate 101 can be a bulk semiconductor, which is composed of a whole body of at least one semiconductor material. The semiconductor material provided to the bulk semiconductor can include any material, or a stack of materials, that has semiconductor properties, including silicon, germanium, silicon- germanium alloy, a III-V compound semiconductor, or a II-VI compound semiconductor, but is not limited thereto. A III-V compound semiconductor is a material that includes at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. A II-VI compound semiconductor is a material that includes at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table. In some embodiments, the substrate 101 can be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. In the described embodiment, the substrate 101 is doped with boron and has a first type of electrons. In some embodiments, the substrate 101 can have an organic semiconductor or a layered semiconductor, such as silicon / silicon germanium, silicon-on-insulator, or silicon germanium-on-insulator.

[0110] Referring to Figure 1 An insulating layer 103 can be disposed in the substrate 101. An upper surface of the insulating layer 103 can be substantially coplanar with an upper surface of the substrate 101. The insulating layer 103 can have an aspect ratio between about 1 :4 and about 1 : 10. In some embodiments, sidewalls of the insulating layer 103 can be tapered. In some embodiments, the sidewalls of the insulating layer 103 can be substantially vertical. For example, the insulating layer 103 can be made of silicon oxide, silicon nitride, silicon oxynitride, nitrided silicon oxide, or fluoride-doped silicate.

[0111] It should be understood that a surface (or sidewall) is "vertical" if it is within three times the root mean square roughness of the surface from a vertical plane.

[0112] It should be understood that, in the description of the present disclosure, silicon oxynitride refers to a substance that includes silicon, nitrogen, and oxygen, and in which the ratio of oxygen is greater than the ratio of nitrogen. Nitrided silicon oxide refers to a substance that includes silicon, oxygen, and nitrogen, and in which the ratio of nitrogen is greater than the ratio of oxygen.

[0113] Please refer to Figure 1 A first isolation layer 105 may be disposed on a substrate 101. A second isolation layer 107 may be disposed on the first isolation layer 105. The first isolation layer 105 and the second isolation layer 107 may have a thickness between approximately 0.5 micrometers and approximately 3.0 micrometers. The first isolation layer 105 and the second isolation layer 107 may be made of the following materials: silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, the like, or combinations thereof. The first isolation layer 105 and the second isolation layer 107 may be made of different materials, but are not limited thereto. The low-k dielectric material may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0.

[0114] Please refer to Figure 1 The channel region 301 may be disposed within the substrate 101. The upper surface of the channel region 301 may be substantially coplanar with the upper surface of the substrate 101. The channel region 301 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. In the described embodiment, the channel region 301 is doped with phosphorus and has a second electron type. The doping concentration of the channel region 301 is greater than the doping concentration of the substrate 101.

[0115] Please refer to Figure 1 The first impurity regions 303 and 305 can be disposed in the substrate 101. The first impurity regions 303 and 305 can be respectively disposed at both ends of the channel region 301. The upper surfaces of the first impurity regions 303 and 305 can be approximately coplanar with the upper surface of the substrate 101. The lower surfaces of the first impurity regions 303 and 305 can be located on a vertical plane, which is a vertical plane lower than the channel region 301.

[0116] The first impurity regions 303 and 305 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. In the described embodiment, the first impurity regions 303 and 305 are doped with phosphorus and have a second electron type. The doping concentration of the first impurity regions 303 and 305 may be greater than the doping concentration of the channel region 301. The first impurity regions 303 and 305 are electrically connected to the channel region 301. The first impurity regions 303 and 305 may also be referred to herein as source / drain regions.

[0117] Please refer to Figure 1The gate structure 201 can be disposed on the channel region 301 and located in the first isolation layer 105. The gate structure 201 can include a gate dielectric layer 203 and a gate lower conductive layer 205.

[0118] Please refer to Figure 1A gate dielectric layer 203 may be disposed on the channel region 301. A width W1 of the gate dielectric layer 203 may be smaller than a width W2 of the channel region 301. In some embodiments, for example, the gate dielectric layer 203 may be made of silicon oxide. In some embodiments, for example, the gate dielectric layer 203 may be made of a high-k dielectric material, such as metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, or combinations thereof. In particular, the gate dielectric layer 203 may be made of the following materials: hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride. The gate dielectric layer 203 may be a multilayer structure, for example, consisting of a layer of silicon oxide and another layer of a high dielectric constant dielectric material.

[0119] In some embodiments, an interface layer ( Figure 1An interface layer (not shown) can be disposed between the gate dielectric layer 203 and the substrate 101. The interface layer can have a thickness between about and about In some embodiments, the interface layer can have a thickness between about and about The interface layer can assist in the formation of the gate dielectric layer 203 during fabrication of the semiconductor device 1A.

[0120] Referring to Figure 1 , a gate-under conductive layer 205 can be disposed on the gate dielectric layer 203. In some embodiments, for example, the gate-under conductive layer 205 can be fabricated from a conductive material such as polysilicon, polysilicon germanium, or combinations thereof. In some embodiments, the gate-under conductive layer 205 can be doped with a dopant such as phosphorus, arsenic, antimony, or boron. In some embodiments, for example, the gate-under conductive layer 205 can be fabricated from tungsten, aluminum, titanium, copper, the like, or combinations thereof. The gate structure 201, the channel region 301, and the first impurity region 303 can represent a depletion mode transistor.

[0121] In some embodiments, the gate dielectric layer 203 and the gate-under conductive layer 205 can have a U-shaped cross-sectional profile and can be suitable for integration in a gate last or gate first process flow.

[0122] Referring to Figure 1 , the first gate spacer 207 can be disposed on sidewalls of the gate-under conductive layer 205 and on sidewalls of the gate dielectric layer 203. The first gate spacer 207 can also be disposed on the channel region 301. For example, the first gate spacer 207 can be fabricated from silicon oxide, silicon nitride, or the like.

[0123] Referring to Figure 1 , a gate-over conductive layer 209 can be disposed on the gate-under conductive layer 205 and in the first isolation layer 105. The gate-over conductive layer 209 can have a thickness between about 2 nm and about 20 nm. For example, the gate-over conductive layer 209 can be fabricated from titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0124] Referring to Figure 1The first conductive layers 307 and 309 can be respectively disposed on the first impurity regions 303 and 305. The first conductive layers 307 and 309 can have the same thickness as the gate conductive layer 209. The first conductive layers 307 and 309 can be made of the same material as the gate conductive layer 209. The gate conductive layer 209 and the first conductive layers 307 and 309 can be used to form ohmic contacts.

[0125] Please refer to Figure 1 A gate via 211 may be disposed on the gate conductive layer 209 and in the first isolation layer 105. The upper surface of the gate via 211 may be substantially coplanar with the upper surface of the first isolation layer 105. For example, the gate via 211 may be made of the following materials: tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. The gate via 211 may be electrically connected to the gate conductive layer 209.

[0126] Please refer to Figure 1 The first contact points 311 and 313 may be respectively disposed on the first conductive layers 307 and 309. The first contact points 311 and 313 may be disposed in the first isolation layer 105. The thickness of the first contact points 311 and 313 may be less than the thickness of the first isolation layer 105. For example, the first contact points 311 and 313 may be made of the following materials: tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. The first contact points 311 and 313 may be electrically connected to the first impurity regions 313 and 305, respectively.

[0127] Please refer to Figure 1The programmable isolation layers 315, 317 can be disposed on the first contact points 311, 313, respectively. The programmable isolation layers 315, 317 can be disposed in the first isolation layer 105. Upper surfaces of the programmable isolation layers 315, 317 can be substantially coplanar with an upper surface of the gate via 211. In some embodiments, the programmable isolation layers 315, 317 can have a same thickness. In some embodiments, the programmable isolation layers 315, 317 can have different thicknesses. In some embodiments, the gate dielectric layer 203 and the programmable isolation layers 315, 317 can have a same thickness. In some embodiments, the gate dielectric layer 203 and the programmable isolation layers 315, 317 can have different thicknesses. Thicknesses of the gate via 211 and the programmable isolation layers 315, 317 can determine a programming current or a programming voltage thereof during a programming process.

[0128] In some embodiments, the programmable isolation layers 315, 317 can be made of a same material as the gate dielectric layer 203. In some embodiments, the programmable isolation layers 315, 317 can be made of a different material than the gate dielectric layer 203. For example, the programmable isolation layers 315, 317 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. The programmable isolation layers 315, 317 can be made of a same material, but are not limited thereto.

[0129] As Figure 2As shown, an upper conductive layer 109 can be disposed in the second isolation layer 107. The upper conductive layer 109 can be disposed on the gate via 211 and the programmable isolation layers 315, 317. The upper conductive layer 109 can be electrically connected to the gate via 211. In some embodiments, the upper conductive layer 109 can be fabricated from the same material as the first contact 311, 313. In some embodiments, the upper conductive layer 109 can be fabricated from a different material than the first contact 311, 313. For example, the upper conductive layer 109 can be fabricated from tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof.

[0130] The upper conductive layer 109, the programmable isolation layer 315, and the first contact 311 can be configured to represent a source capacitor. The upper conductive layer 109, the programmable isolation layer 317, and the first contact 313 can be configured to represent a drain capacitor. It should be understood that source and drain can be used interchangeably in the description of the present disclosure. The upper conductive layer 109, the gate via 211, the gate structure 201, and the channel region 301 can be configured to represent a gate capacitor. The source capacitor, the drain capacitor, and the gate capacitor can be used as programmable elements, such as anti-fuses.

[0131] During a programming procedure of the semiconductor element 1A, a programming voltage can be applied to the semiconductor element 1A, for example, through the upper conductive layer 109 and the substrate 101. After a given programming time, high voltage stress from the programming voltage can cause rupture or breakdown of the gate dielectric layer 203 and / or the programmable isolation layers 315, 317. After the programming procedure, each of the source capacitor, the drain capacitor, and the gate capacitor can be switched from an off state to an on state. In some embodiments, after the programming procedure, all of the gate dielectric layer 203 and the programmable isolation layers 315, 317 can be ruptured. In some embodiments, after the programming procedure, only two of the gate dielectric layer 203 and the programmable isolation layers 315, 317 can be ruptured.

[0132] Figure 2 A circuit schematic diagram of the semiconductor element 1A according to an embodiment of the present disclosure is shown.

[0133] In some embodiments, the semiconductor element 1A as a whole can be used as a programmable element and can be integrated with other semiconductor elements. Please refer to Figure 2 , the exemplary circuit can include a programming portion PP and a sensing portion SP. The programming portion PP can be formed by the semiconductor element 1A in series with a high voltage block switch NW1 and a current limit switch NW2. The series connection of the semiconductor element 1A, the high voltage block switch NW1 and the current limit switch NW2 can avoid the contact burnt problem caused by programming overstress.

[0134] When programming the programming portion PP, a programming voltage Vprog can be applied to the upper conductive layer 109 (not shown in the figure for clarity, Figure 2 ) of the semiconductor element 1A, and a selection voltage Vsel can be applied to the gate node of the current limit switch NW2. After a given programming time, high voltage stress from the programming voltage Vprog can cause rupture or breakdown of the gate dielectric layer 203 (not shown in the figure for clarity, Figure 2 ) of the semiconductor element 1A and / or the programmable isolation layers 315, 317 (not shown in the figure for clarity, Figures 3 to 7 ). The selection voltage Vsel can limit the maximum current during programming, and the selection current Vsel can be applied to avoid the contact burnt by excessive programming current. When programming, the high voltage block switch NW1 can be inserted between the semiconductor element 1A and the sensing portion SP to decouple the sensing portion SP from the high electric field. The bias voltage Vbias is applied to the gate node of the high voltage block switch NW1 and is set to half of the programming voltage Vprog.

[0135] During power up, the sense portion SP can be turned on and the state of the semiconductor element 1A can be detected whether it is in a broken state. If the semiconductor element 1A is not damaged (e.g. not broken), during power up, a pulse signal INIB is used to initialize the latch during power up and can be activated to LOW and the first node Na can be initialized to High. Since the select voltage Vsel and the program voltage Vprog are both grounded, when a sense transistor SENS is activated to High, the state of the semiconductor element 1A can be sensed at the first node Na. If the semiconductor element 1A is in a broken state, a current path from the first node Na to ground (Vprog) can be formed. Thus, the state of the first node Na can be switched to LOW. Otherwise, the first node Na can stay in a precharged state at High.

[0136] It should be understood that the same or similar element numbers used throughout all the drawings are used to represent the same or similar features, elements or structures, and thus the detailed explanation of the same or similar features, elements or structures will not be repeated for each drawing.

[0137] Figure 3 Cross-sectional views of semiconductor elements 1B, 1C, 1D, 1E, 1F according to an embodiment of the present disclosure.

[0138] Referring to Figure 4 In the semiconductor element 1B, the upper conductive layers 109-1, 109-3, 109-5 can be respectively disposed on the gate via 211 and the program isolation layers 315, 317. The upper conductive layers 109-1, 109-3, 109-5 can be electrically coupled to different external voltage sources. With the assistance of the upper conductive layers 109-1, 109-3, 109-5, the programming procedures of the source capacitor, the drain capacitor and the gate capacitor can be respectively performed. After each programming procedure, depending on the upper conductive layer 109-1, 109-3, 109-5 used, only one of the gate dielectric layer 203 and the program isolation layers 315, 317 can be broken.

[0139] Referring to Figure 5In semiconductor device 1C, a plurality of second gate spacers 213 can be disposed on sidewalls of the first gate spacers 207. For example, the first gate spacers 207 can be made of silicon oxide, silicon nitride, or polysilicon. For example, the second gate spacers 213 can be made of silicon oxide. Due to the presence of the second gate spacers 213, a thickness of the first gate spacers 207 can be minimized, thereby reducing overlap capacitance formed between the gate lower conductive layer 205 and the first impurity regions 303, 305.

[0140] Referring to Figure 5 In semiconductor device 1D, a peak portion 111 can be disposed between the channel region 301 and the gate dielectric layer 203. The peak portion 111 can have a cross-sectional profile that is triangular in shape and can have a first facet 111-1 and a second facet 111-3 that intersect each other. An angle a between the first facet 111-1 and the second facet 111-3 can be between about 50 degrees and about 60 degrees. The first facet 111-1 and the second facet 111-3 can have a <111> crystal orientation. In some embodiments, the peak portion 111 can have a cross-sectional profile that is diamond shaped, pentagon shaped, or a shape having more than five sides. For example, the peak portion 111 can be made of silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, indium phosphide, or other group IV-IV, group III-V, or group II-VI semiconductor materials.

[0141] Referring to Figure 6 The gate dielectric layer 203 can be disposed on the peak portion 111 and the channel region 301. The gate dielectric layer 203 can include a capping portion 203-1 and two flat portions 203-3. The capping portion 203-1 can be disposed on the first facet 111-1 and the second facet 111-3. The two flat portions 203-3 can correspond to two ends connected to the capping portion 203-1, respectively. The two flat portions 203-3 can be disposed on the channel region 301. A thickness of the two flat portions 203-3 can be greater than or equal to a thickness of the capping portion 203-1. In some embodiments, the thickness of the two flat portions 203-3 can be greater than the thickness of the capping layer 203-1.

[0142] During programming of the semiconductor device ID, the top of the high peak 111 can be the most vulnerable part because the electric field is concentrated at the sharp profile. Since the top of the high peak 111 can contain the highest electric field, the cap portion 203-1 can collapse to form a rupture point of the cap portion 203-1 adjacent to the high peak 111, and accordingly a reduction of resistance can be caused. Thus, the semiconductor device ID is blown and programmed. During programming, the location of the rupture point of the cap portion 203-1 can be easily limited at the location of the top of the high peak 111 having the highest electric field. Thus, the reliability of the semiconductor device ID can be improved.

[0143] Reference is made to Figure 7 In the semiconductor device IE, a covering layer 113 can be disposed on the base 101, the first conductive layers 307, 309, the first gate gap sub 207, and the gate over conductive layer 209. For example, the covering layer 113 can be made of silicon nitride. The first contacts 311, 313 can be disposed along the covering layer 113 and on the first conductive layers 307, 309, respectively. The covering layer 113 can provide additional protection to the aforementioned elements during the following semiconductor processes.

[0144] Reference is made to Figure 8 In the semiconductor device IF, the insulating layer 103 can define a first active region 501 and a second active region 503 in the base 101. The channel region 301 and the first impurity regions 303, 305 can be disposed in the first active region 501. A second impurity region 401 can be disposed in the second active region 503. The second impurity region 401 can be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. In the embodiment, the second impurity region 401 is doped with boron and has a first type of electron, which is opposite to the first impurity regions 303, 305. A second conductive layer 403 can be disposed on the second impurity region 401. The second conductive layer 403 can have the same thickness as the gate over conductive layer 209. The second conductive layer 403 can be made of the same material as the gate over conductive layer 209. A third conductive layer 405 can be disposed on the second conductive layer 403 and can be electrically coupled to the first contact 311. The third conductive layer 405 can be made of the same material as the first contacts 311, 313.

[0145] It should be understood that the functions or steps mentioned herein can occur in a different order than the order shown in the figures. For example, two figures shown in succession can actually be performed at about the same time or in reverse order, depending upon the functions or steps involved.

[0146] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0147] Figures 9 to 19 This is a schematic flowchart of a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figure 8 This is a cross-sectional schematic diagram of a process for fabricating the semiconductor device 1A according to an embodiment of the present disclosure.

[0148] Please refer to Figure 9 and Figure 9 In step S11, a substrate 101 may be provided, and an insulating layer 103 and a channel region 301 may be formed in the substrate 101.

[0149] Please refer to Figure 9 It can perform a series of deposition processes to deposit a pad oxide layer (in) Figure 8 (not shown in the image) and a nitride layer (in the image) Figure 10 (Not shown) On substrate 101. A photolithography process can be performed to define the location of insulating layer 103. After photolithography, an etching process, such as an anisotropic dry etching process, can be performed to form multiple trenches along pad oxide layer, pad nitride layer, and substrate 101. An isolation material can be deposited into the trenches. A planarization process, such as chemical mechanical polishing, can be performed to remove excess filler material until the upper surface of substrate 101 is exposed. Next, another photolithography-etching process can be performed to define the location of channel region 301. An implantation process can be performed to form channel region 301 in substrate 101.

[0150] Please refer toFigure 10 and Figure 8 In step S13, a gate structure 201 can be formed on the channel region 301.

[0151] Referring to Figure 11 The gate structure 201 can include a gate dielectric layer 203 and a gate lower conductive layer 205. The gate dielectric layer 203 can be formed on the channel region 301. The gate lower conductive layer 205 can be formed on the gate dielectric layer 203. The gate dielectric layer 203 and the gate lower conductive layer 205 can be formed by a plurality of deposition processes and subsequent photolithography-etching processes. For example, the deposition processes can be chemical vapor deposition or atomic layer deposition.

[0152] Referring to Figure 11 and Figure 8 In step S15, a plurality of first gate spacer sub-structures 207 can be formed on the sidewalls of the gate structure 201.

[0153] Referring to Figure 12 A layer of isolation material can be conformally deposited to cover the substrate 101 and the gate structure 201. Next, an etching process, such as a non-isotropic dry etching process, can be performed to remove a portion of the layer of isolation material and simultaneously form the plurality of first gate spacer sub-structures 207 on the sidewalls of the gate lower conductive layer 205 and on the sidewalls of the gate dielectric layer 203. For example, the layer of isolation material can be silicon oxide, silicon nitride or the like. It should be understood that after the first gate spacer sub-structures 207 are formed, some portions of the channel region 301 are still exposed.

[0154] Referring to Figure 12 and Figure 8 In step S17, first impurity regions 303, 305 can be formed in the substrate 101.

[0155] Referring to Figure 13 An implantation process can be performed to form the plurality of first impurity regions 303, 305 in the substrate 101. The first impurity regions 303, 305 can be formed to overlap both ends of the channel region 301. The first impurity regions 303, 305 and the channel region 301 can be electrically connected.

[0156] Referring to Figure 13 and Figure 8 In step S19, a gate upper conductive layer 209 can be formed on the gate structure 201 and the first conductive layers 307, 309, which can be respectively formed on the first impurity regions 303, 305.

[0157] Referring to Figure 14A layer of conductive material can be formed on the substrate 101, the first gate gap sub 207, and the gate-under conductive layer 205. For example, the layer of conductive material can include titanium, nickel, platinum, tantalum, or cobalt. Next, a thermal treatment can be performed. During the thermal treatment, the metal atoms of the metal layer can chemically react with the silicon atoms of the gate-under conductive layer 205 to form the gate-over conductive layer 209 and the first conductive layers 307, 309. The gate-over conductive layer 209 and the first conductive layers 307, 309 can include titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The thermal treatment can be a dynamic surface annealing process. After the thermal treatment, a cleaning process can be performed to remove unreacted conductive material. The cleaning process can use an etchant, such as hydrogen peroxide and a Standard Clean 1 (SC1) solution.

[0158] Referring to Figure 15 , Figure 14 and Figure 13 , at step S21, a first isolation layer 105 can be formed on the substrate 101, and a plurality of first contact points 311, 313 can be formed on the first conductive layers 307, 309.

[0159] Referring to Figure 15 , the first isolation layer 104 can be formed on the intermediate semiconductor element as exemplified in Figure 8 . A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially planar surface for the following processing steps.

[0160] Referring to Figure 16 , a lithography process can be performed to define the locations of the first contact points 311, 313. An etching process, such as a non-isotropic dry etching process, can be performed to form a plurality of contact point openings in the first isolation layer 105. The upper surfaces of the first conductive layers 307, 309 can be exposed via the contact point openings. A conductive material, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, or transition metal aluminide, can be deposited into the contact point openings by a deposition process. After the deposition process, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material, to provide a substantially planar surface for the following processing steps, and to simultaneously form the first contact points 311, 313.

[0161] Referring to Figure 17 , Figure 16 and Figure 17At step S23, a plurality of programmable isolation layers 315, 317 can be formed over the first contact points 311, 313, respectively.

[0162] Referring to Figure 8 An etch back process can be performed to recess the first contact points 311, 313 and simultaneously form a plurality of recesses 601. During the etch back process, the etch rate of the first contact points 311, 313 to the first isolation layer 105 can be between about 100: 1 and about 20: 1.

[0163] Referring to Figure 18 An isolation material can be deposited to fill the recesses 601. A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the first isolation layer 105 is exposed to provide a substantially planar surface for subsequent processing steps. For example, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or combinations thereof.

[0164] Referring to Figure 18 and Figure 8 At step S25, a gate via 211 can be formed over the gate upper conductive layer 209.

[0165] Referring to Figure 19A lithography process can be performed to define the location of the gate via 211. An etching process, such as a non-isotropic dry etching process, can be performed to form a via opening in the first isolation layer 105. The upper surface of the gate upper conductive layer 209 can be exposed through the via opening. A conductive material, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminides, or a combination thereof, can be deposited into the via opening by a deposition process. After the deposition process, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material, provide a substantially planar surface for subsequent processing steps, and simultaneously form the gate via 211.

[0166] Referring to Figure 19 and Figure 18 In step S27, a second isolation layer 107 can be formed in the first isolation layer 105, and an upper conductive layer 109 can be formed in the second isolation layer 107.

[0167] Referring to ​ The second isolation layer 107 can be formed in the intermediate semiconductor element illustrated in ​ A first planarization process, such as chemical mechanical polishing, can be performed to provide a substantially planar surface for subsequent processing steps. A lithography process can be performed to define the location of the upper conductive layer 109. An etching process, such as a non-isotropic dry etching process, can be performed to form a trench in the second isolation layer 107. The upper surfaces of the gate via 211 and the programmable isolation layers 315, 317 can be exposed through the trench. A conductive material, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminides, can be deposited into the trench by a deposition process. After the deposition process, a second planarization process, such as chemical mechanical polishing, can be performed to remove excess material, provide a substantially planar surface for subsequent processing steps, and simultaneously form the upper conductive layer 109.

[0168] One embodiment of the present disclosure provides a semiconductor element having a substrate, a channel region in the substrate, a plurality of first impurity regions in the substrate and respectively on both ends of the channel region, a gate dielectric layer on the channel region, a gate lower conductive layer on the gate dielectric layer, a plurality of first contact points respectively on the first impurity regions, the programmable isolation layers respectively on the first contact points, and an upper conductive layer on the programmable isolation layers and electrically connected to the gate lower conductive layer.

[0169] Another embodiment of the present disclosure provides a semiconductor element having a substrate, a channel region in the substrate, a plurality of first impurity regions in the substrate and respectively on both ends of the channel region, a gate dielectric layer on the channel region, a gate lower conductive layer on the gate dielectric layer, a gate via on the gate lower conductive layer, a plurality of first contact points respectively on the first impurity regions, a plurality of programmable isolation layers respectively on the first contact points, and a plurality of upper conductive layers respectively on the programmable isolation layers and the gate via.

[0170] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor element. The method includes providing a substrate, forming a channel region in the substrate, forming a gate dielectric layer on the channel region, forming a gate lower conductive layer on the gate dielectric layer, forming a plurality of first impurity regions on both ends of the channel region, forming a plurality of first contact points on the first impurity regions, forming a plurality of programmable isolation layers on the contact points, forming a gate via on the gate lower conductive layer, and forming an upper conductive layer on the gate via and the programmable isolation layers.

[0171] Due to the design of the semiconductor element of the present disclosure, the gate dielectric layer 203 and / or the programmable isolation layers 315, 317 can be broken when a programming voltage is applied. Therefore, the semiconductor element 1A can be used as a programmable element and can be used in a repair system of a chip to improve the yield of the chip. In addition, due to the existence of the peak 111, the reliability of programming the semiconductor element 1D can be improved.

[0172] It should be understood that the term "about" modifying the quantity of an ingredient, component described herein, or a reactant of the disclosure, is meant to encompass variations of ± 10% or ± 5%, or ± 1%, or ± 0.5%, or ± 0.1% of the stated value, as such variations are within the capabilities of typical measuring and liquid handling procedures used to manufacture concentrates or solutions. Furthermore, variations can occur in the manufacturing of the compositions or in the methods of using the compositions, or the like, and such variations are intended to be included within the scope of the present disclosure. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0173] While the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, various processes described above can be implemented in different methodologies, and many of the stated methods can be performed in other sequences or in an interlaced manner, or omitted entirely, and some of the described embodiments can be used in combination with others.

[0174] Furthermore, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized. Accordingly, the appended claims are intended to cover all such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A semiconductor device, comprising: a substrate; a channel region in the substrate; a plurality of first impurity regions in the substrate and respectively on two ends of the channel region; a gate dielectric layer on the channel region; a gate lower conductive layer on the gate dielectric layer; a plurality of first contact points respectively on the first impurity regions, and each of the plurality of first contact points is directly disposed on a corresponding one of a plurality of first conductive layers, each of the plurality of first conductive layers simultaneously contacts the channel region and a corresponding one of the plurality of first impurity regions; a plurality of programmable isolation layers respectively on the first contact points; and a upper conductive layer on the programmable isolation layers and the gate lower conductive layer and electrically connected to the gate lower conductive layer. A thickness of the programmable isolation layers is different from a thickness of the gate dielectric layer.

2. The semiconductor device according to claim 1, wherein The gate dielectric layer has a same thickness as the programmable isolation layers.

3. The semiconductor device according to claim 1, wherein 4. The semiconductor device of claim 2, further comprising a gate upper conductive layer on the gate lower conductive layer and electrically connected to the upper conductive layer, wherein the gate upper conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. A thickness of the gate upper conductive layer is between 2 nm and 20 nm.

5. The semiconductor device according to claim 4, wherein 6. The semiconductor device of claim 5, further comprising a plurality of first gate gap spacers on sidewalls of the gate dielectric layer and on sidewalls of the gate lower conductive layer.

7. The semiconductor device of claim 6, further comprising a plurality of second gate gap spacers on sidewalls of the first gate gap spacers.

8. The semiconductor device of claim 6, further comprising a high peak having a triangular cross-sectional profile and between the channel region and the gate dielectric layer, wherein the gate dielectric layer comprises a cap portion on the high peak and a plurality of flat portions respectively connected to two ends of the cap portion and on the channel region. A thickness of the cap portion is equal to or less than a thickness of the flat portions.

9. The semiconductor device according to claim 8, wherein The high peak comprises a first facet and a second facet both contacting the cap portion, and an angle between the first facet and the second facet is between 50 degrees and 60 degrees.

10. The semiconductor device according to claim 9, wherein 11. The semiconductor device of claim 6, further comprising a gate via between the upper conductive layer and the gate upper conductive layer, wherein the upper conductive layer and the gate upper conductive layer are electrically connected via the gate via.

12. The semiconductor device of claim 11, further comprising a capping layer covering the first impurity regions, the first gate gap spacers, and the gate upper conductive layer, wherein the first contact points are respectively disposed along the capping layer and on the first impurity regions, and the gate via is disposed along the capping layer and on the gate upper conductive layer.

13. The semiconductor device of claim 6, further comprising a second impurity region in the substrate and disposed away from the first impurity regions, wherein the second impurity region has a different electronic type than the first impurity regions, and wherein a first contact point is electrically connected to the second impurity region. ​ 14. A method for fabricating a semiconductor device, comprising: providing a substrate; forming a channel region in the substrate; forming a gate dielectric layer on the channel region; forming a gate-under conductive layer on the gate dielectric layer; forming a plurality of first impurity regions on both ends of the channel region; forming a plurality of first conductive layers on the plurality of first impurity regions; forming a plurality of first contact points on the first impurity regions, each of the plurality of first contact points being disposed directly on a corresponding one of the plurality of first conductive layers, each of the plurality of first conductive layers simultaneously contacting the channel region and a corresponding one of the plurality of first impurity regions; forming a plurality of programmable isolation layers on the contact points; forming a gate-via on the gate-under conductive layer; and forming an upper conductive layer on the gate-via, the programmable isolation layers, and the gate-under conductive layer.

15. The method of claim 14, further comprising a step of forming a plurality of first gate-gap sub-regions on sidewalls of the gate-under conductive layer and on sidewalls of the gate dielectric layer.

16. The method of claim 15, further comprising a step of forming a gate-over conductive layer between the gate-via and the gate-under conductive layer. The gate-over conductive layer comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

17. The method for producing a semiconductor element according to claim 16, wherein A doping concentration of the channel region is less than a doping concentration of the first impurity regions.

18. The method for producing a semiconductor element according to claim 17, wherein The channel region and the substrate have different electronic types.

19. The method for producing a semiconductor element according to claim 18, wherein ​

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