Semiconductor package including stacked semiconductor chips

Abstract

The present application relates to semiconductor packages including stacked semiconductor chips. A semiconductor package includes a substrate and a sub-semiconductor package disposed on the substrate. The sub-semiconductor package includes a sub-semiconductor chip having chip pads on an active surface thereof facing the substrate, a sub-molding layer surrounding side surfaces of the sub-semiconductor chip and having one surface facing the substrate, and a redistribution conductive layer connected to the chip pads and extending on the one surface of the sub-molding layer. The redistribution conductive layer includes a signal redistribution conductive layer extending onto an edge of the sub-molding layer and having signal redistribution pads at end portions thereof, and a power redistribution conductive layer having a length shorter than a length of the signal redistribution conductive layer and having power redistribution pads at end portions thereof.

Description

Technical Field

[0001] This patent document relates to semiconductor packaging, and more specifically, to a semiconductor package in which multiple semiconductor chips are vertically stacked. Background Technology

[0002] As electronic products continue to shrink in size, they require greater capacity to process large amounts of data. Therefore, there is an increasing need to increase the integration of semiconductor devices used in these electronic products.

[0003] However, due to limitations in semiconductor integration technology, it is difficult to perform the required functions using only a single semiconductor chip, so semiconductor packages with multiple semiconductor chips embedded are being manufactured. Summary of the Invention

[0004] In one embodiment, a semiconductor package includes a substrate and a sub-semiconductor package disposed on the substrate. The sub-semiconductor package includes: a sub-semiconductor chip having chip pads on its effective surface facing the substrate; a sub-molding layer surrounding a side surface of the sub-semiconductor chip and having a surface facing the substrate; and a redistribution conductive layer connected to the chip pads and extending on said one surface of the sub-molding layer. The redistribution conductive layer includes: a signal redistribution conductive layer extending to an edge of the sub-molding layer and having signal redistribution pads at its ends; and a power redistribution conductive layer having a length shorter than the length of the signal redistribution conductive layer and having power redistribution pads at its ends. The semiconductor package also includes: a signal sub-interconnect having an upper surface connected to the signal redistribution pads and a lower surface connected to the substrate; and a power sub-interconnect having an upper surface connected to the power redistribution pads and a lower surface connected to the substrate. The semiconductor package also includes a capacitor formed in the sub-molding layer. The capacitor includes a first electrode having a first electrode connected to the lower surface of the power redistribution conductive layer, a second electrode having a second electrode connected to the lower surface of the power redistribution conductive layer, and a body portion between the first and second electrodes. The semiconductor package further includes at least one main semiconductor chip formed on the sub-semiconductor package and electrically connected to the substrate.

[0005] In another embodiment, a semiconductor package includes a substrate and a sub-semiconductor package disposed on the substrate. The sub-semiconductor package includes: a sub-semiconductor chip having chip pads on its effective surface facing the substrate; a sub-molding layer surrounding a side surface of the sub-semiconductor chip and having a surface facing the substrate; and a signal redistribution conductive layer and a power redistribution conductive layer connected to the chip pads and extending to the edge of the sub-molding layer on the one surface of the sub-molding layer. The semiconductor package further includes: a signal sub-interconnect having an upper surface connected to a signal redistribution pad formed at an end of the signal redistribution conductive layer and a lower surface connected to the substrate; a first power sub-interconnect having an upper surface connected to a first power redistribution pad formed at a portion of the power redistribution conductive layer other than at the end of the power redistribution conductive layer and a lower surface connected to the substrate; and a capacitor formed in the sub-molding layer. The capacitor includes a first electrode connected to the lower surface of the power redistribution conductive layer, a second electrode connected to the lower surface of the power redistribution conductive layer, and a body portion between the first and second electrodes. The semiconductor package also includes at least one main semiconductor chip formed on the sub-semiconductor package and electrically connected to the substrate. Attached Figure Description

[0006] Figure 1 This is a plan view of a sub-semiconductor package from above, according to an embodiment of the present disclosure.

[0007] Figure 2 It is along Figure 1 The cross-sectional view taken by line A1-A1'.

[0008] Figure 3 It is along Figure 1 The cross-sectional view taken by line A2-A2'.

[0009] Figure 4 It is along Figure 1 The cross-sectional view taken by line A3-A3'.

[0010] Figure 5 This is a plan view of a semiconductor package viewed from above, illustrating an embodiment of the present disclosure.

[0011] Figure 6 This is an example Figure 5 A plan view of the upper surface of the substrate of a semiconductor package.

[0012] Figure 7 and Figure 8 This is an example Figure 5 A cross-sectional view of a semiconductor package.

[0013] Figure 9AThis is an illustration of an example used to describe the effect of a semiconductor package according to an embodiment of the present disclosure.

[0014] Figure 9B This is a diagram used to illustrate the effect of the semiconductor packaging according to the comparative example.

[0015] Figure 10A This is a diagram illustrating another example of the effect of a semiconductor package according to an embodiment of the present disclosure.

[0016] Figure 10B This is another illustration demonstrating the effect of the semiconductor packaging in the comparative example.

[0017] Figure 11 This is a plan view of a sub-semiconductor package according to another embodiment of the present disclosure, viewed from top.

[0018] Figure 12 It is along Figure 11 The cross-sectional view taken by line A4-A4'.

[0019] Figure 13 This is a plan view of a semiconductor package viewed from above, illustrating another embodiment of the present disclosure.

[0020] Figure 14 This is an example Figure 13 A plan view of the upper surface of the substrate of a semiconductor package.

[0021] Figure 15 This is an example Figure 13 A cross-sectional view of a semiconductor package.

[0022] Figure 16 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0023] Figure 17 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. Detailed Implementation

[0024] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated in order to clearly show specific features of the described embodiments. When a particular example of a multilayer structure with two or more layers is presented in the drawings or description, the relative positioning of these layers or the order in which they are arranged reflects a specific implementation of the described or illustrated example, and different relative positioning or orders in which they are arranged may be possible. Furthermore, the described or illustrated example of a multilayer structure may not reflect all the layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in a described or illustrated multilayer structure is referred to as "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also indicate a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0026] A semiconductor package according to embodiments of the present disclosure may include a main semiconductor chip performing a primary function and sub-semiconductor chips performing various functions required for the operation of the main semiconductor chip. The main semiconductor chip may include non-volatile memory such as NAND flash memory, and in this case, the sub-semiconductor chips may include a memory controller. However, the present disclosure is not limited thereto; each of the main semiconductor chip and the sub-semiconductor chips may include various types of memory, logic circuits, etc. In this embodiment, the sub-semiconductor chips may be packaged and implemented as a sub-semiconductor package, on which the main semiconductor chip may be formed.

[0027] In the following text, before describing the semiconductor package of this embodiment, the sub-semiconductor package included in the semiconductor package will be described first.

[0028] Figure 1 This is a plan view of a sub-semiconductor package according to an embodiment of the present disclosure, viewed from top. Figure 2 It is along Figure 1 The cross-sectional view taken by line A1-A1'. Figure 3 It is along Figure 1 The cross-sectional view taken by line A2-A2'. Figure 4 It is along Figure 1 The cross-sectional view taken by line A3-A3'. Figures 2 to 4 This shows the state where the effective surface of the sub-semiconductor chip is facing upwards.

[0029] Reference Figures 1 to 4 The sub-semiconductor package 110 of this embodiment may include a sub-semiconductor chip 114, a sub-molding layer 116, a redistribution structure 118, a sub-interconnector 119, and a capacitor 160.

[0030] The sub-semiconductor chip 114 may have an active surface 114A with a plurality of sub-chip pads 115, an inactive surface 114B opposite to the active surface 114A, and a side surface 114C connecting the active surface 114A and the inactive surface 114B. In this embodiment, the sub-semiconductor chip 114 may have four side surfaces 114C, which have a rectangular shape in a plan view. The four side surfaces 114C may be located on both sides in a first direction and on both sides in a second direction perpendicular to the first direction.

[0031] Multiple sub-chip pads 115 can be arranged in various configurations, all having an upper surface exposed from the effective surface 114A. As an example, the sub-chip pads 115 can be arranged along the entire edge of the sub-semiconductor chip 114. That is, the sub-chip pads 115 can be located at two side edges of the sub-semiconductor chip 114 in a first direction and at two side edges of the sub-semiconductor chip 114 in a second direction. In this case, a large number of sub-chip pads 115 can be formed in the sub-semiconductor chip 114, which has a relatively small planar area, thus allowing a large number of input / output signals to be transmitted through the sub-semiconductor chip 114.

[0032] The sub-semiconductor chip 114 may be located in the central region of the sub-semiconductor package 110. This may be to reduce the variation in length of the multiple signal redistribution conductive layers 118B-S (described later).

[0033] The sub-molding layer 116 may have a surface 116A having a level substantially the same as the effective surface 114A of the sub-semiconductor chip 114, while surrounding the side surface 114C of the sub-semiconductor chip 114. Therefore, the sub-molding layer 116 may expose the effective surface 114A and the sub-chip pads 115 of the sub-semiconductor chip 114. In this embodiment, the sub-molding layer 116 may cover the ineffective surface 114B of the sub-semiconductor chip 114. However, this disclosure is not limited thereto. In another embodiment, the sub-molding layer 116 may have another surface 116B disposed opposite to this surface 116A and having a level substantially the same as the ineffective surface 114B of the sub-semiconductor chip 114. The sub-molding layer 116 may comprise various molding materials such as epoxy molding compound (EMC).

[0034] The redistribution structure 118 may be formed on the effective surface 114A of the sub-semiconductor chip 114 and one surface 116A of the sub-molding layer 116. The redistribution structure 118 may include a redistribution conductive layer 118B extending to one surface 116A of the sub-molding layer 116 and electrically connected to the sub-chip pad 115. That is, the sub-semiconductor package 110 according to this embodiment may be a fan-out package.

[0035] More specifically, the redistribution structure 118 may include a first redistribution insulating layer 118A, a redistribution conductive layer 118B, and a second redistribution insulating layer 118C.

[0036] A first redistribution insulating layer 118A may cover an effective surface 114A of the sub-semiconductor chip 114 and a surface 116A of the sub-molding layer 116. The first redistribution insulating layer 118A may have openings exposing a first electrode 162 and a second electrode 164 of the sub-chip pad 115 and the capacitor 160 (described later). A redistribution conductive layer 118B may be formed on the first redistribution insulating layer 118A. The redistribution conductive layer 118B may be electrically connected to the sub-chip pad 115 and the first electrode 162 and the second electrode 164 of the capacitor 160 through the openings in the first redistribution insulating layer 118A. The redistribution conductive layer 118B may include a signal redistribution conductive layer 118B-S and a power redistribution conductive layer 118B-P. A second redistribution insulating layer 118C may cover the first redistribution insulating layer 118A and the redistribution conductive layer 118B. The second redistribution insulating layer 118C may have openings exposing the ends of the signal redistribution conductive layers 118B-S and the ends of the power redistribution conductive layers 118B-P. The ends of the signal redistribution conductive layers 118B-S exposed through the openings in the second redistribution insulating layer 118C will be referred to as signal redistribution pads 118BP-S, and the ends of the power redistribution conductive layers 118B-P exposed through the openings in the second redistribution insulating layer 118C will be referred to as power redistribution pads 118BP-P. The signal redistribution conductive layers 118B-S, signal redistribution pads 118BP-S, power redistribution conductive layers 118B-P, and power redistribution pads 118BP-P will be described in more detail below. The first redistribution insulating layer 118A and / or the second redistribution insulating layer 118C may comprise insulating materials such as oxides, nitrides, or oxynitrides. Alternatively, the first redistribution insulating layer 118A and / or the second redistribution insulating layer 118C may comprise resin materials such as epoxy resin, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicone resin, or acrylic. The redistribution conductive layer 118B may comprise a metallic material such as copper or a copper alloy.

[0037] The signal redistribution conductive layer 118B-S can be used for signal transmission between the sub-semiconductor chip 114 and other components. As an example, the signal redistribution conductive layer 118B-S can be used for signal exchange between the sub-semiconductor chip 114 and the main semiconductor chip (described later) or between the sub-semiconductor chip 114 and the substrate (described later). Hereinafter, the signals exchanged between the sub-semiconductor chip 114 and the main semiconductor chip will be referred to as internal signals, and the signals exchanged between the sub-semiconductor chip 114 and the substrate will be referred to as external signals.

[0038] Multiple signal redistribution conductive layers 118B-S may extend toward two side edges of the sub-molding layer 116 in a first direction. As an example, signal redistribution conductive layers 118B-S connected to sub-chip pads 115 disposed at the first side edges of the sub-semiconductor chip 114 in both the first and second directions may extend to the first side edge of the sub-molding layer 116 in the first direction. Additionally, signal redistribution conductive layers 118B-S connected to sub-chip pads 115 disposed at the second side edges of the sub-semiconductor chip 114 in both the first and second directions may extend to the second side edge of the sub-molding layer 116 in the first direction. The signal redistribution conductive layers 118B-S extending from the two side edges of the sub-semiconductor chip 114 in the second direction may have a curved shape toward the two side edges of the sub-molding layer 116 in the first direction. Alternatively, the signal redistribution conductive layers 118B-S extending from the two side edges of the sub-semiconductor chip 114 in the first direction may not need to be curved. However, the signal redistribution conductive layer 118B-S extending from the two side edges of the sub-semiconductor chip 114 in the first direction may also have a curved shape so as to have a length similar to the length of the signal redistribution conductive layer 118B-S extending from the two side edges of the sub-semiconductor chip 114 in the second direction. As a result, the signal redistribution conductive layer 118B-S may have a spiral shape centered on the sub-semiconductor chip 114. For example, as... Figure 1 As shown, the signal redistribution conductive layer 118B-S presents a spiral pattern on the sub-semiconductor chip 114. This connection scheme reduces the variation in the length of the signal redistribution conductive layer 118B-S.

[0039] According to the arrangement of the signal redistribution conductive layers 118B-S, the signal redistribution pads 118BP-S can be arranged along the second direction at each of the two side edges of the sub-molding layer 116 in the first direction. For reference, the signal redistribution conductive layer 118B-S may have a linear portion extending from the sub-chip pad 115 and having a relatively small width, and a plate-shaped end located at the end of the linear portion and having a relatively large width. An opening in the second redistribution insulating layer 118C can expose the plate-shaped end of the signal redistribution conductive layer 118B-S, and can have a planar area less than or equal to the planar area of ​​the plate-shaped end while overlapping with it.

[0040] The power redistribution conductive layer 118B-P can be used to supply power from the substrate (described later) to the sub-semiconductor chip 114. Various levels of power supply voltage or ground voltage can be supplied to the sub-semiconductor chip 114 through the power redistribution conductive layer 118B-P. Hereinafter, the power redistribution conductive layer 118B-P with an applied ground voltage will be referred to as the first power redistribution conductive layer 118B-P1, and the power redistribution conductive layer 118B-P with an applied power supply voltage will be referred to as the second power redistribution conductive layer 118B-P2.

[0041] Multiple power redistribution conductive layers 118B-P may be connected to sub-chip pads 115 and may extend onto a surface 116A of sub-molding layer 116. Power redistribution conductive layers 118B-P may have a shorter length than signal redistribution conductive layers 118B-S. That is, unlike signal redistribution conductive layers 118B-S, power redistribution conductive layers 118B-P may not extend to the edge of sub-molding layer 116. Power redistribution conductive layers 118B-P may be substantially parallel to a portion of adjacent signal redistribution conductive layers 118B-S. This is likely to prevent electrical short circuits between power redistribution conductive layers 118B-P and signal redistribution conductive layers 118B-S.

[0042] Depending on the arrangement of the power redistribution conductive layers 118B-P, a plurality of power redistribution pads 118BP-P can be configured to surround the sub-semiconductor chip 114 at predetermined intervals. For reference, the power redistribution conductive layers 118B-P may have a linear portion extending from the sub-chip pads 115 and having a relatively small width, and a plate-shaped end located at the end of the linear portion and having a relatively large width. An opening in the second redistribution insulating layer 118C can expose the plate-shaped end of the power redistribution conductive layers 118B-P, and can overlap with the plate-shaped end while having a planar area less than or equal to the planar area of ​​the plate-shaped end.

[0043] The capacitor 160 may be formed as a power redistribution conductive layer 118B-P electrically connected to the sub-molding layer 116.

[0044] The capacitor 160 may include a first electrode 162, a second electrode 164, and a body portion 166 therebetween. The body portion 166 may have various structures, as long as it can store charge according to the voltage applied to the first electrode 162 and the second electrode 164. As an example, the capacitor 160 may be a multilayer ceramic capacitor (MLCC). In this case, the body portion 166 may have a structure in which multiple ceramic dielectric layers and multiple internal electrodes are alternately stacked. The first electrode 162 and the second electrode 164 may include various conductive materials and may have a pillar shape that respectively contacts two side surfaces of the body portion 166.

[0045] Capacitor 160 may be embedded in sub-molding layer 116 together with sub-semiconductor chip 114. That is, the side and bottom surfaces of capacitor 160 may be surrounded by sub-molding layer 116. On the other hand, the upper surfaces of capacitor 160 (specifically, the upper surfaces of first electrode 162 and second electrode 164) may be positioned at substantially the same height as a surface 116A of sub-molding layer 116, so that at least a portion of each upper surface of first electrode 162 and second electrode 164 may be exposed through an opening in first redistribution insulating layer 118A. The upper surface of first electrode 162 may be connected to first power redistribution conductive layer 118B-P1, and the upper surface of second electrode 164 may be connected to second power redistribution conductive layer 118B-P2. More specifically, first power redistribution conductive layer 118B-P1 and second power redistribution conductive layer 118B-P2 may be connected to the upper surfaces of first electrode 162 and second electrode 164, respectively, through openings in first redistribution insulating layer 118A. On the other hand, the main body portion 166 may be insulated from the redistributed conductive layer 118B. Therefore, there may be no opening at the portion of the first redistributed insulating layer 118A corresponding to the main body portion 166. For reference, and for ease of description, in Figure 1 In the plan view, the first electrode 162 of the capacitor 160 is indicated as an unshaded rectangle, and the second electrode 164 of the capacitor 160 is indicated as a shaded rectangle. However, the shading is only used to distinguish between the first electrode 162 and the second electrode 164. Furthermore, the planar shapes of the first electrode 162 and the second electrode 164 can be modified in various ways.

[0046] As described above, the redistribution conductive layer 118B can also be connected to the sub-chip pad 115 through the opening of the first redistribution insulating layer 118A. Therefore, the upper surfaces of the first electrode 162 and the second electrode 164 can be positioned at substantially the same height as the upper surface of the sub-chip pad 115. As shown, the upper surface of the body portion 166 can be positioned at a lower level than the upper surfaces of the first electrode 162 and / or the second electrode 164. In this case, the first redistribution insulating layer 118A and the sub-molding layer 116 can be interposed between the body portion 166 and the redistribution conductive layer 118B. However, in another embodiment, the upper surface of the body portion 166 can be positioned at substantially the same height as the upper surfaces of the first electrode 162 and / or the second electrode 164.

[0047] Capacitor 160 can be electrically connected to the path for supplying power supply voltage and / or ground voltage to sub-semiconductor chip 114 (i.e., power redistribution conductive layer 118B-P) and can be used to prevent power shortages that occur during the operation of sub-semiconductor chip 114. In this embodiment, each of the first electrode 162 and the second electrode 164 of capacitor 160 can be connected to the portion of power redistribution conductive layer 118B-P between power redistribution pads 118BP-P and side surface 114C of sub-semiconductor chip 114. In this case, capacitor 160 can be disposed adjacent to sub-semiconductor chip 114, thus immediately compensating for transient voltage drops that occur during the operation of sub-semiconductor chip 114. As a result, power shortages can be prevented more effectively.

[0048] In this embodiment, four capacitors 160 may be provided for each of the four side surfaces 114C facing the sub-semiconductor chip 114. However, this disclosure is not limited thereto, and the number and position of the capacitors 160 may be modified in various ways.

[0049] One or more signal redistribution conductive layers 118B-S may be disposed between the first power redistribution conductive layer 118B-P1 and the second power redistribution conductive layer 118B-P2. In this case, the main body portion 166 may overlap with one or more signal redistribution conductive layers 118B-S disposed between the first power redistribution conductive layer 118B-P1 and the second power redistribution conductive layer 118B-P2.

[0050] Sub-interconnectors 119 may include signal sub-interconnectors 119-S that overlap and are connected to signal redistribution pads 118BP-S, and power sub-interconnectors 119-P that overlap and are connected to power redistribution pads 118BP-P. Since the signal redistribution pads 118BP-S and signal sub-interconnectors 119-S are substantially at the same position in the plan view, and the power redistribution pads 118BP-P and power sub-interconnectors 119-P are substantially at the same position, the signal redistribution pads 118BP-S and signal sub-interconnectors 119-S are... Figure 1 The power redistribution pad 118BP-P and the power sub-interconnect 119-P are shown together in the plan view. Figure 1 The plan view shows them together. Multiple signal sub-interconnects 119-S can be arranged along the second direction at each of the two side edges of the sub-molding layer 116 in the first direction. Multiple power sub-interconnects 119-P can be arranged to surround the sub-semiconductor chip 114 at predetermined intervals.

[0051] Sub-interconnect 119 can be connected to signal redistribution pads 118BP-S or power redistribution pads 118BP-P through openings in the second redistribution insulation layer 118C and can protrude onto the surface of the second redistribution insulation layer 118C. Sub-interconnect 119 may include solder balls, metal bumps, or combinations thereof. However, this embodiment is not limited to this; various forms of electrical interconnects that connect to signal redistribution pads 118BP-S or power redistribution pads 118BP-P while protruding onto the surface of the second redistribution insulation layer 118C can be used as sub-interconnect 119.

[0052] The signal redistribution pads 118BP-S and signal sub-interconnectors 119-S can be classified into those used for exchanging the aforementioned internal signals and those used for exchanging the aforementioned external signals. The signal redistribution pads 118BP-S and signal sub-interconnectors 119-S used for exchanging internal signals will be referred to as internal signal redistribution pad 118BP-S1 and internal signal sub-interconnector 119-S1, respectively. Furthermore, the signal redistribution pads 118BP-S and signal sub-interconnectors 119-S used for exchanging external signals will be referred to as external signal redistribution pad 118BP-S2 and external signal sub-interconnector 119-S2, respectively.

[0053] For reference, see Figure 2 and Figure 3 The upper surfaces of the first electrode 162 and the second electrode 164 of capacitor 160 can be connected to the lower surface of the power redistribution conductive layer 118B-P, and the lower surface of the power sub-interconnect 119-P can be connected to the upper surface of the power redistribution conductive layer 118B-P (specifically, the power redistribution pad 118BP-P). However, as will be described later, the sub-semiconductor package 110 can be mounted on the substrate in a downward orientation, and in this case, the positions of the upper and lower surfaces can be reversed. Even in this case, the positions of capacitor 160 and power sub-interconnect 119-P can be opposite to each other in the vertical direction, and the power redistribution conductive layer 118B-P is interposed between them.

[0054] The following will refer to Figures 5 to 8 The description includes the semiconductor package 110 described above.

[0055] Figure 5 This is a plan view of a semiconductor package according to an embodiment of the present disclosure, viewed from top. Figure 6 This is an example Figure 5 A plan view of the upper surface of the substrate of a semiconductor package. Figure 7 and Figure 8 This is an example Figure 5 A cross-sectional view of a semiconductor package. Specifically, Figure 7 This is an example Figure 5A cross-sectional view of the internal signal exchange between the first and second main chip stacks and the sub-semiconductor package. Figure 8 This is an example Figure 5 Cross-sectional views of external signal exchange between the sub-semiconductor package and the substrate, power transfer between the first and second main chip stacks and the substrate, and power transfer between the sub-semiconductor package and the substrate. Additionally, Figure 8 A capacitor is also shown for addressing potential power shortages that may occur when transferring power between a sub-semiconductor package and a substrate.

[0056] Reference Figures 5 to 8 The semiconductor package according to the embodiments of the present disclosure may include a substrate 100, a sub-semiconductor package 110 disposed on the substrate 100, and a first main chip stack 120 and a second main chip stack 130 disposed on the sub-semiconductor package 110.

[0057] The substrate 100 may be a substrate for semiconductor packaging, having circuit and / or wiring structures for transmitting electrical signals. For example, the substrate 100 may include a printed circuit board (PCB).

[0058] The substrate 100 may have an upper surface 100A, a lower surface 100B configured to be opposite to the upper surface 100A, and a side surface connecting the upper surface 100A and the lower surface 100B.

[0059] Sub-semiconductor package 110, first main chip stack 120, and second main chip stack 130 can be disposed on the upper surface 100A of substrate 100. Specifically, sub-semiconductor package 110 can be mounted on substrate 100 such that the effective surface 114A of sub-semiconductor chip 114 and one surface 116A of sub-molding layer 116 face the upper surface 100A of substrate 100. That is, sub-semiconductor package 110 can be mounted on substrate 100 in a downward orientation. Therefore, in Figure 5 In the plan view, detailed components included in the sub-semiconductor package 110 may not be visible except for the other surface 116B of the sub-molding layer 116. However, for ease of description, some components of the sub-semiconductor package 110 not covered by the first main chip stack 120 and the second main chip stack 130 are shown in the diagram. Figure 5 The components are shown in dashed lines. Additionally, for ease of description, detailed components of the sub-semiconductor package 110 are shown in... Figure 6 The image is also shown by dashed lines. For reference, since the sub-semiconductor package 110 is mounted on the substrate 100 in a downward orientation, Figure 5 and Figure 6 The detailed left and right positions of the components in the semiconductor package 110. Figure 1In contrast to the reverse, the external connection terminal 140 for connecting the semiconductor package of this embodiment to external components may be provided on the lower surface 100B of the substrate 100. For reference, the upper and lower surfaces described below are expressions indicating the relative positions of various surfaces of the components rather than indicating absolute positions. For example, unlike the example, in the case where the semiconductor package is reversed, the surface on which the sub-semiconductor package 110, the first main chip stack 120, and the second main chip stack 130 are disposed may be the lower surface of the substrate 100, and the surface on which the external connection terminal 140 is disposed may be the upper surface of the substrate 100.

[0060] Sub-substrate pads 102S, first main substrate pads 102M1, and second main substrate pads 102M2 may be disposed on the upper surface 100A of substrate 100. Sub-substrate pads 102S may be electrically connected to sub-semiconductor packages 110, the first main substrate pads 102M1 may be electrically connected to the first main chip stack 120, and the second main substrate pads 102M2 may be electrically connected to the second main chip stack 130. Lower surface substrate pads 104 for connection to external connection terminals 140 may be disposed on the lower surface 100B of substrate 100. For reference, substrate pads may refer to conductive elements or terminals exposed on the surface of substrate 100 for electrically connecting substrate 100 to other components. These substrate pads may be connected to circuitry and / or wiring structures within substrate 100.

[0061] Sub-substrate pads 102S may overlap and connect with sub-interconnects 119. When sub-interconnects 119 include metal bumps, sub-substrate pads 102S may include bump-engaging fingers.

[0062] Sub-substrate pads 102S may include power sub-substrate pads 102S-P connected to power sub-interconnects 119-P and signal sub-substrate pads 102S-S connected to signal sub-interconnects 119-S. Furthermore, signal sub-substrate pads 102S-S may include internal signal sub-substrate pads 102S-S1 connected to internal signal sub-interconnects 119-S1 and external signal sub-substrate pads 102S-S2 connected to external signal sub-interconnects 119-S2. Multiple power sub-substrate pads 102S-P may overlap and connect to power sub-interconnects 119-P respectively; therefore, power sub-substrate pads 102S-P may be arranged to surround sub-semiconductor chips 114 on the upper surface 100A of substrate 100. Multiple signal sub-substrate pads 102S-S may overlap and connect to signal sub-interconnects 119-S respectively. The signal sub-substrate pads 102S-S can be arranged to overlap with the two side edges of the sub-molding layer 116 in a first direction on the upper surface 100A of the substrate 100.

[0063] A first main substrate pad 102M1 may be connected to a first main interconnect 127 (described later), and a second main substrate pad 102M2 may be connected to a second main interconnect 137 (described later). When the first main interconnect 127 and the second main interconnect 137 are bonding leads, the first main substrate pad 102M1 and the second main substrate pad 102M2 may include wire bonding fingers. A plurality of first main substrate pads 102M1 may be arranged along a second direction at a first side edge of the substrate 100 in a first direction. A plurality of second main substrate pads 102M2 may be arranged along a second direction at a second side edge of the substrate 100 in a first direction. The first main substrate pads 102M1 and the second main substrate pads 102M2 may be exposed and not covered by the sub-semiconductor package 110. For this purpose, the sub-semiconductor package 110 may have a width in the first direction smaller than the width of the upper surface 100A of the substrate 100, and may be disposed relative to the center of the substrate 100. Furthermore, the first main substrate pad 102M1 and the second main substrate pad 102M2 can be exposed without being covered by the first main chip stack 120 and the second main chip stack 130.

[0064] The first main substrate pad 102M1 may include: a first signal main substrate pad 102M1-S for exchanging internal signals between the sub-semiconductor package 110 and the first main chip stack 120; and a first power main substrate pad 102M1-P for supplying power to the first main chip stack 120. In this case, the first signal main substrate pad 102M1-S can be electrically connected to the internal signal sub-substrate pads 102S-S1 overlapping the first side edge of the sub-molding layer 116 via a connection line CL formed in the substrate 100. The connection line CL can connect the first signal main substrate pad 102M1-S, to which the first main chip stack 120 is electrically connected, and the internal signal sub-substrate pads 102S-S1, to which the sub-semiconductor package 110 is electrically connected, to each other. Therefore, an electrical connection can be made between the first main chip stack 120 and the sub-semiconductor package 110. In a cross-sectional view, the connecting line CL may be located at the same level as the first signal main substrate pad 102M1-S and the internal signal sub-substrate pads 102S-S1. Furthermore, the connecting line CL may have a linear shape to minimize the distance between the first signal main substrate pad 102M1-S and the internal signal sub-substrate pads 102S-S1 in a planar view. This may be to form an internal signal transmission path between the first signal main substrate pad 102M1-S and the internal signal sub-substrate pads 102S-S1 with the shortest distance. However, this disclosure is not limited to this; the position and shape of the connecting line CL can be modified in various ways as long as the first signal main substrate pad 102M1-S and the internal signal sub-substrate pads 102S-S1 are connected to each other in the substrate 100.

[0065] The second main substrate pad 102M2 may include: a second signal main substrate pad 102M2-S for exchanging internal signals between the sub-semiconductor package 110 and the second main chip stack 130; and a second power main substrate pad 102M2-P for supplying power to the second main chip stack 130. In this case, the second signal main substrate pad 102M2-S can be electrically connected to the internal signal sub-substrate pads 102S-S1 overlapping the second side edge of the sub-molding layer 116 via a connection line CL formed in the substrate 100. The connection line CL can connect the second signal main substrate pad 102M2-S, to which the second main chip stack 130 is electrically connected, and the internal signal sub-substrate pads 102S-S1, to which the sub-semiconductor package 110 is electrically connected, to each other. Therefore, an electrical connection can be made between the second main chip stack 130 and the sub-semiconductor package 110. In a cross-sectional view, the connecting line CL may be located at the same level as the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1. Furthermore, the connecting line CL may have a linear shape to minimize the distance between the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1 in a planar view. This may be to form an internal signal transmission path between the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1 with the shortest distance. However, this disclosure is not limited to this; the position and shape of the connecting line CL can be modified in various ways as long as the second signal main substrate pad 102M2-S and the internal signal sub-substrate pad 102S-S1 are connected to each other in the substrate 100.

[0066] The lower surface substrate pad 104 can be connected to the external connection terminal 140. When the external connection terminal 140 includes solder balls, the lower surface substrate pad 104 can include ball pads.

[0067] Since the detailed configuration of the sub-semiconductor package 110 has already been described, its detailed description will be omitted. The sub-semiconductor package 110 can be electrically connected to the substrate 100 via the sub-interconnect 119.

[0068] Specifically, refer to Figure 6 and Figure 8The power sub-interconnect 119-P can be connected to the power sub-substrate pad 102S-P. Therefore, an electrical path (i.e., a power supply path) can be formed through the sub-semiconductor chip 114, the power redistribution conductive layer 118B-P, the power sub-interconnect 119-P, and the power sub-substrate pad 102S-P. In this case, since the length of the power redistribution conductive layer 118B-P connected to the power sub-interconnect 119-P is relatively shorter than the length of the signal redistribution conductive layer 118B-S, the length of the power supply path can be reduced. Furthermore, by forming a capacitor 160 in the sub-molding layer 116, which includes a first electrode 162 and a second electrode 164 respectively connected to the first power redistribution conductive layer 118B-P1 and the second power redistribution conductive layer 118B-P2, and a body portion 166 between the first electrode 162 and the second electrode 164, power can be supplied to the sub-semiconductor chip 114 more stably. Although not shown, the power sub-substrate pad 102S-P can be electrically connected to the external connection terminal 140 via the circuitry and / or wiring structure inside the substrate 100, thereby connecting to and being powered by an external component (not shown).

[0069] Additionally, refer to Figure 6 and Figure 8 External signal sub-interconnects 119-S2 can be connected to external signal sub-substrate pads 102S-S2. Therefore, an electrical path (i.e., an external signal transmission path) can be formed through the sub-semiconductor chip 114, the signal redistribution conductive layer 118B-S, the external signal sub-interconnects 119-S2, and the external signal sub-substrate pads 102S-S2. Although not shown, the external signal sub-substrate pads 102S-S2 can be electrically connected to external connection terminals 140 via circuitry and / or wiring structures within the substrate 100, thereby connecting to and exchanging signals with external components (not shown).

[0070] In addition, refer to Figure 6 and Figure 7Internal signal sub-interconnects 119-S1 can be connected to internal signal sub-substrate pads 102S-S1. As described later, internal signal sub-substrate pads 102S-S1 can be connected to first signal main substrate pads 102M1-S and second signal main substrate pads 102M2-S via connection lines CL. Therefore, electrical connections can be made between each of the first main chip stack 120 and the second main chip stack 130 and the sub-semiconductor chip 114. This will be described together with the first main chip stack 120 and the second main chip stack 130. The power supply path through the power redistribution conductive layer 118B-P, power sub-interconnects 119-P, and power sub-substrate pads 102S-P of the substrate 100 can be shorter than the signal transmission path through the signal redistribution conductive layer 118B-S, signal sub-interconnects 119-S, and signal sub-substrate pads 102S-S of the substrate 100. Capacitor 160 can be electrically connected to this power supply path.

[0071] The first master chip stack 120 may include a plurality of first master semiconductor chips 124. The first master semiconductor chips 124 may be formed on the sub-semiconductor package 110 and may be stacked in the vertical direction relative to the upper surface 100A of the substrate 100. Although this embodiment illustrates a case in which the first master chip stack 120 includes four first master semiconductor chips 124, the present disclosure is not limited thereto, and the number of first master semiconductor chips 124 included in the first master chip stack 120 may be modified in various ways to one or more first master semiconductor chips 124.

[0072] The first main semiconductor chip 124 can be located in a direction toward the second side of the first direction (e.g., toward the direction of the first direction). Figure 5 The lower side of the middle and Figure 7 and Figure 8 (in the direction of the right side of the first main semiconductor chip 124) with a predetermined offset stacking. Therefore, a first main chip stack 120 having a stepped shape when viewed as a whole can be formed. The offset stacking direction of the first main semiconductor chip 124 will be referred to as the first offset direction. According to this offset stacking, the first side edge of the upper surface of each of the remaining first main semiconductor chips 124, except for the uppermost first main semiconductor chip 124, can be exposed without being covered by the first main semiconductor chip 124 directly located thereon. For example... Figure 5 The upper edge of the upper surface of each of the remaining first main semiconductor chips 124 and Figure 7 and Figure 8The left edge of the upper surface of each of the remaining first master semiconductor chips 124 is exposed. The first side edge of the upper surface of the uppermost first master semiconductor chip 124 is exposed and not covered by the lowermost second master semiconductor chip 134 of the second master chip stack 130 (described later). First chip pads 125 may be disposed on these exposed portions of the first master semiconductor chips 124. A plurality of first chip pads 125 may be arranged in a row along a second direction at the first side edge of the upper surface of each first master semiconductor chip 124. However, this disclosure is not limited thereto, and the number and arrangement of the first chip pads 125 at the first side edge of the upper surface of each first master semiconductor chip 124 may be modified in various ways. For reference, since Figure 1 The portion of the first main chip stack 120 that is hidden by the second main chip stack 130 is not shown in the plan view, so the remaining portion of the first main chip stack 120 (e.g., the first side edge of the bottommost first main semiconductor chip 124) is shown.

[0073] Each first main semiconductor chip 124 can be attached to the sub-semiconductor package 110 or directly beneath it via a first adhesive layer 122. The first adhesive layer 122 can be formed on the lower surface of each first main semiconductor chip 124 to have a shape that overlaps with the lower surface.

[0074] The first main chip stack 120 or the first main semiconductor chip 124 may have a planar area smaller than that of the sub-semiconductor package 110 and a planar area larger than that of the sub-semiconductor chip 114. The first main chip stack 120 may be configured to expose at least the first main substrate pad 102M1 and the second main substrate pad 102M2 disposed at two side edges of the substrate 100 in a first direction.

[0075] The first master chip stack 120 can be connected to the substrate 100 and the sub-semiconductor package 110 via the first master interconnect 127. In this embodiment, the first master chip stack 120 is electrically connected to the substrate 100 to receive power from the substrate 100 for the operation of the first master chip stack 120. Additionally, the first master chip stack 120 is electrically connected to the sub-semiconductor package 110 to exchange internal signals with the sub-semiconductor chip 114. The interconnect in the first master interconnect 127 connecting the first master chip stack 120 and the substrate 100 will be referred to as the first power master interconnect 127P. Furthermore, the interconnect in the first master interconnect 127 connecting the first master chip stack 120 and the sub-semiconductor package 110 will be referred to as the first signal master interconnect 127S.

[0076] Specifically, refer to Figure 5 and Figure 7The first signal main interconnect 127S can connect the first chip pads 125 that are adjacent to each other in the vertical direction, and can connect the first chip pad 125 of the lowest first main semiconductor chip 124 and the first signal main substrate pad 102M1-2. Therefore, the first main semiconductor chips 124 can be electrically connected to each other, and the first main chip stack 120 can be electrically connected to the sub-semiconductor package 110 through the substrate 100. More specifically, an electrical path (i.e., a signal transmission path) can be formed through the first main chip stack 120, the first signal main interconnect 127S, the first signal main substrate pads 102M1-S, the connection line CL, the internal signal sub-substrate pads 102S-S1, the internal signal sub-interconnects 119-S1, the signal redistribution conductive layers 118B-S, and the sub-semiconductor chip 114.

[0077] In addition, specifically, refer to Figure 5 and Figure 8 The first power main interconnect 127P can connect the first chip pads 125 that are vertically adjacent to each other, and can connect the first chip pad 125 of the lowest first main semiconductor chip 124 to the first power main substrate pad 102M1-P of the substrate 100. Therefore, the first main semiconductor chips 124 can be electrically connected to each other, and the first main chip stack 120 can be electrically connected to the substrate 100. More specifically, an electrical path (i.e., a power supply path) can be formed through the first main chip stack 120, the first power main interconnect 127P, and the first power main substrate pad 102M1-P.

[0078] The first master interconnect 127 may be a bonding lead. However, this embodiment is not limited to this, and various types of electrical interconnects may be used as the first master interconnect 127.

[0079] The second master chip stack 130 may include a plurality of second master semiconductor chips 134. The second master semiconductor chips 134 may be formed on the first master chip stack 120 and may be stacked in the vertical direction. Although this embodiment illustrates a case where the second master chip stack 130 includes four second master semiconductor chips 134, this disclosure is not limited thereto, and the number of second master semiconductor chips 134 included in the second master chip stack 130 may be modified in various ways to one or more second master semiconductor chips 134. Furthermore, although in this embodiment the number of second master semiconductor chips 134 included in the second master chip stack 130 is the same as the number of first master semiconductor chips 124 included in the first master chip stack 120, it should be noted that these numbers may differ from each other.

[0080] The second main semiconductor chip 134 can be in the direction toward the first side of the first direction (e.g., toward the direction of the first side). Figure 5 The upper side of the middle and Figure 7 and Figure 8 The second main semiconductor chip 134 is stacked at a predetermined offset (in the direction of the left side of the stack). Therefore, a second main semiconductor chip stack 130 with a stepped shape when viewed as a whole can be formed. The offset stacking direction of the second main semiconductor chip 134 will be referred to as the second offset direction. The second offset direction may be opposite to the first offset direction. According to this offset stacking, the second side edge of the upper surface of each of the remaining second main semiconductor chips 134, except for the uppermost second main semiconductor chip 134, can be exposed without being covered by the second main semiconductor chip 134 directly above it. For example... Figure 5 The lower edge of the upper surface of each of the remaining second main semiconductor chips 134 and Figure 7 and Figure 8 The right edge of the upper surface of each of the remaining second main semiconductor chips 134 can be exposed. The uppermost second main semiconductor chip 134 can be in a state where its entire upper surface is exposed. Second chip pads 135 can be provided on the exposed portions of the remaining second main semiconductor chips 134 excluding the uppermost second main semiconductor chip 134, and the second chip pads 135 of the uppermost second main semiconductor chip 134 can also be provided at the same position as the second chip pads 135 of the remaining second main semiconductor chips 134. A plurality of second chip pads 135 can be arranged in a row along a second direction at the second side edge of the upper surface of each second main semiconductor chip 134. However, this disclosure is not limited thereto, and the number and arrangement of the second chip pads 135 at the second side edge of the upper surface of each second main semiconductor chip 134 can be modified in various ways.

[0081] When the second main semiconductor chip 134 is the same semiconductor chip as the first main semiconductor chip 124, each second main semiconductor chip 134 can correspond to the state in which each first main semiconductor chip 124 is rotated 180 degrees about an axis extending in the vertical direction.

[0082] Each of the second main semiconductor chips 134 can be attached to the second main semiconductor chip 134 directly below it or the uppermost first main semiconductor chip 124 of the first main semiconductor chip stack 120 via a second adhesive layer 132. The second adhesive layer 132 can be formed on the lower surface of each of the second main semiconductor chips 134 to have a shape that overlaps with the lower surface.

[0083] The second main chip stack 130 or the second main semiconductor chip 134 may have a planar area smaller than that of the sub-semiconductor package 110 and may have a planar area larger than that of the sub-semiconductor chip 114. The second main chip stack 130 may be configured to expose at least the first main substrate pad 102M1 and the second main substrate pad 102M2 disposed at two side edges of the substrate 100 in a first direction.

[0084] The second master chip stack 130 can be connected to the substrate 100 and the sub-semiconductor package 110 via the second master interconnect 137. In this embodiment, the second master chip stack 130 is electrically connected to the substrate 100 to receive power from the substrate 100 for the operation of the second master chip stack 130. Additionally, the second master chip stack 130 is electrically connected to the sub-semiconductor package 110 to exchange internal signals with the sub-semiconductor chip 114. The interconnect in the second master interconnect 137 connecting the second master chip stack 130 and the substrate 100 will be referred to as the second power master interconnect 137P. Furthermore, the interconnect in the second master interconnect 137 connecting the second master chip stack 130 and the sub-semiconductor package 110 will be referred to as the second signal master interconnect 137S.

[0085] Specifically, refer to Figure 5 and Figure 7 The second signal master interconnect 137S can connect the second chip pads 135 that are vertically adjacent to each other, and can also connect the second chip pads 135 of the lowest second master semiconductor chip 134 and the second signal master substrate pads 102M2-2. Therefore, the second master semiconductor chips 134 can be electrically connected to each other, and the second master chip stack 130 can be electrically connected to the sub-semiconductor package 110 via the substrate 100. More specifically, an electrical path (i.e., a signal transmission path) can be formed through the second master chip stack 130, the second signal master interconnect 137S, the second signal master substrate pads 102M2-S, the interconnect line CL, the internal signal sub-substrate pads 102S-S1, the internal signal sub-interconnects 119-S1, the signal redistribution conductive layers 118B-S, and the sub-semiconductor chip 114.

[0086] In addition, specifically, refer to Figure 5 and Figure 8 The second power main interconnect 137P can connect the second chip pads 135 that are vertically adjacent to each other, and can connect the second chip pads 135 of the lowest second main semiconductor chip 134 to the second power main substrate pads 102M2-P of the substrate 100. Therefore, the second main semiconductor chips 134 can be electrically connected to each other, and the second main chip stack 130 can be electrically connected to the substrate 100. More specifically, an electrical path (i.e., a power supply path) can be formed through the second main chip stack 130, the second power main interconnect 137P, and the second power main substrate pads 102M2-P.

[0087] The second main interconnect 137 can be a bonding lead. However, this embodiment is not limited to this, and various types of electrical interconnects can be used as the second main interconnect 137.

[0088] For reference, Figure 5 and Figure 6In the plan view, for ease of description, the first main interconnect 127 and the second main interconnect 137 are shown by different dashed lines. However, it should be noted that these dashed lines do not reflect the actual shapes of the first main interconnect 127 and the second main interconnect 137.

[0089] The sub-semiconductor package 110, the first main chip stack 120, and the second main chip stack 130 may be covered by a molding layer 150 formed on the substrate 100. The molding layer 150 may include various molding materials such as EMC.

[0090] The external connection terminal 140 described above may include solder balls. However, this disclosure is not limited thereto, and various conductive terminals such as bumps may be used as external connection terminals 140.

[0091] In the semiconductor package of this embodiment, the first master chip stack 120 can be identified as a single semiconductor chip group while being connected to the substrate 100 and the sub-semiconductor package 110 via the first master interconnect 127. Additionally, the second master chip stack 130 can be identified as another single semiconductor chip group different from the first master chip stack 120 while being connected to the substrate 100 and the sub-semiconductor package 110 via the second master interconnect 137. The sub-semiconductor chip 114 can be connected to the substrate 100 via the redistribution structure 118 and the sub-interconnect 119.

[0092] The following advantages can be obtained based on the above semiconductor packaging.

[0093] First, since the sub-chip pads 115 are arranged along the entire edge of the sub-semiconductor chip 114, a relatively large number of sub-chip pads 115 can be provided compared to the size of the sub-semiconductor chip 114. Furthermore, the arrangement of the sub-chip pads 115 is facilitated by redistributing them using fan-out technology.

[0094] Furthermore, since some sub-chip pads 115 are redistributed to internal signal redistribution pads 118BP-S1 using fan-out technology, and the internal signal redistribution pads 118BP-S1 are connected to the first signal main substrate pads 102M1-S and the second signal main substrate pads 102M2-S through internal signal sub-interconnectors 119-S1, internal signal sub-substrate pads 102S-S1 and the connection line CL inside the substrate 100, the signal transmission distance between the sub-semiconductor chip 114 and the first main chip stack 120 and the second main chip stack 130 can be reduced.

[0095] Furthermore, by using fan-out technology to place a sub-semiconductor package 110, which is larger than the first main chip stack 120 and the second main chip stack 130, below the first main chip stack 120 and the second main chip stack 130, the first main chip stack 120 and the second main chip stack 130 can be stably formed. In a structure where the first main chip stack 120 and the second main chip stack 130 are formed on the sub-semiconductor chip 114, if the sub-semiconductor chip 114 is smaller than the first main semiconductor chip 124 and the second main semiconductor chip 134, it may cause the first main chip stack 120 and the second main chip stack 130 to tilt. This problem can be avoided by significantly increasing the area of ​​the sub-semiconductor chip 114 using fan-out technology.

[0096] Furthermore, by adjusting the shape and / or arrangement of the signal redistribution conductive layers 118B-S to ensure they have similar lengths, the operational characteristics of the semiconductor package can be guaranteed. For example, when there is a first channel connecting the first master chip stack 120 to the sub-semiconductor package 110 and a second channel connecting the second master chip stack 130 to the sub-semiconductor package 110, the paths of the first and second channels can have similar lengths. Therefore, signal transmission rates can be prevented from varying with different channels to the greatest extent possible.

[0097] Furthermore, since the length of the power redistribution conductive layer 118B-P is shorter than the length of the signal redistribution conductive layer 118B-S, and the power redistribution conductive layer 118B-P and the substrate 100 are connected via the power sub-interconnect 119, power can be easily supplied to the sub-semiconductor chip 114. In this case, the length of the power supply path from the substrate 100 to the sub-semiconductor chip 114 can be shortened, and therefore, the impedance of the power supply path can be reduced. This will be explained below. Figure 9A and Figure 9B Further description.

[0098] Furthermore, a smooth power supply is achieved by incorporating a capacitor 160 connected to the power redistribution conductive layer 118B-P within the sub-semiconductor package 110. Specifically, compared to the case where the capacitor is disposed around the sub-semiconductor package 110, the AC path through the capacitor 160 is shortened, thereby further reducing the impedance of the power supply path. This will be explained below. Figure 10A and Figure 10B Further description.

[0099] Figure 9A This is an illustration used to depict an example of the effect of a semiconductor package according to an embodiment of the present disclosure. Figure 9B This is a diagram used to illustrate the effect of the semiconductor packaging according to the comparative example. Unlike this embodiment, Figure 9BAn example is shown where the power redistribution conductive layer extends to the edge of the sub-molding layer in a similar manner to the signal redistribution conductive layer, and the end of the power redistribution conductive layer is connected to the substrate via a power sub-interconnector.

[0100] Reference Figure 9A It can form a relatively short current path (see dashed arrow), which passes through a short power redistribution conductive layer 118B-P, a power sub-interconnector 119-P disposed below and connected to the power redistribution conductive layer 118B-P, a substrate 100, and an external connection terminal 140 for power supply.

[0101] On the other hand, refer to Figure 9B It can form a relatively long current path (see dashed arrow), which passes through a relatively long power redistribution conductive layer 118B-P', a power sub-interconnector 119-P' disposed below and connected to the power redistribution conductive layer 118B-P', a substrate 100', and an external connection terminal 140' for power supply.

[0102] In other words, in Figure 9B In the comparative example, regardless of the location of the external connection terminal 140' used to supply power to the substrate 100', a power supply path can be formed that extends through a relatively long power redistribution conductive layer 118B-P' to the edge of the sub-molding layer. Therefore, compared with... Figure 9A Compared to other implementation methods, a relatively long power supply path may be unavoidable.

[0103] As a result, according to this embodiment, such as Figure 9A As shown, a shorter current path can be formed, thus reducing the impedance of the power supply path. Therefore, power supply can be facilitated.

[0104] Figure 10A This is a diagram illustrating another example of the effect of a semiconductor package according to an embodiment of the present disclosure. Figure 10B This is a diagram illustrating another example of the effect of the comparative example semiconductor package. Unlike this embodiment, Figure 10B This illustrates a case where the power redistribution conductive layer extends to the edge of the sub-molding layer in a similar manner to the signal redistribution conductive layer, and the capacitor is disposed separately outside the sub-semiconductor package.

[0105] Reference Figure 10A Since capacitor 160 is connected to a portion of each of the shorter first power redistribution conductive layers 118B-P1 and 118B-P2, a short AC current path can be formed through a portion of the second power redistribution conductive layer 118B-P2, capacitor 160, and a portion of the first power redistribution conductive layer 118B-P1 (refer to the dashed arrow).

[0106] On the other hand, refer to Figure 10B This can form a long AC current path passing through the entire second power redistribution conductive layer 118B-P2', a power sub-interconnector 119-P' disposed below the second power redistribution conductive layer 118B-P2' and connected to the end of the second power redistribution conductive layer 118B-P2', a substrate 100', an external connection terminal 140' for supplying power supply voltage, a capacitor 160', a substrate 100', an external connection terminal 140' for supplying ground voltage, a substrate 100', a power sub-interconnector 119-P' disposed below the first power redistribution conductive layer 118B-P1' and connected to the end of the first power redistribution conductive layer 118B-P1', and the entire first power redistribution conductive layer 118B-P1' (refer to the dashed arrow).

[0107] As a result, in such Figure 10A In the case of this embodiment shown, since a short AC current path can be formed through the capacitor 160, the impedance of the power supply path can be reduced, and therefore, power supply can be performed more easily and stably.

[0108] Furthermore, in the above embodiments, the case where the power redistribution conductive layer is shorter than the signal redistribution conductive layer was described. However, this disclosure is not limited to this; the length of the power redistribution conductive layer may be the same as or similar to the length of the signal redistribution conductive layer. In this case, the power supply path of the sub-semiconductor chip can be shortened by using a power sub-interconnect connected to a specific point of the power redistribution conductive layer. This will be referred to... Figures 11 to 15 describe.

[0109] Figure 11 This is a plan view of a sub-semiconductor package according to another embodiment of the present disclosure, viewed from top. Figure 12 It is along Figure 11 The cross-sectional view taken by line A4-A4'. Figure 12 This shows the state where the effective surface of the sub-semiconductor chip is facing down. Figure 13 This is a plan view of a semiconductor package according to another embodiment of the present disclosure, viewed from top. Figure 14 This is an example Figure 13 A plan view of the upper surface of the substrate of a semiconductor package. Figure 15 This is an example Figure 13 A cross-sectional view of a semiconductor package. Specifically, Figure 15 The sub-semiconductor package shows along Figure 14 The cross-section cut by line A5-A5' Figure 15 The remaining portion describes the power transfer between the first and second main chip stacks and the substrate. Detailed descriptions of portions substantially the same as those in the above embodiments will be omitted.

[0110] First, refer to Figure 11 and Figure 12 The sub-semiconductor package 310 of this embodiment may include a sub-semiconductor chip 314, a sub-molding layer 316, a redistribution structure 318, a sub-interconnector 319, and a capacitor 360.

[0111] The sub-semiconductor chip 314 may have an effective surface 314A on which a plurality of sub-chip pads 315 are disposed, an ineffective surface 314B disposed opposite to the effective surface 314A, and a side surface 314C connecting the effective surface 314A and the ineffective surface 314B. The plurality of sub-chip pads 315 may be arranged along the entire edge of the sub-semiconductor chip 314.

[0112] The sub-molding layer 316 may have a surface 316A at substantially the same level as the effective surface 314A of the sub-semiconductor chip 314, while surrounding the side surface 314C of the sub-semiconductor chip 314. Therefore, the sub-molding layer 316 may expose the effective surface 314A and the sub-chip pads 315 of the sub-semiconductor chip 314. Another surface 316B of the sub-molding layer 316 may be disposed opposite to this surface 316A.

[0113] A redistribution structure 318 may be formed on the effective surface 314A of the sub-semiconductor chip 314 and one surface 316A of the sub-molding layer 316. The redistribution structure 318 may include a first redistribution insulating layer 318A, a redistribution conductive layer 318B, and a second redistribution insulating layer 318C. The redistribution conductive layer 318B may extend to one surface 316A of the sub-molding layer 316 while being electrically connected to the first electrode 362 and the second electrode 364 of the capacitor 360.

[0114] The redistribution conductive layer 318B may include a signal redistribution conductive layer 318B-S and a power redistribution conductive layer 318B-P. In this embodiment, regardless of the signal redistribution conductive layers 318B-S and the power redistribution conductive layers 318B-P, all redistribution conductive layers 318B may extend toward the two side edges of the sub-molding layer 316 in the first direction. As an example, the signal redistribution conductive layers 318B-S and the power redistribution conductive layers 318B-P connected to the sub-chip pads 315 disposed at the first side edges of the sub-semiconductor chip 314 in the first and second directions may extend toward the first side edge of the sub-molding layer 316 in the first direction. Additionally, the signal redistribution conductive layers 318B-S and the power redistribution conductive layers 318B-P connected to the sub-chip pads 315 disposed at the second side edges of the sub-semiconductor chip 314 in the first and second directions may extend toward the second side edge of the sub-molding layer 316 in the first direction. As a result, the redistribution conductive layers 318B may have a spiral shape centered on the sub-semiconductor chip 314. This connection method can reduce the variation in the length of the redistributed conductive layer 318B.

[0115] As described above, based on the arrangement of the signal redistribution conductive layers 318B-S and the power redistribution conductive layers 318B-P, the ends of the signal redistribution conductive layers 318B-S and 318B-P can be arranged along the second direction at each of the two side edges of the sub-molding layer 316 in the first direction. The ends of the signal redistribution conductive layers 318B-S can be exposed through openings in the second redistribution insulating layer 318C to form signal redistribution pads 318BP-S. The signal redistribution pads 318BP-S may include an inner signal redistribution pad 318BP-S1 and an outer signal redistribution pad 318BP-S2. On the other hand, the ends of the power redistribution conductive layers 318B-P can be exposed through openings in the second redistribution insulating layer 318C. Furthermore, a predetermined portion of the power redistribution conductive layer 319B-P located between the sub-semiconductor chip 314 and the ends can be exposed through openings in the second redistribution insulating layer 318C. The end of the power redistribution conductive layer 318B-P exposed through the second redistribution insulating layer 318C will be referred to as the second power redistribution pad 318BP-P2, and a predetermined portion of the power redistribution conductive layer 318B-P exposed through the second redistribution insulating layer 318C will be referred to as the first power redistribution pad 318BP-P1. That is, the first power redistribution pad 318BP-P1 can be configured to be closer to the sub-semiconductor chip 314 than the second power redistribution pad 318BP-P2. The first power redistribution pad 318BP-P1 and the second power redistribution pad 318BP-P2 will be referred to as power redistribution pad 318BP-P.

[0116] Capacitor 360 may be formed to be electrically connected to the power redistribution conductive layer 318B-P within the sub-molding layer 316. Capacitor 360 may include a first electrode 362, a second electrode 364, and a body portion therebetween (not shown). The first electrode 362 of capacitor 360 may be connected to a first power redistribution conductive layer 318B-P1 within the power redistribution conductive layer 318B-P to which a ground voltage is applied, and the second electrode 364 of capacitor 360 may be connected to a second power redistribution conductive layer 318B-P2 within the power redistribution conductive layer 318B-P to which a power supply voltage is applied. In this embodiment, each of the first electrode 362 and the second electrode 364 of capacitor 360 may be connected to a portion of the power redistribution conductive layer 318B-P between the first power redistribution pad 318BP-P1 and the side surface 314C of the sub-semiconductor chip 314. In this case, capacitor 360 may be disposed adjacent to the sub-semiconductor chip 314, thus more effectively preventing power shortages. However, this disclosure is not limited thereto, and the position of capacitor 360 can be modified in various ways, as long as capacitor 360 is connected to a portion of power redistribution conductive layer 318B-P. For example, capacitor 360 can be connected to the portion of power redistribution conductive layer 318B-P between the first power redistribution pad 318BP-P1 and the second power redistribution pad 318BP-P2.

[0117] Sub-interconnectors 319 may include signal sub-interconnectors 319-S that overlap and are connected to signal redistribution pads 318BP-S and power sub-interconnectors 319-P that overlap and are connected to power redistribution pads 318BP-P. Signal sub-interconnectors 319-S may include an internal signal sub-interconnector 319-S1 that overlaps and is connected to an internal signal redistribution pad 318BP-S1 and an external signal sub-interconnector 319-S2 that overlaps and is connected to an external signal redistribution pad 318BP-S2. Power sub-interconnectors 319-P may include a first power sub-interconnector 319-P1 that overlaps and is connected to a first power redistribution pad 318BP-P1 and a second power sub-interconnector 319-P2 that overlaps and is connected to a second power redistribution pad 318BP-P2.

[0118] Next, we will refer to Figures 13 to 15 Description includes Figure 11 and Figure 12 The semiconductor package of the 310.

[0119] Reference Figures 13 to 15 According to another embodiment of the present disclosure, a semiconductor package may include a substrate 300, a sub-semiconductor package 310 disposed on the substrate 300, and a first main chip stack 320 and a second main chip stack 330 disposed on the sub-semiconductor package 310.

[0120] The substrate 300 may have an upper surface 300A, a lower surface 300B configured to be opposite to the upper surface 300A, and a side surface connecting the upper surface 300A and the lower surface 300B.

[0121] Sub-semiconductor package 310, first main chip stack 320, and second main chip stack 330 can be disposed on the upper surface 300A of substrate 300. Specifically, sub-semiconductor package 310 can be mounted on substrate 300 such that the effective surface 314A of sub-semiconductor chip 314 and one surface 316A of sub-molding layer 316 face the upper surface 300A of substrate 300. That is, sub-semiconductor package 310 can be mounted on substrate 300 in a downward orientation. For ease of description, some components of sub-semiconductor package 310 not covered by first main chip stack 320 and second main chip stack 330 are described in detail below. Figure 13 The components are shown by dashed lines. Additionally, for ease of description, detailed components of the sub-semiconductor package 310 are shown in... Figure 14 The image is also shown by dashed lines. For reference, since the sub-semiconductor package 310 is mounted on the substrate 300 in a downward orientation, Figure 13 and Figure 14 The detailed left and right positions of the components in the 310 sub-semiconductor package. Figure 11 In contrast, the external connection terminal 340 for connecting the semiconductor package of this embodiment to external components may be provided on the lower surface 300B of the substrate 300.

[0122] Sub-substrate pads 302S, first main substrate pads 302M1, and second main substrate pads 302M2 can be disposed on the upper surface 300A of substrate 300. Sub-substrate pads 302S can be electrically connected to sub-semiconductor packages 310, first main substrate pads 302M1 can be electrically connected to first main chip stacks 320, and second main substrate pads 302M2 can be electrically connected to second main chip stacks 330. Lower surface substrate pads 304 for connection to external connection terminals 340 can be disposed on the lower surface 300B of substrate 300.

[0123] Sub-substrate pads 302S may overlap and connect with sub-interconnects 319. Sub-substrate pads 302S may include a power sub-substrate pad 302S-P connected to a power sub-interconnect 319-P and a signal sub-substrate pad 302S-S connected to a signal sub-interconnect 319-S. Power sub-substrate pads 302S-P may include a first power sub-substrate pad 302S-P1 connected to a first power sub-interconnect 319-P1 and a second power sub-substrate pad 302S-P2 connected to a second power sub-interconnect 319-P2. Signal sub-substrate pads 302S-S may include an internal signal sub-substrate pad 302S-S1 connected to an internal signal sub-interconnect 319-S1 and an external signal sub-substrate pad 302S-S2 connected to an external signal sub-interconnect 319-S2. Multiple first power sub-substrate pads 302S-P1 may be arranged to surround the sub-semiconductor chip 314 on the upper surface 300A of the substrate 300. Multiple signal sub-substrate pads 302S-S and multiple second power sub-substrate pads 302S-P2 may be arranged to overlap each of the two side edges of the sub-molding layer 316 in a first direction on the upper surface 300A of the substrate 300.

[0124] A first main substrate pad 302M1 can be connected to a first main interconnect 327 (described later), and a second main substrate pad 302M2 can be connected to a second main interconnect 337 (described later). A plurality of first main substrate pads 302M1 can be arranged along a second direction at a first side edge of the substrate 300 in a first direction. A plurality of second main substrate pads 302M2 can be arranged along a second direction at a second side edge of the substrate 300 in a first direction. The first main substrate pads 302M1 and the second main substrate pads 302M2 are exposed and not covered by the sub-semiconductor package 310. Furthermore, the first main substrate pads 302M1 and the second main substrate pads 302M2 are exposed and not covered by the first main chip stack 320 and the second main chip stack 330.

[0125] The first main substrate pad 302M1 may include: a first signal main substrate pad 302M1-S, which is used to exchange internal signals between the sub-semiconductor package 310 and the first main chip stack 320; and a first power main substrate pad 302M1-P, which is used to supply power to the first main chip stack 320. In this case, the first signal main substrate pad 302M1-S can be electrically connected to the internal signal sub-substrate pads 302S-S1 via interconnects CL formed in the substrate 300.

[0126] The second main substrate pad 302M2 may include: a second signal main substrate pad 302M2-S for exchanging internal signals between the sub-semiconductor package 310 and the second main chip stack 330; and a second power main substrate pad 302M2-P for supplying power to the second main chip stack 330. In this configuration, the second signal main substrate pad 302M2-S can be electrically connected to the internal signal sub-substrate pads 302S-S1 via interconnects CL formed in the substrate 300.

[0127] Since the detailed configuration of the sub-semiconductor package 310 has already been described, its detailed description will be omitted. The sub-semiconductor package 310 can be electrically connected to the substrate 300 via the sub-interconnect 319.

[0128] Specifically, the first power sub-interconnect 319-P1 can be connected to the first power sub-substrate pad 302S-P1, and the second power sub-interconnect 319-P2 can be connected to the second power sub-substrate pad 302S-P2. Therefore, an electrical path (i.e., a power supply path) can be formed through the sub-semiconductor chip 314, the power redistribution conductive layer 318B-P, the first power sub-interconnect 319-P1 and the second power sub-interconnect 319-P2, and the first power sub-substrate pad 302S-P1 and the second power sub-substrate pad 302S-P2. In this case, the first power sub-interconnect 319-P1 allows for the formation of a shorter power supply path. Furthermore, the first power sub-interconnect 319-P1 and the second power sub-interconnect 319-P2 allow for the formation of multiple power supply paths. Furthermore, by forming a capacitor 360 in the sub-molding layer 316, the capacitor 360 includes a first electrode 362 and a second electrode 364 respectively connected to the first power redistribution conductive layer 318B-P1 and the second power redistribution conductive layer 318B-P2, as well as a body portion (not shown) between the first electrode 362 and the second electrode 364, power supply to the sub-semiconductor chip 314 can be performed more stably. Although not shown, the first power sub-substrate pads 302S-P1 and the second power sub-substrate pads 302S-P2 can be electrically connected to external connection terminals 340 through circuitry and / or wiring structures within the substrate 300, thereby connecting to and being powered from external components (not shown).

[0129] Additionally, the external signal sub-interconnect 319-S2 can be connected to the external signal sub-substrate pads 302S-S2. Therefore, an electrical path (i.e., an external signal transmission path) can be formed through the sub-semiconductor chip 314, the signal redistribution conductive layer 318B-S, the external signal sub-interconnect 319-S2, and the external signal sub-substrate pads 302S-S2. Although not shown, the external signal sub-substrate pads 302S-S2 can be electrically connected to the external connection terminal 340 via circuitry and / or wiring structures within the substrate 300, thereby connecting to and exchanging signals with external components (not shown).

[0130] Furthermore, the internal signal sub-interconnect 319-S1 can be connected to the internal signal sub-substrate pads 302S-S1. The internal signal sub-substrate pads 302S-S1 can be connected to the first signal main substrate pads 302M1-S and the second signal main substrate pads 302M2-S via connection lines CL. Therefore, electrical connections can be made between each of the first main chip stack 320 and the second main chip stack 330 and the sub-semiconductor chip 314. The structure of the first main chip stack 320, the connection relationship between the substrate 300 and the first main chip stack 320, and the connection relationship between the sub-semiconductor package 310 and the first main chip stack 320 are substantially the same as in the above embodiments. Additionally, the structure of the second main chip stack 330, the connection relationship between the substrate 300 and the second main chip stack 330, and the connection relationship between the sub-semiconductor package 310 and the second main chip stack 330 are substantially the same as in the above embodiments. Reference numerals 324, 322, 325, 327, 327S, and 327P can represent the first main semiconductor chip, the first adhesive layer, the first chip pad, the first main interconnect, the first signal main interconnect, and the first power main interconnect, respectively. Additionally, reference numerals 334, 332, 335, 337, 337S, and 337P can represent the second main semiconductor chip, the second adhesive layer, the second chip pad, the second main interconnect, the second signal main interconnect, and the second power main interconnect, respectively.

[0131] The sub-semiconductor package 310, the first main chip stack 320, and the second main chip stack 330 may be covered by a molding layer 350 formed on the substrate 300.

[0132] In this embodiment, all the effects of the above-described embodiments can be ensured.

[0133] Furthermore, a current path can be formed from a power redistribution conductive layer 318B-P through the first power sub-interconnect 319-P1 and the second power sub-interconnect 319-P2. That is, multiple current paths and short current paths can be formed. As a result, the impedance and inductance of the power supply path can be reduced, thus facilitating power supply between the sub-semiconductor package 310 and the substrate 300.

[0134] In addition, the power redistribution conductive layer 318B-P disposed between the two signal redistribution conductive layers 318B-S can suppress interference between the two signal redistribution conductive layers 318B-S.

[0135] According to the above embodiments of this disclosure, a high-capacity and multifunctional semiconductor package can be realized by forming a main chip stack including one or more main semiconductor chips on the sub-semiconductor package, and it is convenient to supply power to the sub-semiconductor package.

[0136] Figure 16 A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment is shown. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 are capable of storing or retrieving stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiment.

[0137] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that, in response to a read / write request from the host 7830, stored data or stored data can be read.

[0138] Figure 17 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing a path for data movement.

[0139] In embodiments, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include one or more semiconductor packages according to embodiments of this disclosure. Input / output device 8712 may include at least one selected from keypads, keyboards, display devices, touchscreens, etc. Memory 8713 is a means for storing data. Memory 8713 may store data and / or commands, etc., to be executed by controller 8711.

[0140] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory may be installed in an information processing system such as a mobile terminal or desktop computer. Flash memory may constitute a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0141] The electronic system 8710 may also include an interface 8714 configured to transmit data to and receive data from a communication network. The interface 8714 may be wired or wireless. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0142] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logical system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0143] If electronic system 8710 represents a device capable of performing wireless communication, then electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0144] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made to these described embodiments without departing from the spirit and scope of this teaching as defined by the following claims.

[0145] Cross-reference to related applications

[0146] This application claims priority to Korean Patent Application No. 10-2020-0095876, filed on July 31, 2020, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor package comprising: substrate; Sub-semiconductor package, disposed on the substrate and comprising: A sub-semiconductor chip having chip pads on its effective surface facing the substrate; A sub-molding layer, the sub-molding layer surrounding a side surface of the sub-semiconductor chip and having a surface facing the substrate; and A redistribution conductive layer, the redistribution conductive layer being connected to the chip pads and extending on one surface of the sub-molding layer, wherein the redistribution conductive layer comprises: A signal redistribution conductive layer extending to the edge of the sub-molding layer and having signal redistribution pads at its ends; and A power redistribution conductive layer having a length shorter than that of the signal redistribution conductive layer, and having power redistribution pads at the ends of the power redistribution conductive layer; a signal sub-interconnect having an upper surface connected to the signal redistribution pads and a lower surface connected to the substrate. A power sub-interconnect having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate; A capacitor formed in the sub-molding layer and electrically connected to the sub-semiconductor chip via the power redistribution conductive layer, and the capacitor comprising: A first electrode having a lower surface connected to the power redistribution conductive layer; A second electrode, the second electrode having a lower surface connected to the power redistribution conductive layer; and The main body portion, located between the first electrode and the second electrode; and At least one main semiconductor chip, the at least one main semiconductor chip being formed on the sub-semiconductor package and electrically connected to the substrate. In this configuration, the capacitor is adjacent to the sub-semiconductor chip, compared to the power redistribution pad.

2. The semiconductor package according to claim 1, wherein, The power redistribution conductive layer includes: The first power redistribution conductive layer to which a ground voltage is applied; and The second power redistribution conductive layer is subjected to a power supply voltage. The first electrode is connected to the first power redistribution conductive layer, and The second electrode is connected to the second power redistribution conductive layer.

3. The semiconductor package of claim 1, wherein, Each of the first electrode and the second electrode is positioned between the power redistribution pad and the side surface of the sub-semiconductor chip.

4. The semiconductor package according to claim 2, wherein, At least one signal redistribution conductive layer is disposed between the first power redistribution conductive layer and the second power redistribution conductive layer, and The main body overlaps with the at least one signal redistribution conductive layer.

5. The semiconductor package of claim 2, wherein, The AC path passes through the first power redistribution conductive layer, the capacitor, and the second power redistribution conductive layer.

6. The semiconductor package of claim 1, wherein, The power supply path through the power redistribution conductive layer, the power sub-interconnector, and the substrate is shorter than the signal transmission path through the signal redistribution conductive layer, the signal sub-interconnector, and the substrate.

7. The semiconductor package of claim 1, wherein, Each of the signal sub-interconnectors and the power sub-interconnectors includes at least one of solder balls and metal bumps.

8. The semiconductor package of claim 1, further comprising a main interconnect for connecting the main semiconductor chip to the substrate, wherein, The signal sub-interconnect includes an internal signal sub-interconnect for exchanging signals between the main semiconductor chip and the sub-semiconductor chip. The main interconnect includes a signal main interconnect for exchanging the signals between the main semiconductor chip and the sub-semiconductor chip. The substrate includes internal signal sub-substrate pads connected to the internal signal sub-interconnectors and signal main substrate pads connected to the signal main interconnectors. The internal signal sub-substrate pads and the signal main substrate pads are connected to each other by connection lines formed in the substrate.

9. The semiconductor package of claim 1, further comprising a primary interconnect connecting the primary semiconductor die to the substrate, wherein, The main interconnect includes bonding leads.

10. The semiconductor package according to claim 1, wherein, The chip pads are disposed along a first side edge and a second side edge of the sub-semiconductor chip in a first direction, and also along a first side edge and a second side edge of the sub-semiconductor chip in a second direction, the second direction being perpendicular to the first direction. The signal redistribution pads include a plurality of signal redistribution pads disposed at the first side edge and the second side edge of the sub-molding layer in the first direction. The signal redistribution conductive layer includes multiple signal redistribution conductive layers. The signal redistribution conductive layer, connected to the chip pads disposed at the first side edge of the sub-semiconductor chip in the first direction and the first side edge in the second direction, extends toward the signal redistribution pads disposed at the first side edge of the sub-molding layer in the first direction, and The signal redistribution conductive layer, which is connected to the chip pads disposed at the second side edge of the sub-semiconductor chip in the first direction and at the second side edge in the second direction, extends toward the signal redistribution pads disposed at the second side edge of the sub-molding layer in the first direction.

11. The semiconductor package of claim 10, wherein, The signal redistribution conductive layer has a spiral shape centered on the sub-semiconductor chip.

12. The semiconductor package according to claim 1, wherein, The substrate includes substrate pads disposed at a first side edge and a second side edge in a first direction, and The main semiconductor chip includes: At least one first main semiconductor chip, the at least one first main semiconductor chip being connected via a first main interconnect to a substrate pad disposed at the first side edge of the substrate; and At least one second main semiconductor chip, the at least one second main semiconductor chip being connected to the substrate pad disposed at the second side edge of the substrate via a second main interconnect.

13. The semiconductor package according to claim 12, wherein, The first main semiconductor chip includes a plurality of first main semiconductor chips offset and stacked in a direction away from the first side edge of the substrate in the first direction, and The second main semiconductor chip includes a plurality of second main semiconductor chips offset and stacked in a direction away from the second side edge of the substrate in the first direction.

14. The semiconductor package according to claim 1, wherein, The main semiconductor chip includes a memory, and The sub-semiconductor chip includes a memory controller.

15. A semiconductor package comprising: substrate; Sub-semiconductor package, disposed on the substrate and comprising: A sub-semiconductor chip having chip pads on its effective surface facing the substrate; A sub-molding layer, the sub-molding layer surrounding a side surface of the sub-semiconductor chip and having a surface facing the substrate; and A signal redistribution conductive layer and a power redistribution conductive layer are connected to the chip pads and extend to the edge of the sub-molding layer on one surface of the sub-molding layer; A signal sub-interconnector having an upper surface connected to a signal redistribution pad formed at an end of the signal redistribution conductive layer and a lower surface connected to the substrate; A second power sub-interconnect has an upper surface connected to a second power redistribution pad and a lower surface connected to the substrate, wherein the second power redistribution pad is formed at the end of the power redistribution conductive layer. A first power sub-interconnect has an upper surface connected to a first power redistribution pad and a lower surface connected to the substrate, the first power redistribution pad being formed on a portion of the power redistribution conductive layer other than the ends of the power redistribution conductive layer. A capacitor formed in the sub-molding layer and electrically connected to the sub-semiconductor chip via the power redistribution conductive layer, and the capacitor comprising: A first electrode having a lower surface connected to the power redistribution conductive layer; A second electrode, the second electrode having a lower surface connected to the power redistribution conductive layer; and The main body portion, located between the first electrode and the second electrode; and At least one main semiconductor chip, the at least one main semiconductor chip being formed on the sub-semiconductor package and electrically connected to the substrate. In this configuration, the capacitor is adjacent to the sub-semiconductor chip, compared to the first power redistribution pad and the second power redistribution pad.

16. The semiconductor package of claim 15, wherein, The power supply path through the power redistribution conductive layer, the first power sub-interconnector, and the substrate is shorter than the signal transmission path through the signal redistribution conductive layer, the signal sub-interconnector, and the substrate.

17. The semiconductor package of claim 15, wherein, The first power supply path passes through the power redistribution conductive layer, the first power sub-interconnector, and the substrate, and The second power supply path passes through the power redistribution conductive layer, the second power sub-interconnector, and the substrate.

18. The semiconductor package of claim 15, wherein, Each of the signal sub-interconnect, the first power sub-interconnect, and the second power sub-interconnect includes at least one of solder balls and metal bumps.

19. The semiconductor package according to claim 15, wherein, The chip pads are disposed along a first side edge and a second side edge of the sub-semiconductor chip in a first direction, and also along a first side edge and a second side edge of the sub-semiconductor chip in a second direction, the second direction being perpendicular to the first direction. The signal redistribution conductive layer includes multiple signal redistribution conductive layers, and signal redistribution pads are formed at the ends of the multiple signal redistribution conductive layers. The power redistribution conductive layer includes multiple power redistribution conductive layers, and second power redistribution pads are formed at the ends of each of the multiple power redistribution conductive layers. The signal redistribution pad and the second power redistribution pad are disposed at the first side edge and the second side edge of the sub-molding layer in the first direction. The signal redistribution conductive layer and the power redistribution conductive layer, connected to the chip pads disposed at the first side edge in the first direction and the first side edge in the second direction of the sub-semiconductor chip, extend toward the signal redistribution pads and the second power redistribution pads disposed at the first side edge in the first direction of the sub-molding layer, and The signal redistribution conductive layer and the power redistribution conductive layer, which are connected to the chip pads disposed at the second side edge of the sub-semiconductor chip in the first direction and the second side edge in the second direction, extend toward the signal redistribution pads and the second power redistribution pads disposed at the second side edge of the sub-molding layer in the first direction.

20. The semiconductor package of claim 19, wherein, The signal redistribution conductive layer and the power redistribution conductive layer have a spiral shape centered on the sub-semiconductor chip.

21. The semiconductor package of claim 15, wherein, The power redistribution conductive layer is inserted between the two signal redistribution conductive layers.

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