Contact for semiconductor device and method for forming the same

Abstract

The present disclosure relates to contacts for semiconductor devices and methods of forming the same. Methods for forming contacts to source / drain regions and gate electrodes in low voltage devices and high voltage devices and devices formed by the methods are disclosed. In an embodiment, a device includes a first channel region adjacent a first source / drain region in a substrate, a first gate over the first channel region, a second channel region adjacent a second source / drain region in the substrate, a top surface of the second channel region being lower than a top surface of the first channel region, a second gate over the second channel region, an ILD over the first and second gates, a first contact extending through the ILD and coupled to the first source / drain region, and a second contact extending through the ILD, coupled to the second source / drain region, and having a width greater than a width of the first contact and a height greater than a height of the first contact.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to contacts of semiconductor devices and methods of forming the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric materials, conductive materials, and semiconductive materials over a semiconductor substrate and patterning the various material layers using photolithography to form electrical circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. SUMMARY

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first channel region adjacent to a first source / drain region in a semiconductor substrate; a first gate stack over the first channel region; a second channel region adjacent to a second source / drain region in the semiconductor substrate, wherein a top surface of the second channel region is disposed lower than a top surface of the first channel region; a second gate stack over the second channel region; an interlayer dielectric (ILD) over the first gate stack, the second gate stack, the first source / drain region, and the second source / drain region; a first source / drain contact extending through the ILD and electrically coupled to the first source / drain region, the first source / drain contact having a first width and a first height; and a second source / drain contact extending through the ILD and electrically coupled to the second source / drain region, the second source / drain contact having a second width greater than the first width and a second height greater than the first height.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first transistor, the first transistor comprising: a first gate stack over a semiconductor substrate, the first gate stack having a first height; a first source / drain region adjacent to the first gate stack; a first gate contact electrically coupled to the first gate stack, a top surface of the first gate contact having a first width; and a first source / drain contact electrically coupled to the first source / drain region, a top surface of the first source / drain contact having a second width greater than the first width; and a second transistor, the second transistor comprising: a second gate stack over a semiconductor substrate, the second gate stack having a second height less than the first height; a second source / drain region adjacent to the second gate stack; and a second source / drain contact electrically coupled to the second source / drain region, a top surface of the second source / drain contact having a third width less than the second width.

[0006] According to yet another embodiment of the present disclosure, a method of forming a semiconductor device is provided, comprising: forming a first transistor and a second transistor over a semiconductor substrate, the first transistor comprising a first gate stack and a first source / drain region adjacent to the first gate stack, the second transistor comprising a second gate stack and a second source / drain region adjacent to the second gate stack; forming an interlayer dielectric (ILD) over the first transistor and the second transistor; depositing a photoresist over the ILD; patterning the photoresist to form a patterned photoresist, the patterned photoresist comprising a first opening directly over the first source / drain region, a second opening directly over the second source / drain region, and a third opening directly over the first gate stack, the first opening having a first width, the second opening having a second width, the third opening having a third width, wherein the first width is greater than each of the second width and the third width; etching the ILD using the patterned photoresist as a mask; and forming a first contact electrically coupled to the first source / drain region, a second contact electrically coupled to the second source / drain region, and a third contact electrically coupled to the first gate stack, the first contact having a first height greater than each of a second height of the second contact and a third height of the third contact. BRIEF DESCRIPTION OF DRAWINGS

[0007] This disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B and Figure 21C These are cross-sectional and top views of intermediate stages in the fabrication of a field-effect transistor (FET) according to some embodiments.

[0009] Figure 21D Illustrations of the material properties of the contact element according to some embodiments are shown. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0012] Various embodiments provide methods for forming contacts for low-voltage semiconductor devices and high-voltage semiconductor devices, and semiconductor devices formed by the method. The method includes: forming a low-voltage semiconductor device in a first region of a substrate and forming a high-voltage semiconductor region in a second region of the substrate. The second region of the substrate is recessed below the first region of the substrate. A gate is formed in the first and second regions, wherein the height of the gate in the second region is greater than the height of the gate in the first region. One or more interlayer dielectrics are formed over the first and second regions. A patterned photoresist is formed over the interlayer dielectrics and used to form an opening that exposes a first source / drain region in the first region, a second source / drain region in the second region, and the gate in both regions.

[0013] The photoresist is patterned to include a first opening above a first source / drain region, a second opening above a second source / drain region, and a third opening above a gate. The second opening may have a width greater than the first and third openings, and the first opening may have a width equal to or greater than the third opening. As the opening width increases, the etching rate of the underlying interlayer dielectric can increase. As a result, openings of different widths can be used to expose the first source / drain region, the second source / drain region, and the gate at different heights without over-etching the first source / drain region, the second source / drain region, or the gate. This reduces device defects and improves device performance. Moreover, the masking step can be eliminated, thereby reducing costs.

[0014] Some embodiments discussed herein are presented in the context of planar FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are considered for use in FinFETs, nanostructures (e.g., nanosheets, nanowires, gate-all-around, etc.), non-field-effect transistors (NSFETs), and the like.

[0015] exist Figure 1A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is located on a substrate that is typically silicon or a glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0016] Substrate 50 has a low-voltage (LV) device region 100 and a high-voltage (HV) device region 200. The LV device region 100 is the region in which a low-voltage device (e.g., a low-voltage metal-oxide-semiconductor (MOS) device) is to be formed. The HV device region is the region in which a high-voltage device (e.g., a high-voltage MOS device) is to be formed. The LV device is configured to operate at an operating voltage and supply voltage lower than the corresponding operating voltage and supply voltage of the HV device. It should be understood that the concepts of HV and LV are relative to each other. The maximum voltage that an LV device can withstand without damage is lower than the maximum voltage that an HV device can withstand without damage. In some embodiments, the operating voltage and supply voltage of the HV device are between about 2.5V and about 15V, and the operating voltage and supply voltage of the LV device are between about 0.5V and about 1V. The LV device region 100 and the HV device region 200 can be physically separated (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the LV device region 100 and the HV device region 200.

[0017] Further in Figure 1In this process, a pad layer 52 and a mask layer 54 are formed on a substrate 50. The pad layer 52 may comprise a thin film of silicon oxide or the like, which may be formed using a thermal oxidation process or the like. In some embodiments, the pad layer 52 may comprise silicon nitride, silicon oxynitride, combinations thereof, or multiple layers thereof. The pad layer 52 may act as an adhesion layer between the substrate 50 and the mask layer 54. The pad layer 52 may also act as an etch stop layer for etching the mask layer 54. In some embodiments, the mask layer 54 is formed of a material such as silicon nitride. In some embodiments, the mask layer 54 may comprise silicon oxynitride, polysilicon, combinations thereof, or multiple layers thereof. The mask layer 54 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The mask layer 54 may be used as a hard mask during subsequent photolithography processes.

[0018] exist Figure 2 In this process, mask layer 54, pad layer 52, and substrate 50 are etched to form trench 56. A first patterned mask (not shown separately), such as a patterned photoresist, can be formed on mask layer 54. The first patterned mask can be formed by depositing a first photosensitive layer on mask layer 54 using spin coating or the like. The first photosensitive layer can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions of the first photosensitive layer, thereby forming a patterned mask. Mask layer 54, pad layer 52, and substrate 50 can be etched using a suitable etching process (e.g., reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof) to transfer the pattern of the first patterned mask to mask layer 54, pad layer 52, and substrate 50, thereby forming trench 56. In some embodiments, the etching process can be anisotropic. The first patterned mask can then be removed using any acceptable process (e.g., ashing, stripping, or a combination thereof).

[0019] exist Figure 3Shallow trench isolation (STI) regions 58 are formed in trenches 56 adjacent to mask layer 54, pad layer 52, and substrate 50. STI regions 58 can be formed by forming an insulating material (not shown separately) that fills trench 56 and extends along the top and side surfaces of substrate 50, side surfaces of pad layer 52, and top and side surfaces of mask layer 54. The insulating material can be an oxide, such as silicon dioxide, nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowing CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, where post-curing transforms the deposited material into another material (e.g., an oxide)), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon dioxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed such that excess insulating material covers mask layer 54. The insulating material can comprise a single layer or can utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, the padding layer 52, and the mask layer 54. A filler material, such as that described above, may then be formed on top of the liner.

[0020] A removal process is then applied to the insulating material to remove excess insulating material above the mask layer 54. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., may be utilized. The removal process can planarize the insulating material and the mask layer 54, thereby forming the STI region 58. The removal process exposes the mask layer 54 such that, after the planarization process is complete, the top surfaces of the mask layer 54 and the STI region 58 are horizontal.

[0021] exist Figure 4In this process, a second patterned mask 60 is formed over the LV device region 100 and the STI region 58, and the mask layer 54, the pad layer 52, and the substrate 50 are etched in the HV device region 200. The second patterned mask 60 can be a patterned photoresist. The second patterned mask 60 can be formed by depositing a second photosensitive layer over the mask layer 54 and the STI region 58 using spin coating or the like. The second photosensitive layer can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions, thereby forming the second patterned mask 60 covering the LV device region 100 and exposing the HV device region 200. The mask layer 54, the pad layer 52, the substrate 50, and the STI region 58 in the HV device region 200 can then be etched using a suitable etching process. The etching process can be a wet etching process, a dry etching process, etc. In some embodiments, the etching process may be reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. In some embodiments, the etching process may be anisotropic. In some embodiments, the mask layer 54, the pad layer 52, and the substrate 50 may be etched separately from the STI region 58. The mask layer 54, the pad layer 52, and the substrate 50 may be etched before or after etching the STI region 58.

[0022] like Figure 4 As shown, in a direction perpendicular to the main surface of the substrate 50, the top surfaces of the mask layer 54 and STI region 58 in the LV device region 100 can be configured to be higher than the top surfaces of the substrate 50 and STI region 58 in the HV device region 200. The top surfaces of the mask layer 54 and STI region 58 in the LV device region 100 can be configured to be approximately 50 nm to approximately 350 nm higher than the top surfaces of the substrate 50 and STI region 58 in the HV device region 200 by a height H1. The height of the gate structure subsequently formed in the HV device region 200 can be higher than the height of the gate structure subsequently formed in the LV device region 100. Recessing the substrate 50 and STI region 58 in the HV device region 200 allows the gate structures subsequently formed in the LV device region 100 and the HV device region 200 to be formed simultaneously.

[0023] exist Figure 5In this process, a second patterned mask 60, a mask layer 54, and a pad layer 52 are removed from the LV device region 100. The second patterned mask 60 can be removed by any acceptable process (e.g., ashing, stripping, or a combination thereof). In embodiments where the mask layer 54 comprises silicon nitride and the pad layer 52 comprises silicon oxide, the mask layer 54 can be removed by a wet cleaning process using phosphoric acid (H3PO4) or the like, and the pad layer 52 can be removed by a wet etching process using dilute hydrofluoric acid (dHF) or the like. The STI region 58 may also be recessed such that the top surface of the STI region 58 is substantially coplanar with the top surface of the substrate 50. In some embodiments, a planarization process, such as a CMP process, can be performed to make the top surface of the STI region 58 in the LV device region 100 flush with the top surface of the substrate 50. In some embodiments, when a planarization process is performed on the LV device region 100, the HV device region 200 can be masked.

[0024] exist Figure 6 In this embodiment, a first well 62 is formed in the substrate 50 of the LV device region 100, and a second well 64 is formed in the substrate 50 of the HV device region 200. The first well 62 and the second well 64 may be doped with the same or different dopants, and the first well 62 and the second well 64 may be doped with the same or different dopant concentrations. Furthermore, either the first well 62 or the second well 64 may be implanted with an n-type or p-type dopant. In embodiments with different dopants or dopant concentrations, different implantation steps for the LV device region 100 and the HV device region 200 may be implemented using photoresist or other masks (not shown separately). For example, photoresist may be formed on the substrate 50 and the STI region 58 in the LV device region 100. The photoresist is patterned to expose the HV device region 200 of the substrate 50. The photoresist can be formed using spin coating techniques, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, impurity implantation is performed in the HV device region 200, and the photoresist can be used as a mask to prevent impurities from being implanted into the LV device region 100. Impurities can be phosphorus, arsenic, antimony, boron, boron fluoride, indium, etc., implanted into this region, with a concentration equal to or less than 1 × 10⁻⁶. 18 atoms per cubic centimeter, for example, between approximately 1 × 10⁻⁶ 16 atoms per cubic centimeter and approximately 1 × 10 18 Between atoms per cubic centimeter. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0025] After implantation into the HV device region 200, a photoresist is formed on the substrate 50 and STI region 58 within the HV device region 200. The photoresist is patterned to expose the LV device region 100 of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, impurity implantation can be performed in the LV device region 100, and the photoresist can be used as a mask to prevent impurities from being implanted into the HV device region 200. p-type impurities can be phosphorus, arsenic, antimony, boron, boron fluoride, indium, etc., implanted into the region, with a concentration equal to or less than 1 x 10⁻⁶. 18 Atoms per cubic centimeter, for example, between approximately 1 x 103 16 atoms per cubic centimeter and approximately 1 x 103 18 Between atoms per cubic centimeter. After implantation, the photoresist can be removed, for example, by an acceptable ashing process. After implantation in the LV device region 100 and the HV device region 200, annealing can be performed to repair implantation damage and activate the implanted impurities. The bottom surfaces of the first well 62 and the second well 64 are shown as being below and extending below the bottom surface of the STI region 58. In some embodiments, the first well 62 and the second well 64 do not extend below the STI region 58. In some embodiments, the bottom surface of the STI region 58 is below the bottom surface of the first well 62 and / or the second well 64.

[0026] exist Figure 7 In this configuration, a first gate dielectric layer 66 is formed over the STI region 58, the first well 62, and the second well 64. The first gate dielectric layer 66 can be a dielectric material, which may include: oxides, such as silicon oxide; nitrides, such as silicon nitride; composite structures, such as oxide / nitride / oxide; combinations or multiple layers thereof; and so on. The first gate dielectric layer 66 can be formed by deposition processes such as CVD, ALD, etc. In some embodiments, the first gate dielectric layer 66 forms the gate oxide for a subsequently formed high-voltage transistor. The first gate dielectric layer 66 may have a thickness between about 10 nm and about 100 nm.

[0027] exist Figure 8 In this process, the first gate dielectric layer 66 is removed from the LV device region 100. The first gate dielectric layer 66 can be removed using acceptable photolithography and etching processes. Figure 8As shown, the top surface of the first gate dielectric layer 66 in the HV device region 200 may be coplanar with the top surfaces of the first well 62 and the STI region 58 in the LV device region 100. After removing the first gate dielectric layer 66 from the LV device region 100, the top surfaces of the first well 62 and the STI region 58 may be exposed. In some embodiments, the top surface of the first gate dielectric layer 66 in the HV device region 200 may be higher or lower than the top surfaces of the first well 62 and the STI region 58 in the LV device region 100.

[0028] exist Figure 9 In this process, a second gate dielectric layer 70 is formed over the STI region 58, the first well 62, and the first gate dielectric layer 66. The second gate dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A gate layer 72 is formed over the second gate dielectric layer 70, and a mask layer 74 is formed over the gate layer 72. The gate layer 72 can be deposited over the second gate dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited over the gate layer 72. The gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. Gate layer 72 may be made of other materials that have high etch selectivity for etching isolation regions (e.g., STI region 58, first gate dielectric layer 66, and / or second gate dielectric layer 70). Mask layer 74 may comprise one or more layers of materials such as silicon nitride, silicon oxynitride, etc. Figure 9 In the illustrated embodiment, a single gate layer 72 and a single mask layer 74 are formed across the LV device region 100 and the HV device region 200. Note that, for illustrative purposes, the second gate dielectric layer 70 is shown covering the first well 62 and the STI region 58. In some embodiments, the second gate dielectric layer 70 may be deposited such that it covers only the first well 62 and the first gate dielectric layer 66.

[0029] exist Figure 10 In this process, acceptable photolithography and etching techniques can be used to mask layer 74 (see...). Figure 7The mask 86 is patterned to form a mask 86. The pattern of the mask 86 can then be transferred to the gate layer 72 to form a gate 84. In some embodiments, the pattern of the mask 86 can also be transferred to the second gate dielectric layer 70 in the LV device region 100 and the HV device region 200 to form a second gate dielectric 82, and can be transferred to the first gate dielectric layer 66 in the HV device region 200 to form a first gate dielectric 80. The pattern of the mask 86 can be transferred using acceptable etching techniques. The gate 84 covers the corresponding channel regions 87 of the first well 62 and the second well 64. The pattern of the mask 86 separates each gate 84 from the adjacent gate entity.

[0030] After patterning the mask layer 74, gate layer 72, second gate dielectric layer 70, and first gate dielectric layer 66 to form mask 86, gate 84, second gate dielectric 82, and first gate dielectric 80, implantation can be performed for the lightly doped source / drain (LDD) regions (not shown separately). In embodiments where LV device region 100 and HV device region 200 have different device types, similar to the above... Figure 6 The implantation discussed earlier can involve forming a mask, such as a photoresist, over the HV device region 200 while exposing the LV device region 100, and implanting an impurity of an appropriate type (e.g., n-type or p-type) into the exposed first well 62 in the LV device region 100. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the LV device region 100 while exposing the HV device region 200, and implanting an impurity of an appropriate type (e.g., n-type or p-type) into the exposed second well 64 in the HV device region 200. The mask can then be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. The lightly doped source / drain regions can have approximately 10 15 atoms / cubic centimeter to approximately 10 19 Impurity concentration in atoms per cubic centimeter. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0031] Note that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be utilized. In some embodiments, gate sealing spacers (not shown separately) can be formed along the sidewalls of mask 86, gate 84, second gate dielectric 82, and first gate dielectric 80, and LDD regions can be formed after the formation of the gate sealing spacers. Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, LDD regions for n-type devices can be formed before the formation of the gate sealing spacers, while LDD regions for p-type devices can be formed after the formation of the gate sealing spacers.

[0032] exist Figure 11 In this configuration, a gate spacer 88 is formed along the sidewalls of a mask 86, a gate 84, a second gate dielectric 82, and a first gate dielectric 80. The gate spacer 88 can be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacer 88 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0033] exist Figure 12 In the first well 62 and the second well 64, source / drain regions 90A and 90B are formed, respectively. The source / drain regions 90A and 90B can be formed by implantation, etching, subsequent epitaxial growth, etc. The source / drain region 90A is formed in the first well 62 such that the gate 84 in the LV device region 100 is located between corresponding adjacent pairs of source / drain regions 90A. Similarly, the source / drain region 90B is formed in the second well 64 such that the gate 84 in the HV device region 200 is located between corresponding adjacent pairs of source / drain regions 90B. In some embodiments, a gate spacer 88 is used to separate the source / drain regions 90A and 90B from the gate 84 by an appropriate lateral distance so that the source / drain regions 90A and 90B do not short-circuit the subsequently formed gate of the resulting FET.

[0034] In embodiments where source / drain regions 90A and 90B are formed via epitaxial growth, source / drain region 90A in LV device region 100 can be formed by masking HV device region 200 and etching the source / drain region of first well 62 in LV device region 100 to form a recess in first well 62. Then, source / drain region 90A in LV device region 100 is epitaxially grown in the recess. Source / drain region 90A can comprise any acceptable material, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The material of source / drain region 90A can be selected to apply stress in the corresponding channel region 87, thereby improving performance. In some embodiments, source / drain region 90A in LV device region 100 can have a surface raised from the corresponding surface of first well 62 and can have a facet.

[0035] The source / drain region 90B in the HV device region 200 can be formed by masking the LV device region 100 and etching the source / drain region of the second well 64 in the HV device region 200 to form a recess in the second well 64. Then, the source / drain region 90B in the HV device region 200 is epitaxially grown in the recess. The source / drain region 90B can comprise any acceptable material, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The material of the source / drain region 90B can be selected to apply stress in the corresponding channel region 87, thereby improving performance. In some embodiments, the source / drain region 90B in the HV device region 200 can have a surface raised from the corresponding surface of the second well 64 and can have a facet.

[0036] In embodiments where source / drain regions 90A and 90B are formed by implantation or epitaxial growth, dopant can be implanted into source / drain regions 90A and 90B, the first well 62, and / or the second well 64 to form the source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. Source / drain regions 90A and 90B can have approximately 10-1 19 atoms / cubic centimeter to approximately 10 21 Impurity concentration in atoms per cubic centimeter. The n-type and / or p-type impurities in the source / drain regions 90A and 90B can be any of the impurities discussed previously. In some embodiments, the source / drain regions 90A and 90B can be doped in situ during growth.

[0037] Further in Figure 12 In the LV device region 100 and HV device region 200, silicide regions 90A and 90B are formed, respectively. The silicide regions 92A and 92B can be formed by: forming a metal layer (not shown separately) over the source / drain regions 90A and 90B, performing annealing to form the silicide regions 92A and 92B, and removing unreacted portions of the metal layer.

[0038] exist Figure 13In this process, mask 86 is removed and gate spacer 88 is etched. In some embodiments, a planarization process such as CMP may be performed to make the top surface of gate 84 flush with the top surface of gate spacer 88. In some embodiments, mask 86 may be removed and gate spacer 88 may be etched by one or more suitable etching processes, which may be isotropic or anisotropic. In some embodiments, mask 86 and gate spacer 88 may be etched by a dry etching process that has high etch selectivity for the materials of mask 86 and gate spacer 88 (relative to the materials of gate 84, STI region 58, and silicide regions 92A and 92B). The top surface of gate spacer 88 may be higher or lower than the top surface of gate 84. Etching mask 86 and gate spacer 88 can reduce the aspect ratio (e.g., height-to-width ratio) of the opening between adjacent gate stacks, which facilitates subsequent deposition of interlayer dielectrics (e.g., referred to below). Figure 14 The first interlayer dielectric (96) is discussed. This can reduce device defects and improve device performance.

[0039] exist Figure 14 In the middle, the first interlayer dielectric (ILD) 96 is deposited in Figure 13 The structure shown is above the first ILD 96. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is located between the first ILD 96 and the silicide regions 92A and 92B, the STI region 58, the gate spacer 88, and the gate 84. The CESL 94 may include a dielectric material whose etch rate is lower than that of the material overlying the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0040] exist Figure 15 In this process, a planarization process such as CMP is performed to make the top surface of the first ILD 96 flush with the top surface of the gate 84. After the planarization process, the top surfaces of the gate 84, gate spacer 88, first ILD 96, and CESL 94 are flush. Therefore, the top surface of the gate 84 is exposed through the first ILD 96 and CESL 94.

[0041] exist Figure 16In this process, the gate 84 is removed by an appropriate etching process to form a recess 102. A portion of the second gate dielectric 82 within the recess 102 may also be removed. In some embodiments, only the gate 84 is removed, while the second gate dielectric 82 remains and is exposed through the recess 102. The first gate dielectric 80 in the HV device region 200 may remain relatively unetched. In some embodiments, the gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the gate 84, with little or no etching of the first ILD 96, gate spacer 88, or CESL 94. The recess 102 in the LV device region 100 exposes and / or covers the channel region 87 of the first well 62. The recess 102 in the HV device region 200 exposes and / or covers the first gate dielectric 80. During removal, the second gate dielectric 82 may be used as an etch stop layer when etching the gate 84. Then, after removing the gate 84, the second gate dielectric 82 can optionally be removed.

[0042] exist Figure 17 In this process, a gate dielectric layer 104 and a gate electrode 106 are formed to replace the gate. The gate dielectric layer 104 may include one or more layers deposited in the recess 102, such as on the top surface of the first well 62, the top surface of the first gate dielectric 80, and the sidewalls of the gate spacer 88. The gate dielectric layer 104 may also be formed extending along the top surface of the first ILD 96, CESL 94, and the gate spacer 88. In some embodiments, the gate dielectric layer 104 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 104 includes an interface layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide, or a silicate of tellurium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 104 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric layer 104 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the second gate dielectric 82 is retained in the recess 102, the gate dielectric layer 104 may include the material of the second gate dielectric 82 (e.g., SiO2).

[0043] Gate electrode 106 is deposited on top of gate dielectric layer 104 and fills the remainder of recess 102. Gate electrode 106 may comprise a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although in Figure 17A single-layer gate electrode 106 is shown, but the gate electrode 106 may include any number of liner layers, any number of work function adjustment layers, and filler material. After filling the recess 102, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 104 and the gate electrode 106 above the top surface of the first ILD 96. The remaining portions of the gate electrode 106 and the gate dielectric layer 104 form the replacement gate of the resulting FET. The gate electrode 106 and the gate dielectric layer 104 in the LV device region 100 and the gate electrode 106, the gate dielectric layer 104, and the first gate dielectric 80 in the HV device region 200 can be collectively referred to as the “gate stack”. The gate stack may extend along the top surface of the channel region 87 of the first well 62 and the second well 64.

[0044] The formation of the gate dielectric layer 104 in the LV device region 100 and the HV device region 200 can occur simultaneously, such that the gate dielectric layer 104 in each region is formed of the same material, and the formation of the gate electrode 106 can occur simultaneously, such that the gate electrode 106 in each region is formed of the same material. In some embodiments, the gate dielectric layer 104 in each region can be formed using different processes so that the gate dielectric layer 104 can be made of different materials, and / or the gate electrode 106 in each region can be formed using different processes so that the gate electrode 106 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0045] exist Figure 18 In this process, a gate mask 110 is formed over the gate stack. The gate mask 110 may be located between opposing portions of the gate spacers 88. In some embodiments, forming the gate mask 110 includes recessing the gate dielectric layer 104 and the gate electrode 106 of the gate stack such that a recess is formed directly over the remainder of the gate stack and between opposing portions of the gate spacers 88. The recess is then filled with the gate mask 110 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), and excess portions of the dielectric material extending over the first ILD 96 are subsequently removed by a planarization process.

[0046] Further in Figure 18 In this process, the second ILD 108 is deposited on the first ILD 96. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc. The gate contacts subsequently formed (e.g., as described below) Figures 21A to 21CThe gate contact 130 discussed can penetrate the second ILD 108 and the gate mask 110 to contact the top surface of the recessed gate electrode 106.

[0047] exist Figures 19A to 19C In the process, a patterned photoresist 112, including openings 114, 116 and 118, is formed on the second ILD 108. Figure 19C A top view is shown, and further details are provided. Figure 19A and Figure 19B The reference cross section used is shown. Cross section A-A' extends through openings 114 and 116 in a direction perpendicular to the longitudinal axis of the gate stack, and is shown along cross section A-A'. Figures 1 to 19A , Figure 20A and Figure 21A The cross-sectional view shown. Cross-section B-B' is parallel to cross-section A-A' and extends through opening 118, and is shown along cross-section B-B'. Figure 19B , Figure 20B and Figure 21B The cross-sectional view shown. Figure 19B As shown, the gate stack can extend over the side surfaces of the first well 62 and the second well 64 above the STI region 58.

[0048] A patterned photoresist 112 can be formed by depositing a photosensitive layer on the second ILD 108 using methods such as spin coating. The photosensitive layer can then be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove exposed or unexposed portions, thereby forming the patterned photoresist 112. Openings 114, 116, and 118 exposing the second ILD 108 are formed to extend through the patterned photoresist 112. The pattern of the patterned photoresist 112 corresponds to contacts to be formed in the second ILD 108, the first ILD 96, CESL 94, and the gate mask 110, as will be discussed below. Figures 21A to 21C The subject of discussion.

[0049] Figure 19D and Figure 19E The etch loading effect is shown, which can then be used to etch the second ILD 108, the first ILD 96, CESL 94, and the gate mask 110 using a patterned photoresist 112 as a mask without over-etching and damaging the silicide region 92A, the source / drain region 90A, and the gate electrode 106. Figure 19DIn this embodiment, a substrate 202 is provided, and a patterned photoresist 204 including openings 206 is formed on the substrate 202. The material of the substrate 202 may be the same as or similar to the material of the second ILD 108, the first ILD 96, and / or the gate mask 110. In some embodiments, the substrate 202 may be formed of an oxide such as silicon oxide. The patterned photoresist 204 may be formed of the same or similar material or process as the patterned photoresist 112. Figure 19E In this process, a patterned photoresist 204 is used as a mask, while the opening 206 extends into the substrate 202. For example... Figure 19E As shown, as the width of the openings 206 in the patterned photoresist 204 increases, the depth to which the openings 206 extend into the substrate 202 increases. For example, the ratio of the width of each opening 206 to its corresponding depth can be from about 0.02 to about 1. For openings 114, 116, and 118, the widths of openings 114, 116, and 118 can be selected to control the openings patterned through them (e.g., as described below regarding...). Figures 20A to 20C The depths of the openings 120, 122, and 124 discussed are used to prevent over-etching of the silicide region 92A, the source / drain region 90A, and the gate electrode 106.

[0050] return Figures 19A to 19C Opening 114 can be formed to have a width W1, opening 116 can be formed to have a width W2, and opening 118 can be formed to have a width W3. Width W2 can be greater than both width W1 and width W3. In some embodiments, the ratio of width W2 to width W1 can be in the range of about 1.5 to about 50 or about 1.5 to about 15, and the ratio of width W2 to width W3 can be in the range of about 1.5 to about 50 or about 1.5 to about 15. In some embodiments, width W1 can be equal to or greater than width W3. In some embodiments, width W1 can be in the range of about 10 nm to about 100 nm, width W2 can be in the range of about 15 nm to about 500 nm, and width W3 can be in the range of about 10 nm to about 100 nm. As will be discussed below regarding... Figures 20A to 20CIn more detail, the patterned photoresist 112 can be used as a mask to extend openings 114, 116, and 118 to expose silicide region 92A, silicide region 92B, and gate electrode 106, respectively. Providing openings 114, 116, and 118 with specified widths and relationships allows control over the depth to which they extend, preventing over-etching of silicide region 92A, source / drain region 90A, and gate electrode 106 while allowing exposure of silicide region 92B. Providing opening 116 with a width W2 greater than the specified value results in undesirable area loss, requiring the formation of larger source / drain regions 90B and silicide regions 92B, which reduces device density. Providing opening 116 with a width W2 less than the specified value may be insufficient to prevent over-etching of silicide region 92A, source / drain region 90A, and gate electrode 106, and may lead to degraded device performance.

[0051] exist Figures 20A to 20C In this process, a patterned photoresist 112 is used as a mask to etch the second ILD 108, the first ILD 96, CESL 94, and the gate mask 110, thereby extending openings 114, 116, and 118 to form openings 120, 122, and 124, respectively. Opening 120 can be etched through the second ILD 108, the first ILD 96, and CESL 94 in the LV device region 100, exposing the silicide region 92A. Opening 122 can be etched through the second ILD 108, the first ILD 96, and CESL 94 in the HV device region 200, exposing the silicide region 92B. Opening 124 can be etched through the second ILD 108 and the gate mask 110 in both the LV device region 100 and the HV device region 200, exposing the gate electrode 106 in both the LV device region 100 and the HV device region 200. ILD 108, first ILD 96, CESL 94, and gate mask 110 can be etched using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching process can be anisotropic.

[0052] Openings 120, 122, and 124 can be etched simultaneously. Because openings 114, 116, and 118 are formed in patterned photoresist 112 with defined widths W1, W2, and W3, respectively, openings 120, 122, and 124 can be etched simultaneously and can extend to different depths. This allows each of the silicide region 92A, silicide region 92B, and gate electrode 106 to be exposed without over-etching silicide region 92A and gate electrode 106. This improves device performance and reduces device defects. Furthermore, no additional masking process is required to form openings 120, 122, and 124 with different heights. This reduces costs.

[0053] Opening 120 may have a top width W1 flush with the top surface of the second ILD 108, which is equal to the width W1 of opening 114 in the patterned photoresist 112. Opening 120 may have a height H2 in the range of about 50 nm to about 1000 nm, and a bottom width W1' flush with the bottom surface of CESL 94 in the range of about 10 nm to about 100 nm. Opening 122 may have a top width W2 flush with the top surface of the second ILD 108, which is equal to the width W2 of opening 116 in the patterned photoresist 112. Opening 122 may have a height H3 in the range of about 100 nm to about 1,500 nm, and a bottom width W2' flush with the bottom surface of CESL 94 in the range of about 15 nm to about 500 nm. Opening 124 may have a top width W3 flush with the top surface of the second ILD 108, which is equal to the width W3 of opening 118 in the patterned photoresist 112. Opening 124 may have a height H4 in the range of about 50 nm to about 1000 nm, and a bottom width W3' flush with the bottom surface of the gate mask 110 in the range of about 10 nm to about 100 nm. Height H3 may be greater than height H2, and height H2 may be greater than height H4. In some embodiments, the ratio of height H3 to height H2 (H3 / H2) may be in the range of about 1.5 to about 50, and the ratio of height H3 to height H4 (H3 / H4) may be in the range of about 1.5 to about 50. In some embodiments, width W2' may be equal to or greater than width W1'. Forming an opening 122 with a width W2' greater than width W1' can reduce the contact resistance of contacts subsequently formed in the opening 122, which can improve device performance.

[0054] exist Figures 21A to 21C In this process, the patterned photoresist 112 is removed, and LV contact 126, HV contact 128 and gate contact 130 are formed in openings 120, 122 and 124, respectively. Figure 21CA top view is shown, in which the second ILD 108 and the first ILD 96 have been removed to reveal the underlying structure. The patterned photoresist 112 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. The LV contacts 126, HV contacts 128, and gate contacts 130 are formed by depositing a liner (not shown separately) such as a diffusion barrier layer, adhesion layer, etc., in the openings 120, 122, and 124, and depositing a conductive material on the liner to fill the openings 120, 122, and 124. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form the LV contacts 126, HV contacts 128, and gate contacts 130. LV contact 126 is physically and electrically coupled to source / drain region 90A via silicide region 92A. HV contact 128 is physically and electrically coupled to source / drain region 90B via silicide region 92B. Gate contact 130 is physically and electrically coupled to gate electrode 106. LV contact 126, HV contact 128, and gate contact 130 can be formed using different processes or the same process.

[0055] The LV contact 126, HV contact 128, and gate contact 130 may have the same dimensions as the openings 120, 122, and 124, respectively. For example, the LV contact 126 may have a width W1, a width W1', and a height H2; the HV contact 128 may have a width W2, a width W2', and a height H3; and the gate contact 130 may have a width W3, a width W3', and a height H4. The width W3 and height H4 of the gate contact 130 may be the same in both the LV device region 100 and the HV device region 200. The ratio of width W1 to height H2 may be in the range of about 0.01 to about 0.2; the ratio of width W2 to height H3 may be in the range of about 0.01 to about 0.2; and the ratio of width W3 to height H4 may be in the range of about 0.01 to about 0.2.

[0056] Figure 21D The cumulative probability as a function of the contact resistance (Rc) between the HV contact 128 and the silicide region 92B is shown. Line 300 shows an embodiment where the HV contact 128 is formed to have a wider width than the LV contact 126. Line 302 shows an embodiment where the HV contact 128 is formed to have a width equal to that of the LV contact 126. Figure 21DAs shown, providing an HV contact 128 with a wider width reduces the contact resistance of the HV contact 128 and reduces the variation in contact resistance. Specifically, the contact resistance of the embodiment shown by line 300 is 15% or more smaller than that of the embodiment shown by line 302. This improves device performance and reduces device defects.

[0057] The embodiments can achieve various advantages. For example, forming openings 114, 116, and 118 of different widths in the patterned photoresist 112 allows openings 120, 122, and 124 to be formed simultaneously without over-etching the silicide region 92A, the source / drain region 90A, and the gate electrode 106 located above the silicide region 92B. This prevents device defects, improves device performance, and reduces the number of masks required to pattern the openings 120, 122, and 124, thereby reducing costs. Furthermore, the HV contact 128 can be formed with a larger width, which reduces contact resistance and further improves device performance.

[0058] The disclosed planar FET embodiments can also be applied to fin-type devices, such as fin field-effect transistors (FinFETs); nanostructure devices, such as nanostructures (e.g., nanosheets, nanowires, gate-all-around, etc.), field-effect transistors (NSFETs), etc. In NSFET embodiments, the fins are replaced by nanostructures formed by patterning an alternating stack of channel and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to those described in the embodiments above. After removing the dummy gate stacks, the sacrificial layer can be partially or completely removed in the channel region. Replacement gate structures are formed in a manner similar to those described in the embodiments above, and the replacement gate structures can partially or completely fill the openings left by removing the sacrificial layer, and can partially or completely surround the channel layer in the channel region of the NSFET device. Contacts and ILDs for the replacement gate structures and source / drain regions can be formed in a manner similar to those described in the embodiments above. A nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0059] According to an embodiment, a semiconductor device includes: a first channel region adjacent to a first source / drain region in a semiconductor substrate; a first gate stack above the first channel region; a second channel region adjacent to a second source / drain region in the semiconductor substrate, the top surface of the second channel region being configured to be lower than the top surface of the first channel region; a second gate stack above the second channel region; an interlayer dielectric (ILD) above the first gate stack, the second gate stack, the first source / drain region, and the second source / drain region; a first source / drain contact extending through the ILD and electrically coupled to the first source / drain region, the first source / drain contact having a first width and a first height; and a second source / drain contact extending through the ILD and electrically coupled to the second source / drain region, the second source / drain contact having a second width greater than the first width and a second height greater than the first height. In an embodiment, the semiconductor device further includes: a first gate contact electrically coupled to a first gate stack; and a second gate contact electrically coupled to a second gate stack. The first gate contact has a third width and a third height, and the second gate contact has a fourth width equal to the third width and a fourth height equal to the third height. In an embodiment, the second width is greater than each of the third width and the fourth width, and the second height is greater than each of the third height and the fourth height. In an embodiment, the top surfaces of the first source / drain contact, the second source / drain contact, the first gate contact, and the second gate contact are flush with each other. The bottom surface of the second source / drain contact is configured to be lower than the bottom surface of the first source / drain contact, and the bottom surface of the first source / drain contact is configured to be lower than the bottom surfaces of the first gate contact and the second gate contact. The bottom surfaces of the first source / drain contact and the first source / drain contact are located below the bottom surfaces of the first gate contact and the second gate contact. In an embodiment, the first width is equal to each of the third width and the fourth width. In one embodiment, the first height is greater than each of the third and fourth heights. In another embodiment, the ratio of the second width to the first width is between 1.5 and 50.

[0060] According to another embodiment, a semiconductor device includes: a first transistor, the first transistor including: a first gate stack stacked on a semiconductor substrate, the first gate stack having a first height; a first source / drain region adjacent to the first gate stack; a first gate contact electrically coupled to the first gate stack, the top surface of the first gate contact having a first width; and a first source / drain contact electrically coupled to the first source / drain region, the top surface of the first source / drain contact having a second width greater than the first width; and a second transistor including: a second gate stack stacked on a semiconductor substrate, the second gate stack having a second height less than the first height; a second source / drain region adjacent to the second gate stack; and a second source / drain contact electrically coupled to the second source / drain region, the top surface of the second source / drain contact having a third width less than the second width. In an embodiment, the ratio of the second width to the first width is 1.5 to 50, and the ratio of the second width to the third width is 1.5 to 50. In an embodiment, the second transistor further includes a first channel region, the second gate stack includes a first dielectric material contacting the first channel region, the first transistor further includes a second channel region, and the first gate stack includes a first dielectric material separated from the second channel region by a gate oxide layer. In an embodiment, the top surface of the first channel region is configured to be a first distance higher than the top surface of the second channel region in a direction perpendicular to the main surface of the semiconductor substrate, and the thickness of the gate oxide layer is equal to the first distance. In an embodiment, the top surface of the first gate stack is flush with the top surface of the second gate stack. In an embodiment, the bottom surface of the first source / drain contact has a fourth width, which is greater than the fifth width of the bottom surface of the second source / drain contact. In one embodiment, the top surfaces of the first source / drain contact, the second source / drain contact, and the first gate contact are flush with each other. The first source / drain contact has a first height that is greater than the second height of the second source / drain contact, and the second height is greater than the third height of the first gate contact.

[0061] According to another embodiment, a method includes forming a first transistor and a second transistor on a semiconductor substrate, the first transistor including a first gate stack and a first source / drain region adjacent to the first gate stack, and the second transistor including a second gate stack and a second source / drain region adjacent to the second gate stack; forming an interlayer dielectric (ILD) on the first transistor and the second transistor; depositing a photoresist on the ILD; and patterning the photoresist to form a patterned photoresist, the patterned photoresist including a first opening directly above the first source / drain region and an opening directly above the second source / drain region. The method includes a second opening above the first gate stack and a third opening directly above the first gate stack. The first opening has a first width, the second opening has a second width, and the third opening has a third width, wherein the first width is greater than each of the second and third widths. The ILD is etched using a patterned photoresist as a mask. A first contact electrically coupled to a first source / drain region, a second contact electrically coupled to a second source / drain region, and a third contact electrically coupled to the first gate stack are formed. The first contact has a first height, which is greater than each of the second height of the second contact and the third height of the third contact. In an embodiment, forming the first transistor and the second transistor includes: recessing a first region of the semiconductor substrate relative to a second region of the semiconductor substrate, forming the first transistor in the first region and the second transistor in the second region. In an embodiment, the first transistor and the second transistor further include: forming a gate oxide layer over the first and second regions; and removing the gate oxide layer from the second region, wherein the first gate stack includes the remainder of the gate oxide layer. In an embodiment, the method further includes planarizing the top surfaces of the first gate stack, the second gate stack, and the ILD. In one embodiment, forming the first contact, the second contact, and the third contact further includes planarizing the top surfaces of the first contact, the second contact, the third contact, and the ILD. In another embodiment, the third width is equal to the second width.

[0062] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0063] Example 1 is a semiconductor device comprising: a first channel region adjacent to a first source / drain region in a semiconductor substrate; a first gate stack above the first channel region; a second channel region adjacent to a second source / drain region in the semiconductor substrate, wherein a top surface of the second channel region is configured to be lower than a top surface of the first channel region; a second gate stack above the second channel region; an interlayer dielectric (ILD) above the first gate stack, the second gate stack, the first source / drain region, and the second source / drain region; a first source / drain contact extending through the ILD and electrically coupled to the first source / drain region, the first source / drain contact having a first width and a first height; and a second source / drain contact extending through the ILD and electrically coupled to the second source / drain region, the second source / drain contact having a second width greater than the first width and a second height greater than the first height.

[0064] Example 2 is the semiconductor device described in Example 1, further comprising: a first gate contact electrically coupled to the first gate stack; and a second gate contact electrically coupled to the second gate stack, the first gate contact having a third width and a third height, and the second gate contact having a fourth width equal to the third width and a fourth height equal to the third height.

[0065] Example 3 is the semiconductor device described in Example 2, wherein the second width is greater than each of the third width and the fourth width, and wherein the second height is greater than each of the third height and the fourth height.

[0066] Example 4 is the semiconductor device described in Example 2, wherein the top surfaces of the first source / drain contact, the second source / drain contact, the first gate contact, and the second gate contact are flush with each other, wherein the bottom surface of the second source / drain contact is configured to be lower than the bottom surface of the first source / drain contact, and wherein the bottom surface of the first source / drain contact is configured to be lower than the bottom surfaces of the first gate contact and the second gate contact.

[0067] Example 5 is the semiconductor device described in Example 2, wherein the first width is equal to each of the third width and the fourth width.

[0068] Example 6 is the semiconductor device described in Example 5, wherein the first height is greater than each of the third height and the fourth height.

[0069] Example 7 is the semiconductor device described in Example 1, wherein the ratio of the second width to the first width is 1.5 to 50.

[0070] Example 8 is a semiconductor device comprising: a first transistor, the first transistor including: a first gate stack, the first gate stack being disposed on a semiconductor substrate, the first gate stack having a first height; a first source / drain region, the first source / drain region being adjacent to the first gate stack; a first gate contact, the first gate contact being electrically coupled to the first gate stack, the top surface of the first gate contact having a first width; and a first source / drain contact, the first source / drain contact being electrically coupled to the first source / drain region, the top surface of the first source / drain contact having a second width greater than the first width; and a second transistor, the second transistor including: a second gate stack, the second gate stack being disposed on a semiconductor substrate, the second gate stack having a second height less than the first height; a second source / drain region, the second source / drain region being adjacent to the second gate stack; and a second source / drain contact, the second source / drain contact being electrically coupled to the second source / drain region, the top surface of the second source / drain contact having a third width less than the second width.

[0071] Example 9 is the semiconductor device described in Example 8, wherein the ratio of the second width to the first width is 1.5 to 50, and the ratio of the second width to the third width is 1.5 to 50.

[0072] Example 10 is the semiconductor device described in Example 8, wherein the second transistor further includes a first channel region, wherein the second gate stack includes a first dielectric material in contact with the first channel region, wherein the first transistor further includes a second channel region, and wherein the first gate stack includes the first dielectric material separated from the second channel region by a gate oxide layer.

[0073] Example 11 is the semiconductor device described in Example 10, wherein the top surface of the first channel region is configured to be higher than the top surface of the second channel region by a first distance in a direction perpendicular to the main surface of the semiconductor substrate, and wherein the thickness of the gate oxide layer is equal to the first distance.

[0074] Example 12 is the semiconductor device described in Example 8, wherein the top surface of the first gate stack is flush with the top surface of the second gate stack.

[0075] Example 13 is the semiconductor device described in Example 8, wherein the bottom surface of the first source / drain contact has a fourth width, which is greater than the fifth width of the bottom surface of the second source / drain contact.

[0076] Example 14 is the semiconductor device described in Example 8, wherein the top surfaces of the first source / drain contact, the second source / drain contact, and the first gate contact are flush with each other, wherein the first source / drain contact has a first height greater than the second height of the second source / drain contact, and wherein the second height is greater than the third height of the first gate contact.

[0077] Example 15 is a method of forming a semiconductor device, comprising: forming a first transistor and a second transistor on a semiconductor substrate, the first transistor including a first gate stack and a first source / drain region adjacent to the first gate stack, the second transistor including a second gate stack and a second source / drain region adjacent to the second gate stack; forming an interlayer dielectric (ILD) on the first transistor and the second transistor; depositing a photoresist on the ILD; and patterning the photoresist to form a patterned photoresist, the patterned photoresist including a first opening directly above the first source / drain region and an opening directly above the second source / drain region. A second opening and a third opening directly above the first gate stack, the first opening having a first width, the second opening having a second width, and the third opening having a third width, wherein the first width is greater than each of the second width and the third width; etching the ILD using the patterned photoresist as a mask; and forming a first contact electrically coupled to the first source / drain region, a second contact electrically coupled to the second source / drain region, and a third contact electrically coupled to the first gate stack, the first contact having a first height, the first height being greater than each of the second height of the second contact and the third height of the third contact.

[0078] Example 16 is the method of Example 15, wherein forming the first transistor and the second transistor includes: recessing a first region of the semiconductor substrate relative to a second region of the semiconductor substrate, wherein the first transistor is formed in the first region and the second transistor is formed in the second region.

[0079] Example 17 is the method of Example 16, wherein forming the first transistor and the second transistor further includes: forming a gate oxide layer over the first region and the second region; and removing the gate oxide layer from the second region, wherein the first gate stack includes the remainder of the gate oxide layer.

[0080] Example 18 is the method of Example 17, further comprising: planarizing the top surface of the first gate stack, the second gate stack, and the ILD.

[0081] Example 19 is the method described in Example 15, wherein forming the first contact, the second contact, and the third contact further includes: planarizing the top surfaces of the first contact, the second contact, the third contact, and the ILD.

[0082] Example 20 is the method described in Example 15, wherein the third width is equal to the second width.

Claims

1. A semiconductor device, comprising: A first channel region, which is adjacent to a first source / drain region in the semiconductor substrate; A first gate stack, wherein the first gate stack is stacked on the first channel region; A second channel region, which is adjacent to a second source / drain region in the semiconductor substrate, wherein the top surface of the second channel region is configured to be lower than the top surface of the first channel region; The second gate stack is stacked on top of the second channel region; An interlayer dielectric (ILD) is disposed above the first gate stack, the second gate stack, the first source / drain region, and the second source / drain region; A first source / drain contact extends through the ILD and is electrically coupled to the first source / drain region, the first source / drain contact having a first width and a first height; A second source / drain contact extends through the ILD and is electrically coupled to the second source / drain region, the second source / drain contact having a second width greater than the first width and a second height greater than the first height; A first gate contact, the first gate contact being electrically coupled to the first gate stack; and A second gate contact electrically coupled to the second gate stack, the first gate contact having a third width and a third height, and the second gate contact having a fourth width equal to the third width and a fourth height equal to the third height.

2. The semiconductor device according to claim 1, wherein, The second width is greater than each of the third width and the fourth width, and the second height is greater than each of the third height and the fourth height.

3. The semiconductor device according to claim 1, wherein, The top surfaces of the first source / drain contact, the second source / drain contact, the first gate contact, and the second gate contact are flush with each other, wherein the bottom surface of the second source / drain contact is configured to be lower than the bottom surface of the first source / drain contact, and wherein the bottom surface of the first source / drain contact is configured to be lower than the bottom surfaces of the first gate contact and the second gate contact.

4. The semiconductor device according to claim 1, wherein, The first width is equal to each of the third width and the fourth width.

5. The semiconductor device according to claim 4, wherein, The first height is greater than each of the third height and the fourth height.

6. The semiconductor device according to claim 1, wherein, The ratio of the second width to the first width is 1.5 to 50.

7. A semiconductor device, comprising: A first transistor, the first transistor comprising: A first gate stack, the first gate stack being stacked on a semiconductor substrate, the first gate stack having a first height; The first source / drain region is adjacent to the first gate stack; A first gate contact, electrically coupled to the first gate stack, wherein the top surface of the first gate contact has a first width; and A first source / drain contact, electrically coupled to a first source / drain region, wherein the top surface of the first source / drain contact has a second width greater than the first width; and The second transistor includes: A second gate stack is stacked on the semiconductor substrate, and the second gate stack has a second height that is less than the first height; The second source / drain region is adjacent to the second gate stack; A second gate contact, electrically coupled to the second gate stack, having a top surface with the first width, and wherein the first gate contact and the second gate contact have the same third height; and The second source / drain contact is electrically coupled to the second source / drain region, and the top surface of the second source / drain contact has a third width that is smaller than the second width.

8. The semiconductor device according to claim 7, wherein, The ratio of the second width to the first width is 1.5 to 50, and the ratio of the second width to the third width is 1.5 to 50.

9. The semiconductor device according to claim 7, wherein, The second transistor further includes a first channel region, wherein the second gate stack includes a first dielectric material in contact with the first channel region, wherein the first transistor further includes a second channel region, and wherein the first gate stack includes the first dielectric material separated from the second channel region by a gate oxide layer.

10. The semiconductor device according to claim 9, wherein, The top surface of the first channel region is configured to be a first distance higher than the top surface of the second channel region in a direction perpendicular to the main surface of the semiconductor substrate, and wherein the thickness of the gate oxide layer is equal to the first distance.

11. The semiconductor device according to claim 7, wherein, The top surface of the first gate stack is flush with the top surface of the second gate stack.

12. The semiconductor device according to claim 7, wherein, The bottom surface of the first source / drain contact has a fourth width, which is greater than the fifth width of the bottom surface of the second source / drain contact.

13. The semiconductor device according to claim 7, wherein, The top surfaces of the first source / drain contact, the second source / drain contact, and the first gate contact are flush with each other, wherein the first source / drain contact has a first height that is greater than the second height of the second source / drain contact, and wherein the second height is greater than the third height of the first gate contact.

14. A method of forming a semiconductor device, comprising: A first transistor and a second transistor are formed on a semiconductor substrate. The first transistor includes a first gate stack and a first source / drain region adjacent to the first gate stack. The second transistor includes a second gate stack and a second source / drain region adjacent to the second gate stack. An interlayer dielectric (ILD) is formed on the first transistor and the second transistor; A photoresist is deposited on the ILD; The photoresist is patterned to form a patterned photoresist, the patterned photoresist including a first opening directly above the first source / drain region, a second opening directly above the second source / drain region, a third opening directly above the first gate stack, and a fourth opening directly above the second gate stack, the first opening having a first width, the second opening having a second width, the third opening and the fourth opening having a third width, wherein the first width is greater than each of the second width and the third width; The patterned photoresist is used as a mask to etch the ILD; and A first contact electrically coupled to the first source / drain region, a second contact electrically coupled to the second source / drain region, a third contact electrically coupled to the first gate stack, and a fourth contact electrically coupled to the second gate stack are formed. The first contact has a first height, which is greater than each of a second height of the second contact and a third height of the third contact. The third contact and the fourth contact have the same fourth width and the same third height.

15. The method according to claim 14, wherein, Forming the first transistor and the second transistor includes: recessing a first region of the semiconductor substrate relative to a second region of the semiconductor substrate, wherein the first transistor is formed in the first region and the second transistor is formed in the second region.

16. The method according to claim 15, wherein, The formation of the first transistor and the second transistor further includes: A gate oxide layer is formed over the first region and the second region; and The gate oxide layer is removed from the second region, wherein the first gate stack includes the remaining portion of the gate oxide layer.

17. The method of claim 16, further comprising: Planarize the top surfaces of the first gate stack, the second gate stack, and the ILD.

18. The method according to claim 14, wherein, Forming the first contact, the second contact, and the third contact further includes: planarizing the top surfaces of the first contact, the second contact, the third contact, and the ILD.

19. The method of claim 14, wherein, The third width is equal to the second width.

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