A semiconductor device and its manufacturing method

Abstract

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor manufacturing technology, to solve the problem of large parasitic capacitance generated between the memory contact and the bit line structure, thereby affecting the operating performance of the semiconductor device. The semiconductor device includes: a semiconductor substrate having an active region; a bit line structure formed on the semiconductor substrate, the bit line structure including a contact and a bit line body located on the contact, the contact contacting a portion of the active region; and a memory contact formed between two adjacent bit line structures, the memory contact contacting another portion of the active region; wherein the portion of the bit line body above the contact has a lower top height than the rest of the bit line body. The manufacturing method of the semiconductor device is used to manufacture a semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Figure 1 A schematic diagram of a semiconductor device structure in the prior art is shown. For example... Figure 1 As shown, with the gradual miniaturization of semiconductor devices, parasitic capacitance is easily generated between the storage contact 4 and the bit line structure 20. The parasitic capacitance c = ε·A / d, where ε is the relative permittivity, A is the area of ​​the conductive portion of the bit line structure 20 (contact 200 and the bit line body 201 above contact 200) facing the storage contact 4, and d is the vertical distance between the bit line body 201 above contact 200 and the storage contact 4. From the formula c = ε·A / d, it can be seen that the parasitic capacitance c is affected by the area A of the conductive portion of the bit line structure 20 facing the storage contact 4.

[0003] As the integration of semiconductor memory elements becomes increasingly higher, the parasitic capacitance generated between the memory contacts and bit line structures during DRAM manufacturing is relatively large. This capacitance reduces the driving capability of the semiconductor device during operation, thus degrading its performance. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, for reducing parasitic capacitance generated between the storage contact and the bit line structure.

[0005] To achieve the above objectives, the present invention provides a semiconductor device. The semiconductor device includes: a semiconductor substrate having an active region;

[0006] A bit line structure formed on a semiconductor substrate, the bit line structure including a contact portion and a bit line body located on the contact portion, the contact portion being in contact with a portion of the active region;

[0007] And a memory contact formed between two adjacent bit line structures, the memory contact contact being in contact with another part of the active region;

[0008] The portion of the bit line body above the contact area has a lower top height than the rest of the bit line body.

[0009] Compared with the prior art, the semiconductor device provided by the present invention has a bit line structure formed on a semiconductor substrate. The bit line structure includes a contact portion and a bit line body located above the contact portion. The contact portion contacts a portion of the active region, so the bit line body located above the contact portion can be connected to a portion of the active region through the contact portion, while the other portions of the bit line body are not connected to the active region. Simultaneously, the portion of the bit line body above the contact portion has a lower top height than the other portions of the bit line body. Therefore, along the length extension direction of the bit line body, the top height of the bit line body exhibits a undulating curved or broken-line variation, whereas in the prior art, the top height of each portion of the bit line body is equal. In the semiconductor device provided by this invention, the portion of the bit line body above the contact has a lower top height than other portions of the bit line body. This results in the contact portion in the bit line structure and the facing area between the bit line body above the contact and the storage contact being smaller than the facing area between the contact portion and the bit line body above the contact and the storage contact in the prior art. This effectively reduces the parasitic capacitance generated between the storage contact and the bit line structure, improves the driving capability of the semiconductor device, and enhances the operating performance of the semiconductor device.

[0010] The present invention also provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes:

[0011] Provide a semiconductor substrate with an active region;

[0012] A semiconductor layer is formed on a semiconductor substrate;

[0013] The semiconductor layer and semiconductor substrate are etched to form contact holes on the semiconductor substrate; the contact holes contact a portion of the active region.

[0014] A contact material layer is formed inside the contact hole, and the top surface of the contact material layer is lower than the top surface of the semiconductor layer.

[0015] A bit line material layer and an isolation material layer are sequentially deposited on the contact material layer and the semiconductor layer;

[0016] The isolation material layer, bit line material layer, contact material layer, and semiconductor layer are etched to form the isolation layer, bit line body, contact portion, and connection portion.

[0017] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention are the same as those of the semiconductor device described in the above technical solutions, and will not be repeated here. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0019] Figure 1 A schematic diagram of a semiconductor device structure in the prior art is shown;

[0020] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention is shown;

[0021] Figure 3 This diagram illustrates the height variation of the bitline body according to an embodiment of the present invention.

[0022] Figure 4 This diagram illustrates the structure after the semiconductor layer is formed in an embodiment of the present invention.

[0023] Figure 5 A schematic diagram of the structure after forming the contact hole is shown in an embodiment of the present invention;

[0024] Figure 6 This diagram illustrates the structure after the contact material layer is formed in an embodiment of the present invention.

[0025] Figure 7 This diagram illustrates the structure after etching back the contact material layer in an embodiment of the present invention.

[0026] Figure 8 This diagram illustrates the structure after forming the bit line material layer and the isolation material layer in an embodiment of the present invention.

[0027] Figure 9 This shows a schematic diagram of the structure after the bit line structure is formed in an embodiment of the present invention;

[0028] Figure 10 This shows a schematic diagram of the structure after the first sidewall is formed in an embodiment of the present invention;

[0029] Figure 11 This diagram illustrates the structure after the second, third, and fourth side walls are formed in an embodiment of the present invention.

[0030] Figure 12 A schematic diagram of the structure after the storage contact portion is formed in an embodiment of the present invention is shown.

[0031] Figure label:

[0032] 10 is a semiconductor substrate, 100 is an active region, 101 is a contact hole, 20 is a bit line structure, 200 is a contact portion, 201 is a bit line body, 202 is a connection portion, 203 is an isolation layer, 204 is a first transition portion, 205 is a second transition portion, 206 is a horizontal connection portion, 207 is a semiconductor layer, 208 is a contact material layer, 209 is a bit line material layer, 210 is an isolation material layer, 30 is a sidewall, 300 is a first sidewall, 301 is a second sidewall, 302 is a third sidewall, 303 is a fourth sidewall, and 4 is a memory contact portion. Detailed Implementation

[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0034] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0035] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] To address the problem of reduced driving capability and poor performance of semiconductor devices due to large parasitic capacitance between the storage contacts and the bit line structure, this invention provides a semiconductor device and its manufacturing method. In this device, the portion of the bit line body above the contacts has a lower top height than the rest of the bit line body. This effectively reduces the parasitic capacitance between the storage contacts and the bit line structure, improving the driving capability and overall performance of the semiconductor device.

[0039] For ease of description, the following only describes the differences between the semiconductor devices provided in the embodiments of the present invention and those in the prior art. Other structures not described can be referred to the descriptions in the prior art. Of course, those skilled in the art can also improve other existing semiconductor devices based on the following descriptions of the embodiments of the present invention.

[0040] To address the aforementioned problems, embodiments of the present invention provide a semiconductor device. This semiconductor device includes at least a semiconductor substrate having an active region, and bit line structures formed on the semiconductor substrate. The bit line structure includes a contact portion and a bit line body, with the contact portion contacting a portion of the active region. The portion of the bit line body above the contact portion has a lower top height than the rest of the bit line body. A storage contact portion is formed between two adjacent bit line structures, and the storage contact portion contacts another portion of the active region.

[0041] This semiconductor device can be used in electronic devices such as DRAM (Dynamic Random Access Memory) or FLASH (Flash Memory). Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention is shown. (Refer to...) Figure 2 The semiconductor device includes at least: a semiconductor substrate 10, a bit line structure 20, and a storage contact 4.

[0042] The semiconductor substrate 10 described above can be a stacked structure with a partially formed semiconductor structure. The semiconductor substrate 10 has active regions 100, for example, source and drain regions have been formed on the active regions 100. The number and arrangement of the active regions 100 can be set according to the actual application scenario, as long as it can be applied to the semiconductor device provided in the embodiments of this invention. For example, the active regions 100 can be arranged in an intersecting direction with the bit line structure 20. The semiconductor substrate 10 may also include a gate (word line), which, together with the aforementioned source and drain regions, forms a transistor structure, serving as a switching transistor for the memory.

[0043] Bit line structure 20 is formed on semiconductor substrate 10. Bit line structure 20 includes a contact portion 200 and a bit line body 201 located on the contact portion 200. The contact portion 200 contacts a portion of the active region 100. The portion of the bit line body 201 above the contact portion 200 has a lower top height than the rest of the bit line body 201. It should be understood that the region containing a portion of the active region 100 is the region containing the source region (or drain region) formed on the active region 100. The contact portion 200 is connected to the source region (or drain region) on the active region 100.

[0044] The contact portion 200 is made of a conductive material. This conductive material can be doped polycrystalline silicon or boron-doped silicon-germanium. The bit line body 201 includes a barrier layer ( Figure 2 (Not shown in the diagram), and a metal layer located on the barrier layer. The material of the barrier layer may include one or more of TiN, TaN, and WN. For example, the material of the barrier layer may include TiN, and the material of the metal layer may include W.

[0045] In one possible implementation, the bit line structure 20 further includes a connection portion 202. The connection portion 202 is located between the other portion of the bit line body 201 and the semiconductor substrate 10. Exemplarily, the connection portion 202 may be formed on the semiconductor substrate 10, but is not connected to the active region 100. The material of the connection portion 202 may include a material such as polysilicon, and the top surface of the connection portion 202 is higher than the top surface of the contact portion 200.

[0046] The bit line structure 20 may also include an isolation layer 203, which is formed on the bit line body 201. During the manufacturing process of the semiconductor device, the isolation layer 203 protects the bit line body 201 from subsequent etching, cleaning, and other operations. The material of the isolation layer 203 may include insulating materials such as SiCN, SiOCN, or SiN. The thickness of the isolation layer 203 can be set according to the actual application scenario and is not specifically limited here.

[0047] Storage contacts 4 are formed between two adjacent bit line structures 20. Each storage contact 4 contacts another portion of the active region 100. The storage contact 4 contains a conductive material. The conductive material can be impurity-doped polysilicon, boron-doped silicon-germanium, or silicon-germanium, etc. The other portion of the active region 100 is the region where the drain region (or source region) formed on the active region 100 is located. The storage contact 4 is connected to the drain region (or source region) on the active region 100.

[0048] To better isolate the bit line structure 20 from structures such as the memory contact portion 4, the semiconductor device further includes sidewalls 30. These sidewalls 30 are located on both sides of the connection portion 202, the contact portion 200, the bit line body 201, and the isolation layer 203. The sidewalls 30 include a first sidewall 300 formed on the outer periphery of the bit line structure 20, and a second sidewall 301 formed on the semiconductor substrate 10 and located on the outer periphery of the first sidewall 300, wherein the height of the second sidewall 301 is the same as the height of the semiconductor substrate 10. A third sidewall 302 and a fourth sidewall 303 are sequentially formed on the outer periphery of the first sidewall 300 and the second sidewall 301. The first sidewall 300, the second sidewall 301, and the fourth sidewall 303 can be SiN sidewalls, and the third sidewall 302 can be a SiO2 sidewall. The material and thickness of the sidewalls 30 can also be selected according to actual conditions, and will not be elaborated further here.

[0049] Reference Figure 1 and Figure 2 In the prior art, the portion of the bit line body 201 above the contact portion 200 has the same top height as the other portions of the bit line body 201 (i.e., the portion of the bit line body 201 above the connecting portion 202), and the top height of the contact portion 200 is the same as that of the connecting portion 202. That is, the top height of the contact portion 200 is equal to the bottom height of the bit line body 201 located on the connecting portion 202. In this prior art, the area of ​​the contact portion 200 and the bit line body 201 above the contact portion 200 facing the storage contact portion 4 is A. In the embodiment provided by the present invention, the area of ​​the contact portion 200 and the bit line body 201 above the contact portion 200 facing the storage contact portion 4 in the bit line structure 20 is A'. In summary, the comparison shows that A is greater than A', meaning that the area between the contact portion 200 and the bit line body 201 located above the contact portion 200 and the storage contact portion 4 is reduced. This reduces the parasitic capacitance formed between the storage contact portion 4 and the bit line structure 20, thereby improving the driving capability of the semiconductor device and the performance of the semiconductor device.

[0050] The top height of the contact portion 200 is less than the bottom height of the bit line body 201 located on the connecting portion 202. With the thickness of the bit line body 201 on the contact portion 200 and the connecting portion 202 remaining constant compared to the thickness of the bit line body 201 in the prior art, the portion of the bit line body 201 above the contact portion 200 has a lower top height than the other portions of the bit line body 201. Therefore, the height of the contact portion 200 is reduced compared to the height of the contact portion 200 in the prior art, meaning the facing area between the contact portion 200 and the bit line body 201 on the contact portion 200 and the storage contact portion 4 in the bit line structure 20 is reduced, thereby reducing the parasitic capacitance formed between the storage contact portion 4 and the bit line structure 20. The difference in the reduction of the height of the contact portion 200 compared to the height of the contact portion 200 in the prior art can be set according to actual conditions and is not specifically limited here.

[0051] Figure 3 A schematic diagram illustrating the height variation of the bitline body according to an embodiment of the present invention is shown. (Refer to...) Figure 1 and Figure 2 Since the portion of the bit line body 201 above the contact portion 200 has a lower top height than other portions of the bit line body 201, and the thickness of the bit line body 201 located within the contact portion 200 and the connecting portion 202 remains unchanged compared to the thickness of the bit line body 201 in the prior art, the bit line body 201 located on the contact portion 200 and the bit line body 201 located on the connecting portion 202 can exhibit a curved or zigzag shape with varying heights along the length extension direction of the bit line body 201 in the semiconductor device (see reference). Figure 3 ).

[0052] Reference Figure 3 The other parts of the bit line body 201 include a first transition portion 204, a second transition portion 205, and a horizontal connecting portion 206. The horizontal connecting portion 206 is located between the first transition portion 204 and the second transition portion 205. The top height of the horizontal connecting portion 206 is greater than the top height of the bit line body 201 located on the contact portion 200. The horizontal connecting portion 206 is connected to the bit line body 201 located on the contact portion 200 via the first transition portion 204 and the second transition portion 205. In this way, the parasitic capacitance between the storage contact portion 4 and the bit line structure 20 is reduced without affecting the normal operation of the semiconductor device. Of course, the orientation of the bit line body 201 can also be other shapes, and is not limited to this.

[0053] This invention also provides a method for manufacturing a semiconductor device. The following description uses DRAM manufacturing as an example; it should be understood that the following description is for illustrative purposes only and is not intended to limit the scope of the invention. (Refer to...) Figures 4 to 12 The method for manufacturing this semiconductor device includes:

[0054] First, a semiconductor substrate with active regions is provided. The semiconductor substrate can be Si, SiGe, or other compound semiconductors, or it can be an SOI substrate. An interleaved distribution of active regions intersecting with bit lines can be formed on the semiconductor substrate according to the layout of the active regions in a DRAM. BCAT (Buried Channel Array) transistors can be formed on the semiconductor substrate, wherein the word lines (gates) of the BCAT pass through these active regions, thereby constituting a switching transistor.

[0055] Reference Figure 4 A semiconductor layer 207 can be formed on the semiconductor substrate 10.

[0056] For example, the semiconductor layer 207 can be formed directly on the semiconductor substrate 10 by methods such as epitaxy or chemical vapor deposition. It should be understood that other practically suitable methods can also be used to form the semiconductor layer 207. Since the semiconductor layer 207 will subsequently form interconnects, the material contained in the semiconductor layer 207 can be set according to the material contained in the interconnects. In the manufacture of DRAM, the semiconductor layer 207 can be a polysilicon layer used for the gates of logic transistors in the peripheral region of the chip.

[0057] Reference Figure 5 The semiconductor layer 207 and the semiconductor substrate 10 are etched to form a contact hole 101 on the semiconductor substrate 10. The contact hole 101 contacts a portion of the active region 100.

[0058] For example, wet etching or dry etching can be used to selectively remove a portion of the semiconductor layer 207 formed above the semiconductor substrate 10. Then, the semiconductor substrate 10 is etched to form contact holes 101 on the semiconductor substrate 10 by photolithography, exposing a portion of the active region 100 at the bottom of the contact hole 101. The region containing a portion of the active region 100 is the region containing the source (or drain) region on the active region 100. There are many ways to form the contact hole 101, and it is not limited to the methods described above.

[0059] In another example, wet etching or dry etching can be used to simultaneously etch the semiconductor layer 207 and the semiconductor substrate 10 to obtain a new semiconductor layer 207 and a contact hole 101 formed on the semiconductor substrate 10.

[0060] Reference Figure 6 A contact material layer 208 is formed inside the contact hole 101.

[0061] For example, the contact material layer 208 can be formed directly on the contact hole 101 and the semiconductor layer 207 using methods such as chemical vapor deposition. It should be understood that other practically suitable methods can also be used to form the contact material layer 208. The contact material layer 208 can be a doped polysilicon layer. Of course, since the contact material layer 208 will subsequently form a contact portion, the material of the contact material layer can be set according to the material of the contact portion.

[0062] In another example, a contact material layer 208 may be formed only within the contact hole 101, with the top surface of the contact material layer 208 being lower than the top surface of the semiconductor layer 207. The top surface of the contact material layer 208 may also be lower than the top surface of the semiconductor substrate 10. It should be understood that the thickness of the contact material layer 208 can be deposited according to actual needs, and will not be elaborated further here.

[0063] Reference Figure 7 The contact material layer 208 (i.e., the doped polysilicon layer) is etched back to the top surface below the semiconductor layer 207.

[0064] For example, after a contact material layer 208 is formed on the contact hole and the semiconductor layer 207, due to the height difference between the bottom of the contact hole and the semiconductor layer 207, the contact material layer 208 formed on the contact hole and the semiconductor layer 207 will also have a certain height difference when the contact material is deposited. When the contact material layer 208 needs to be etched back later, in order to ensure that the top height of the new contact material layer 208 is less than the top height of the semiconductor layer 207 to meet the actual working requirements, the formed contact material layer 208 can be planarized before etching back, so that the thickness of the later etched back is consistent, and thus the newly formed contact material layer 208 is flat and has a regular shape. For example, plasma etching can be used, and the etching depth of the contact material layer 208 can be 25nm. It should be understood that the etching depth can be selected according to the thickness of the formed contact material layer 208 and the final required thickness of the contact material layer 208.

[0065] For example, if the top height of the formed contact material layer 208 is greater than or equal to the top height of the semiconductor layer 207, the initially deposited contact material layer 208 can be etched back according to the required thickness of the contact material layer 208 for actual operation, so that the top height of the new contact material layer 208 is less than the top height of the semiconductor layer 207. The etching back can be performed using plasma etching or wet etching. The etching depth of the contact material layer 208 is greater than 0 nm and less than or equal to 50 nm.

[0066] In another example, when a contact material layer is formed only within a contact hole, if the top height of the formed contact material layer is the height required for actual operation, there is no need to etch back the contact material layer; that is, the deposited contact material layer can be directly used as the required contact material layer. If the top height of the formed contact material layer is greater than the thickness of the contact material layer required for actual operation, the contact material layer is etched back to make the top height of the obtained contact material layer less than the top height of the semiconductor layer. The specific etch-back method and thickness are described above and will not be repeated here.

[0067] Reference Figure 8 A bit line material layer 209 and an isolation material layer 210 are sequentially deposited on the contact material layer 208 and the semiconductor layer 207.

[0068] For example, a bit line material layer 209 and an isolation material layer 210 can be sequentially deposited on the etched contact material layer 208 and semiconductor layer 207 using methods such as chemical vapor deposition. The bit line material layer 209 is made of a conductive material. The conductive material used to form the barrier layer may include one or more of TiN, TaN, and WN, and the material used to form the metal layer may include W. The isolation material layer 210 may be an insulating material, which may include SiCN, SiOCN, or SiN, etc.

[0069] Reference Figure 9 The aforementioned isolation material layer, bit line material layer, contact material layer and semiconductor layer are etched to form an isolation layer 203, a bit line body 201, a contact portion 200 and a connection portion 202.

[0070] For example, since the top height of the contact material layer after etching back is less than the top height of the semiconductor layer, there is a height difference between the bit line material layer formed on the contact material layer and the semiconductor layer, and there is also a height difference between the isolation material layer and the isolation material layer. To facilitate subsequent processing of the isolation material layer, bit line material layer, contact material layer, and semiconductor layer, the isolation material layer needs to be planarized first. This ensures that the thickness of the isolation material layer, bit line material layer, contact material layer, and semiconductor layer is consistent during subsequent etching, resulting in a flat and regular bit line structure. Then, dry etching can be used to process the isolation material layer to obtain the isolation layer. Finally, using the isolation layer as a mask, the bit line material layer, contact material layer, and semiconductor layer are processed to obtain the bit line body 201, contact portion 200, and connecting portion 202.

[0071] The bit line structure 20 includes a contact portion 200, a bit line body 201, and an isolation layer 203. The bit line body 20 is connected to the source region (or drain region) at the bottom of the contact hole through the contact portion 200. After dry etching of the semiconductor layer, bit line material layer, and isolation material layer, a connection portion 202, a bit line body 201, and an isolation layer 203 are obtained, respectively. The bit line body 201 is connected to the semiconductor substrate 10 through the connection portion 202, but the bit line body 201 is not connected to the active region 100.

[0072] The top height of the bit line body 201 above the contact portion 200 is less than the top height of the bit line body 201 above the connection portion 202, and the top height of the contact portion 200 is less than the bottom height of the bit line body 201 above the connection portion 202. At this time, the area between the contact portion 200 and the bit line body 201 above the contact portion 200 and the memory contact portion 4 in the bit line structure 20 is reduced, thereby reducing the parasitic capacitance formed between the memory contact portion 4 and the bit line structure 20, and thus improving the driving capability and performance of the semiconductor device.

[0073] The isolation layer 203 protects the bit line body 201 from subsequent etching, cleaning, and other operations. The material of the isolation layer 203 can be an insulating material such as SiCN, SiOCN, or SiN. The thickness of the isolation layer 203 can be set according to the actual application scenario and is not specifically limited here.

[0074] Reference Figure 10 A first sidewall 300 can be formed on both sides of the isolation layer 203, the main body of the bit line 201, the contact part 200, and the connecting part 202.

[0075] For example, first sidewalls 300 are first formed on both sides of the bit line structure 20. The first sidewalls 300 can be SiN sidewalls. Of course, the material and thickness of the first sidewalls 300 can also be selected according to the actual situation, which will not be elaborated here.

[0076] Reference Figure 11 A second side wall 301, a third side wall 302, and a fourth side wall 303 can be formed sequentially around the outer periphery of the first side wall 300.

[0077] For example, a second sidewall 301 is formed on the outer periphery of the first sidewall 300 located within the contact hole, and the height of the second sidewall 301 is consistent with the height of the semiconductor substrate 10. The second sidewall 301 can be a SiN sidewall. A third sidewall 302 and a fourth sidewall 303 are sequentially formed on the outer periphery of the first sidewall 300 and the second sidewall 301. The third sidewall 302 can be a SiO2 sidewall, and the fourth sidewall 303 can be a SiN sidewall. At this time, the first sidewall 300, the second sidewall 301, the third sidewall 302, and the fourth sidewall 303 constitute the sidewall 30 on the outer periphery of the on-line structure 20. It should be understood that the material and thickness of the sidewall 30 can also be selected according to the actual situation, which will not be elaborated here.

[0078] Reference Figure 12 Storage contact 4 is formed between two adjacent bit line structures 20.

[0079] For example, using the isolation layer 203 and sidewall 30 as a mask, the semiconductor substrate 10 is etched downwards to form trenches, exposing the drain region (or source region) on the active region 100. Then, storage contacts 4 are formed in the trenches exposing the drain region (or source region) on the active region 100 by means of epitaxy or chemical vapor deposition, etc., and the storage contacts 4 contact the drain region (or source region) on the active region 100. The material of the storage contacts 4 is a conductive material. The conductive material can be impurity-doped polysilicon, boron-doped silicon-germanium, or silicon-germanium. Then, an isolation structure ( Figure 12 (Not shown in the image). The material of the isolation structure is an insulating material. The insulating material may include one of SiBCN, SiCN, SiOCN, or SiN.

[0080] It should be understood that the storage contacts and isolation structures described above can be formed in various ways. How the storage contacts and isolation structures are formed is not a key feature of the embodiments of the present invention; therefore, it is only briefly described in this specification so that those skilled in the art can easily implement the embodiments provided by the present invention. Those skilled in the art can certainly imagine other ways of manufacturing the storage contacts and isolation structures.

[0081] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0082] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate with active region; A bit line structure is formed on the semiconductor substrate, the bit line structure including a contact portion and a bit line body located on the contact portion, the contact portion being in contact with a portion of the active region; And a storage contact formed between two adjacent bit line structures, the storage contact contact being in contact with another portion of the active region; Wherein, the portion of the bit line body above the contact portion has a lower top height than the other portions of the bit line body; The other parts of the bit line body include a first transition portion, a second transition portion, and a horizontal connecting portion; the horizontal connecting portion is located between the first transition portion and the second transition portion, and the top height of the horizontal connecting portion is greater than the top height of the bit line body located on the contact portion. The horizontal connecting portion is connected to the bit line body located on the contact portion through the first transition portion and the second transition portion, respectively.

2. The semiconductor device according to claim 1, characterized in that, The other portion of the bit line body includes a connection between itself and the semiconductor substrate, the material of the connection including polycrystalline silicon, and the top surface of the connection being higher than the top surface of the contact portion.

3. The semiconductor device according to claim 2, characterized in that, The bit line structure also includes an isolation layer located on the bit line body; The semiconductor device also includes sidewalls located on both sides of the connection portion, contact portion, bit line body and isolation layer.

4. The semiconductor device according to claim 1, characterized in that, The bit line body includes a barrier layer and a metal layer located on the barrier layer; the material of the barrier layer includes one or more of TiN, TaN, and WN.

5. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor substrate with an active region; A semiconductor layer is formed on the semiconductor substrate; Etch the semiconductor layer and the semiconductor substrate to form contact holes on the semiconductor substrate; The contact hole contacts a portion of the active region; A contact material layer is formed inside the contact hole, and the top surface of the contact material layer is lower than the top surface of the semiconductor layer; A bit line material layer and an isolation material layer are sequentially deposited on the contact material layer and the semiconductor layer; The isolation material layer, bit line material layer, contact material layer and semiconductor layer are etched to form an isolation layer, a bit line body, a contact portion and a connection portion; The other parts of the bit line body include a first transition portion, a second transition portion, and a horizontal connecting portion; the horizontal connecting portion is located between the first transition portion and the second transition portion, and the top height of the horizontal connecting portion is greater than the top height of the bit line body located on the contact portion. The horizontal connecting portion is connected to the bit line body located on the contact portion through the first transition portion and the second transition portion, respectively.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, Sidewalls are formed on both sides of the isolation layer, the main body of the bit line, the contact part, and the connecting part.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The method for manufacturing the semiconductor device further includes: The semiconductor substrate is etched using the isolation layer and sidewalls as a mask to form trenches; Storage contacts are formed in the trench, and an isolation structure is located between two adjacent storage contacts.

8. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The step of forming a contact material layer within the contact hole, wherein the top surface of the contact material layer is lower than the top surface of the semiconductor layer, includes: A doped polysilicon layer is deposited inside the contact hole; The doped polysilicon layer is etched back to a surface below the top surface of the semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The depth of the etch is greater than 0 nm and less than or equal to 50 nm.

Images