NAND flash block architecture enhancements for preventing block promotion

Abstract

This application relates to NAND flash block architecture enhancements to prevent block promotion. A three-dimensional memory device is disclosed. In one embodiment, a device is disclosed, the device comprising: a source plate; plugs fabricated on the source plate or partially formed in the source plate; a stack formed on a substrate and plugs, the stack comprising alternating insulative layers and conductive layers, and strings of channel material of memory cells extending through the insulative layers and conductive layers; a first set of pillars formed by a process that includes etching the alternating insulative layers and conductive layers, and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates on top of a respective plug in a plurality of plugs; and a second set of pillars formed by a process that includes etching the alternating insulative layers and conductive layers, and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.

Description

TECHNICAL FIELD

[0001] The disclosed embodiments relate to NAND flash memory storage devices. In particular, at least some of the disclosed embodiments relate to 3D NAND flash memory improvements. BACKGROUND

[0002] Various types of non-volatile storage devices can be used to store data. Non-volatile storage devices can include NAND flash memory devices. NAND flash is a type of flash memory that is constructed using NAND logic gates. Alternatively, NOR flash is a type of flash memory that is constructed using NOR logic gates. Currently, the use of NAND flash dominates the flash memory market.

[0003] In a typical flash memory, NAND or NOR transistors are used to store information and are arranged in an array or grid of gates that can be accessed via bit lines and word lines, the intersection of which is referred to as a cell. The simplest flash memory stores one bit of information per cell and is referred to as single-level cell (SLC) flash memory. In multi-level cell (MLC) flash memory, a cell stores more than one bit of information. In particular, MLC flash memory has traditionally stored two bits of information per cell. Thus, triple-level cell (TLC) flash memory stores three bits of information per cell, and quad-level cell (QLC) flash memory stores four bits of information per cell.

[0004] Flash memory devices (e.g., NAND, NOR, etc.) have evolved into a popular nonvolatile memory source for various electronic applications. Nonvolatile memory is memory that can hold its data values for extended periods without the application of power. Flash memory devices typically use single transistor memory cells that allow for high memory density, high reliability, and low power consumption. The data value for each cell is determined by a programmed (sometimes referred to as written) change in the cell's threshold voltage caused by programming of a charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization). Common uses of flash memory and other nonvolatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the use of nonvolatile memory continues to expand.

[0005] Memory cell arrays for NAND flash memory devices are typically arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. A column in the array contains a string of memory cells (often referred to as a NAND string) connected in series from source to drain between a pair of select transistors (e.g., between a source select transistor and a drain select transistor). Each source select transistor is connected to a source line, and each drain select transistor is connected to a data line, such as a column bit line. A column is a group of memory cells that are commonly coupled to a local data line, such as a local bit line. The column does not require any specific orientation or linear relationship, but rather refers to the logical relationship between the memory cells and the data lines.

[0006] To meet the demand for higher capacity memories, designers have been striving to increase memory density (e.g., the number of memory cells in a given area of ​​an integrated circuit die). One way to increase memory device density is to form stacked memory arrays (e.g., often referred to as three-dimensional memory arrays).

[0007] For example, memory cells at a common location in a stacked memory array (e.g., at a common vertical layer) can form a layer of memory cells. Memory cells in each layer can be coupled to one or more access lines, such as local access lines (e.g., local word lines), which are in turn selectively coupled to drivers via transistors (e.g., pass transistors). In some instances, memory cells in each layer can be commonly coupled to a common access line or board.

[0008] One way to increase memory density in non-volatile memory devices is by utilizing vertical memory array (e.g., three-dimensional (3D) memory array) architectures. Conventional vertical memory arrays comprise semiconductor pillars extending through openings in layers of conductive structures (e.g., word line layers or boards, control gate layers or boards) and insulating material at each junction of the semiconductor pillars and conductive structures. Compared to conventional planar (e.g., two-dimensional) arrangements with transistors, this configuration allows for a larger number of switching devices (e.g., transistors) to be positioned within cells of a die region by building the array upwards (e.g., longitudinally, vertically) on the die. A disadvantage is that as the vertical height of these semiconductor pillars increases, various defects can arise during manufacturing. Notably, as the height of the semiconductor pillars increases, the stacking can "lift" the underlying substrate, resulting in defective wafers. Summary of the Invention

[0009] One embodiment of this disclosure provides a semiconductor device comprising: a source plate; a plurality of plugs fabricated on or at least partially formed in the source plate; a stack formed on the substrate and the plurality of plugs, the stack including alternating insulating and conductive layers; a first set of pillars formed by a process extending through the stack, the process including etching the alternating insulating and conductive layers and depositing pillar material therein, wherein each pillar of the first set of pillars terminates on top of a corresponding plug of the plurality of plugs and forms a channel material memory cell string extending through the insulating and conductive layers; and a second set of pillars formed by a process extending through the stack, the process including etching the alternating insulating and conductive layers and depositing pillar material therein, wherein each pillar of the second set of pillars terminates in the source plate.

[0010] One embodiment of this disclosure provides a method of manufacturing a semiconductor device, comprising: depositing a silicon oxide layer on a source plate; depositing a photoresist layer on the silicon oxide layer; forming a plurality of holes in the silicon oxide layer via a mask pattern placed on top of the photoresist layer, the plurality of holes being formed on or at least partially in the source plate; depositing a conductive material layer in the plurality of holes; depositing a stack on the silicon oxide layer and the plurality of holes, the stack including alternating insulating and conductive layers; forming a first set of pillars on the plug by etching the alternating insulating and conductive layers and depositing pillar material therein; and forming a second set of pillars in the source plate by etching the alternating insulating and conductive layers and depositing pillar material therein. Attached Figure Description

[0011] The embodiments are illustrated by way of example rather than limitation in the figures of the accompanying drawings, in which similar references indicate similar elements.

[0012] Figure 1 This describes a memory system according to some embodiments, which has a controller for accessing data stored in a memory device.

[0013] Figure 2A This is a block diagram illustrating a block-enhanced 3D NAND memory according to some embodiments of the present disclosure.

[0014] Figure 2B and 2C This is a block diagram illustrating the stress distribution on a tungsten plug flush with a silicon oxide substrate according to some embodiments of the present disclosure.

[0015] Figures 3A to 3G This invention describes a manufacturing process for creating a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 4A This is a logical view of a memory block according to some embodiments of the present disclosure.

[0017] Figure 4B This is a top view of a portion of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figures 5A to 5G This invention describes a manufacturing process for creating a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 6A and 6B This is a block diagram illustrating the stress distribution on an inserted tungsten plug according to some embodiments of the present disclosure. Detailed Implementation

[0020] Generally, a 3D electronic device can be considered as a device formed by combining multilayer electronic devices (e.g., a device formed on another layer) using planar constructions (e.g., multiple devices on a single layer). Since the multiple layers in a 3D device can utilize substantially the same area on a substrate, the total density of the device (e.g., a memory device) can increase relative to the number of layers. Three-dimensional (3D) memories, memory cells, and methods of their manufacture and use are generally discussed herein.

[0021] As will be discussed, to prevent the stacking of conductive and insulating films (e.g., ONON stacking), the disclosed embodiments describe the use of “dummy” pillars in conjunction with active channel pillar etching. Although the active pillars terminate on plugs (e.g., tungsten plugs), the dummy pillars are etched deeper into the silicon substrate, thereby strengthening the connection between the stack and the substrate. Alternatively, or in combination with the foregoing, the plugs beneath the active pillars are partially inserted into the substrate to increase surface friction and distribute the pillar load throughout the substrate.

[0022] Figure 1 This describes a memory system 184 according to some embodiments, having a controller 190 that accesses data stored in a memory device 192. In one example, the memory array 120 is a three-dimensional (3D) memory array. In some embodiments, multiple memory arrays 120 may be used.

[0023] For example, the memory system 184 may be a solid-state drive (SSD), a multimedia card (MMC), a USB flash drive, a compact flash card (CF), a universal flash storage device (UFS), or other storage devices, and may include a host interface 188, a controller 190 (e.g., a processor and / or other control circuitry) providing storage capacity for the memory system 184, and a memory device 192 (e.g., a solid-state memory device, such as a NAND flash memory device). The memory device 192 may include one or more memory arrays 120.

[0024] In several embodiments, the controller 190, memory device 192, and / or host interface 188 may be physically located on a single die or within a single package (e.g., in managed NAND applications). In some embodiments, the controller 190, memory device 192, and / or host interface 188 are contained in a stack of dies within a package. In one example, the stacked dies include through-silicon vias (TSVs) for transmitting power and signals to each die. In some embodiments, the controller 190, memory device 192, and / or host interface 188 are soldered to a printed circuit board (PCB). The controller 190, memory device 192, and / or host interface 188 may be packaged, for example, in a BGA module, M.2 module, mSATA module, slimSATA module, flash memory card, embedded USB card, small form factor (SFF) disk format (e.g., SFF-2.5, SFF-1.8, etc.), or other form factors.

[0025] The memory device 192 includes a driver 121 for applying signals to word line layers of the memory array 120. In one embodiment, the controller 190 uses a first word line to access data stored in a first block of the memory array 120. Under the control of the controller 190, one of the drivers 121 is used to access data by applying signals to the first word line. The word line signals are applied to corresponding layers of the left and right block portions of the first block. These two layers logically correspond to the first word line. In one embodiment, each pair of corresponding layers is connected by the aforementioned conductive connector.

[0026] The controller 190 may be coupled to the host interface 188 and the memory device 192 via one or more channels, and may be used to transfer data between the memory system 184 and the host 182. The host interface 188 may be in the form of a standardized interface. For example, when the memory system 184 is used for data storage in a computing system, the host interface 188 may be a Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), Peripheral Component Interconnect High Speed ​​(PCIe), or Universal Serial Bus (USB), as well as other connectors and interfaces. However, generally, the host interface 188 provides an interface for transferring control, address, data, and other signals between the memory system 184 and the host 182 (e.g., a host computing device with a receiver compatible with the host interface 188).

[0027] The host 182 may be a host system, such as a personal laptop computer, desktop computer, server, embedded computer, digital camera, mobile phone, memory card reader, or other electronic device controlled by a processor, as well as various other types of host systems. The host 182 may include a system motherboard and / or backplane, and may include multiple memory access devices (e.g., multiple processors). The host 182 may be coupled to the host interface 188 via communication channel 186.

[0028] The controller 190 can communicate with the memory device 192 to control data read, write, and erase operations, as well as other operations, including equalization, discharging, and serial driver operations. The controller 190 may include, for example, hardware and / or firmware (e.g., one or more integrated circuits) and / or software components for controlling access to the memory device 192 and / or for facilitating data transfer between the host 182 and the memory device 192. In some embodiments, multiple memory devices may be used.

[0029] Memory device 192 may include multiple memory cell arrays. For example, the array may be a flash memory array with a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. Memory cells may, for example, be grouped into multiple blocks comprising multiple physical pages. Multiple blocks may be contained in a plane of memory cells, and the array may contain multiple planes.

[0030] In some embodiments, host 182 may be a computer (e.g., a mobile phone or other computing device) having one or more central processing units (CPUs), and computer peripherals such as memory system 184 may be attached to the central processing unit via interconnects such as a computer bus.

[0031] The memory system 184 can be used to store data from the host 182. Examples of the memory system 184 include solid-state drives, USB flash drives, multimedia cards (MMC), compact flash cards (CF), universal flash storage devices (UFS), memory cards, flash memory, or other memory devices.

[0032] The controller 190 can run firmware 104 to perform operations in response to communication from the host 182. Generally, firmware is a type of computer program that provides control, monitoring, and data manipulation of an engineered computing device. Figure 1 In this context, firmware 104 controls the operation of controller 190 when operating memory system 184, such as translating logical addresses into physical addresses to store and access data in memory device 192. In one example, controller 190 is an internal controller for a managed NAND device that stores data in TLC NAND flash memory.

[0033] Examples of non-volatile storage media used in memory array 120 are memory cells in integrated circuits (e.g., SLC, TLC, QLC). The storage medium is non-volatile because no power is required to maintain the data / information stored in it, and the data / information can be retrieved after the non-volatile storage medium is powered off and then powered on again. Various memory types (e.g., NAND-based flash memory, phase-change memory (PCM), magnetic RAM, resistive random access memory, and 3D XPoint) can be used to implement memory cells such that the storage medium is non-volatile and can retain the data stored therein for days, months, and / or years without power.

[0034] In one embodiment, during operation, controller 109 receives various commands from host 182. These commands may include read commands or write commands. In one instance, a read command includes a logical address and is received from host 182 to access data stored in the non-volatile storage medium of memory array 120.

[0035] In one instance, controller 190 receives a logical address and determines a physical address. The determined physical address is used to read the portion of stored data corresponding to the received logical address. Controller 190 then sends the read data to host 182. In some cases, controller 190 has multiple processors, each with its own in-processor cache.

[0036] The storage system 184 can be used in various computing systems, such as cloud computing systems, edge computing systems, fog computing systems, and / or standalone computers. In cloud computing systems, remote computer servers are connected to a network to store, manage, and process data. Edge computing systems optimize cloud computing by performing data processing at the edge of a computer network, close to the data source, and thus reduce data communication with centralized servers and / or data storage devices.

[0037] At least some embodiments of this disclosure may be implemented using computer instructions executed by controller 190 (e.g., firmware 104). In some cases, hardware circuitry may be used to implement at least some functions of firmware 104. Firmware 104 may be initially stored in a non-volatile storage medium of memory array 120 or another non-volatile device and loaded into volatile memory (not shown) and / or in-processor cache memory for execution by controller 190.

[0038] Non-transitory computer storage media may be used to store instructions for firmware 104. When executed by controller 190 of memory system 184, the instructions cause controller 190 or other processing means to perform the methods as described herein.

[0039] In one embodiment, a local manager (not shown) of memory system 184 receives data access commands. Data access requests (e.g., read, write) from host 182 identify LBA addresses to read, write, or erase data from memory cells identified by the LBA addresses. The local manager translates logical addresses into physical addresses.

[0040] In one embodiment, the controller is implemented by one or more processing devices. For example, the processing device may be a microprocessor, a central processing unit (CPU), a processor core, an execution unit, an embedded processor, an embedded controller, a graphics processor, etc. For example, the processing device may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), etc.), or another suitable processor. The processing device may consist of a single processor with a single processing core, a single processor with multiple processing cores, or multiple processors.

[0041] In some embodiments, the controller includes a host I / O management component, a flash translation layer (FTL), and a memory cell management component.

[0042] In embodiments where the memory (e.g., non-volatile storage media) comprises an array of multiple memory cells, the array may be, for example, a flash memory array with a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. Memory cells may, for example, be grouped into multiple blocks, which are erased together as a group, and each block may store multiple data pages. Multiple blocks may be contained in a plane of memory cells, and the array may contain multiple planes. As used herein, a "data page" refers to the amount of data that a controller is configured to write to / read from a non-volatile storage medium as part of a single write / read operation, and may be referred to as a "flash memory page." As an example, a memory device may have a page size of 8 KB (kilobytes) and may be configured to store 128 data pages per block, 2048 blocks per plane, and 16 planes per device.

[0043] Unlike traditional hard disk drives, data stored in a flash memory array cannot be directly overwritten. That is, a flash memory block must be erased before data can be rewritten to it (e.g., one page at a time). In some embodiments, the controller manages the transfer of data between the host processor and the flash memory array via a logical-to-physical mapping scheme. For example, the flash translation layer may employ a logical addressing scheme (e.g., logical block addressing (LBA)). As an example, when new data received from the host processor replaces older data already written to the flash memory array, the controller may write the new data to a new location on the non-volatile storage medium and update the logical-to-physical mapping of the FTL so that the corresponding logical address associated with the new data being written indicates (e.g., points to) the new physical location. The old location, which no longer stores valid data, will be erased before being written again.

[0044] Figure 2A This is a diagram illustrating a memory block boosting according to some embodiments of the present disclosure.

[0045] In the illustrated embodiment, alternating stacks of conductive and insulating materials (202) are located above the source plate (212) and the silicon oxide layer (206). In one embodiment, the stack (202) includes a stack of memory cells having multiple charge storage structures (e.g., floating gates, charge traps, etc.), a stack of alternating control gates and insulating or insulating materials, and a charge blocking material disposed between the charge storage structure (hereinafter referred to by example primarily as a floating gate) and the adjacent control gate. For example, oxide materials of silicon oxide are conventionally used as insulating materials. The charge blocking material may be an inter-polysilicon insulating (IPD) material, such as an oxide-nitride-oxide (ONO) material.

[0046] In the illustrated embodiment, a plurality of pillars (204) are etched into a stack (202) terminating at corresponding plugs (208). In the illustrated embodiment, the pillars (204) extend from the upper portion of the stack (202) to a horizontal plane adjacent to the upper surface of the silicon oxide layer (206) within the stack (202). Each of the pillars (204) may have a high aspect ratio. The aspect ratio of a pillar is defined as the ratio of the depth of an opening to the diameter of an opening. For example, the depth (e.g., length) of the opening of a pillar may be about 2 μm, and the diameter of the opening of a pillar may be about 60 to 100 nm. In some embodiments, the opening of a pillar may have an insulating liner (not shown) formed (e.g., deposited) on the inner wall of the pillar. Thus, the high aspect ratio of the opening may be, for example, between about 20 and 33. In some embodiments, the insulating liner may comprise an oxide material or a nitride material.

[0047] In the illustrated embodiment, the silicon oxide layer (206) on the bottom of the stack (202) includes a plurality of plugs (e.g., tungsten plugs) (208). In the illustrated embodiment, the plugs (208) act as etch-reach layers to stop further etching during the device formation process and also act as conductive contacts to provide electrical contact between polysilicon channels formed in the stack (202) and subsequent polysilicon channels in the stack (202) during device operation.

[0048] In the illustrated embodiment, an air gap (210) exists between the silicon oxide layer (206) and the source plate (212). This air gap (210) is generated during the fabrication of the memory wafer in the illustrated embodiment. Specifically, as the number of alternating layers in the stack (202) increases, the through-hole etching process (or similar etching process) used to connect the pillars to the substrate and / or source plate (212) cannot reach the substrate and / or source plate (212), resulting in pillars being lifted from the substrate and / or source plate (212). When lifted from the substrate and / or source plate (212), the transistors formed in the pillars (204) become inoperable. Furthermore, even when not "lifted" from the substrate and / or source plate (212), the arrangement of the plugs (208) in FIG. 2a exhibits negative stress characteristics around the plugs (208), which is discussed below. Figure 2B and 2C To describe it simply.

[0049] As in Figure 2B As explained, the stress distribution terminates at the end of the support pillar and is directly distributed at the interface between the silicon oxide layer (206) and the substrate and / or the source plate (212). Additionally, as... Figure 2CAs described, surface friction is applied to the plug (208) itself from the surrounding silicon oxide layer (206). In addition to the foregoing, the stress distribution of the plug (208) also helps to lift the ONON stack (202) from the source plate (212). Figure 2B and 2C This is a block diagram illustrating the stress distribution on a tungsten plug flush with a silicon oxide substrate according to some embodiments of the present disclosure. (As shown in...) Figure 2B As explained, the stress in the support (204) terminates at the end of the support and is directly distributed on the upper surface of the silicon oxide layer (206). Additionally, some stress is deposited vertically on the surface of the silicon oxide layer (206) surrounding the plug (208). Furthermore, as... Figure 2C As depicted, surface friction pressure is applied to the plug (208) itself from the surrounding silicon oxide layer (206). The result is that the net force pushes the plug (208) and the silicon oxide layer (206) away from the source plate (212).

[0050] Figures 3A to 3G It is a cross-sectional view illustrating the manufacturing process used to create semiconductor devices. Figures 3A to 3G The specific number of steps described herein is exemplary, and more steps may be employed as discussed.

[0051] Figure 3A The source plate (302) is described. In the described embodiment, the source plate (302) includes a silicon substrate and one or more fabrication layers forming source gates for a string of transistor elements.

[0052] The source plate (302) includes a silicon substrate subjected to various manufacturing processes to form source lines. Specific steps used to form the source lines are not intended to be limiting. As an example, in some embodiments, a tungsten silicide (WSix) layer may be deposited on top of the source plate (302). Next, a polysilicon layer may be deposited on top of the WSix. Subsequently, a photoresist may be layered on top of the polysilicon. The WSix and polysilicon can then be dry-etched or wet-etched using the photoresist to form source lines in the source plate (302). Generally, any manufacturing technique known in the art for producing select gates (SGS) can be used in the fabrication of the source plate (302). It is worth noting that... Figure 3A The embodiments described do not explicitly illustrate, for example, the various layers of polysilicon or WSix used to form the source wire.

[0053] exist Figure 3B In this process, a silicon oxide (304) layer is then deposited on the fully formed source plate (302). In some embodiments, the silicon oxide layer (304) is formed using tetraethyl orthosilicate (TEOS) deposition.

[0054] exist Figure 3CIn this process, a photoresist layer (316) is deposited on top of a silicon oxide layer (304). The photoresist layer (316) may include photopolymerized, photodecomposed, photocrosslinked photoresists or other suitable photoresists. Figure 3C In this process, a mask pattern is placed on top of the photoresist layer. As will be discussed, the mask is patterned to create multiple holes spaced apart throughout the photoresist.

[0055] Next, in Figure 3D In this process, multiple "holes" (314) are formed into the silicon oxide layer (304) via a photoresist (316). It is noteworthy that... Figure 3C and 3D The photolithography process is configured to etch plugs only below the active column locations where the 3D NAND array will be formed.

[0056] exist Figure 3E In this process, after etching the plug position (314), tungsten (W) is used to fill the etched cavity, thereby forming the plug (306). In some embodiments, tungsten plug chemical mechanical polishing (WCMP) may be applied additionally after forming the tungsten plug. In some embodiments, conductive materials other than tungsten may be used.

[0057] exist Figure 3E At the end of the processing stage described herein, a plurality of plugs (306) are formed on the source plate (302), each plug (306) being located below the active pillar of the resulting 3D NAND device.

[0058] exist Figure 3F In this configuration, multiple conductive and insulating layers are deposited on top of a silicon oxide layer (304) to form a stack (312). In one embodiment, the conductive layer comprises a silicon oxide layer, and the insulating layer comprises a silicon nitride layer. In the illustrated embodiment, a first insulating layer is deposited on the silicon oxide layer (304), followed by a second conductive layer, followed by a second insulating layer, and so on. In some embodiments, the alternating layers of silicon oxide and silicon nitride are referred to as an "ONON" stack. As is known in the art, the ONON stack (312) can be used to form individual memory cells or transistors via through-hole etching or tunnel etching.

[0059] exist Figure 3G In this process, after the deposition stack (312), a plurality of pillars (308, 310) are etched into the stack (312). In one embodiment, a hard mask is deposited on top of the stack (312). In some embodiments, the hard mask includes a pillar pattern (illustrated in more detail in FIG4). Generally, the pillar pattern defines a plurality of circular openings in which the pillars (308, 310) are located. In some embodiments, the pillar openings are separated by larger gaps between the sub-blocks forming the transistor matrix.

[0060] Once a hard mask is applied, a high aspect ratio (HAR) etching is performed to etch the pillars (308, 310) into the stack (312). In some embodiments, the insulating (e.g., nitride) layer of the stack can be removed and tungsten is applied via a inside-out tungsten deposition process. If the nitride layer of the ONON stack is removed in this manner, an OWOW stack can be used instead of the ONON stack.

[0061] In the illustrated embodiment, compared to conventional etching, the embodiment includes additional “dummy” pillars (310). In the illustrated embodiment, the first set of pillars (308) is etched and terminates at corresponding plugs (306). In the illustrated embodiment, the plugs (306) comprise tungsten plugs. Conversely, the dummy pillars (310) terminate deeper in the source plate (302). In the illustrated embodiment, the dummy pillars (310) terminate at a distance D from the upper surface of the source plate. Because the dummy pillars (310) are not located above the plugs (306), the HAR etching penetrates the stack (312) and partially enters the source plate (302). Conversely, the use of tungsten plugs (306) prevents higher power HAR etching from penetrating into the substrate, thereby forming on Figure 3G The serrated support structure depicted in the painting.

[0062] In subsequent steps, a dummy pillar (310) identical to the active pillar (308) is further formed. That is, in some embodiments, both sets of pillars (308, 310) are lined with a polysilicon coating and subsequently filled with silicon dioxide. However, since the dummy pillar (310) is not used to store information, the dummy pillar does not affect the operation of the active pillar (308).

[0063] Each of the materials described herein can be applied, deposited, or otherwise formed according to techniques and methods independently known in the art. These techniques and methods may include one or more deposition activities, such as chemical vapor deposition (CVD), atomic-level deposition (ALD), physical vapor deposition (PVD), or other techniques. A variety of materials can be formed at various levels via stacked deposition operations.

[0064] While the process actions and operations described herein may refer to specific conductors, semiconductors, or insulating materials, such as silicon, silicon dioxide, silicon nitride, or others, those skilled in the art who are familiar with this disclosure will recognize that other conductors, semiconductors, and insulating materials may be substituted and remain within the scope of the disclosed subject matter. Therefore, the presented material options and selections are provided merely as an aid to understanding one example of the manufacturing process.

[0065] For example, various types of semiconductor materials (e.g., single-crystal or amorphous silicon, germanium, other elemental semiconductor materials, compound semiconductor materials, etc.) can be used as alternatives to other types of semiconductor materials or in combination with other types of semiconductor materials. Additionally, various types of insulating materials, such as tantalum pentoxide (Ta₂O₅) and silicon nitride (SiO₂), can also be used. x N y Alumina (Al₂O₃), hafnium oxide (HfO₂), and various other organic or inorganic insulating materials may be used as alternatives to or in combination with the other described materials. Furthermore, various other combinations of materials may be substituted for or included. For example, in some applications, the described semiconductor materials may be replaced by conductor materials, including, for example, silver (Ag), copper (Cu), aluminum (Al), zinc (Zn), platinum (Pt), tungsten (W), titanium (Ti), or tantalum (Ta).

[0066] Furthermore, the various constructions, processes, and other discussions described below may refer to a material, for example, placed "on," "above," or "on top of" another material. These descriptors are relative terms and obviously depend on the precise orientation of any resulting device. However, those skilled in the art will readily understand the context of these relative terms upon reading and understanding the disclosure provided herein in conjunction with the accompanying drawings.

[0067] Figure 4A This is a logical view of a memory block according to some embodiments of the present disclosure. In the illustrated embodiments, in Figure 4A The views presented include cross-sectional views of memory blocks.

[0068] In the illustrated embodiment, a given memory block (400a) is positioned in series with a plurality of other memory blocks (402a, 404a). The memory blocks (400a, 402a, 404b) are substantially similar in design.

[0069] A given memory block (400a) contains a plurality of bit lines (BL0-BL3). The specific number of bit lines is not intended to be limiting. In the illustrated embodiment, the bit lines are connected via... Figures 3A to 3GThe stacking of conductive insulating layers described in 5A to 5G is also used. In the illustrated embodiment, the source plate of a given block (400a) includes a shared select gate source (SGS1) and a write line (WL1). As illustrated, multiple bit lines share a single SGS, unlike memories where each bit line contains a dedicated SGS and WL transistor structure. Therefore, the block (400a) includes a "merged block" where a single SGS layer controls access to multiple bit lines (BL0-BL3). As in existing memories, the write line WL1 implements the writing of transistors into the bit lines (BL0-BL3). Additionally, as illustrated, each bit line (BL0-BL3) has a dedicated select gate drain (SGD0-SGD3) transistor to implement the output from the bit line (BL0-BL3) to the word line.

[0070] In the illustrated embodiment, each bit line (BL0-BL3) includes a plurality of vertically formed transistor elements. As previously described, these bit lines are formed by etching transistors through layering conductive and insulating materials and etching via pillars. Details of this fabrication process have been previously described and will not be repeated herein.

[0071] In the illustrated embodiment, blocks (400a, 402a, 404a) are separated to form a logical partition of memory cells. In the illustrated embodiment, blocks (400a, 402a, 404a) are separated by slots (406a). In one embodiment, these slots comprise an unetched stack of conductive insulating material. For example, turning... Figure 3F This allows for simple segmentation between memory blocks without etching the stack (312).

[0072] Conversely, the individual bit lines (BL0-BL3) are separated by slits (408a). In one embodiment, the slits (408a) correspond to pillars (310). In the illustrated embodiment, the slits (408a) are formed via through-hole etching when forming the pillars for forming transistors in the positioning lines. However, the aforementioned plug layer is used to vary the depth of the pillars during formation. Details of this manufacturing process have been described and are further described herein.

[0073] Figure 4B This is a top view of a portion of a semiconductor structure according to some embodiments of the present disclosure. In the illustrated embodiments, Figure 4B Provides Figure 4A A top-down view of the larger surface area of ​​the cross-sectional memory block.

[0074] In the illustrated embodiment, a single block (400a) depicting the bit line (402b) (e.g., Figure 4AThe merged block (400a) partially depicts portions of other blocks (402a, 404a). Block (400a) is separated from other blocks via a slot (406a). A slit (408a) provides column separation between the bit lines (402b) of the merged block (400a).

[0075] As in Figures 3A to 3G As described in the process, trench columns are etched through stacked conductive insulating layers to form bit lines (402b). As discussed, each of these columns terminates on a plug formed on top of the source plate. In contrast, the staggered groups of dummy pillars (408a) are etched deeper into the substrate and do not terminate on plugs.

[0076] Figures 5A to 5D This describes the manufacturing process used to create 3D NAND flash memory.

[0077] Figure 5A The source plate (302) is described. In the illustrated embodiment, the source plate (302) includes a silicon substrate and one or more fabrication layers forming source gates for a string of transistor elements. The source plate (302) includes a silicon substrate subjected to various fabrication processes to form source lines. Specific steps for forming the source lines are not intended to be limiting. As an example, in some embodiments, a tungsten silicide (WSix) layer may be deposited on top of the source plate (302). Next, a polysilicon layer may be deposited on top of the WSix. Subsequently, a photoresist may be layered on top of the polysilicon. The WSix and polysilicon may then be etched using the photoresist to form source lines in the source plate (302). Generally, any fabrication technique known in the art for producing select gates (SGS) can be used in the fabrication of the source plate (302). It is worth noting that... Figure 3A The embodiments described do not explicitly illustrate, for example, the various layers of polysilicon or WSix used to form the source wire.

[0078] exist Figure 5B In this process, a silicon oxide (304) layer is deposited on the fully formed source plate (302). In some embodiments, the silicon oxide layer (304) is formed using tetraethyl orthosilicate (TEOS) deposition.

[0079] In Figure 5c, a photoresist layer (316) is deposited on top of the silicon oxide layer (304). The photoresist layer (316) may include photopolymerized, photodecomposed, photocrosslinked photoresists or other suitable photoresists. Figure 3C In this process, a mask pattern is placed on top of the photoresist layer. As will be discussed, the mask is patterned to create multiple holes spaced apart throughout the photoresist.

[0080] Next, multiple "holes" are etched into the silicon oxide layer (304) and the source plate (302) via photoresist patterning and dry etching. These holes (502) are located at the locations of the plugs (506). Notably, in one embodiment, the photolithography used in this sub-stage is configured to etch the plugs only below the active column locations where the 3D NAND array will be formed.

[0081] exist Figure 5E In the middle, after etching the plug position, in Figure 5C In the next stage described herein, tungsten is used to fill the etching cavity, thereby forming a plug (506). In some embodiments, tungsten plug chemical mechanical polishing (WCMP) may be applied additionally after the tungsten plug is formed. In some embodiments, conductive materials other than tungsten may be used.

[0082] exist Figure 5F In this configuration, multiple conductive and insulating layers are deposited on top of a silicon oxide layer (304) to form a stack (312). In one embodiment, the conductive layer comprises a silicon oxide layer, and the insulating layer comprises a silicon nitride layer. In the illustrated embodiment, a first insulating layer is deposited on the silicon oxide layer (304), followed by a second conductive layer, followed by a second insulating layer, and so on. In some embodiments, the alternating layers of silicon oxide and silicon nitride are referred to as an "ONON" stack. As is known in the art, the ONON stack (312) can be used to form individual memory cells or transistors via through-hole etching or tunnel etching.

[0083] Finally, Figure 5G In the process, the stack (312) and pillars (308, 310) are etched. In the illustrated embodiment, this process is as follows: Figure 3G The execution described herein will not be repeated here. However, as mentioned, the active support (308) is located on the partially inserted plug (506). As in Figure 6A and 6B As described in the discussion, the design of this partially inserted plug can be optional, which moves the stress distribution path at the end of the pillar from the interface between the silicon oxide layer (304) and the substrate and / or the source plate (302) into the substrate and / or the source plate (302), and in conjunction with the dummy pillar to prevent lift. Furthermore, in some embodiments, the dummy pillar may not be used at all, and the partially inserted plug may be used to reinforce the active pillar.

[0084] Each of the materials described herein can be applied, deposited, or otherwise formed according to techniques and methods independently known in the art. These techniques and methods may include one or more deposition activities, such as chemical vapor deposition (CVD), atomic-level deposition (ALD), physical vapor deposition (PVD), or other techniques. A variety of materials can be formed at various levels via stacked deposition operations.

[0085] While the process actions and operations described herein may refer to specific conductors, semiconductors, or insulating materials, such as silicon, silicon dioxide, silicon nitride, or others, those skilled in the art who are familiar with this disclosure will recognize that other conductors, semiconductors, and insulating materials may be substituted and remain within the scope of the disclosed subject matter. Therefore, the presented material options and selections are provided merely as an aid to understanding one example of the manufacturing process.

[0086] For example, various types of semiconductor materials (e.g., single-crystal or amorphous silicon, germanium, other elemental semiconductor materials, compound semiconductor materials, etc.) can be used as alternatives to other types of semiconductor materials or in combination with other types of semiconductor materials. Additionally, various types of insulating materials, such as tantalum pentoxide (Ta₂O₅) and silicon nitride (SiO₂), can also be used. x N y Alumina (Al₂O₃), hafnium oxide (HfO₂), and various other organic or inorganic insulating materials may be used as alternatives to or in combination with the other described materials. Furthermore, various other combinations of materials may be substituted for or included. For example, in some applications, the described semiconductor materials may be replaced by conductor materials, including, for example, silver (Ag), copper (Cu), aluminum (Al), zinc (Zn), platinum (Pt), tungsten (W), titanium (Ti), or tantalum (Ta).

[0087] Furthermore, the various constructions, processes, and other discussions described below may refer to a material, for example, placed "on," "above," or "on top of" another material. These descriptors are relative terms and obviously depend on the precise orientation of any resulting device. However, those skilled in the art will readily understand the context of these relative terms upon reading and understanding the disclosure provided herein in conjunction with the accompanying drawings.

[0088] Figure 6A and 6B This is a block diagram illustrating the stress distribution on an inserted tungsten plug according to some embodiments of the present disclosure. (As shown in...) Figure 6A As explained, when the plug (506) is further inserted into the source plate (302) and passes through the silicon oxide layer (304), the downward stress distribution is distributed within the substrate itself, thus firmly fixing the support within the substrate itself. Furthermore, as in... Figure 6B As explained, the surface friction applied to the plug (506) is also distributed in both the silicon oxide layer (304) and the source plate (302), the source plate further holding the plug and the support above the plug.

[0089] This disclosure includes various means for performing the methods and implementing the systems described above, including a data processing system for performing these methods, and a computer-readable medium containing instructions that, when executed on the data processing system, cause the system to perform the methods.

[0090] The descriptions and figures are illustrative and should not be construed as limiting. Many specific details are described to provide a thorough understanding. However, in some cases, well-known or conventional details are omitted to avoid obscuring the description. References to one or more embodiments in this disclosure do not necessarily refer to the same embodiment; and such references imply at least one.

[0091] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. The appearance of the phrase "in one embodiment" at various points in this specification does not necessarily refer to the exact same embodiment, nor is it a single or alternative embodiment that must be mutually exclusive with other embodiments. Furthermore, various features that may be manifested by some embodiments but not by others are described. Similarly, various requirements are described that may be requirements of some embodiments but not by others.

[0092] In this description, various functions and operations may be described as being executed or caused by software code for the sake of simplicity. However, those skilled in the art will recognize that such expressions mean that the functions are caused by the execution of code by one or more processors, such as microprocessors, application-specific integrated circuits (ASICs), graphics processors, and / or field-programmable gate arrays (FPGAs). Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems (e.g., logic circuit systems) with or without software instructions. Embodiments may be implemented using hardwired circuit systems without software instructions or in combination with software instructions. Therefore, the techniques described are neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a computing device.

[0093] While some embodiments may be implemented in fully functional computers and computer systems, various embodiments can be distributed as a variety of computing products, and are applicable regardless of the particular type of machine or computer-readable medium used to actually implement the distribution.

[0094] At least some of the disclosed aspects may be embodied, at least in part, in software. That is, the technology can be performed in a computing device or other system in response to its processor (e.g., a microprocessor) executing a sequence of instructions contained in memory (e.g., ROM, volatile RAM, non-volatile memory, cache memory, or remote storage device).

[0095] The routines executed to implement the embodiments can be implemented as part of an operating system, middleware, business delivery platform, software development kit (SDK) component, network service, or other specific application, component, program, object, module, or sequence of instructions referred to as a "computer program." The calling interface to these routines can be exposed to the software development community as an application programming interface (API). A computer program typically includes one or more sets of instructions stored in various memories and storage devices within a computer at various times, and these sets of instructions, when read and executed by one or more processors in the computer, cause the computer to perform operations necessary for carrying out various aspects.

[0096] Machine-readable media can be used to store software and data that, when executed by a computing device, cause the device to perform various methods. Executable software and data can be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache memory. A portion of this software and / or data can be stored in any of these storage devices. Furthermore, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of data and instructions can be obtained at different times and in different communication sessions or in the same communication session from different centralized servers and / or peer-to-peer networks. All data and instructions can be obtained before application execution. Alternatively, portions of data and instructions can be obtained dynamically and as needed for execution. Therefore, it is not required that all data and instructions be on the machine-readable media at any given time.

[0097] Examples of computer-readable media include, but are not limited to, recordable and non-recordable media, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, disk storage media, optical storage media (e.g., optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), etc.) and other media. Computer-readable media can store instructions.

[0098] Generally speaking, tangible or non-transitory machine-readable media includes any entity that provides (e.g., stores) information in a form accessible to a machine (e.g., a computer, mobile device, network device, personal digital assistant, manufacturing tool, any device having one or more processors, etc.).

[0099] In various embodiments, hardwired circuitry systems can be used in combination with software and firmware instructions to implement the technology. Therefore, the technology is neither limited to any particular combination of hardware circuitry systems and software, nor to any particular source of instructions executed by a computing device.

[0100] Various types of computing devices can be used to implement the various embodiments described herein. As used herein, examples of "computing device" include, but are not limited to, servers, centralized computing platforms, systems with multiple computing processors and / or components, mobile devices, user terminals, vehicles, personal communication devices, wearable digital devices, electronic self-service terminals, general-purpose computers, electronic document readers, tablet computers, laptops, smartphones, digital cameras, home appliances, televisions, or digital music players. Additional examples of computing devices include portions of devices referred to as "Internet of Things" (IoT). Such "things" may interact incidentally with their owners or administrators who can monitor or modify settings on these things. In some cases, such owners or administrators act as users of the "thing" devices. In some instances, a user's primary mobile device (e.g., an Apple iPhone) may act as an administrator server for paired "thing" devices worn by the user (e.g., an Apple Watch).

[0101] In some embodiments, the computing device may be a computer or a host system, such as a desktop computer, a laptop computer, a web server, a mobile device, or other computing device including memory and processing means. The host system may include or be coupled to a memory subsystem, such that the host system can read data from or write data to the memory subsystem. The host system may be coupled to the memory subsystem via a physical host interface. Generally, the host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0102] In some embodiments, a computing device is a system that includes one or more processing devices. Examples of processing devices may include a microcontroller, a central processing unit (CPU), a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), a system-on-a-chip (SoC), or another suitable processor.

[0103] Although some of the accompanying figures illustrate multiple operations in a specific order, non-orderly dependent operations can be reordered and other operations can be combined or decomposed. While some reorderings or other groupings are specifically mentioned, other reorderings or groupings will be apparent to those skilled in the art, and therefore an exhaustive list of alternatives is not provided. Furthermore, it should be recognized that stages can be implemented using hardware, firmware, software, or any combination thereof.

[0104] In the foregoing description, this disclosure has been described with reference to specific exemplary embodiments of the invention. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A semiconductor device comprising: a source plate; a plurality of plugs fabricated on the source plate or at least partially formed in the source plate; a stack formed on the source plate and plurality of plugs, the stack comprising alternating insulating layers and conductive layers; a first set of pillars formed by a process that includes etching the alternating insulating layers and conductive layers and depositing a pillar material therein, the first set of pillars extending through the stack, wherein each pillar in the first set of pillars terminates on a respective plug in the plurality of plugs and forms a channel material memory cell string extending through the insulating layers and conductive layers; and a second set of pillars formed by a process that includes etching the alternating insulating layers and conductive layers and depositing a pillar material therein, the second set of pillars extending through the stack, wherein each pillar in the second set of pillars terminates in the source plate.

2. The device of claim 1, wherein the source plate comprises a silicon substrate.

3. The device of claim 2, wherein the source plate further comprises one or more layers forming a source gate.

4. The device of claim 3, wherein the source gate conductively contacts each of the first set of pillars.

5. The device of claim 4, wherein the source gate does not conductively contact any of the second set of pillars.

6. The device of claim 1, wherein the plurality of plugs comprises a plurality of tungsten plugs.

7. The device of claim 1, wherein the insulating layers comprise silicon nitride and the conductive layers comprise silicon oxide.

8. A method of fabricating a semiconductor device comprising: depositing a layer of silicon oxide on a source plate; depositing a layer of photoresist on the layer of silicon oxide; forming a plurality of holes in the layer of silicon oxide via a mask pattern placed on top of the layer of photoresist, the plurality of holes formed on or at least partially formed in the source plate; depositing a layer of conductive material in the plurality of holes; depositing a stack on the layer of silicon oxide and plurality of holes, the stack comprising alternating insulating layers and conductive layers; forming a first set of pillars on the layer of conductive material by etching the alternating insulating layers and conductive layers and depositing a pillar material therein; and forming a second set of pillars in the source plate by etching the alternating insulating layers and conductive layers and depositing a pillar material therein.

9. The method of claim 8, wherein the source plate is fabricated by: depositing a layer of tungsten silicide, WSix, on a silicon substrate; depositing a layer of polysilicon on the layer of WSix; depositing a photoresist on the layer of polysilicon; forming a plurality of source lines in the source plate via dry or wet etching.

10. The method of claim 8, wherein the layer of silicon oxide is deposited via tetraethyl orthosilicate (TEOS) deposition.

11. The method of claim 8, the layer of photoresist comprising a photopolymerized, photodecomposed, or photocrosslinked photoresist layer.

12. The method of claim 8, wherein the plurality of holes are formed below a string of channel material of memory cells extending through the insulating layer and conductive layer.

13. The method of claim 8, the conductive material comprising tungsten.

14. The method of claim 13, further comprising applying tungsten plug chemical mechanical polishing (WCMP) after depositing the layer of tungsten.

15. The method of claim 8, wherein forming the first and second sets of pillars comprises depositing a hard mask on the stack, the hard mask comprising a pillar pattern defining the first and second sets of pillars.

16. The method of claim 15, wherein etching the first and second sets of pillars comprises performing a high aspect ratio etch through the stack.

17. The method of claim 8, further comprising removing the insulating layer of the stack and depositing tungsten on the conductive layer via an in-out tungsten deposition process.

18. The method of claim 8, further comprising depositing a polysilicon coating in the first and second sets of pillars.

19. The method of claim 18, further comprising depositing silicon dioxide on the polysilicon coating.

20. The method of claim 8, wherein the insulating layer comprises silicon nitride and the conductive layer comprises silicon oxide.

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