Semiconductor device, manufacturing method and three-dimensional memory

Abstract

The present invention provides a semiconductor device, a manufacturing method and a three-dimensional memory. The manufacturing method of the semiconductor device includes: forming a semiconductor structure, the semiconductor structure including a substrate, a stack structure including alternatingly stacked gate layers and insulating layers located on the substrate, a channel structure penetrating the stack structure and extending into the substrate, and a gate line gap penetrating the stack structure and dividing the stack structure into several parts; forming a first filling layer in the gate line gap; forming a second filling layer on at least a portion of the inner wall of the first filling layer; wherein the material of the first filling layer includes oxide, the material of the second filling layer includes amorphous silicon, the first filling layer and the second filling layer constitute a gate line gap structure, and by forming the first filling layer and the second filling layer with different materials in the gate line gap, the warping value of the semiconductor device in the horizontal direction and the vertical direction is adjusted, thereby improving the warping problem of the semiconductor device and improving the product yield of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method and a three-dimensional memory. Background Art

[0002] Flash memory has experienced rapid growth in recent years. Its key features include its ability to retain stored information for long periods without power, high integration, fast access speeds, and ease of erasure and rewriting. Consequently, it has found widespread application in a variety of fields, including microcomputers and automated control. Against this backdrop, three-dimensional NAND flash memory (3D NAND Flash) has emerged to address the challenges of planar flash memory and achieve lower unit cell production costs. 3D NAND flash memory consists of alternating layers of data storage cells, transforming a planar structure into a three-dimensional one, thereby increasing its storage density and integration. 3D NAND flash memory can accommodate higher storage capacity in a smaller footprint, resulting in significant cost savings, reduced energy consumption, and significant performance improvements to fully meet the needs of numerous consumer mobile devices and the most demanding enterprise deployments.

[0003] As the number of stacked layers in three-dimensional memory increases, controlling stress in the memory becomes increasingly important. However, the gate line slit structure in the memory creates significant stress, which can cause wafer warping during the manufacturing process, potentially reducing product yield.

[0004] Therefore, the existing technology has defects and needs to be improved and developed. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor device, a manufacturing method and a three-dimensional memory, which can effectively improve the warping problem of the semiconductor device and improve the product yield of the semiconductor device.

[0006] In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising: forming a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure located on the substrate and comprising alternatingly stacked gate layers and insulating layers, a channel structure penetrating the stack structure and extending into the substrate, and a gate line gap penetrating the stack structure and dividing the stack structure into several parts; forming a first filling layer in the gate line gap; forming a second filling layer on at least a portion of the inner wall of the first filling layer; wherein the material of the first filling layer comprises oxide, and the material of the second filling layer comprises amorphous silicon.

[0007] Wherein, after the second filling layer is formed on at least a portion of the inner wall of the first filling layer, the method further comprises:

[0008] Perform in-situ annealing.

[0009] The step of forming a first filling layer in the gaps between the gate lines specifically includes:

[0010] A first filling layer is formed in the gate line gap by a deposition process, so that at least a portion of the first filling layer is located at the bottom of the gate line gap.

[0011] The material of the second filling layer is doped with carbon element.

[0012] Before the second filling layer is formed on at least a portion of the inner wall of the first filling layer, the method further comprises:

[0013] Part of the inner wall forming the bottom of the gate line gap in the stacked structure is removed, so that the bottom of the gate line gap extends into the substrate.

[0014] The channel structure includes a functional layer, a channel layer, and an isolation layer formed in sequence from the outside to the inside in the radial direction, and after the second filling layer is formed on the inner wall of the first filling layer, further includes:

[0015] removing the substrate;

[0016] removing a portion of the functional layer at the end of the channel structure to expose the channel layer at the end of the channel structure;

[0017] A source region is formed, wherein the stack structure includes a front side and a back side facing each other, the back side is the side close to the substrate, the source region is located on the back side of the stack structure, and the source region covers the end of the channel structure and the gate line gap structure.

[0018] After removing the substrate, the method further includes:

[0019] A portion of the first filling layer at the end of the gate line gap structure is removed to expose the second filling layer at the end of the gate line gap structure so as to be connected with the source region after the source region is formed.

[0020] The first filling layer has a first thickness in the second direction, the second filling layer has a second thickness in the second direction, and the ratio of the first thickness to the second thickness ranges from 1 / 10 to 10.

[0021] Before forming the first filling layer in the gate line gap, the method further includes:

[0022] A spacer layer is formed in the gap between the gate lines.

[0023] In order to solve the above problems, an embodiment of the present application further provides a semiconductor device, comprising: a source region;

[0024] A stacking structure located on the source region includes alternately stacked gate layers and insulating layers; a channel structure penetrating the stacking structure and extending into the source region, the channel structure including a functional layer, a channel layer and an isolation layer formed radially from the outside to the inside, the channel layer at the end of the channel structure extending into the source region and connected to the source region; a gate line gap structure penetrating the stacking structure and extending into the source region to divide the stacking structure into several parts, the gate line gap structure including a first filling layer and a second filling layer formed in sequence from the outside to the inside; wherein the material of the first filling layer includes oxide, and the material of the second filling layer includes amorphous silicon.

[0025] The material of the second filling layer is doped with carbon element.

[0026] The second filling layer extends into the source region and is connected to the source region.

[0027] Part of the first filling layer in the first direction is located between the end of the second filling layer and the source region.

[0028] The first filling layer has a first thickness in the second direction, the second filling layer has a second thickness in the second direction, and the ratio of the first thickness to the second thickness ranges from 1 / 10 to 10.

[0029] In order to solve the above problems, an embodiment of the present application further provides a three-dimensional memory, which includes a first chip and a second chip bonded together, and at least one of the first chip and the second chip includes a semiconductor device as described above.

[0030] The beneficial effects of the present invention are as follows: Different from the prior art, the present invention provides a semiconductor device, a manufacturing method, and a three-dimensional memory. The manufacturing method of the semiconductor device includes: forming a semiconductor structure, the semiconductor structure including a substrate, a stacked structure including alternating gate layers and insulating layers located on the substrate, a channel structure extending through the stacked structure and into the substrate, and a gate line gap extending through the stacked structure and dividing the stacked structure into several parts; forming a first filling layer within the gate line gap; and forming a second filling layer on at least a portion of the inner wall of the first filling layer; wherein the material of the first filling layer includes oxide, and the material of the second filling layer includes amorphous silicon. By forming the first filling layer and the second filling layer of different materials in the gate line gap, the warpage of the semiconductor device in the horizontal and vertical directions is adjusted, thereby improving the warpage problem of the semiconductor device and increasing the product yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0032] Figure 1 This is a flow chart of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0033] Figures 2a to 2d A schematic structural diagram of each step of a method for manufacturing a semiconductor device provided by a first embodiment of the present invention;

[0034] Figure 3 This is a flow chart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[0035] Figures 4a to 4e A schematic structural diagram of each step of a method for manufacturing a semiconductor device provided in a second embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0037] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the present invention.

[0038] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0039] As used herein, the term "layer" refers to a material portion comprising an area having a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. A layer may extend over the entire lower or upper structure, or may have a range that is smaller than the range of the lower or upper structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is smaller than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer (wherein contacts, interconnect lines, and one or more dielectric layers are formed).

[0040] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.

[0041] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed at will, and the component layout type may also be more complicated.

[0042] See also Figure 1 , which is a flow chart of a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and the specific process is compared with Figures 2a to 2d The structure diagram may include the following:

[0043] Step S101: forming a semiconductor structure, the semiconductor structure including a substrate 110, a stacking structure 120 located on the substrate 110 and including alternatingly stacked gate layers 121 and insulating layers 122, a channel structure 130 penetrating the stacking structure 120 and extending to the substrate 110, and a gate line gap 140 penetrating the stacking structure 120 and dividing the stacking structure 120 into several parts.

[0044] Figure 2a The structure formed in step S101 includes: a substrate 110 , a stacked structure 120 located on the substrate 110 and including alternately stacked gate layers 121 and insulating layers 122 , a channel structure 130 , and a gate line gap 140 .

[0045] Specifically, the substrate 110 may be a semiconductor substrate 110, such as silicon (Si), germanium (Ge), a SiGe substrate 110, a silicon-on-insulator (SOI), or a germanium-on-insulator (GOI). In other embodiments, the semiconductor substrate 110 may also be a substrate 110 including other elemental semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0046] Specifically, in a semiconductor structure, a channel hole structure serves as a data storage unit in a semiconductor device, implementing data storage functionality. The gate layer 121 in the stacked structure 120 (NO stack) controls the conduction of the channel structure 130, while the gate line slit 140 divides the stacked structure 120 into several sections. Furthermore, the gate line slit can also connect to the source region 150 at the bottom to form a common source region.

[0047] The specific formation process of the semiconductor structure may be that after providing a substrate 110, first, a stacked structure 120 including alternating sacrificial layers and insulating layers 122 may be formed on the substrate 110 through a deposition process. The number of sacrificial layers and insulating layers 122 may be controllable, for example, by adjusting the parameters of the deposition process to form the required number of sacrificial layers and insulating layers 122. The insulating layer 122 is used to separate the multiple sacrificial layers. The material of the insulating layer 122 may be composed of an oxide, such as silicon oxide (SiO2), and the material of the sacrificial layer may be composed of a nitride, such as silicon nitride (SiN). Since the material of the sacrificial layer is mostly nitride, it is conducive to the simultaneous formation of a stacked structure 120 of multiple alternating sacrificial layers and multiple insulating layers 122. Therefore, a semiconductor structure including sacrificial layers and insulating layers 122 alternately stacked along a first longitudinal direction perpendicular to the main surface of the substrate 110 may be formed through a deposition process. Subsequently, an etching process, such as dry etching, can be used to form a trench in the stacked structure 120 that penetrates the stacked structure 120 and extends to the substrate 110. A deposition process can then be used to sequentially fill the inner wall of the trench with a filling material one or more times, thereby forming a channel structure 130. The filling material can be an insulating material or a conductive material, etc. A gate line gap 140 can then be formed in the stacked structure 120 that penetrates the stacked structure 120 and extends to the substrate 110. Finally, because the stacked structure 120 has a large number of layers and it is not possible to directly form alternating stacks of gate layers 121 and insulating layers 122 at once, a deposition process is required to form alternating stacks of sacrificial layers and insulating layers 122 at once. The sacrificial layers are then removed by a wet etching process. Finally, a gate layer 121 is formed in the position of the original sacrificial layer, thereby forming a semiconductor structure including alternating stacks of gate layers 121 and stacked layers.

[0048] Specifically, step S102 : forming a first filling layer 141 in the gate line gap 140 .

[0049] Figure 2b The structure formed in step S102 is shown, including: a substrate 110, a stacked structure 120 including alternating gate layers 121 and insulating layers 122 stacked on the substrate 110, a channel structure 130, a gate line gap 140, and a first filling layer 141 located on the inner wall of the gate line gap 140. The first filling layer 141 can be formed in the gate line gap 140 by a deposition process, such as atomic layer deposition (ALD).

[0050] Before forming the first filling layer 141 in the gate line gap 140, the method further includes:

[0051] A spacer layer 160 is formed in the gate line gap 140 .

[0052] See also Figure 2b Generally, before forming the first filling layer 141 in the gate line gap 140, a spacer layer 160 may be formed in the gate line gap 140 by a deposition process. The spacer layer 160 may include one or more dielectric layers, such as Figure 2b As shown, the spacer layer 160 may include a first dielectric layer 161 and a second dielectric layer 162. The first dielectric layer 161 may be a high-K oxide dielectric, such as aluminum oxide (Al2O3), and the second dielectric layer may be an oxide, such as silicon oxide (SiO2).

[0053] Step S103: forming a second filling layer 142 on at least a portion of the inner wall of the first filling layer 141; wherein the material of the first filling layer 141 includes oxide, and the material of the second filling layer 142 includes amorphous silicon, and the first filling layer 141 and the second filling layer 142 constitute a gate line gap 140 structure.

[0054] Figure 2c The structure formed in step S103 is shown, including: a substrate 110, a stacked structure 120 comprising alternating gate layers 121 and insulating layers 122 on the substrate 110, a channel structure 130, a gate line gap 140, and a first filling layer 141 and a second filling layer 142 located on the inner wall of the gate line gap 140. The first filling layer 141 is made of oxide, the second filling layer 142 is made of amorphous silicon, and the gate line gap structure 143 includes the first filling layer 141 and the second filling layer 142.

[0055] Specifically, a second filling layer 142 can be formed on the inner wall of the first filling layer 141 through a deposition process, such as atomic layer deposition (ALD). Simultaneously, the deposition process parameters, such as reaction time, can be controlled to form the first filling layer 141 and the second filling layer 142 with controllable thickness. As the number of layers in the stacked structure 120 increases, stress control in semiconductor devices becomes increasingly important. However, the gate line gap 140 structure in a semiconductor device exhibits significant stress, which can cause warping (wafer bow) during the semiconductor device formation process, easily leading to reduced product yield. Therefore, a first filling layer 141 made of an oxide, such as silicon oxide, and a second filling layer 142 made of amorphous silicon are employed. Amorphous silicon is a semiconductor material that is a product of the silicon manufacturing process that does not crystallize. Its structure contains many so-called "dangling bonds," meaning electrons that are not bonded to surrounding silicon atoms. These electrons can generate current under the action of an electric field, making amorphous silicon a conductive material. Furthermore, amorphous silicon exhibits excellent electrical and mechanical properties and stability. In the prior art, since a filling layer of other materials is used to form the gate line gap structure 143, after the gate line gap structure 143 is formed, because there are multiple heat treatment processes in the subsequent process, the material of the gate line gap structure 143 will change due to the heat treatment process, causing the gate line gap structure 143 to generate stress, thereby causing the wafer to warp. By selecting a second filling layer 142 of amorphous silicon, the filling layer of amorphous silicon is more stable, which can effectively improve the impact of subsequent heat treatment processes on wafer warping and improve the stability of the process. At the same time, by adjusting the thickness of the first filling layer 141 and the second filling layer 142, the wafer warping can be arbitrarily adjusted in the horizontal and vertical directions, and the process is simple and the cost is low.

[0056] In addition, it should be noted that the material of the second filling layer 142 may also include crystalline silicon. During the manufacturing process, amorphous silicon may have a small amount of crystallization after heat treatment. The following is similar to this and will not be repeated.

[0057] After the second filling layer 142 is formed on at least a portion of the inner wall of the first filling layer 141, the method further includes:

[0058] Perform in-situ annealing.

[0059] Specifically, after the first filling layer 141 and the second filling layer 142 are formed through a deposition process, stress will exist in the gate line gap 140 structure including the first filling layer 141 and the second filling layer 142. By adopting in-situ annealing, that is, directly performing an annealing process after the deposition process is completed without cooling or leaving the vacuum environment, the stress generated by the formation of the first filling layer 141 and the second filling layer 142 is reduced, further improving the warpage problem of the semiconductor device and improving the product yield of the semiconductor device. At the same time, by performing in-situ annealing on the semiconductor device in advance, the first filling layer 141 and the second filling layer 142 are easily changed during the subsequent heat treatment process, which can lead to a large change in wafer warpage.

[0060] The first filling layer 141 is in the second direction (eg Figure 2c The second filling layer 142 has a first thickness in the second direction (the X direction), and the second filling layer 142 has a second thickness in the second direction (the X direction). The ratio of the first thickness to the second thickness ranges from 1 / 10 to 10.

[0061] As can be seen from the above, by adjusting the thickness of the first filling layer 141 and the second filling layer 142, the wafer warping can be arbitrarily adjusted in the horizontal and vertical directions. The first filling layer 141 has a first thickness in the second direction (X direction), and the second filling layer 142 has a second thickness in the second direction (X direction). The ratio of the first thickness to the second thickness can be in the range of 1 / 10-10. In order to ensure the role of the second filling layer 142 in isolating the stacking structure 120, preferably, the ratio of the first thickness to the second thickness is in the range of 1-10, and more preferably, the ratio of the first thickness to the second thickness is 1:1. In addition, it should be noted that when the first thickness of the first filling layer 141 is larger and the second thickness of the second filling layer 142 is smaller, the gate line gap structure 143 can be solid or there can be gaps (also called void or seam). The same applies to the following and will not be repeated hereafter.

[0062] The step S102 of forming a first filling layer 141 in the gate line gap 140 specifically includes:

[0063] A first filling layer 141 is formed in the gate line gap 140 through a deposition process, so that at least a portion of the first filling layer 141 is located at the bottom of the gate line gap 140 .

[0064] Please continue reading Figure 2b , a first filling layer 141 can be formed in the gate line gap 140 through a deposition process. By controlling the reaction parameters of the deposition process, at least a portion of the first filling layer 141 is formed at the bottom of the gate line gap 140, that is, the first filling layer 141 covers the bottom of the gate line gap 140.

[0065] Please continue reading Figure 2c After executing step S102: forming the first filling layer 141 in the gate line gap 140, the deposition process can be continued on the inner wall of the first filling layer 141 to form the second filling layer 142 on at least part of the inner wall of the first filling layer 141. Since the first filling layer 141 covers the bottom of the gate line gap 140, part of the first filling layer 141 in the first direction (Y direction) is located between the end of the second filling layer 142 and the substrate 110, that is, part of the first filling layer 141 in the Y direction is located between the end (that is, the bottom) of the second filling layer 142 and the substrate 110, so that the second filling layer 142 is not in direct contact with the substrate 110.

[0066] The channel structure 130 includes a functional layer 131, a channel layer 132, and an isolation layer 133 formed in sequence from the outside to the inside in the radial direction. After the second filling layer 142 is formed on the inner wall of the first filling layer 141, the channel structure 130 further includes:

[0067] Step S104: removing the substrate 110;

[0068] Step S105: removing a portion of the functional layer 131 at the end of the channel structure 130 to expose the channel layer 132 at the end of the channel structure 130;

[0069] Step S106: forming a source region 150, wherein the stacking structure 120 includes a front side and a back side facing each other, the back side being the side close to the substrate 110, the source region 150 being located on the back side of the stacking structure 120, and the source region 150 covering the end of the channel structure 130 and the gate line gap 140 structure.

[0070] Figure 2d The structure formed after steps S104 to S106 is shown, including: a substrate 110, a stacked structure 120 located on the substrate 110 and including alternating stacked gate layers 121 and insulating layers 122, a channel structure 130, a gate line gap 140, a first filling layer 141 and a second filling layer 142 located on the inner wall of the gate line gap 140, and a source region 150 located below the stacked structure 120.

[0071] Specifically, the substrate 110 can be removed by wet etching or dry etching, for example, using a chemical solution with a certain selectivity ratio. The solution has a high etching rate for the substrate 110 and a low etching rate for other film layers. When removing the substrate 110, the other film layers are substantially not damaged, thereby removing the substrate 110. Subsequently, a portion of the functional layer 131 at the bottom of the channel structure 130 can be removed by wet etching to expose the channel layer 132 at the end of the channel structure 130. Finally, a source region 150 can be formed by depositing one or more polysilicon layers at the bottom of the stacked structure 120, i.e., at the location of the original substrate 110, and then performing ion implantation on the polysilicon layer. The source region 150 is used to provide carriers for the semiconductor device. The carriers can be electrons or holes. The channel layer 132 is used to provide a path for the movement of carriers between the source region 150 and the functional layer 131. Therefore, the material of the channel layer 132 needs to be a conductive material, such as polysilicon. The functional layer 131 generally includes a tunneling layer, a charge trap layer, and a blocking layer. By removing the substrate 110, a portion of the functional layer 131 at the end of the channel structure 130 is removed to expose the channel layer 132 (polychannel layer) at the end of the channel structure 130. The source region 150 covers the bottom of the channel structure 130 and the gate line gap 140 structure, allowing the source region 150 to directly contact the channel layer 132 of the channel structure 130, thereby enabling carriers in the source region 150 to move freely in the channel layer 132.

[0072] In a modified example, other elements including amorphous silicon may be doped to form the second filling layer, wherein the material of the second filling layer 142 is doped with carbon.

[0073] It can be understood that the material for forming the second filling layer 142 of the modification example is different from that of the first embodiment. The first embodiment uses amorphous silicon to form the second filling layer 142, while the modification example uses amorphous silicon doped with carbon to form the second filling layer 142, and the manufacturing method of the modification example is basically the same as that of the first embodiment. Correspondingly, the corresponding structural diagrams formed in steps S101 to S106 of the modification example are basically the same as those of the first embodiment. Since the corresponding structural diagrams and manufacturing processes formed in steps S101 to S106 have been described in detail, they will not be repeated here.

[0074] In a modified embodiment, the second filling layer 142 can be formed of a material including amorphous silicon and carbon. By doping the second filling layer 142 with carbon, the amorphous silicon and carbon-doped filling layer becomes more stable, further reducing the impact of wafer warpage and improving process stability. Furthermore, by adjusting the thickness of the first filling layer 141 and the second filling layer 142, wafer warpage can be arbitrarily adjusted in the horizontal (X-direction) and vertical (Y-direction) directions, with a simple process and low cost.

[0075] As can be seen from the above, a portion of the first filling layer 141 is located between the end of the second filling layer 142 and the substrate 110. That is, the second filling layer 142 is surrounded by the first filling layer 141, so that the second filling layer 142 does not directly contact the substrate 110. It can be understood that the second filling layer 142 is separated from the substrate 110 by a portion of the first filling layer 141. After the substrate 110 is subsequently removed to form the source region 150, the second filling layer 142 does not directly contact the source region 150. In other words, the gate line gap 140 structure including the first filling layer 141 and the second filling layer 142 only serves to divide the stack structure 120 into several parts and does not provide an electrical connection to the source region 150.

[0076] Generally, before executing step S102: forming the first filling layer 141 on the inner wall of the gate line slit 140, it is necessary to perform a SPA ET process (also known as spacer etch), that is, removing part of the top and part of the bottom of the gate line slit 140. By removing part of the top, a trumpet-shaped shape is formed, which is conducive to the subsequent filling of the gate line slit 140 with a conductive material to ensure the electrical properties of the conductive material. By removing part of the bottom, the bottom of the gate line slit 140 is directly in contact with the substrate 110 to ensure the electrical connection between the gate line slit 140 structure and the source region 150 in the substrate 110. Given that the gate line slit 140 structure of the modified example of the present application only serves to isolate the stacked structure 120, before executing step S102: forming the first filling layer 141 on the inner wall of the gate line slit 140, the process of removing part of the top and part of the bottom of the gate line slit 140 (i.e., the SPA ET process) can be omitted, thereby simplifying the process flow and greatly reducing production costs.

[0077] Among them, since the SPA ET process is omitted, when the gate line gap 140 is formed by the etching process, some ions are not vertically incident into the hole for etching, resulting in the cross-sectional shape of the formed gate line gap 140 in the X direction and the Y direction being narrow at the top and wide in the middle (that is, there is a bulge in the middle of the gate line gap 140), and the narrow at the top and wide in the middle structure is not conducive to improving the impact of wafer warpage. By forming a first filling layer 141 and a second filling layer 142 in the gate line gap 140, and the second filling layer 142 includes amorphous silicon and doped carbon elements, the second filling layer 142 using amorphous silicon and doped carbon elements is more stable. At the same time, doping carbon elements in the second filling layer 142 of the gate line gap 140 is likely to produce voids, which absorb stress through the voids, thereby improving the impact of wafer warpage.

[0078] In addition, it should be noted that in a modified embodiment, the wafer warpage can be arbitrarily adjusted in the horizontal and vertical directions by adjusting the thickness of the first filling layer 141 and the second filling layer 142. Preferably, the first filling layer 141 has a first thickness in the second direction (X direction), and the second filling layer 142 has a second thickness in the second direction (X direction). The ratio of the first thickness to the second thickness can be in the range of 1 / 10-10. In order to ensure that the second filling layer 142 can isolate the stacked structure 120, preferably, the ratio of the first thickness to the second thickness is in the range of 1-10, and more preferably, the ratio of the first thickness to the second thickness is 1:1.

[0079] See also Figure 3 , which is a flow chart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, wherein the second embodiment is a variation of a variation, in which the material of the second filling layer 242 is also amorphous silicon doped with carbon. Figures 4a to 4e The structure diagram may include the following:

[0080] See also Figure 4a , which is a semiconductor device formed by performing step S101 in the second embodiment, includes: a substrate 210, a stacked structure 220 located on the substrate 210 and including alternately stacked gate layers 221 and insulating layers 222, a channel structure 230 and a gate line gap 240.

[0081] Wherein, before forming the second filling layer 242 on at least a portion of the inner wall of the first filling layer 241 in step S103, the method further includes:

[0082] Step S107 : removing a portion of the inner wall at the bottom of the gate line gap 240 formed in the stacked structure 220 , so that the bottom of the gate line gap 240 extends into the substrate 210 .

[0083] See also Figure 4b, is a structure formed by performing step S107 in the second embodiment, comprising: a substrate 210, a stacked structure 220 comprising alternately stacked gate layers 221 and insulating layers 222 located on the substrate 210, a channel structure 230, and a gate line gap 240. The width L1 of the top of the gate line gap 240 in the first direction is greater than the width L2 of the middle of the gate line gap 240 in the first direction, i.e., a gate line gap 240 that is wide at the top and narrow at the bottom is formed. After the gate line gap 240 is filled with amorphous silicon material doped with carbon, a void is easily formed, which absorbs stress and thus improves the effect of wafer warpage. The SPAET process can be performed to remove part of the inner wall at the bottom of the gate line gap 240 so that the bottom of the gate line gap 240 extends into the substrate 210, thereby allowing the formed gate line gap structure 243 to be electrically connected to the source region 250 formed subsequently. While removing a portion of the inner wall at the bottom of the gate line slit 240, a portion of the top of the gate line slit 240 can also be removed. By removing a portion of the top of the gate line slit 240, a gate line slit 240 is formed that is wider at the top and narrower at the bottom, which helps to alleviate the impact of wafer warpage. Since the SPAET process has been described in detail above, it will not be repeated here.

[0084] In addition, it should be noted that when step S107 is executed: part of the inner wall at the bottom of the gate line gap 240 formed in the stacked structure 220 is removed so that the bottom of the gate line gap 240 extends into the substrate 210 after the first filling layer 241 is formed. At this time, a first filling layer 241 is formed in the gate line gap 240. In order to ensure that the formed gate line gap structure 243 can be electrically connected to the subsequently formed source region 250, part of the bottom of the first filling layer 241 will be removed during the execution of step S107 so that the formed gate line gap structure 243 can be electrically connected to the subsequently formed source region 250.

[0085] Before forming the first filling layer 241 in the gate line gap 240, the method further includes:

[0086] A spacer layer 260 is formed in the gate line gap 240 .

[0087] Please continue reading Figure 4b Generally, before forming the first filling layer 241 in the gate line gap 240, a spacer layer 260 may be formed in the gate line gap 240 by a deposition process. The spacer layer 260 may include one or more dielectric layers, such as Figure 4b As shown, the spacer layer 260 may include a first dielectric layer 261 and a second dielectric layer 262. The first dielectric layer 261 may be a high-K oxide dielectric, such as aluminum oxide (Al2O3), and the second dielectric layer 262 may be an oxide, such as silicon oxide (SiO2).

[0088] See also Figure 4c, performing step S102 in the second embodiment: forming a first filling layer 241 on the inner wall of the gate line gap 240. The formed semiconductor device includes: a substrate 210, a stacked structure 220 including alternating gate layers 221 and insulating layers 222 stacked on the substrate 210, a channel structure 230, a gate line gap 240, and a first filling layer 241 located on the inner wall of the gate line gap 240. The first filling layer 241 can be formed on the inner wall of the gate line gap 240 by a deposition process, such as atomic layer deposition (ALD), and the thickness of the first filling layer 241 is controllable.

[0089] See also Figure 4d In the second embodiment, step S103 is performed: a second filling layer 242 is formed on at least a portion of the inner wall of the first filling layer 241. The formed semiconductor device includes: a substrate 210, a stacked structure 220 including alternating gate layers 221 and insulating layers 222 stacked on the substrate 210, a channel structure 230, a gate line gap 240, and a first filling layer 241 and a second filling layer 242 located on the inner wall of the gate line gap 240. The material of the first filling layer 241 includes oxide, the material of the second filling layer 242 includes amorphous silicon, and the gate line gap structure 243 includes the first filling layer 241 and the second filling layer 242.

[0090] Specifically, a second filling layer 242 can be formed on the inner wall of the first filling layer 241 through a deposition process, such as atomic layer deposition (ALD). At the same time, the parameters of the deposition process, such as the reaction time, can be controlled to form a first filling layer 241 and a second filling layer 242 with controllable thickness. By using a first filling layer 241 made of an oxide, such as silicon oxide, and a second filling layer 242 made of amorphous silicon, and the thickness of the first filling layer 241 and the second filling layer 242 are controllable, by selecting a second filling layer 242 made of amorphous silicon, the filling layer of amorphous silicon is more stable, which can effectively improve the influence of subsequent heat treatment processes on wafer warpage and improve the stability of the process. At the same time, by adjusting the thickness of the first filling layer 241 and the second filling layer 242, the wafer warpage can be arbitrarily adjusted in the horizontal and vertical directions, and the process is simple and the cost is low.

[0091] After removing the substrate 210, the method further includes:

[0092] Step S108: removing part of the first filling layer 241 at the end of the gate line gap 240 structure to expose the second filling layer 242 at the end of the gate line gap 240 structure so as to be connected to the source region 250 after the source region 250 is formed.

[0093] See also Figure 4e, which is the structure formed after steps S104 to S106 and S108 in the second embodiment, includes: a substrate 210, a stacked structure 220 comprising alternating gate layers 221 and insulating layers 222 stacked on the substrate 210, a channel structure 230, a gate line gap 240, a first filling layer 241 and a second filling layer 242 located on the inner wall of the gate line gap 240, and a source region 250 located below the stacked structure 220. The channel structure 230 includes a functional layer 231, a channel layer 232, and an isolation layer 233 formed sequentially from the outside to the inside in the radial direction.

[0094] Specifically, since the material of the functional layer 231 at the bottom of the channel structure 230 includes oxide, and the material of the first filling layer 241 at the bottom of the gate line gap 240 structure includes oxide, step S105 can be performed: part of the functional layer 231 at the end of the channel structure 230 is removed to expose the channel layer 232 at the end of the channel structure 230, and at the same time, step S108 is performed: part of the first filling layer 241 at the end of the gate line gap 240 structure is removed to expose the second filling layer 242 at the end of the gate line gap 240 structure, so as to connect with the source region 250 after the source region 250 is formed.

[0095] Specifically, a portion of the functional layer 231 at the bottom of the channel structure 230 and a portion of the first filling layer 241 at the bottom of the gate line gap 240 structure can be removed by wet etching or dry etching. For example, a chemical solution with a certain selectivity ratio can be used, which has a high etching rate for oxides and a low etching rate for other materials. When removing the substrate 210, other film layers are substantially not damaged, thereby removing the substrate 210. Subsequently, a portion of the functional layer 231 at the bottom of the channel structure 230 and a portion of the first filling layer 241 at the bottom of the gate line gap 240 structure can be removed by wet etching to expose the channel layer 232 at the end of the channel structure 230 and the second filling layer 242 at the end of the gate line gap 240 structure. Subsequently, one or more polysilicon layers can be deposited at the bottom of the stacked structure 220, i.e., at the location of the original substrate 210, and ion implantation can be performed on the polysilicon layer to form the source region 250. By removing the substrate 210, a portion of the functional layer 231 at the bottom of the channel structure 230 and a portion of the first filling layer 241 at the bottom of the gate line gap 240 structure are removed to expose the channel layer 232 (poly channel layer) at the end of the channel structure 230 and the second filling layer 242 at the bottom of the gate line gap 240 structure. This allows the source region 250 to directly contact the channel layer 232 of the channel structure 230, thereby enabling carriers in the source region 250 to move freely in the channel layer 232. At the same time, the source region 250 is directly in contact with the second filling layer 242 of the gate line gap 240 structure, thereby achieving communication between the gate line gap 240 structure and the source region 250. This reduces the need for additional structures and processes that communicate with the source region 250, further simplifies the process flow, and significantly reduces production costs.

[0096] In addition, it should be noted that in the second embodiment, by adjusting the thickness of the first filling layer 241 and the second filling layer 242, the wafer warpage can be arbitrarily adjusted in the horizontal and vertical directions. The first filling layer 241 has a first thickness in the second direction (X direction), and the second filling layer 242 has a second thickness in the second direction (X direction). The ratio of the first thickness to the second thickness can be in the range of 1 / 10-10. In order to ensure the connectivity between the second filling layer 242 and the source region 250, preferably, the ratio of the first thickness to the second thickness is in the range of 1-10, and more preferably, the ratio of the first thickness to the second thickness is 1:1.

[0097] Based on the manufacturing method of the semiconductor device described in the above embodiment, the embodiment of the present application also provides a semiconductor device, including: a source region 150; a stack structure 120 located on the source region 150 and including alternating stacked gate layers 121 and insulating layers 122; a channel structure 130 that penetrates the stack structure 120 and extends into the source region 150, the channel structure 130 including a functional layer 131, a channel layer 132 and an isolation layer 133 formed radially from the outside to the inside, the channel layer 132 at the end of the channel structure 130 extends into the source region 150 and is connected to the source region 150; a gate line gap 140 structure that penetrates the stack structure 120 and extends into the source region 150 to divide the stack structure 120 into several parts, the gate line gap 140 structure including a first filling layer 141 and a second filling layer 142 formed from the outside to the inside; wherein the material of the first filling layer 141 includes oxide, and the material of the second filling layer 142 includes amorphous silicon.

[0098] In addition, it should be noted that the material of the second filling layer 142 may also include crystalline silicon. During the manufacturing process, amorphous silicon may have a small amount of crystallization after heat treatment. The following is similar to this and will not be repeated.

[0099] Part of the first filling layer 141 in the first direction (Y direction) is located between the end of the second filling layer 142 and the source region 150 .

[0100] See also Figure 2d , a semiconductor device of the first embodiment, includes: a substrate 110, a stacked structure 120 comprising alternating gate layers 121 and insulating layers 122 located on the substrate 110, a channel structure 130, a gate line gap 140, a first filling layer 141 and a second filling layer 142 located on the inner wall of the gate line gap 140, and a source region 150 located below the stacked structure 120. Part of the first filling layer 141 in the first direction (Y direction) is located between the end of the second filling layer 142 and the source region 150, so that the second filling layer 142 is not connected to the source region 150. The amorphous silicon second filling layer 142 is more stable and can effectively reduce the impact of subsequent heat treatment processes on wafer warpage, thereby improving process stability. At the same time, by adjusting the thickness of the first filling layer 141 and the second filling layer 142, the wafer warpage can be arbitrarily adjusted in the horizontal and vertical directions, and the process is simple and low-cost.

[0101] In a modified example, other elements including amorphous silicon may be doped to form the second filling layer 142 , wherein the material of the second filling layer 142 is doped with carbon.

[0102] Unlike the first embodiment, which forms a second filling layer 142 comprising amorphous silicon, this modified embodiment of the present application uses a material comprising amorphous silicon and carbon to form the second filling layer 142. By doping the second filling layer 142 with carbon, the amorphous silicon and carbon-doped filling layer becomes more stable, further improving the impact of subsequent heat treatment processes on wafer warpage and enhancing process stability. Furthermore, by adjusting the thickness of the first filling layer 141 and the second filling layer 142, the wafer warpage can be adjusted in any manner in the horizontal and vertical directions, with a simple process and low cost.

[0103] At the same time, as can be seen from the above, since the gate line gap 140 structure of the modified embodiment of the present application serves to isolate the stacked structure 120 and is not connected to the source region 150, the process of removing part of the top and part of the bottom of the gate line gap 140 (i.e., the SPA ET process) can be omitted, simplifying the process flow and greatly reducing production costs. In particular, since the SPA ET process is omitted, the gate line gap 140 will be narrow at the top and wide in the middle. Filling the gate line gap 140 with doped carbon elements can easily produce voids, which absorb stress and thus improve the impact of wafer warpage.

[0104] The first filling layer 141 has a first thickness in the second direction (X direction), the second filling layer 142 has a second thickness in the second direction, and the ratio of the first thickness to the second thickness ranges from 1 / 10 to 10.

[0105] Specifically, the first filling layer 141 has a first thickness in the second direction (X direction), and the second filling layer 142 has a second thickness in the second direction (X direction). The ratio of the first thickness to the second thickness can be in the range of 1 / 10 to 10. To ensure that the second filling layer 142 functions to isolate the stacked structure 120, preferably, the ratio of the first thickness to the second thickness is in the range of 1 to 10, and more preferably, the ratio of the first thickness to the second thickness is 1:1.

[0106] The second filling layer 242 extends into the source region 250 and is connected to the source region 250 .

[0107] See also Figure 4e, a semiconductor device according to a second embodiment, includes: a substrate 210, a stacked structure 220 comprising alternating gate layers 221 and insulating layers 222 on the substrate 210, a channel structure 230, a gate line gap 240, a first filling layer 241 and a second filling layer 242 located on the inner wall of the gate line gap 240, and a source region 250 located below the stacked structure 220. The second filling layer 242 extends into and connects to the source region 250. The channel structure 230 includes a functional layer 231, a channel layer 232, and an isolation layer 233, formed radially inward. The first filling layer 241 is made of oxide, the second filling layer 242 is made of amorphous silicon, and the gate line gap structure 243 includes the first filling layer 241 and the second filling layer 242. By selecting carbon-doped amorphous silicon for the second filling layer 242, the carbon-doped amorphous silicon becomes more stable, effectively mitigating the effects of subsequent heat treatment on wafer warpage and improving process stability. At the same time, by adjusting the thickness of the first filling layer 241 and the second filling layer 242, the wafer warpage can be arbitrarily adjusted in the horizontal and vertical directions, and the process is simple and the cost is low. The first filling layer 241 has a first thickness in the second direction (X direction), and the second filling layer 242 has a second thickness in the second direction (X direction). The ratio of the first thickness to the second thickness can be in the range of 1 / 10-10. In order to ensure the connectivity between the second filling layer 242 and the source region 250, preferably, the ratio of the first thickness to the second thickness is in the range of 1-10, and more preferably, the ratio of the first thickness to the second thickness is 1:1.

[0108] In addition, as can be seen from the above, by adopting the second filling layer 242 to extend into the source region 250 and connect to the source region 250, the gate line gap 240 structure and the source region 250 are connected, thereby reducing the additional setting of other structures and process steps for connecting to the source region 250, further simplifying the process flow, and greatly reducing production costs.

[0109] Based on the semiconductor device described in the above embodiments, an embodiment of the present application further provides a wafer (not shown in the figure), on which any semiconductor device as described above is formed.

[0110] An embodiment of the present application further provides a three-dimensional memory, which includes a first chip and a second chip bonded together, wherein at least one of the first chip and the second chip includes any of the semiconductor devices described above.

[0111] Specifically, the three-dimensional memory (3D NAND Flash) includes a bonded first chip and a second chip, wherein the first chip and the second chip can be an array storage structure (array) and a peripheral circuit (periphery circuit), respectively, and the array storage structure and the peripheral circuit are wire-bonded to form a three-dimensional memory. The array storage structure is used to store information, and the peripheral circuit can be located above or below the array storage structure, and the peripheral circuit is used to control the corresponding array storage structure. At least one of the first chip and the second chip includes a semiconductor device as described above. By adopting a three-dimensional memory including a semiconductor device of any of the above embodiments, the influence of subsequent heat treatment processes on wafer warpage can be effectively improved, thereby improving the process stability of the three-dimensional memory.

[0112] Different from the prior art, the semiconductor device, fabrication method, and three-dimensional memory device in this embodiment include the following steps: forming a semiconductor structure comprising a substrate, a stacked structure comprising alternating gate layers and insulating layers located on the substrate, a channel structure extending through the stacked structure and into the substrate, and a gate line gap extending through the stacked structure and dividing the stacked structure into a plurality of sections; forming a first filling layer within the gate line gap; and forming a second filling layer on at least a portion of the inner wall of the first filling layer; wherein the material of the first filling layer comprises an oxide, and the material of the second filling layer comprises amorphous silicon. By forming the first and second filling layers of different materials within the gate line gap, the warpage of the semiconductor device in the horizontal and vertical directions is adjusted, thereby improving the warpage problem of the semiconductor device and enhancing the product yield of the semiconductor device.

[0113] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a semiconductor structure comprising a substrate, a stack structure comprising alternately stacked gate layers and insulating layers on the substrate, a channel structure penetrating the stack structure and extending into the substrate, and a gate line gap penetrating the stack structure and dividing the stack structure into several parts; forming a first filling layer in the gate line gap; forming a second filling layer on at least a portion of the inner wall of the first filling layer; The material of the first filling layer includes oxide, the material of the second filling layer includes amorphous silicon, and the material of the second filling layer is doped with carbon.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After a second filling layer is formed on at least a portion of the inner wall of the first filling layer, the method further comprises: Perform in-situ annealing.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The forming of the first filling layer in the gate line gap specifically includes: A first filling layer is formed in the gate line gap, so that at least a portion of the first filling layer is located at the bottom of the gate line gap.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming a second filling layer on at least a portion of the inner wall of the first filling layer, the method further comprises: A portion of the inner wall of the stacked structure forming the bottom of the gate line gap is removed, so that the bottom of the gate line gap extends into the substrate.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The channel structure includes a functional layer, a channel layer, and an isolation layer formed radially from the outside to the inside, and after a second filling layer is formed on the inner wall of the first filling layer, further includes: removing the substrate; removing a portion of the functional layer at the end of the channel structure to expose the channel layer at the end of the channel structure; A source region is formed, wherein the stack structure includes a front side and a back side facing each other, the back side is a side close to the substrate, the source region is located on the back side of the stack structure, and the source region covers the end portions of the channel structure and the gate line gap structure.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: After removing the substrate, the method further includes: A portion of the first filling layer at the end of the gate line gap structure is removed to expose the second filling layer at the end of the gate line gap structure so as to be connected to the source region after the source region is formed.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The first filling layer has a first thickness in the second direction, the second filling layer has a second thickness in the second direction, and a ratio of the first thickness to the second thickness ranges from 1 / 10 to 10.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the first filling layer in the gate line gap, the method further includes: A spacer layer is formed in the gate line gap.

9. A semiconductor device, characterized in that: include: source area; a stack structure located on the source region and including alternately stacked gate layers and insulating layers; a channel structure penetrating the stacked structure and extending into the source region, the channel structure comprising a functional layer, a channel layer, and an isolation layer formed radially from the outside to the inside, the channel layer at an end of the channel structure extending into the source region and connected to the source region; a gate line gap structure that penetrates the stack structure and extends into the source region to divide the stack structure into several parts, the gate line gap structure comprising a first filling layer and a second filling layer that are sequentially formed from the outside to the inside; The material of the first filling layer includes oxide, the material of the second filling layer includes amorphous silicon, and the material of the second filling layer is doped with carbon.

10. The semiconductor device according to claim 9, wherein The second filling layer extends into the source region and is connected to the source region.

11. The semiconductor device according to claim 9, wherein A portion of the first filling layer in the first direction is located between an end portion of the second filling layer and the source region.

12. The semiconductor device according to claim 9, wherein The first filling layer has a first thickness in the second direction, the second filling layer has a second thickness in the second direction, and a ratio of the first thickness to the second thickness ranges from 1 / 10 to 10.

13. A three-dimensional memory, characterized in that: The three-dimensional memory includes a first chip and a second chip bonded together, and at least one of the first chip and the second chip includes the semiconductor device according to any one of claims 9 to 12.

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