Layout pattern for magnetoresistive random access memory

Abstract

The application discloses a layout pattern of a magnetoresistive random access memory, which mainly comprises a first unit area, a second unit area, a third unit area, a fourth unit area arranged on a substrate, and a diffusion area arranged on the substrate and extending to the first unit area, the second unit area, the third unit area and the fourth unit area, wherein the diffusion area comprises an H-shaped structure according to an upper view angle.

Description

TECHNICAL FIELD

[0001] The present application relates to a layout pattern of a magnetoresistive random access memory. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component for mobile phones matched with a global positioning system (GPS) to provide the user with information about the direction of movement. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] One embodiment of the present application discloses a layout pattern of a magnetoresistive random access memory, which mainly comprises a first cell region, a second cell region, a third cell region and a fourth cell region disposed on a substrate, and a diffusion region disposed on the substrate and extending to the first cell region, the second cell region, the third cell region and the fourth cell region, wherein the diffusion region comprises an H shape according to the top view angle.

[0005] Another embodiment of the present application discloses a semiconductor element, which mainly comprises a first cell region and a second cell region disposed on a substrate, and a diffusion region disposed on the substrate and extending to the first cell region and the second cell region, wherein the diffusion region comprises a first H shape and a second H shape according to the top view angle. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 5Layout diagram of an MRAM element according to an embodiment of the present application

[0007] Figures 6 to 10 Layout diagram of an MRAM element according to an embodiment of the present application

[0008] Explanation of main element symbols

[0009] 12: substrate

[0010] 14: first cell region

[0011] 16: second cell region

[0012] 18: third cell region

[0013] 20: fourth cell region

[0014] 22: diffusion region

[0015] 24: first portion

[0016] 26: second portion

[0017] 28: third portion

[0018] 30: fourth portion

[0019] 32: fifth portion

[0020] 34: first gate pattern

[0021] 36: second gate pattern

[0022] 38: third gate pattern

[0023] 40: fourth gate pattern

[0024] 42: first metal pattern

[0025] 44: second metal pattern

[0026] 46: third metal pattern

[0027] 48: fourth metal pattern

[0028] 50: fifth metal pattern

[0029] 52: contact hole pattern

[0030] 54: contact hole pattern

[0031] 56: contact hole pattern

[0032] 58: contact hole pattern

[0033] 62: metal pattern

[0034] 64: metal pattern

[0035] 66: metal pattern

[0036] 68: metal pattern

[0037] 72: first magnetic tunnel junction

[0038] 74: second magnetic tunnel junction

[0039] 76: third magnetic tunnel junction

[0040] 78: fourth magnetic tunnel junction

[0041] 82: metal pattern

[0042] 84: metal pattern

[0043] 112: substrate

[0044] 114: first cell region

[0045] 116: second cell region

[0046] 122: diffusion region

[0047] 124: first portion

[0048] 126: second portion

[0049] 128: third portion

[0050] 134: first gate pattern

[0051] 136: second gate pattern

[0052] 138: third gate pattern

[0053] 142: first metal pattern

[0054] 144: second metal pattern

[0055] 146: third metal pattern

[0056] 148: fourth metal pattern

[0057] 150: fifth metal pattern

[0058] 152: contact hole pattern

[0059] 154: contact hole pattern

[0060] 156: contact hole pattern

[0061] 158: contact hole pattern

[0062] 162: metal pattern

[0063] 164: metal pattern

[0064] 166: metal pattern

[0065] 168: metal pattern

[0066] 172: first magnetic tunnel junction

[0067] 174: second magnetic tunnel junction

[0068] 176: third magnetic tunnel junction

[0069] 178: fourth magnetic tunnel junction

[0070] 182: metal pattern

[0071] 184: metal pattern

[0072] 186: metal pattern

[0073] 188: metal pattern

[0074] S1: first source region

[0075] S2: second source region

[0076] S3: third source region

[0077] D1: first drain region

[0078] D2: first drain region

[0079] D3: first drain region

[0080] D4: first drain region DETAILED DESCRIPTION

[0081] Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to." Also, the term "couple" or "coupled" means any direct or indirect electrical association between the things that are connected.

[0082] Reference will now be made to Figures 1 to 5 , Figures 1 to 5This is a schematic diagram of the actual layout of an MRAM element according to an embodiment of the present invention. Figure 1 As shown, the MRAM device of the present invention first provides a substrate 12 made of semiconductor material, and the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. Then, a first cell region 14, a second cell region 16, a third cell region 18, and a fourth cell region 20 are defined on the substrate, wherein each cell region or memory cell region preferably includes two sets of transistors and a magnetic tunneling junction (MTJ) in subsequent fabrication processes, thereby forming a cell region structure of two transistors with one MTJ (or simply 2T1MTJ).

[0083] The substrate 12 includes a diffusion region 22 extending to a first unit region 14, a second unit region 16, a third unit region 18, and a fourth unit region 20, wherein the diffusion region 22 comprises an H-shape according to a top view angle. In detail, the diffusion region 22 further includes a first portion 24 extending from the first unit region 14 to the third unit region 18 along a first direction (e.g., the Y direction), a second portion 26 extending from the second unit region 16 to the fourth unit region 20 along the first direction, a third portion 28 extending from the first unit region 14 to the second unit region 16 along a second direction (e.g., the X direction) and connecting the first portion 24 and the second portion 26, a fourth portion 30 extending from the third unit region 18 to the fourth unit region 20 along the second direction and connecting the first portion 24 and the second portion 26, and a fifth portion 32 extending between the third portion 28 and the fourth portion 30 along the second direction and connecting the first portion 24 and the second portion 26.

[0084] Overall, the third part 28, the fourth part 30 and the fifth part 32 all extend along the X direction and are set in parallel. The fifth part 32 is located between the third part 28 and the fourth part 30 and overlaps the first unit area 14, the second unit area 16, the third unit area 18 and the fourth unit area 20.

[0085] In addition, multiple gate patterns or word lines (WL), such as the first gate pattern 34, the second gate pattern 36, the third gate pattern 38, and the fourth gate pattern 40, are disposed on the diffusion region 22. The first gate pattern 34 extends from the first unit region 14 to the second unit region 16 along the second direction, the second gate pattern 36 extends from the first unit region 14 to the second unit region 16 along the second direction, the third gate pattern 38 extends from the third unit region 18 to the fourth unit region 20 along the second direction, and the fourth gate pattern 40 extends from the third unit region 18 to the fourth unit region 20 along the second direction.

[0086] The MRAM element further includes a first source region S1 disposed on the third portion 28 of the diffusion region 22, a second source region S2 disposed on the fourth portion 30, a third source region S3 disposed on the fifth portion 32, a first drain region D1 disposed on the first cell region 14 between the first gate pattern 34 and the second gate pattern 36, a second drain region D2 disposed on the second cell region 16 between the first gate pattern 34 and the second gate pattern 36, a third drain region D3 disposed on the third cell region 18 between the third gate pattern 38 and the fourth gate pattern 40, and a fourth drain region D4 disposed on the fourth cell region 20 between the third gate pattern 38 and the fourth gate pattern 40. It should be noted that each of the first source region S1, the second source region S2, the third source region S3, the first drain region D1, the second drain region D2, the third drain region D3, and the fourth drain region D4 is provided with rectangular contact plugs (not shown) to connect to the subsequent first layer metal pattern. However, each source region and drain region is actually located on the substrate 12 on both sides of each gate pattern, rather than being limited to the rectangular block.

[0087] like Figure 2 As shown, the MRAM element further includes multiple first-layer metal patterns (M1) disposed on the first cell region 14, the second cell region 16, the third cell region 18 and the fourth cell region 20, and overlapping each gate pattern. The first-layer metal pattern includes a first metal pattern 42 extending along a first direction such as the Y direction, overlapping and connecting the first source region S1, the second source region S2 and the third source region S3 below, a second metal pattern 44 extending along the first direction, overlapping and connecting the first drain region D1, a third metal pattern 46 extending along the first direction, overlapping and connecting the second drain region D2, a fourth metal pattern 48 extending along the first direction, overlapping and connecting the third drain region D3, and a fifth metal pattern 50 extending along the first direction, overlapping and connecting the fourth drain region D4.

[0088] From a top-view perspective, the first metal pattern 42, second metal pattern 44, third metal pattern 46, fourth metal pattern 48, and fifth metal pattern 50 in the first layer of metal patterns preferably extend along the Y direction in an approximately rectangular or rectangular shape, overlapping the source and drain regions in each unit area. It should also be noted that the first metal pattern in the first layer of metal pattern 42 is simultaneously coupled to or directly connected to a source line (SL) and transmits the signal through the source line SL.

[0089] The MRAM element further includes multiple first-layer contact hole patterns (V1) disposed on the first-layer metal patterns of the first cell region 14, the second cell region 16, the third cell region 18 and the fourth cell region 20. The first-layer contact hole patterns include contact hole pattern 52 disposed on the second metal pattern 44, contact hole pattern 54 disposed on the third metal pattern 46, contact hole pattern 56 disposed on the fourth metal pattern 48 and contact hole pattern 58 disposed on the fifth metal pattern 50.

[0090] Then as Figure 3 As shown, the MRAM element further includes multiple second-layer metal patterns (M2) disposed on the first cell region 14, the second cell region 16, the third cell region 18, and the fourth cell region 20, overlapping each first-layer metal pattern and the first-layer contact hole pattern. The second-layer metal patterns include a second metal pattern 44 overlapping a metal pattern 62 on the first cell region 14, a third metal pattern 46 overlapping a metal pattern 64 on the second cell region 16, a fourth metal pattern 48 overlapping a metal pattern 66 on the third cell region 18, and a fifth metal pattern 50 overlapping a metal pattern 68 on the fourth cell region 20. From a top viewpoint, each metal pattern in the second-layer metal pattern preferably presents an approximately rectangular shape, such as a square, and overlaps the drain region in each cell region.

[0091] Then as Figure 4 As shown, the MRAM element includes multiple magnetic tunneling junctions (MTJs) disposed on a second-layer metal pattern and coupled to the next second-layer metal pattern and the drain region of the next lower layer. Each MTJ includes a first magnetic tunneling junction 72 disposed on the metal pattern 62 of the first cell region 14 and connected to the first drain region D1; a second magnetic tunneling junction 74 disposed on the metal pattern 64 of the second cell region 16 and connected to the second drain region D2; a third magnetic tunneling junction 76 disposed on the metal pattern 66 of the third cell region 18 and connected to the third drain region D3; and a fourth magnetic tunneling junction 78 disposed on the metal pattern 68 of the fourth cell region 20 and connected to the fourth drain region D4. Since each MTJ is disposed on the second-layer metal pattern, the MTJ can be considered as a third-layer metal pattern (abbreviated as M3).

[0092] In this embodiment, each MTJ preferably comprises, from bottom to top, a lower electrode, a pinned layer, a barrier layer, a free layer, and an upper electrode disposed on the second metal pattern. In this embodiment, the lower and upper electrodes preferably comprise conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer may comprise ferromagnetic materials, such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Alternatively, the pinned layer may be composed of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), and nickel oxide (NiO), to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer may be composed of an insulating material comprising oxides, such as aluminum oxide (AlO). x The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys like cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field.

[0093] Overall, each cell region preferably includes a cell region structure consisting of a pair of two transistors paired with an MTJ (2T1MTJ). Taking the first cell region 14 as an example, the first source region S1, the first gate pattern 34, the first drain region D1, the second gate pattern 36, the third source region D3, and the first magnetic tunnel junction 72 preferably together constitute the 2T1MTJ structure in the first cell region 14.

[0094] Finally, as Figure 5 As shown, the MRAM element includes multiple fourth-layer metal patterns (M4) disposed on the first cell region 14, the second cell region 16, the third cell region 18 and the fourth cell region 20 and overlapping each M4. The fourth-layer metal pattern includes a metal pattern 82 extending from the first cell region 14 to the third cell region 18 along a first direction such as the Y direction and overlapping a first magnetic tunneling junction 72 and a third magnetic tunneling junction 76, and a metal pattern 84 extending from the second cell region 16 to the fourth cell region 20 along a first direction and overlapping a second magnetic tunneling junction 74 and a fourth magnetic tunneling junction 78.

[0095] From a top-view perspective, the metal patterns in the fourth layer of the metal pattern preferably appear as roughly rectangular or elongated rectangles extending along the Y direction and overlapping the drain regions and MTJs in each cell area. It should also be noted that the metal patterns 82 and 84 in the fourth layer of the metal pattern are respectively coupled to or directly connected to a bit line (BL) and transmit signals through the bit line.

[0096] Please refer to Figures 6 to 10 , Figures 6 to 10 This is a schematic diagram of the actual layout of an MRAM element according to an embodiment of the present invention. For the sake of simplicity, some identical elements disclosed in this embodiment and the previous embodiments are preferably referred to by the same reference numerals. Figure 6 As shown, the MRAM device of the present invention first provides a substrate 112 made of semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. Then, a first cell region 114 and a second cell region 116 are defined on the substrate 112, wherein each cell region or memory cell region preferably includes three sets of transistors and two magnetic tunneling junctions (MTJs) in subsequent fabrication processes, thereby forming a cell region structure of three transistors with two MTJs (or simply 3T2MTJ).

[0097] The substrate 112 includes a diffusion region 122 extending to a first unit region 114 and a second unit region 116, wherein the diffusion region 122 comprises a first H-shape and a second H-shape according to a top viewing angle. In detail, the diffusion region 122 further includes a first portion 124 extending along a first direction (e.g., the Y direction) within the first unit region 114, a second portion 126 extending along the first direction within the second unit region 116, a third portion 128 extending along a second direction (e.g., the X direction) from the first unit region 114 to the second unit region 116 and connecting the first portion 124 and the second portion 126, and a fourth portion 130 extending along the second direction from the first unit region 114 to the second unit region 116 and connecting the first portion 124 and the second portion 126.

[0098] It is noted that the third portion 128 and the fourth portion 130 overlap the junction of the first cell region 114 and the second cell region 116, respectively, from the top view, and the first portion 124, the second portion 126, the third portion 128 and the fourth portion 130 all partially extend beyond the boundary of the first cell region 114 and the second cell region 116, but the present application is not limited thereto. According to other embodiments of the present application, the peripheral boundary of the first portion 124, the second portion 126, the third portion 128 and the fourth portion 130 can all be controlled within the first cell region 114 and the second cell region 116, and the four portions of the diffusion region 122 do not extend beyond the boundary of the two cell regions. Such a variation also falls within the scope of the present application.

[0099] The MRAM element further includes a plurality of gate patterns, such as a first gate pattern 134, a second gate pattern 136 and a third gate pattern 138, disposed on the diffusion region 122, wherein the first gate pattern 134 extends along the second direction from the first cell region 114 to the second cell region 116, the second gate pattern 136 extends along the second direction from the first cell region 114 to the second cell region 116, and the third gate pattern 138 extends along the second direction from the first cell region 114 to the second cell region 116.

[0100] The MRAM element further includes a first source region S1 disposed on the third portion 128 of the diffusion region 122, a second source region S2 disposed on the fourth portion 130, a first drain region D1 disposed on the first cell region 114 between the first gate pattern 134 and the second gate pattern 136, a second drain region D2 disposed on the second cell region 116 between the first gate pattern 134 and the second gate pattern 136, a third drain region D3 disposed on the first cell region 114 between the third gate pattern 136 and the fourth gate pattern 138, and a fourth drain region D4 disposed on the second cell region 116 between the third gate pattern 136 and the fourth gate pattern 138. As in the foregoing embodiment, each of the first source region S1, the second source region S2, the first drain region D1, the second drain region D2, the third drain region D3 and the fourth drain region D4 is provided with a rectangular square-shaped contact plug (not shown) connected to a subsequent first layer metal pattern, but each of the source regions and the drain regions is actually disposed on the substrate 12 on both sides of each of the gate patterns, rather than being limited within the rectangular square.

[0101] As Figure 7As shown, the MRAM element further includes multiple first-layer metal patterns (M1) disposed on the first cell region 114 and the second cell region 116 and overlapping each gate pattern. The first-layer metal patterns include a first metal pattern 142 extending along a first direction such as the Y direction, overlapping and connecting the first source region S1 and the second source region S2; a second metal pattern 144 extending along the first direction, overlapping and connecting the first drain region D1; a third metal pattern 146 extending along the first direction, overlapping and connecting the second drain region D2; a fourth metal pattern 148 extending along the first direction, overlapping and connecting the third drain region D3; and a fifth metal pattern 150 extending along the first direction, overlapping and connecting the fourth drain region D4.

[0102] From a top-view perspective, the first metal pattern 142, second metal pattern 144, third metal pattern 146, fourth metal pattern 148, and fifth metal pattern 150 in the first layer of metal pattern preferably extend along the Y direction in an approximately rectangular or rectangular shape, overlapping the source and drain regions in each unit area. As in the aforementioned embodiment, the first metal pattern 142 in the first layer of metal pattern is also coupled to or directly connected to a source line (SL) and transmits the signal through the source line.

[0103] The MRAM element further includes multiple first-layer contact hole patterns (V1) disposed on the first cell region 114 and the second cell region 116 and overlapping each first-layer metal pattern. The first-layer contact hole patterns include contact hole pattern 152 disposed on the second metal pattern 144, contact hole pattern 154 disposed on the third metal pattern 146, contact hole pattern 156 disposed on the fourth metal pattern 148, and contact hole pattern 158 disposed on the fifth metal pattern 150.

[0104] Then as Figure 8 As shown, the MRAM element includes multiple second-layer metal patterns (M2) disposed on the first cell region 114 and the second cell region 116, overlapping each first-layer metal pattern and the first-layer contact hole pattern. The second-layer metal patterns include a second metal pattern 144 overlapping a metal pattern 162 on the first cell region 114, a third metal pattern 146 overlapping a metal pattern 164 on the second cell region 116, a fourth metal pattern 148 overlapping a metal pattern 166 on the first cell region 114, and a fifth metal pattern 150 overlapping a metal pattern 168 on the second cell region. From a top viewpoint, each metal pattern in the second-layer metal pattern preferably presents an approximately rectangular shape, such as a square, and overlaps the drain region in each cell region.

[0105] In addition, such as Figure 9As shown, the MRAM element includes multiple magnetic tunneling junctions (MTJs) disposed on a second-layer metal pattern and coupled to the next second-layer metal pattern and the drain region of the next lower layer. Each magnetic tunneling junction includes a first magnetic tunneling junction 172 disposed on the metal pattern 162 of the first cell region 114 and connected to the first drain region D1; a second magnetic tunneling junction 174 disposed on the metal pattern 164 of the second cell region 116 and connected to the second drain region D2; a third magnetic tunneling junction 176 disposed on the metal pattern 166 of the first cell region 114 and connected to the third drain region D3; and a fourth magnetic tunneling junction 178 disposed on the metal pattern 168 of the second cell region 116 and connected to the fourth drain region D4. Since each MTJ is disposed on the second-layer metal pattern, the MTJ can be considered as a third-layer metal pattern (abbreviated as M3). As in the aforementioned embodiments, each MTJ preferably comprises, from bottom to top, a lower electrode, a pinned layer, a barrier layer, a free layer, and an upper electrode disposed on the second metal pattern.

[0106] Overall, each cell region preferably includes a cell region structure consisting of a set of three transistors paired with two MTJs (3T2MTJ). Taking the first cell region 114 as an example, the first source region S1, the first gate pattern 134, the first drain region D1, the second gate pattern 136, the second source region D2, the first magnetic tunnel junction 172, and the third magnetic tunnel junction 176 preferably together constitute the 3T2MTJ structure in the first cell region 114.

[0107] Finally, as Figure 10 As shown, the MRAM element includes multiple fourth-layer metal patterns (M4) disposed on the first cell region 114 and the second cell region 116 and overlapping each MTJ. The fourth-layer metal patterns include metal patterns 182 and 184 extending along a first direction, such as the Y direction, within the first cell region 114 and overlapping the first magnetic tunnel junction 172 and the third magnetic tunnel junction 176, respectively. Metal patterns 186 and 188 extend along the first direction within the second cell region 116 and overlap the second magnetic tunnel junction 174 and the fourth magnetic tunnel junction 178.

[0108] From a top-view perspective, the metal patterns in the fourth layer of the metal pattern ideally appear as roughly rectangular or elongated rectangles extending along the Y direction and overlapping the drain regions and MTJs in each cell area. It should also be noted that each metal pattern in the fourth layer of the metal pattern is either coupled to or directly connected to a bit line (BL) and transmits the signal through the bit line.

[0109] In summary, compared with the prior art MRAM element, in which the second metal layer pattern is generally used to connect the source line SL and transmit signals, the preferred adjustment of the diffusion region and the pattern configuration of the first metal layer pattern allows the first metal layer pattern to directly connect the source line. This design not only saves the space of each storage unit region in the MRAM element, but also adjusts the position of the MTJ, so that the MTJ is less likely to deviate from the underlying metal interconnection and affect the element performance.

[0110] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be within the scope of the present application.

Claims

1. A layout pattern of a magnetoresistive random access memory, characterized by, Comprising: a substrate comprising a first memory cell region, a second memory cell region, a third memory cell region, and a fourth memory cell region; and a diffusion region disposed on the substrate and extending to the first memory cell region, the second memory cell region, the third memory cell region, and the fourth memory cell region, wherein the diffusion region comprises an H shape, the H shape comprising a portion overlapping the first memory cell region, the second memory cell region, the third memory cell region, and the fourth memory cell region, wherein the diffusion region comprises: a first portion extending from the first memory cell region to the third memory cell region along a first direction; a second portion extending from the second memory cell region to the fourth memory cell region along the first direction; a third portion extending from the first memory cell region to the second memory cell region along a second direction and connecting the first portion and the second portion; a fourth portion extending from the third memory cell region to the fourth memory cell region along the second direction and connecting the first portion and the second portion; and a fifth portion extending between the third portion and the fourth portion along the second direction and connecting the first portion and the second portion.

2. The layout pattern of a magnetoresistive random access memory as claimed in claim 1, wherein the fifth portion overlaps the first memory cell region, the second memory cell region, the third memory cell region, and the fourth memory cell region.

3. The layout pattern of a magnetoresistive random access memory as claimed in claim 1, further comprising: a first gate pattern extending from the first memory cell region to the second memory cell region along the second direction; a second gate pattern extending from the first memory cell region to the second memory cell region along the second direction; a third gate pattern extending from the third memory cell region to the fourth memory cell region along the second direction; and a fourth gate pattern extending from the third memory cell region to the fourth memory cell region along the second direction.

4. The layout pattern of a magnetoresistive random access memory as claimed in claim 3, further comprising: a first source region disposed on the third portion; a second source region disposed on the fourth portion; and a third source region disposed on the fifth portion.

5. The layout pattern of a magnetoresistive random access memory as claimed in claim 4, further comprising: a first metal pattern extending to overlap and connect the first source region, the second source region, and the third source region along the first direction.

6. The layout pattern of a magnetoresistive random access memory as claimed in claim 5, wherein the first metal pattern connects a source line.

7. The layout pattern of a magnetoresistive random access memory as claimed in claim 4, further comprising: a first drain region disposed on the first memory cell region between the first gate pattern and the second gate pattern; a second drain region disposed on the second memory cell region between the first gate pattern and the second gate pattern; a third drain region disposed on the third memory cell region between the third gate pattern and the fourth gate pattern; and a fourth drain region disposed on the fourth memory cell region between the third gate pattern and the fourth gate pattern. ​ ​ ​ 8. The layout pattern of a magnetoresistive random access memory as recited in claim 7, further comprising: a second metal pattern extending along the first direction to overlap and connect the first drain region; a third metal pattern extending along the first direction to overlap and connect the second drain region; a fourth metal pattern extending along the first direction to overlap and connect the third drain region; and a fifth metal pattern extending along the first direction to overlap and connect the fourth drain region.

9. The layout pattern of a magnetoresistive random access memory as recited in claim 7, further comprising: a first magnetic tunnel junction connected to the first drain region; a second magnetic tunnel junction connected to the second drain region; a third magnetic tunnel junction connected to the third drain region; and a fourth magnetic tunnel junction connected to the fourth drain region. comprising:

10. A semiconductor device, characterized by comprising: a substrate including a first memory cell region and a second memory cell region; and a diffusion region disposed on the substrate and extending into the first memory cell region and the second memory cell region, wherein the diffusion region includes a first H-shape and a second H-shape, the first H-shape and the second H-shape including two horizontal portions connected between two vertical portions.

11. The semiconductor element as recited in claim 10, wherein the diffusion region includes: a first portion extending in the first memory cell region along a first direction; a second portion extending in the second memory cell region along the first direction; a third portion extending from the first memory cell region to the second memory cell region along a second direction and connecting the first portion and the second portion; and a fourth portion extending from the first memory cell region to the second memory cell region along the second direction and connecting the first portion and the second portion.

12. The semiconductor element as recited in claim 11, wherein the third portion overlaps a boundary of the first memory cell region and the second memory cell region.

13. The semiconductor element as recited in claim 11, further comprising: a first gate pattern extending from the first memory cell region to the second memory cell region along the second direction; a second gate pattern extending from the first memory cell region to the second memory cell region along the second direction; and a third gate pattern extending from the first memory cell region to the second memory cell region along the second direction.

14. The semiconductor element as recited in claim 13, further comprising: a first source region disposed on the third portion; and a second source region disposed on the fourth portion.

15. The semiconductor element as recited in claim 14, further comprising a first metal pattern extending along the first direction to overlap and connect the first source region and the second source region.

16. The semiconductor element as recited in claim 15, wherein the first metal pattern connects a source line.

17. The semiconductor element as recited in claim 14, further comprising: a first drain region disposed on the first memory cell region between the first gate pattern and the second gate pattern; a second drain region disposed on the second memory cell region between the first gate pattern and the second gate pattern; ​ ​ a third drain region provided on the first memory cell region between the second gate pattern and the third gate pattern; and a fourth drain region provided on the second memory cell region between the second gate pattern and the third gate pattern.

18. The semiconductor device according to claim 17, further comprising: a second metal pattern extending along the first direction to overlap and connect the first drain region; a third metal pattern extending along the first direction to overlap and connect the second drain region; a fourth metal pattern extending along the first direction to overlap and connect the third drain region; and a fifth metal pattern extending along the first direction to overlap and connect the fourth drain region.

19. The semiconductor device according to claim 17, further comprising: a first magnetic tunnel junction connected to the first drain region; a second magnetic tunnel junction connected to the second drain region; a third magnetic tunnel junction connected to the third drain region; and a fourth magnetic tunnel junction connected to the fourth drain region.

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