Display device

Abstract

A display device is disclosed, which includes: a first power sharing line, which is arranged to be parallel to a first direction; a first pixel and a second pixel, which are arranged along a second direction intersecting the first direction with the first power sharing line interposed therebetween; and a second power sharing line, which is arranged to be parallel to the first power sharing line with any one of the first pixel and the second pixel interposed therebetween.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] As the information age progresses, demand for display devices for displaying images has increased in various forms. Therefore, various types of display devices such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and organic light emitting display (OLED) devices have recently been used.

[0003] Among such display devices, an organic light emitting display device is a self-luminous display device using an organic light emitting diode, which injects holes from an anode and electrons from a cathode into a light emitting layer and emits light when excitons generated by the recombination of the injected holes and electrons change their state from an excited state to a ground state.

[0004] Organic light emitting display devices may be classified into a top emission type, a bottom emission type, and a double-sided emission type according to a direction in which light is emitted, and may be classified into a passive matrix type and an active matrix type according to a driving method.

[0005] Unlike liquid crystal display (LCD) devices, organic light-emitting display devices do not require a separate light source and can therefore be manufactured in a lightweight and thin form. Furthermore, organic light-emitting display devices are advantageous in terms of power consumption because they are driven by a low voltage. Furthermore, organic light-emitting display devices have excellent color rendering capabilities, high response speed, wide viewing angle, and high contrast ratio (CR). Therefore, organic light-emitting display devices have been developed as next-generation display devices.

[0006] Organic light-emitting display devices include storage capacitors to maintain a certain current during light emission. These storage capacitors are installed pixel by pixel and occupy a certain area, thereby reducing the aperture ratio. With the trend toward higher resolutions in display devices, the aperture ratio has recently become a significant issue. Increasing the aperture ratio can reduce the current density of the light-emitting diodes, thereby increasing their lifespan. As high-resolution display devices become increasingly popular, there is a need to develop organic light-emitting display devices with high aperture ratios.

[0007] The disclosure of the above background technology is technical information owned by the inventor of the present disclosure in designing the present disclosure or obtained through the process of designing the present disclosure, but it cannot be considered as known technology disclosed to the public before the disclosure of the present disclosure. Summary of the Invention

[0008] The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a display device that can improve an aperture ratio within a limited space of a sub-pixel, simplify a structure, and reduce a load deviation of a sensing line.

[0009] In addition to the objects of the present disclosure as described above, those skilled in the art will clearly understand further objects and features of the present disclosure from the following description of the present disclosure.

[0010] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a display device, which includes: a first power sharing line, which is arranged to be parallel to a first direction; a first pixel and a second pixel, which are arranged along a second direction intersecting the first direction and with the first power sharing line inserted therebetween; and a second power sharing line, which is arranged to be parallel to the first power sharing line and with any one of the first pixel and the second pixel inserted therebetween.

[0011] According to another aspect of the present disclosure, the above and other purposes can be achieved by providing a display device, which includes: a plurality of pixels having a plurality of sub-pixels arranged along a first direction and a second direction intersecting the first direction; a first power sharing line arranged between a first pixel arranged in a (2i)th (i is a natural number)th horizontal line and a second pixel arranged in a (2i-1)th horizontal line among the plurality of pixels; and a second power sharing line arranged on one side of the first pixel or on the other side of the second pixel.

[0012] In the display device according to the present disclosure, the driving thin film transistor can be arranged on the upper side of the light-emitting area based on each sub-pixel, so that the power lines of the sub-pixels adjacent to each other can be shared, and the number of sensing line contact holes of the corresponding sub-pixels can be reduced. This can improve the aperture ratio within the limited space of the sub-pixels, simplify the structure, and reduce the load deviation of the sensing lines. Therefore, the display performance can be improved by increasing the brightness based on the increase in the aperture ratio, and the life of the light-emitting diode can be increased.

[0013] In addition to the effects of the present disclosure as described above, other objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0015] Figure 1 is a schematic block diagram illustrating a display device according to various embodiments of the present disclosure;

[0016] Figure 2 This is an example Figure 1 Schematic circuit driving diagram of a sub-pixel of a display device;

[0017] Figure 3 This is an example Figure 1 An equivalent circuit diagram of an example of a sub-pixel of a display device shown;

[0018] Figure 4 is a schematic plan view illustrating a unit pixel of a display device according to various embodiments of the present disclosure;

[0019] Figure 5 This is an example Figure 4 A schematic plan view showing the relationship between a unit pixel, a power supply line, and a signal supply line;

[0020] Figure 6 is a plan view illustrating a pixel array of a display device according to various embodiments of the present disclosure;

[0021] Figure 7 yes Figure 6 an enlarged view of part A;

[0022] Figure 8 It is along Figure 7 A cross-sectional view taken along line II';

[0023] Figure 9 yes Figure 6 an enlarged view of part B;

[0024] Figure 10 is a schematic plan view illustrating a unit pixel of a display device according to various embodiments of the present disclosure;

[0025] Figure 11 It is along Figure 10 A cross-sectional view taken along line II-II';

[0026] Figure 12 It is along Figure 10 A cross-sectional view taken along line III-III';

[0027] Figure 13 It is along Figure 10 A cross-sectional view taken along line IV-IV';

[0028] Figure 14 This is an example Figure 10 An equivalent circuit diagram of a storage capacitor of a sub-pixel of part C; and

[0029] Figures 15 to 19 This is an example Figure 5 A plan view of a single-layer structure of a portion of a unit pixel shown in FIG. DETAILED DESCRIPTION

[0030] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0031] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details illustrated. Like reference numerals refer to like elements throughout the specification. In the following description, when a detailed description of a related known function or configuration is determined to be unnecessary to obscure the main points of the present disclosure, the detailed description will be omitted.

[0032] In the case where “including,” “having,” and “comprising” described in this specification are used, another component may be added unless “only” is used. Terms in the singular form may include plural forms unless mentioned otherwise.

[0033] When explaining an element, although not explicitly described, the element is interpreted as including an error range.

[0034] When describing a positional relationship, for example, when the positional relationship is described as "on," "above," "below," and "next to," one or more parts may be arranged between two other parts unless "just" or "directly" is used.

[0035] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," or "before," discontinuous cases may be included unless "just" or "directly" is used.

[0036] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present invention.

[0037] The terms "first horizontal axis direction", "second horizontal axis direction" and "vertical axis direction" should not be interpreted solely based on a geometric relationship in which the corresponding directions are perpendicular to each other, and may mean directions with wider directionality within the range in which the components of the present disclosure can functionally operate.

[0038] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of two or more items from the first, second, and third items, as well as all items proposed from the first, second, or third items.

[0039] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways and be driven technically, as will be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0040] Hereinafter, preferred embodiments of the display device according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar components. Since the scale of each element shown in the drawings is different from the actual scale for ease of description, the present disclosure is not limited to the scale shown.

[0041] Figure 1 is a schematic block diagram illustrating a display device according to various embodiments of the present disclosure. Figure 2 This is an example Figure 1 Schematic circuit driving diagram of a sub-pixel of a display device. Figure 3 This is an example Figure 1 FIG. 1 is an equivalent circuit diagram of an example of a sub-pixel of a display device shown.

[0042] Reference Figures 1 to 3 , the display device 100 according to various embodiments of the present disclosure may include a display panel 110 , an image processor 120 , a timing controller 130 , a data driver 140 , and a scan driver 150 .

[0043] The display panel 110 may display an image in response to a data signal DATA and a scan signal respectively provided from the data driver 140 and the scan driver 150. The display panel 110 may include sub-pixels SP that operate to display an image.

[0044] The sub-pixels may be formed as top-emission type, bottom-emission type, or double-sided emission type depending on the structure. The sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels, or may include red sub-pixels, blue sub-pixels, white sub-pixels, and green sub-pixels, but the present disclosure is not limited thereto. The sub-pixels SP may have one or more different light-emitting regions according to light-emitting characteristics.

[0045] The image processor 120 may output a data enable signal DE together with a data signal DATA provided from the outside. In addition to the data enable signal DE, the image processor 120 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, but for ease of description, these signals will be omitted and not shown.

[0046] The data signal DATA may be provided from the image processor 120 to the timing controller 130 together with a driving signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 130 may output a data timing control signal DDC for controlling the operation timing of the data driver 140 and a gate timing control signal GDC for controlling the operation timing of the scan driver 150 based on the driving signal.

[0047] The data driver 140 can sample and latch the data signal data provided by the timing controller 130 in response to the data timing control signal DDC provided by the timing controller 130, convert the latched data signal into a gamma reference voltage, and output the converted gamma reference voltage. The data driver 140 can output the data signal DATA through the data lines DL1 to DLn. The data driver 140 can be implemented in the form of an integrated circuit (IC).

[0048] The scan driver 150 may output a scan signal in response to a gate timing control signal GDC provided from the timing controller 130. The scan driver 150 may output the scan signal through the gate lines GL1 to GLm. The scan driver 150 may be implemented in the form of an IC (Integrated Circuit) or may be implemented in the display panel 110 in a gate-in-panel (GIP) type.

[0049] like Figure 2 As shown, one sub-pixel SP constituting a unit pixel may include a switching thin film transistor SW, a driving thin film transistor DR, a storage capacitor Cst, a compensation circuit CC, and a light emitting diode EL.

[0050] The switching thin film transistor SW can perform a switching operation to store a data signal provided through the first data line DL1 as a data voltage in the storage capacitor Cst in response to a scan signal provided through the first gate line GL1. The driving thin film transistor DR can operate to flow a driving current between the first power line EVDD (e.g., a high potential voltage) and the second power line EVSS (e.g., a low potential voltage) according to the data voltage stored in the storage capacitor Cst. The light emitting diode EL can operate to emit light according to the driving current formed by the driving thin film transistor DR.

[0051] The compensation circuit CC is a circuit added to the sub-pixel to compensate for the threshold voltage of the driving thin film transistor DR. The compensation circuit CC may include one or more thin film transistors. The compensation circuit CC may have various configurations depending on the compensation method, so examples thereof will be described below.

[0052] like Figure 3 As shown, the compensation circuit CC may include a sensing thin film transistor ST and a sensing line VREF.

[0053] The sensing thin film transistor ST may be connected between the drain electrode of the driving thin film transistor DR and the anode electrode (hereinafter, a sensing node) of the light emitting diode EL. The sensing thin film transistor ST may be operated to provide an initialization voltage (or a sensing voltage) transmitted through the sensing line VREF to the sensing node of the driving thin film transistor DR or to sense a voltage or current of the sensing node of the driving thin film transistor DR or the sensing line VREF.

[0054] A first electrode (eg, source electrode) of the switching thin film transistor SW may be connected to the first data line DL1 , and a second electrode (eg, drain electrode) of the switching thin film transistor SW may be connected to the gate electrode of the driving thin film transistor DR.

[0055] A first electrode (eg, source electrode) of the driving thin film transistor DR may be connected to the first power line EVDD, and a second electrode (eg, drain electrode) of the driving thin film transistor DR may be connected to the anode electrode of the light emitting diode EL.

[0056] The storage capacitor Cst may include a first electrode connected to the gate electrode of the driving thin film transistor DR and a second electrode connected to the anode electrode of the light-emitting diode EL. In the display device according to various embodiments of the present disclosure, the storage capacitor Cst may include a first electrode pattern DTG connected to the gate electrode of the driving thin film transistor DR and a second electrode pattern DTS connected to the source electrode of the driving thin film transistor DR. The first electrode pattern DTG and the second electrode pattern DTS may be formed by making the active layer conductive. In addition, the storage capacitor Cst may include a first capacitor formed in the horizontal direction and a second capacitor formed in the vertical direction according to various modifications of the first electrode pattern DTG and the second electrode pattern DTS. For example, each of the first electrode pattern DTG and the second electrode pattern DTS may include a finger pattern structure, wherein the first electrode pattern and the second electrode pattern are arranged parallel to each other on the same plane. The horizontal capacitor may be formed by structures spaced apart from each other in the horizontal direction. The storage capacitor Cst will be described in more detail later.

[0057] An anode electrode of the light emitting diode EL may be connected to the second electrode of the driving thin film transistor DR, and a cathode electrode thereof may be connected to the second power line EVSS. For example, the light emitting diode EL may be an organic light emitting diode (OLED).

[0058] A first electrode (eg, source electrode) of the sensing thin film transistor ST may be connected to the sensing line VREF, and a second electrode (eg, drain electrode) thereof may be connected to the anode electrode of the light emitting diode EL as a sensing node and the second electrode of the driving thin film transistor DR.

[0059] Depending on the compensation algorithm (or the configuration of the compensation circuit), the operating time of the sensing thin film transistor ST may be similar to, the same as, or different from the operating time of the switching thin film transistor SW. For example, the gate electrode of the switching thin film transistor SW may be connected to the first gate line GL1, and the gate electrode of the sensing thin film transistor ST may be connected to the second gate line GL2. In this case, the scan signal Scan may be transmitted to the first gate line GL1, and the sensing signal Sense may be transmitted to the second gate line GL2. For another example, the first gate line GL1 connected to the gate electrode of the switching thin film transistor SW and the second gate line GL2 connected to the gate electrode of the sensing thin film transistor ST may be connected to each other.

[0060] The sensing line VREF may be connected to the data driver 140. In this case, the data driver 140 may sense the sensing node of the sub-pixel in real time, during the non-display period of the image, or during N frame periods (N is an integer of 1 or greater), and may generate a sensing result. In addition, the switching thin film transistor SW and the sensing thin film transistor ST may be turned on at the same time. In this case, the sensing operation through the sensing line VREF and the data output operation for outputting the data signal may be separated (individualized) from each other by the time division method of the data driver 140.

[0061] In addition, the compensation target based on the sensing result can be a digital type data signal, an analog type data signal, or a gamma voltage. The compensation circuit for generating a compensation signal (or compensation voltage) based on the sensing result can be implemented as an internal circuit of the data driver 140, an internal circuit of the timing controller 130, or a separate circuit.

[0062] In addition, Figure 3 In the example, although a sub-pixel of a 3T (transistor) 1C (capacitor) structure including a switching thin film transistor SW, a driving thin film transistor DR, a storage capacitor Cst, a light emitting diode EL and a sensing thin film transistor ST has been described as an example, when a compensation circuit CC is added thereto, each sub-pixel may have a structure of 3T2C, 4T2C, 5T1C, 6T2C, etc.

[0063] Figure 4 is a schematic plan view illustrating a unit pixel of a display device according to various embodiments of the present disclosure. Figure 4 Briefly illustrate the Figure 3 The unit pixel is a sub-pixel.

[0064] Reference Figure 4 , a unit pixel of a display device according to various embodiments of the present disclosure may include first to fourth sub-pixels R, B, W, and G, which include a red sub-pixel R, a blue sub-pixel B, a white sub-pixel W, and a green sub-pixel G. However, the present disclosure is not limited to Figure 4 In this example, a unit pixel may include a first subpixel R, a third subpixel G, and a third subpixel B, which include a red subpixel R, a green subpixel G, and a blue subpixel B. Furthermore, various modifications may be made to the arrangement of at least three or four subpixels included in a unit pixel. In the following description, a 3T1C subpixel will be described as an example.

[0065] Each of the first to fourth sub-pixels R, B, W, and G may include an opening area LE in which a light-emitting area is located, and a first circuit area C1 and a second circuit area C2 respectively provided on both sides (i.e., the upper side and the lower side in the figure) of the opening area (or light-emitting area) LE. That is, in the display device according to various embodiments of the present disclosure, the first circuit area C1 and the second circuit area C2 in each of the sub-pixels R, B, W, and G may be separated from each other based on the opening area LE.

[0066] In the display device according to various embodiments of the present disclosure, the driving thin film transistors DR included in the first to fourth subpixels R, B, W and G can be respectively arranged in the first circuit regions RC1, BC1, WC1 and GC1, and the switching thin film transistor SW and the sensing thin film transistor ST can be respectively arranged in the second circuit regions RC2, BC2, WC2 and GC2, and the storage capacitor Cst can respectively overlap with the opening regions RLE, BLE, WLE and LE and be arranged between the first circuit regions RC1, BC1, WC1 and GC1 and the second circuit regions RC2, BC2, WC2 and GC2.

[0067] Since the display device according to various embodiments of the present disclosure includes the first circuit area C1 and the second circuit area C2 at both the upper and lower sides of the opening area LE based on the sub-pixels R, B, W, and G, the sub-pixels R, B, W, and G in different rows adjacent to each other can be arranged in a mirror shape to share a common line therebetween, thereby achieving an effect of increasing the aperture ratio.

[0068] Figure 5 This is an example Figure 4Schematic plan view of the relationship between unit pixels, power supply lines and signal supply lines.

[0069] Reference Figure 5 , a display device according to various embodiments of the present disclosure may include four first to fourth sub-pixels R, B, W, and G constituting a unit pixel, a plurality of first power lines EVDD1 and EVDD2, data lines DL1 to DL4, gate lines GL1 and GL2, and a second power line VREF.

[0070] The corresponding sub-pixels R, B, W, and G constituting one unit pixel may be repeatedly arranged to be spaced apart from each other along a first direction (e.g., a horizontal direction) to constitute a row. The arrangement of the sub-pixels of a row may be repeatedly applied along a second direction (e.g., a vertical direction) intersecting the first direction to constitute a pixel array including a plurality of rows of sub-pixels R, B, W, and G.

[0071] Multiple first power lines EVDD1 and EVDD2 may extend in parallel along the second direction with four first to fourth sub-pixels R, B, W, and G interposed therebetween. The multiple first power lines EVDD1 and EVDD2 may be separated by adjacent unit pixels in the first direction. For example, the multiple first power lines EVDD1 and EVDD2 may be arranged on the left side of the first sub-pixel R arranged along the second direction and on the right side of the fourth sub-pixel G arranged along the second direction, respectively. A first power sharing line EVDD_H, extending in the first direction and electrically connected to the left and right first power lines EVDD1 and EVDD2, may be included between the multiple first power lines EVDD1 and EVDD2. The first power sharing line EVDD_H may be formed in a straight line between the multiple first power lines EVDD1 and EVDD2. The multiple first power lines EVDD1 and EVDD2 may be connected to the drive thin film transistors DR provided in the first circuit region of the first to fourth sub-pixels R, B, W, and G via the first power sharing line EVDD_H.

[0072] In the display device according to various embodiments of the present disclosure, the first power sharing line EVDD_H may be provided in the first to fourth sub-pixels R, B, W, and G (e.g., Figure 5 ) and the first to fourth sub-pixels R, B, W, and G arranged in the (2i-1)th horizontal line (for example, Figure 5For example, the first to fourth sub-pixels R, B, W, and G arranged in the (2i)th horizontal line and the first to fourth sub-pixels R, B, W, and G arranged in the (2i-1)th horizontal line may be arranged to be symmetrical to each other in a mirror shape, and the first circuit area of ​​the first to fourth sub-pixels R, B, W, and G arranged in the (2i)th horizontal line and the first circuit area of ​​the first to fourth sub-pixels R, B, W, and G arranged in the (2i-1)th horizontal line may be arranged to be adjacent to each other with the first power sharing line EVDD_H interposed therebetween.

[0073] The first power sharing line EVDD_H may be commonly connected to the first to fourth sub-pixels R, B, W, and G disposed in the (2i)th horizontal line and the first to fourth sub-pixels R, B, W, and G disposed in the (2i-1)th horizontal line. For example, the first power sharing line EVDD_H may be connected to each of the driving thin film transistors DR disposed in the first circuit region of the first to fourth sub-pixels R, B, W, and G disposed in the (2i)th horizontal line, and to each of the driving thin film transistors DR disposed in the first circuit region of the first to fourth sub-pixels R, B, W, and G disposed in the (2i-1)th horizontal line.

[0074] The four first to fourth sub-pixels R, B, W, and G constituting a unit pixel may include first branch power patterns extending in a second direction toward the first power sharing line EVDD_H. For example, the respective sub-pixels R, B, W, and G may include: first branch power patterns EVDD_H_br1 and EVDD_H_br2 connecting the first sub-pixel R to the first power sharing line EVDD_H; first branch power patterns EVDD_H_bb1 and EVDD_H_bb2 connecting the second sub-pixel B to the first power sharing line EVDD_H; first branch power patterns EVDD_H_bw1 and EVDD_H_bw2 connecting the third sub-pixel W to the first power sharing line EVDD_H; and first branch power patterns EVDD_H_bg1 and EVDD_H_bg2 connecting the fourth sub-pixel G to the first power sharing line EVDD_H.

[0075] The data lines DL1 to DL4 may be arranged to extend in parallel along the second direction between the first sub-pixel R and the second sub-pixel B, and between the third sub-pixel W and the fourth sub-pixel G. For example, the first data line DL1 and the second data line DL2 may be arranged in parallel between the first sub-pixel R and the second sub-pixel B, and the third data line DL3 and the fourth data line DL4 may be arranged in parallel between the third sub-pixel W and the fourth sub-pixel G. Each of the data lines DL1 to DL4 may provide a data signal to a switching thin film transistor SW provided in the second circuit region of the sub-pixels R, B, W, and G adjacent thereto.

[0076] The gate lines GL1 and GL2 may extend along the first direction at positions corresponding to the second circuit regions of the four first to fourth sub-pixels R, B, W, and G constituting one unit pixel, and may be arranged in parallel along the first direction. For example, the first gate line GL1 may be arranged along the first direction at positions corresponding to the second circuit regions of the first to fourth sub-pixels R, B, W, and G arranged in the (2i-1)th horizontal line, and the second gate line GL2 may be arranged along the first direction at positions corresponding to the second circuit regions of the first to fourth sub-pixels R, B, W, and G arranged in the (2i)th horizontal line.

[0077] The second power line VREF may be disposed between the plurality of first power lines EVDD1 and EVDD2 and extend along the second direction. For example, the second power line VREF may be disposed between the second sub-pixel B and the third sub-pixel W and parallel to the plurality of first power lines EVDD1 and EVDD2. The second power line VREF may include a second power sharing line VREF_H extending horizontally toward the left and right sides. The second power sharing line VREF_H may be formed to extend to the left and right sides based on the center connected to the second power line. The second power line VREF may be connected to a sensing thin film transistor ST via the second power sharing line VREF_H, and the sensing thin film transistor ST is disposed in the second circuit region of the first to fourth sub-pixels R, B, W, and G.

[0078] In the display device according to various embodiments of the present disclosure, the second power sharing lines VREF_H1 and VREF_H2 may be provided in parallel with the first power sharing line EVDD_H and provided in the first to fourth sub-pixels R, B, W, and G in the (2i)th (i is a natural number) horizontal line (e.g., in Figure 5 The unit pixel located at the lower side in the figure) is inserted therebetween, and can be arranged to be parallel to the first power sharing line EVDD_H and arranged in the first to fourth sub-pixels R, B, W and G in the (2i-1)th (i is a natural number) horizontal line (for example, in Figure 5For example, the first to fourth sub-pixels R, B, W, and G arranged in the (2i)th horizontal line and the first to fourth sub-pixels R, B, W, and G arranged in the (2i-1)th horizontal line may be arranged to be symmetrical to each other in a mirror shape, and the second power sharing lines VREF_H1 and VREF_H2 may be arranged in each of the second circuit region of the first to fourth sub-pixels R, B, W, and G arranged in the (2i)th horizontal line and the second circuit region of the first to fourth sub-pixels R, B, W, and G arranged in the (2i-1)th horizontal line. For example, the second power sharing line VREF_H1 can be connected to each of the sensing thin film transistors ST in the second circuit area of ​​the first to fourth sub-pixels R, B, W and G set in the (2i-1)th horizontal line, and the second power sharing line VREF_H2 can be connected to each of the sensing thin film transistors ST in the second circuit area of ​​the first to fourth sub-pixels R, B, W and G set in the (2i)th horizontal line.

[0079] The second power sharing lines VREF_H1 and VREF_H2 may include a first portion extending between the first subpixel R and the second subpixel B based on a center connected to the second power line VREF, and a second portion extending between the third subpixel W and the fourth subpixel G. For example, an end portion of the first portion of the second power sharing lines VREF_H1 and VREF_H2 may be disposed between the data lines DL1 and DL2 between the first subpixel R and the second subpixel B. Furthermore, an end portion of the second portion of the second power sharing lines VREF_H1 and VREF_H2 may be disposed between the data lines DL3 and DL4 between the third subpixel W and the fourth subpixel G.

[0080] The four first to fourth subpixels R, B, W, and G that constitute a unit pixel may include second branch power patterns extending in a first direction parallel to the second power sharing lines VREF_H1 and VREF_H2. For example, the second branch power pattern VREF_H_br extending from the first subpixel R and the second branch power pattern VREF_H_bb extending from the second subpixel B may be connected to the ends of the first portions of the second power sharing lines VREF_H1 and VREF_H2, respectively. Furthermore, the second branch power pattern VREF_H_bw extending from the third subpixel W and the second branch power pattern VREF_H_bg extending from the fourth subpixel G may be connected to the ends of the second portions of the second power sharing lines VREF_H1 and VREF_H2, respectively.

[0081] Figure 6 is a plan view illustrating a pixel array of a display device according to various embodiments of the present disclosure. Figure 6 More detailed examples Figure 5 pixel array.

[0082] Reference Figure 6 , a display device according to various embodiments of the present disclosure may include a pixel array including four first to fourth sub-pixels R, B, W, and G (for example, Figure 6 and four first to fourth sub-pixels R, B, W, and G (for example, Figure 6 The unit pixel located on the upper side in FIG.

[0083] The corresponding sub-pixels R, B, W, and G may be defined by the intersection of gate lines GL1 and GL2 and data lines DL1 to DL4, and may include light emitting diodes PXL ( Figure 6 ), a driving thin film transistor DR, a sensing thin film transistor ST, a switching thin film transistor SW, a first storage capacitor Cst1, and a second storage capacitor Cst2.

[0084] The first electrode ANO of the light emitting diode PXL and the first storage capacitor Cst1 may be disposed in an opening region (or a light emitting region) of each of the sub-pixels R, B, W, and G.

[0085] The driving thin film transistor DR may be disposed at one side of the opening region of the corresponding sub-pixels R, B, W, and G disposed in the (2i)th horizontal line (eg, Figure 6 The first circuit region is provided at the upper side of each sub-pixel of the (2i)-th horizontal line in the first circuit region, and the sensing thin film transistor ST, the switching thin film transistor SW and the second storage capacitor Cst2 can be provided on the other side of the opening region (for example, Figure 6 In the second circuit area provided at the lower side of each sub-pixel of the (2i)th horizontal line in .

[0086] The corresponding sub-pixels R, B, W, and G arranged in the (2i-1)th horizontal line can be arranged in a mirror-image shape with the corresponding sub-pixels R, B, W, and G arranged in the (2i)th horizontal line, and the driving thin film transistor DR can be arranged on one side of the opening area (for example, Figure 6 The first circuit region is provided at the upper side of each sub-pixel of the (2i-1)th horizontal line in the first circuit region, and the sensing thin film transistor ST, the switching thin film transistor SW and the second storage capacitor Cst2 may be provided on the other side of the opening region (for example, Figure 6In the second circuit area provided at the lower side of each sub-pixel of the (2i-1)th horizontal line in .

[0087] The corresponding sub-pixels R, B, W, and G respectively arranged in the (2i)th horizontal line and the (2i-1)th horizontal line can be separated from the unit pixels adjacent thereto by a plurality of first power lines EVDD1 and EVDD2. For example, the plurality of power lines EVDD1 and EVDD2 can be respectively arranged on the right side of the first sub-pixel R and on the left side of the fourth sub-pixel G arranged along the second direction (e.g., the vertical direction). A first power sharing line EVDD_H extending in the first direction and electrically connected to each of the first power lines EVDD1 and EVDD2 on the left and right sides may be included between the plurality of first power lines EVDD1 and EVDD2. The first power sharing line EVDD_H can be formed in a straight line shape between the plurality of first power lines EVDD1 and EVDD2. The plurality of first power lines EVDD1 and EVDD2 can be connected to the driving thin film transistors DR in the first circuit area arranged in the first to fourth sub-pixels R, B, W, and G through the first power sharing line EVDD_H.

[0088] The data lines DL1 to DL4 may be disposed in parallel between the first subpixel R and the second subpixel B arranged along the second direction and between the third subpixel W and the fourth subpixel G arranged along the second direction. Each of the data lines DL1 to DL4 may provide a data signal to a switching thin film transistor SW disposed in the second circuit region of the subpixels R, B, W, and G adjacent thereto.

[0089] Gate lines GL1 and GL2 extending along the first direction and arranged in parallel along the second direction may be disposed at positions corresponding to second circuit regions of corresponding sub-pixels R, B, W, and G disposed in the (2i)th and (2i-1)th horizontal lines, respectively.

[0090] The second power line VREF may be arranged parallel to the plurality of first power lines EVDD1 and EVDD2 between the second subpixel B and the third subpixel W arranged in the second direction. The second power line VREF may include a second power sharing line VREF_H extending horizontally to the left and right sides. The second power sharing line VREF_H may be formed to extend to the left and right sides based on the center connected to the second power line. The second power line VREF may be connected to the sensing thin film transistor ST via the second power sharing line VREF_H, which is provided in the second circuit region of the first to fourth subpixels R, B, W, and G.

[0091] Figure 7 yes Figure 6 An enlarged view of part A of FIG. Figure 8 It is along Figure 7 A cross-sectional view taken along line II'. Figure 9 yes Figure 6 These drawings are intended to describe in detail the first power share line EVDD_H and the second power share line VREF_H in the display device according to various embodiments of the present disclosure.

[0092] Combine Figure 6 Reference Figure 7 and Figure 8 , the first power share line EVDD_H in the display device according to various embodiments of the present disclosure will be described as follows.

[0093] like Figure 7 As shown, the first power sharing line EVDD_H may be provided between the corresponding sub-pixels R1, B1, W1, and G1 respectively provided in the (2i-1)th horizontal line and the corresponding sub-pixels R2, B2, W2, and G2 respectively provided in the (2i)th horizontal line. The first power sharing line EVDD_H may be formed in a straight line shape between the plurality of first power lines EVDD1 and EVDD2. For example, the first to fourth subpixels R1, B1, W1 and G1 arranged in the (2i-1)th horizontal line and the first to fourth subpixels R2, B2, W2 and G2 arranged in the (2i)th horizontal line can be arranged to be symmetrical to each other in a mirror shape, and the first circuit areas of the first to fourth subpixels R1, B1, W1 and G1 arranged in the (2i-1)th horizontal line and the first circuit areas of the first to fourth subpixels R2, B2, W2 and G2 arranged in the (2i)th horizontal line can be arranged to be adjacent to each other with the first power sharing line EVDD_H inserted therebetween.

[0094] The first power sharing line EVDD_H may be commonly connected to each of the first to fourth sub-pixels R1, B1, W1, and G1 disposed in the (2i-1)th horizontal line and the first to fourth sub-pixels R2, B2, W2, and G2 disposed in the (2i)th horizontal line. For example, the first power sharing line EVDD_H may be connected to each of the driving thin film transistors DR disposed in the first circuit region of the first to fourth sub-pixels R1, B1, W1, and G1 disposed in the (2i-1)th horizontal line, and to each of the driving thin film transistors DR disposed in the first circuit region of the first to fourth sub-pixels R2, B2, W2, and G2 disposed in the (2i)th horizontal line.

[0095] The first to fourth subpixels R1, B1, W1 and G1 arranged in the (2i-1)th horizontal line and the first to fourth subpixels R2, B2, W2 and G2 arranged in the (2i)th horizontal line may include a first branch power pattern extending in the second direction toward the first power sharing line EVDD_H. For example, the first branch power patterns EVDD_H_br1 and EVDD_H_br2 extending from the driving thin film transistors DR_r1 and DR_r2 of the first sub-pixels R1 and R2 can be connected to the first power sharing line EVDD_H, the first branch power patterns EVDD_H_bb1 and EVDD_H_BA2 extending from the driving thin film transistors DR_b1 and DR_b2 of the second sub-pixels B1 and B2 can be connected to the first power sharing line EVDD_H, the first branch power patterns EVDD_H_bw1 and EVDD_H_bw2 extending from the driving thin film transistors DR_w1 and DR_w2 of the third sub-pixels W1 and W2 can be connected to the first power sharing line EVDD_H, and the first branch power patterns EVDD_H_bg1 and EVDD_H_bg2 extending from the driving thin film transistors DR_g1 and DR_g2 of the fourth sub-pixels G1 and G2 can be connected to the first power sharing line EVDD_H.

[0096] The first branch power pattern may be formed as an active layer of the driving thin film transistor DR. For example, the active layer may be conductive to serve as the first branch power pattern. In addition, the active layer may include a common active layer commonly connected to one side of each first branch power pattern and formed to partially overlap with the first power line EVDD while overlapping with the first power sharing line EVDD_H.

[0097] like Figure 8 As shown, a light shielding layer LS, a buffer layer BUF, an active layer ACT, a gate electrode GAT, an interlayer dielectric film ILD, and source / drain electrodes SD may be disposed on a substrate SUB.

[0098] The active layer ACT of the drive thin film transistor DR may extend to partially overlap the light shielding layer LS while overlapping the source / drain electrode SD, and a contact region EVDD_CNT may be formed in a portion where the light shielding layer LS, the active layer ACT, and the source / drain electrode SD all overlap with each other, with the active layer ACT interposed between the light shielding layer LS and the source / drain electrode SD. The active layer ACT extending to the source / drain electrode SD on a plane may be a first branch power pattern, wherein the portion where the source / drain electrode SD overlaps the active layer ACT may be a first power sharing line EVDD_H, and wherein the portion where the light shielding layer LS overlaps the source / drain electrode SD may be a first power line EVDD.

[0099] In the display device according to various embodiments of the present disclosure, the active layer ACT of the driving thin film transistor DR can extend to partially overlap with the first power line EVDD while overlapping with the first power sharing line EVDD_H. Furthermore, a contact region EVDD_CNT in which the light shielding layer LS, the active layer ACT, and the source / drain electrode SD are in direct contact with each other can be formed within the first power line EVDD, thereby reducing the number of contact holes for supplying a power voltage to the driving thin film transistor DR to one. Furthermore, the first power sharing line EVDD_H can be formed of a double line of the active layer ACT and the source / drain electrode SD, thereby reducing a resistive load.

[0100] Next, combine the attached Figure 6 Reference Figure 9 , a second power sharing line VREF_H in another display device according to various embodiments of the present disclosure will be described.

[0101] like Figure 9 As shown, the second power line VREF can be arranged between the plurality of first power lines EVDD1 and EVDD2 and extend along the second direction. For example, the second power line VREF can be arranged between the second sub-pixel B and the third sub-pixel W and parallel to the plurality of first power lines EVDD1 and EVDD2. The second power line VREF may include a second power sharing line VREF_H extending toward the left and right sides in the horizontal direction. The second power sharing line VREF_H may be formed to extend to the left and right sides based on the center connected to the second power line. The second power line VREF can be connected to the sensing thin film transistor ST through the second power sharing line VREF_H, and the sensing thin film transistor ST is arranged in the second circuit area of ​​the first to fourth sub-pixels R, B, W, and G.

[0102] The second power sharing line VREF_H may include a first portion connected to the second power line VREF at a central portion through a main contact hole VREF_CNT_m and extending between the first sub-pixel R and the second sub-pixel B based on the main contact hole VREF_CNT_m, and a second portion extending between the third sub-pixel W and the fourth sub-pixel G. For example, an end portion of the first portion of the second power sharing line VREF_H may be disposed between the data lines DL1 and DL2 between the first sub-pixel R and the second sub-pixel B. In addition, an end portion of the second portion of the second power sharing line VREF_H may be disposed between the data lines DL3 and DL4 between the third sub-pixel W and the fourth sub-pixel G. Second branch power patterns VREF_H_br and VREF_H_bb extending from each of the sensing thin film transistors ST_r of the first sub-pixel R and the sensing thin film transistors ST_b of the second sub-pixel B may be connected at the end portion of the first portion of the second power sharing line VREF_H through the first sub-contact hole VREF_CNT_s1. Furthermore, second branch power patterns VREF_H_bw and VREF_H_bg extending from the sensing thin film transistor ST_w of the third subpixel W and the sensing thin film transistor ST_g of the fourth subpixel G may be connected through the second subcontact hole VREF_CNT_s2 at an end of the second portion of the second power sharing line VREF_H.

[0103] In the display device according to various embodiments of the present disclosure, the corresponding sub-pixels R, B, W, and G may have the same electrical distance from the center of the second power sharing line VREF_H connected to the second power line VREF. For example, the electrical distance associated with the first sub-pixel R is the sum of the electrical distance Lm_s1 between the main contact hole VREF_CNT_m and the first sub-contact hole VREF_CNT_s1 and the electrical distance Ls1_r between the first sub-contact hole VREF_CNT_s1 and the first sub-pixel R, and the electrical distance associated with the second sub-pixel B is the sum of the electrical distance Lm_s1 between the main contact hole VREF_CNT_m and the first sub-contact hole VREF_CNT_s1 and the electrical distance Ls1_b between the first sub-contact hole VREF_CNT_s1 and the second sub-pixel B. In addition, the electrical distance associated with the third sub-pixel W is the sum of the electrical distance Lm_s2 between the main contact hole VREF_CNT_m and the second sub-contact hole VREF_CNT_s2 and the electrical distance Ls2_w between the second sub-contact hole VREF_CNT_s2 and the third sub-pixel W, and the electrical distance associated with the fourth sub-pixel G is the sum of the electrical distance Lm_s2 between the main contact hole VREF_CNT_m and the second sub-contact hole VREF_CNT_s2 and the electrical distance Ls2_g between the second sub-contact hole VREF_CNT_s2 and the fourth sub-pixel G. In this case, the load deviation of the sensing line of the corresponding sub-pixel can be reduced.

[0104] Figure 10 is a schematic plan view illustrating a unit pixel of a display device according to various embodiments of the present disclosure. Figure 11 It is along Figure 10 A cross-sectional view taken along line II-II'. Figure 12 It is along Figure 10 A cross-sectional view taken along line III-III'. Figure 13 It is along Figure 10 A cross-sectional view taken along line IV-IV'. Figure 14 This is an example Figure 10 1 is an equivalent circuit diagram of a storage capacitor of a sub-pixel of part C. These drawings are intended to specifically describe the storage capacitor Cst in the display device according to various embodiments of the present disclosure. Therefore, in the following description, repeated description of other identical elements except for the description of the storage capacitor Cst will be omitted.

[0105] like Figure 10 As shown, the corresponding sub-pixels R, B, W and G can be defined by the intersection between the gate line GL and the data line DL, and can include a light emitting diode PXL, a driving thin film transistor DR, a sensing thin film transistor ST, a switching thin film transistor SW, a first storage capacitor Cst1 and a second storage capacitor Cst2.

[0106] The first electrode ANO of the light emitting diode PXL and the first storage capacitor Cst1 may be disposed in the opening region (or the light emitting region).

[0107] The driving thin film transistor DR can be set in a first circuit area set on one side of the opening area (for example, the upper side of the opening area), and the second storage capacitor Cst2 can be set in a second circuit area set on the other side of the opening area (for example, the lower side of the opening area).

[0108] like Figure 11 As shown, in the opening region of each of the sub-pixels R, B, W, and G, a buffer layer BUF, an active layer ACT, an interlayer dielectric film ILD, a color filter CF, an overcoat layer OC, and a light emitting diode PXL may be disposed on the substrate SUB.

[0109] The buffer layer BUF may be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF may be connected to any one of the gate electrode and the source electrode of the driving thin film transistor DR. Figure 11 In the embodiment, the active layer ACT may be a first electrode pattern DTG that is conductively connected to the gate electrode of the driving thin film transistor DR. Alternatively, the active layer ACT may be a second electrode pattern DTS that is conductively connected to the source electrode of the driving thin film transistor DR.

[0110] An interlayer dielectric film ILD, a color filter CF, an overcoat layer OC, and a light emitting diode PXL may be formed on the active layer ACT.

[0111] By interposing the interlayer dielectric film ILD, the color filter CF, and the overcoat layer OC, the first electrode pattern DTG formed by the conductive active layer ACT and the first electrode ANO of the light emitting diode PXL can be spaced apart from each other, thereby forming a vertical capacitor Cst_V1 in the vertical direction. Alternatively, the vertical capacitor Cst_V1 can be formed in the vertical direction between the second electrode pattern DTS formed by the conductive active layer ACT and the first electrode ANO of the light emitting diode PXL.

[0112] like Figure 12 As shown, in the opening region of each of the sub-pixels R, B, W, and G, a buffer layer BUF, an active layer ACT, an interlayer dielectric film ILD, a color filter CF, an overcoat layer OC, and a light emitting diode PXL may be disposed on the substrate SUB.

[0113] The buffer layer BUF may be formed on the entire surface of the substrate SUB, and the active layer ACT on the buffer layer BUF may be connected to any one of the gate electrode and the source electrode of the driving thin film transistor DR. Figure 12 In the embodiment, the active layer ACT may have a finger-shaped pattern structure in which each of a plurality of first electrode patterns DTG, which are made conductive by being connected to the gate electrode of the driving thin film transistor DR, and each of a plurality of second electrode patterns DTS, which are made conductive by being connected to the source electrode of the driving thin film transistor DR, are arranged in parallel on the same plane. A width h1 of each of the plurality of first electrode patterns DTG and the second electrode pattern DTS may be smaller than a width h2 between the first electrode pattern DTG and the second electrode pattern DTS.

[0114] A plurality of first electrode patterns DTG and a plurality of second electrode patterns DTS formed by conductively converting the active layer ACT may be alternately disposed, whereby a horizontal capacitor Cst_H may be formed in a horizontal direction between the first and second electrode patterns.

[0115] Reference Figure 11 and Figure 12 ,include Figure 11 The vertical capacitor Cst_V1 and Figure 12 The first storage capacitor Cst1 of the horizontal capacitor Cst_H shown in the figure can be formed in the opening area of ​​each of the sub-pixels R, B, W and G. For example, based on the red sub-pixel R, the first storage capacitor Cst1 of the opening area can be a capacitor in which the vertical capacitor Cst_V1 and the horizontal capacitor Cst_H are combined with each other.

[0116] like Figure 13 As shown, in the second circuit region of each of the sub-pixels R, B, W, and G, a light shielding layer LS, a buffer layer BUF, an active layer ACT, an interlayer dielectric film ILD, and source / drain electrodes SD may be disposed on the substrate SUB.

[0117] The light shielding layer LS may be provided on the substrate SUB to overlap with the active layer ACT and the source / drain electrode SD. The active layer ACT on the buffer layer BUF may be connected to any one of the gate electrode and the source electrode of the driving thin film transistor DR. Figure 13 In the embodiment, the active layer ACT may be a first electrode pattern DTG that is conductively connected to the gate electrode of the driving thin film transistor DR. Alternatively, the active layer ACT may be a second electrode pattern DTS that is conductively connected to the source electrode of the driving thin film transistor DR.

[0118] An interlayer dielectric film ILD and source / drain electrodes SD may be formed on the active layer ACT. That is, a light shielding layer LS may be disposed below the active layer ACT with a buffer layer BUF interposed therebetween, and source / drain electrodes SD may be disposed above the active layer ACT with the interlayer dielectric film ILD interposed therebetween.

[0119] In the first electrode pattern DTG formed by conductively conducting the active layer ACT, it is separated from the light-shielding layer LS by the interposed buffer layer BUF and is separated from the source / drain electrode SD by the interposed interlayer dielectric film ILD, and a dual vertical capacitor Cst_V2 can be formed in the vertical direction to each of the light-shielding layer LS therebelow and the source / drain electrode SD thereover.

[0120] Reference Figure 14 In the display device according to various embodiments of the present disclosure, the storage capacitor Cst may overlap with the opening regions of the sub-pixels R and B and be formed between the driving thin film transistor DR of the first circuit region and the sensing thin film transistor ST of the second circuit region. For example, based on the red sub-pixel R, a capacitor formed by combining the vertical storage capacitor Cst_V1 and the horizontal capacitor Cst_H corresponding to the first storage capacitor Cst1 of the opening region and the dual vertical capacitor Cst_V2 of the non-opening region (or the second circuit region) may be combined to form the storage capacitor Cst.

[0121] Figures 15 to 19 is a plan view illustrating a single-layer structure of a portion of a unit pixel of a display device according to various embodiments of the present disclosure.

[0122] Reference Figures 15 to 19 , sub-pixels constituting a unit pixel in a display device according to various embodiments of the present disclosure will be described in more detail.

[0123] like Figure 15 As shown, a plurality of first power lines EVDD1 and EVDD2 may be formed on a substrate, arranged parallel to each other along a first direction (e.g., a horizontal direction) and extending in a second direction (e.g., a vertical direction) intersecting the first direction. First and second data lines DL1 and DL2, as well as third and fourth data lines DL3 and DL4, may be disposed adjacent to each other and parallel to the plurality of first power lines EVDD1 and EVDD2 between the first power lines EVDD1 and EVDD2. A second power line VREF may be disposed parallel to the second and third data lines DL2 and DL3 between the second and third data lines DL2 and DL3. The plurality of first power lines EVDD1 and EVDD2, the data lines DL1 to DL4, and the second power line VREF may be formed by a light shielding layer LS.

[0124] A light shielding pattern Cst2_LS may be provided corresponding to the sensing thin film transistor ST and the switching thin film transistor SW formed in the second circuit region formed in the first to fourth subpixels R, B, W, and G and forming the second storage capacitor Cst2.

[0125] The buffer layer BUF may be provided with a Figure 15The buffer layer BUF can be used to protect the thin film transistor formed by subsequent processes from impurities such as alkali metal ions leaking from the light shielding layer LS or the substrate. The buffer layer BUF can be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer of SiOx and SiNx.

[0126] like Figure 16 As shown, the active layer ACT may be disposed on the buffer layer BUF.

[0127] The active layer ACT may include an active layer DR_ACT of the drive thin film transistor DR disposed in the first circuit regions RC1, BC1, WC1, and GC1 of the respective sub-pixels R, B, W, and G; an active layer ST_ACT of the sensing thin film transistor ST disposed in the second circuit regions RC2, BC2, WC2, and GC2; and an active layer SW_ACT of the switching thin film transistor SW. Furthermore, the active layer ACT may include an active layer comprising a first electrode pattern DTG and a second electrode pattern DTS disposed in the opening regions of the respective sub-pixels R, B, W, and G. In the active layer ACT, a portion connected to the gate electrode of the drive thin film transistor DR in the first circuit region, a portion comprising the first electrode pattern DTG in the opening region, and a portion comprising the switching thin film transistor SW in the second circuit region may be formed as a single body. Furthermore, a portion connected to the source electrode of the drive thin film transistor DR in the first circuit region, a portion comprising the second electrode pattern DTS in the opening region, and a portion comprising the sensing thin film transistor ST in the second circuit region may be formed as a single body. In addition, the active layer ACT may include a common active layer formed to partially overlap the first power lines EVDD1 and EVDD2 while overlapping the first power share line EVDD_H to be formed between the first power lines EVDD1 and EVDD2 .

[0128] Each of the first and second electrode patterns DTG and DTS of the active layer ACT in the opening region may be formed to be commonly connected to the first and second common patterns and disposed in parallel in a finger pattern structure.

[0129] like Figure 17 As shown, the gate electrode DR_GAT for constituting the driving thin film transistor DR can be formed in the first circuit region of the first to fourth sub-pixels R, B, W, and G, and the gate electrode ST_GAT for constituting the sensing thin film transistor ST and the gate electrode SW_GAT for constituting the switching thin film transistor SW can be provided in the second circuit region. The gate electrode ST_GAT of the sensing thin film transistor ST and the gate electrode SW_GAT of the switching thin film transistor SW can be formed as one body.

[0130] The interlayer dielectric film ILD can be provided Figure 17 The interlayer dielectric film ILD may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer of SiOx and SiNx.

[0131] like Figure 18 As shown, a plurality of first power lines EVDD1 and EVDD2, a first power sharing line EVDD_H, a second power sharing line VREF_H, and a gate line GL may be formed on the interlayer dielectric film ILD. In addition, source / drain electrodes SD of the drive thin film transistor DR formed in the first circuit region of the first to fourth sub-pixels R, B, W, and G, and source / drain electrodes SD of the sensing thin film transistor ST and the switching thin film transistor SW formed in the second circuit region may be formed.

[0132] Figure 18 The elements shown in the figure can be formed of the same material and can be a multilayer made of any one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or alloys thereof. For example, the element can be made of a double layer of Cu / MoTi.

[0133] In addition, a passivation film PAS may be provided to cover Figure 18 The passivation film PAS is an insulating film for protecting the elements therebelow and may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer of SiOx and SiNx.

[0134] Red, blue, white, and green color filters CF may be disposed on the passivation film PAS to correspond to opening areas of the respective subpixels R, B, W, and G. The color filters CF may emit red, blue, white, and green light by passing white light emitted from the light emitting diodes PXL.

[0135] An overcoat layer OC may be disposed on the color filter CF to cover the color filter CF. The overcoat layer OC may be a planarization film that reduces a step difference of a lower structure.

[0136] like Figure 19 As shown, the light emitting diode PXL may be provided on the overcoat layer OC to correspond to the opening area of ​​each of the sub-pixels R, B, W, and G. The light emitting diode PXL may include a first electrode (e.g., an anode electrode ANO), a light emitting layer, and a second electrode (e.g., a cathode electrode). For example, the light emitting diode PXL may be an organic light emitting diode (OLED).

[0137] A display device according to various embodiments of the present disclosure can be described as follows.

[0138] According to various embodiments of the present disclosure, a display device may include: a first power sharing line, which is arranged to be parallel to a first direction; a first pixel and a second pixel, which are arranged along a second direction intersecting the first direction and with the first power sharing line interposed therebetween; and a second power sharing line, which is arranged to be parallel to the first power sharing line and with any one of the first pixel and the second pixel interposed therebetween.

[0139] In a display device according to various embodiments of the present disclosure, each of the first pixel and the second pixel may include an opening area and a first circuit area and a second circuit area respectively arranged on both sides of the opening area in a second direction, and wherein the first power sharing line may be set to be adjacent to the first circuit area of ​​each of the first pixel and the second pixel, and the second power sharing line may be set to be adjacent to the second circuit area of ​​any one of the first pixel and the second pixel.

[0140] In the display device according to various embodiments of the present disclosure, the first pixel and the second pixel may be disposed to be symmetrical to each other in a mirror shape in a plan view.

[0141] In the display device according to various embodiments of the present disclosure, the first power sharing line may be connected to each of the first pixel and the second pixel.

[0142] According to various embodiments of the present disclosure, a display device may include a plurality of first power lines, which are arranged to be parallel to a second direction and a first pixel and a second pixel are interposed between the plurality of first power lines, wherein a first power sharing line may be arranged between the plurality of first power lines and connected to each of the plurality of first power lines.

[0143] In the display device according to various embodiments of the present disclosure, the first power share line may be formed in a straight line shape between the plurality of first power lines.

[0144] The display device according to various embodiments of the present disclosure may include a second power line provided in the first pixel and the second pixel in parallel with the second direction, wherein the second power sharing line may be formed to extend to both sides based on the center connected to the second power line.

[0145] In a display device according to various embodiments of the present disclosure, each of the first pixel and the second pixel may include a plurality of sub-pixels arranged along a first direction, a first power sharing line may be connected to each of the plurality of sub-pixels included in each of the first pixel and the second pixel, and a second power sharing line may be connected to each of the plurality of sub-pixels included in any one of the first pixel and the second pixel.

[0146] In the display device according to various embodiments of the present disclosure, the first power share line may be connected to the first branch power pattern extending from each of the plurality of sub-pixels.

[0147] In a display device according to various embodiments of the present disclosure, an active layer may be included in each of a plurality of sub-pixels, and a first branch power pattern may be made of the same material as that of the active layer and formed to extend from the active layer of each of the plurality of sub-pixels along a second direction toward a first power sharing line.

[0148] In the display device according to various embodiments of the present disclosure, the active layer may be formed to partially overlap the first power line while overlapping the first power share line.

[0149] In the display device according to various embodiments of the present disclosure, the first power sharing line can be formed by a double line of an active layer and a source / drain electrode arranged above the active layer, and the first power line can be formed by a double line of an active layer and a light shielding layer arranged below the active layer.

[0150] In the display device according to various embodiments of the present disclosure, a contact region where the light shielding layer, the active layer, and the source / drain electrodes directly contact each other may be formed within the first power line.

[0151] In the display device according to various embodiments of the present disclosure, the second power sharing line may be connected to the second branch power pattern extending from each of the plurality of sub-pixels.

[0152] In a display device according to various embodiments of the present disclosure, an active layer may be included in each of a plurality of sub-pixels, and a second branch power pattern may be made of the same material as that of the active layer and formed to extend from the active layer of each of the plurality of sub-pixels along a first direction parallel to the second power sharing line.

[0153] In the display device according to various embodiments of the present disclosure, the active layer may be formed to be connected to both ends of the second power sharing line.

[0154] In a display device according to various embodiments of the present disclosure, a plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in sequence along a first direction, a plurality of first power lines arranged parallel to the second direction may be arranged at each of the left side of the first sub-pixel and the right side of the fourth sub-pixel, and a second power line arranged parallel to the first power line may be arranged between the second sub-pixel and the third sub-pixel.

[0155] In a display device according to various embodiments of the present disclosure, a first power sharing line may be disposed between and connected to each of a plurality of first power lines, and may be connected to each of first branch power patterns extending from the first subpixel to the fourth subpixel, respectively.

[0156] In a display device according to various embodiments of the present disclosure, the second power sharing line may include a first portion extending between a first sub-pixel and a second sub-pixel based on a center connected to the second power line, and a second portion extending between a third sub-pixel and a fourth sub-pixel, and second branch power patterns extending from the first sub-pixel and the second sub-pixel, respectively, may be connected to the first portion, respectively, and second branch power patterns extending from the third sub-pixel and the fourth sub-pixel, respectively, may be connected to the second portion, respectively.

[0157] In the display device according to various embodiments of the present disclosure, the first to fourth subpixels may have the same electrical distance from the center of the second power sharing line connected to the second power line.

[0158] According to various embodiments of the present disclosure, a display device may include: a plurality of pixels having a plurality of sub-pixels arranged along a first direction and a second direction intersecting the first direction; a first power sharing line arranged between a first pixel arranged in a (2i)th horizontal line and a second pixel arranged in a (2i-1)th horizontal line among the plurality of pixels, where i is a natural number; and a second power sharing line arranged on one side of the first pixel or on the other side of the second pixel.

[0159] In the display device according to various embodiments of the present disclosure, the first power share line and the second power share line may be connected to the plurality of sub-pixels, respectively.

[0160] In a display device according to various embodiments of the present disclosure, a plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged in sequence along a first direction, a plurality of first power lines arranged parallel to the second direction may be arranged at each of the left side of the first sub-pixel and the right side of the fourth sub-pixel, and a second power line arranged parallel to the first power line may be arranged between the second sub-pixel and the third sub-pixel, a first power sharing line may be arranged between the plurality of first power lines and connected to each of the plurality of first power lines and each of the first to fourth sub-pixels, and the second power sharing line may include a first portion extending between the first sub-pixel and the second sub-pixel based on a center connected to the second power line and connected to each of the first and second sub-pixels, and a second portion extending between the third sub-pixel and the fourth sub-pixel and connected to each of the third and fourth sub-pixels.

[0161] In a display device according to various embodiments of the present disclosure, a first power sharing line may be connected to first branch power patterns extending from a first sub-pixel to a fourth sub-pixel, respectively, a first portion of a second power sharing line may be connected to second branch power patterns extending from the first sub-pixel and the second sub-pixel, respectively, and a second portion of the second power sharing line may be connected to second branch power patterns extending from a third sub-pixel and a fourth sub-pixel, respectively.

[0162] It will be apparent to those skilled in the art that the present disclosure described above is not limited to the above-described embodiments and drawings, and that various substitutions, modifications, and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and it is intended that all variations or modifications derived from the meaning, scope, and equivalents of the claims fall within the scope of the present disclosure.

Claims

1. A display device, comprising: a first power sharing line, the first power sharing line being arranged parallel to the first direction; a first pixel and a second pixel, the first pixel and the second pixel being arranged along a second direction crossing the first direction with the first power sharing line interposed therebetween; as well as a second power sharing line provided in parallel with the first power sharing line with any one of the first pixel and the second pixel interposed therebetween, Each of the first pixel and the second pixel includes a plurality of sub-pixels arranged along the first direction, wherein the first power sharing line is connected to a first branch power pattern extending from each of the plurality of sub-pixels, wherein each of the plurality of sub-pixels includes an active layer, and The first branch power pattern is made of the same material as that of the active layer and is formed to extend from the active layer of each of the plurality of sub-pixels toward the first power sharing line along a second direction.

2. The display device according to claim 1, wherein Each of the first pixel and the second pixel includes an opening area and a first circuit area and a second circuit area respectively provided on both sides of the opening area in the second direction, and The first power sharing line is disposed adjacent to the first circuit region of each of the first pixel and the second pixel, and the second power sharing line is disposed adjacent to the second circuit region of any one of the first pixel and the second pixel.

3. The display device according to claim 1, wherein In a plan view, the first pixel and the second pixel are arranged to be symmetrical to each other in a mirror image shape.

4. The display device according to claim 1, wherein The first power sharing line is connected to each of the first pixel and the second pixel.

5. The display device according to claim 4 , further comprising a plurality of first power lines arranged parallel to the second direction and with the first pixel and the second pixel interposed therebetween, wherein The first power sharing line is provided between the plurality of first power lines and is connected to each of the plurality of first power lines. The display device according to claim 5 , wherein: The first power sharing line is formed in a straight line shape between the plurality of first power lines.

7. The display device according to claim 1, further comprising second lines of force, the second lines of force being arranged in parallel with the second direction in the first pixel and the second pixel, wherein: The second power sharing line is formed to extend to both sides based on the center connected to the second power line.

8. The display device according to claim 1, wherein The first power sharing line is connected to each of the plurality of sub-pixels included in each of the first pixel and the second pixel, and the second power sharing line is connected to each of the plurality of sub-pixels included in any one of the first pixel and the second pixel.

9. The display device according to claim 8, wherein The active layer is formed to partially overlap the first power line while overlapping the first power share line.

10. The display device according to claim 9, wherein The first power sharing line is formed of a double line of the active layer and a source / drain electrode disposed above the active layer, and the first power line is formed of a double line of the active layer and a light shielding layer disposed below the active layer.

11. The display device according to claim 10, wherein: A contact region where the light shielding layer, the active layer, and the source / drain electrodes directly contact each other is formed within the first power line.

12. The display device according to claim 8, wherein The second power sharing line is connected to a second branch power pattern extending from each of the plurality of sub-pixels.

13. The display device according to claim 12, wherein: The second branch power pattern is made of the same material as that of the active layer and is formed to extend from the active layer of each of the plurality of sub-pixels in a first direction parallel to the second power sharing line.

14. The display device according to claim 13, wherein: The active layer is formed to be connected to both ends of the second power sharing line.

15. The display device according to claim 8, wherein The multiple sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along the first direction, a plurality of first power lines arranged parallel to the second direction are arranged on the left side of the first sub-pixel and on the right side of the fourth sub-pixel, and a second power line arranged parallel to the first power line is arranged between the second sub-pixel and the third sub-pixel.

16. The display device according to claim 15, wherein The first power sharing line is disposed between and connected to each of the plurality of first power lines, and is connected to each of first branch power patterns extending from the first subpixel to the fourth subpixel, respectively.

17. The display device according to claim 15, wherein: The second power sharing line includes a first portion extending between the first sub-pixel and the second sub-pixel based on the center connected to the second power line, and a second portion extending between the third sub-pixel and the fourth sub-pixel, and second branch power patterns extending from the first sub-pixel and the second sub-pixel are respectively connected to the first portion, and second branch power patterns extending from the third sub-pixel and the fourth sub-pixel are respectively connected to the second portion.

18. The display device according to claim 17, wherein: The first to fourth subpixels have the same electrical distance from the center of the second power sharing line connected to the second power line.

19. A display device, comprising: a plurality of pixels having a plurality of sub-pixels arranged along a first direction and a second direction intersecting the first direction; a first power sharing line provided between a first pixel provided in a 2i-th horizontal line and a second pixel provided in a 2i-1-th horizontal line among the plurality of pixels, where i is a natural number; as well as a second power sharing line, the second power sharing line being arranged on one side of the first pixel or on the other side of the second pixel, wherein the first power sharing line is connected to a first branch power pattern extending from the first pixel or the second pixel, wherein each of the first pixel and the second pixel includes an active layer, and The first branch power pattern is made of the same material as that of the active layer and is formed to extend from the active layer of the first pixel or the second pixel toward the first power sharing line.

20. The display device according to claim 19, wherein The first power share line and the second power share line are respectively connected to the plurality of sub-pixels.

21. The display device according to claim 20, wherein The multiple sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along the first direction, a plurality of first power lines arranged parallel to the second direction are arranged at each of the left side of the first sub-pixel and the right side of the fourth sub-pixel, and a second power line arranged parallel to the first power line is arranged between the second sub-pixel and the third sub-pixel, the first power sharing line is arranged between the plurality of first power lines and connected to each of the plurality of first power lines and each of the first to fourth sub-pixels, and the second power sharing line includes a first portion extending between the first sub-pixel and the second sub-pixel based on the center connected to the second power line and connected to each of the first sub-pixel and the second sub-pixel, and a second portion extending between the third sub-pixel and the fourth sub-pixel and connected to each of the third sub-pixel and the fourth sub-pixel.

22. The display device according to claim 21, wherein The first power sharing line is connected to first branch power patterns extending from the first sub-pixel to the fourth sub-pixel, respectively, the first portion of the second power sharing line is connected to second branch power patterns extending from the first sub-pixel and the second sub-pixel, respectively, and the second portion of the second power sharing line is connected to second branch power patterns extending from the third sub-pixel and the fourth sub-pixel, respectively.

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