Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate, a method for preparing the same, and a display device, the display substrate comprising a drive circuit layer and a light-emitting device layer sequentially stacked on a base, the drive circuit layer comprising a plurality of light-emitting control circuits, and the light-emitting device layer comprising a plurality of light-emitting elements sequentially stacked on the drive circuit layer, wherein: the plurality of light-emitting control circuits comprise a first light-emitting subcircuit and a second light-emitting subcircuit, the first light-emitting subcircuit being used to control the light emission of a first portion of the plurality of light-emitting elements, the second light-emitting subcircuit being used to control the light emission of a second portion of the plurality of light-emitting elements, the number of light-emitting elements included in the first portion being different from the number of light-emitting elements included in the second portion. The present disclosure achieves the technical effect of switching between high-brightness display and low-brightness display, increasing the brightness of the display device while also prolonging the lifespan of the light-emitting elements.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as luminescence, ultra-thinness, wide viewing angles, high brightness, high contrast, low power consumption, and extremely fast response times. Depending on the driving method, OLEDs can be divided into two types: Passive Matrix (PM) and Active Matrix (AM). AMOLEDs are current-driven devices, using independent thin-film transistors (TFTs) to control each sub-pixel. Each sub-pixel can be driven continuously and independently to emit light. Summary of the Invention

[0003] The embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device, which can improve display effects.

[0004] An embodiment of the present disclosure provides a display substrate, comprising a driving circuit layer and a light-emitting device layer stacked in sequence on a base, wherein the driving circuit layer comprises a plurality of light-emitting control circuits, and the light-emitting device layer comprises a plurality of light-emitting elements stacked in sequence on the driving circuit layer, wherein: the plurality of light-emitting control circuits comprises a first light-emitting sub-circuit and a second light-emitting sub-circuit, the first light-emitting sub-circuit being used to control the light emission of a first portion of the plurality of light-emitting elements, and the second light-emitting sub-circuit being used to control the light emission of a second portion of the plurality of light-emitting elements, and the number of light-emitting elements included in the first portion is different from the number of light-emitting elements included in the second portion.

[0005] In an exemplary embodiment, the light-emitting device layer includes an anode layer, a pixel definition layer, a first organic light-emitting layer, an electron-charge generation layer, a hole-charge generation layer, a second organic light-emitting layer and a cathode stacked in sequence on the driving circuit layer, the first light-emitting sub-circuit is used to control the light emission of the first organic light-emitting layer and the second organic light-emitting layer, and the second light-emitting sub-circuit is used to control the light emission of the second organic light-emitting layer.

[0006] In an exemplary embodiment, the anode layer includes a first anode and a second anode, the light-emitting device layer further includes an electrode layer arranged between the electron-charge generating layer and the hole-charge generating layer, the first anode is connected to the first organic light-emitting layer, and the second anode is connected to any one or more layers of the electron-charge generating layer, the electrode layer, and the hole-charge generating layer.

[0007] In an exemplary embodiment, the anode layer includes a first anode connected to the first organic light emitting layer and a second anode connected to any one or more of the electron-charge generation layer and the hole-charge generation layer.

[0008] In an exemplary embodiment, the pixel definition layer includes a first pixel opening and a second pixel opening, the first pixel opening exposing at least a portion of the first anode, the second pixel opening exposing at least a portion of the second anode, and the orthographic projection of the electron-charge generation layer on the substrate covers the orthographic projections of the first pixel opening and the second pixel opening on the substrate.

[0009] In an exemplary embodiment, the first organic light-emitting layer is located in the first pixel opening, and the first organic light-emitting layer includes a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer stacked in sequence on the first anode;

[0010] The orthographic projection of the second organic light-emitting layer on the substrate covers the orthographic projections of the first pixel opening and the second pixel opening on the substrate, and the second organic light-emitting layer includes a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer stacked in sequence on the hole-charge generating layer.

[0011] In an exemplary embodiment, an orthographic projection of the second organic light emitting layer on the substrate covers an orthographic projection of the electron-charge generation layer and / or the hole-charge generation layer on the substrate.

[0012] In an exemplary embodiment, the driving circuit layer further includes a current control subcircuit, the first light-emitting subcircuit includes a first transistor, and the second light-emitting subcircuit includes a second transistor, wherein:

[0013] The current control subcircuit is configured to receive a data signal and a light-emitting control signal, control whether to generate a driving current according to the light-emitting control signal, and control the current intensity of the generated driving current according to the data signal;

[0014] The control electrode of the first transistor is connected to the second scanning signal line, the source electrode of the first transistor is connected to the output end of the current control sub-circuit, and the drain electrode of the first transistor is connected to the first anode;

[0015] The control electrode of the second transistor is connected to the third scan signal line, the source electrode of the second transistor is connected to the output end of the current control sub-circuit, and the drain electrode of the second transistor is connected to the second anode.

[0016] An embodiment of the present disclosure further provides a display device, comprising: the display substrate as described above.

[0017] The present disclosure also provides a method for preparing a display substrate, comprising: forming a driving circuit layer on a substrate, the driving circuit layer comprising a plurality of light-emitting control circuits, the plurality of light-emitting control circuits comprising a first light-emitting sub-circuit and a second light-emitting sub-circuit;

[0018] A light-emitting device layer is formed on the driving circuit layer, and the light-emitting device layer includes a plurality of light-emitting elements stacked in sequence on the driving circuit layer. The first light-emitting sub-circuit is used to control the emission of a first part of the plurality of light-emitting elements, and the second light-emitting sub-circuit is used to control the emission of a second part of the plurality of light-emitting elements. The number of light-emitting elements included in the first part is different from the number of light-emitting elements included in the second part.

[0019] The display substrate, preparation method thereof, and display device of the embodiments of the present disclosure achieve the technical effect of switching between high-brightness display and low-brightness display by arranging multiple light-emitting sub-circuits in the driving circuit layer and multiple light-emitting elements in a stack in the light-emitting device layer, using the multiple light-emitting elements in the stack for high-brightness display and using at least one of the multiple light-emitting elements in the stack for low-brightness display, thereby increasing the lifespan of the light-emitting elements while improving the brightness of the display device. The present disclosure uses at least one of the multiple light-emitting elements in the stack for low-brightness display, which can also improve the low-grayscale display quality of the display device, thereby improving the display performance. In addition, the preparation process of the present disclosure is well compatible with existing preparation processes, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0020] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0022] Figure 1 This is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 2a and Figure 2b Schematic diagram of the planar structure of two display substrates according to an exemplary embodiment of the present disclosure;

[0024] Figures 3a to 3d Schematic diagrams of cross-sectional structures of four display substrates according to exemplary embodiments of the present disclosure;

[0025] Figure 4 This is a schematic structural diagram of a pixel driving circuit in a display substrate according to an exemplary embodiment of the present disclosure;

[0026] Figure 5a Schematic diagram of an equivalent circuit of a pixel driving circuit in a display substrate according to an exemplary embodiment of the present disclosure;

[0027] Figure 5b 5a is an operating timing diagram of the pixel driving circuit;

[0028] Figure 6 This is a schematic diagram of a display substrate disclosed herein after a driving circuit layer pattern is formed;

[0029] Figure 7 This is a schematic diagram of a display substrate disclosed herein after forming a first organic light-emitting layer pattern;

[0030] Figure 8 This is a schematic diagram of a display substrate disclosed herein after a second organic light-emitting layer pattern is formed;

[0031] Figure 9 This is a schematic diagram of a display substrate disclosed herein after a light-emitting device layer pattern is formed;

[0032] Figures 10a to 10c Schematic diagram of the structure of the RGB stacked light-emitting element;

[0033] Figures 11a to 11f Schematic diagram of comparative test results of RGB stacked light-emitting elements and RGB single-layer light-emitting elements in terms of luminous efficiency and service life;

[0034] Figure 12a and Figure 12b Schematic diagram of the display principle of the RGB stacked light-emitting element during high-brightness and low-brightness display. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0036] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the figures.

[0037] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0038] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0039] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0040] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0041] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0042] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0043] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0044] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0045] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0046] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0047] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, an OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light-emitting signal driver, and a pixel array. The pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light-emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In some exemplary embodiments, the timing controller may provide grayscale values and control signals suitable for the specifications of the data signal driver to the data signal driver, a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and a clock signal, an emission stop signal, etc. suitable for the specifications of the light-emitting signal driver to the light-emitting signal driver. The data signal driver may use the grayscale values and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may sample grayscale values using the clock signal and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver can sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. m can be a natural number. The light signal driver can generate emission signals to be provided to the light signal lines E1, E2, E3, ..., and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light signal driver can sequentially provide emission signals having off-level pulses to the light signal lines E1 to Eo. For example, the light signal driver can be configured as a shift register and can generate light signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o can be a natural number. The pixel array may include a plurality of sub-pixels Pxij, each of which may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, where i and j may be natural numbers. Sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0048] Figure 2a and Figure 2bThis is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and two third and fourth subpixels P3 and P4 that emit a third color light. Each of the four subpixels may include a circuit unit and a light-emitting device. The circuit unit may include scan signal lines, data signal lines, and light-emitting signal lines, and a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal lines under the control of the scan signal lines and the light-emitting signal lines, and output a corresponding current to the light-emitting device. The light-emitting device in each subpixel is respectively connected to the pixel driving circuit of the subpixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0049] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal. In an exemplary embodiment, four sub-pixels may be arranged in a square to form a GGRB pixel arrangement, such as Figure 2a In another exemplary embodiment, the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement, as shown in FIG. Figure 2b In other exemplary embodiments, the four sub-pixels may be arranged in parallel horizontally or vertically. In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0050] In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as pixel rows, and a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as pixel columns. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0051] With the continuous development of display technology, OLED technology is increasingly being used in automotive and other display products. These products require displays that can display high brightness outdoors and low brightness in special scenarios such as nighttime, placing new demands on display products. Furthermore, automotive displays also require long lifespans to extend the display lifespan.

[0052] Figures 3a to 3dSchematic diagrams of cross-sectional structures of four display substrates according to exemplary embodiments of the present disclosure. Figure 4 FIG. 1 is a schematic structural diagram of a pixel driving circuit in a display substrate according to an exemplary embodiment of the present disclosure. Figure 3a 、 Figure 3b 、 Figure 3c 、 Figure 3d and Figure 4 As shown, an embodiment of the present disclosure provides a display substrate, which includes a driving circuit layer 102 and a light-emitting device layer 103 sequentially stacked on a substrate 10, the driving circuit layer 102 including a first light-emitting sub-circuit and a second light-emitting sub-circuit, and the light-emitting device layer 103 including a plurality of light-emitting elements sequentially stacked on the driving circuit layer 102 (for example, assuming that the number of the plurality of light-emitting elements stacked is n, where n is a natural number greater than 1), wherein:

[0053] The first light-emitting sub-circuit is used to control the light emission of a first part of the multiple light-emitting elements (exemplarily, the first part can be the first light-emitting element to the nth light-emitting element), and the second light-emitting sub-circuit is used to control the light emission of a second part of the multiple light-emitting elements (exemplarily, the second part can be the (i+1)th light-emitting element to the nth light-emitting element, where i is a natural number between 1 and n-1). The number of light-emitting elements included in the first part is different from the number of light-emitting elements included in the second part.

[0054] In some exemplary embodiments, the light-emitting device layer 103 includes an anode layer, a pixel definition layer 96, a first organic light-emitting layer 61, an electron-charge generation layer 97, a hole-charge generation layer 98, a second organic light-emitting layer 62 and a cathode 99 stacked in sequence on the driving circuit layer 102, the first light-emitting sub-circuit is used to control the light emission of the first organic light-emitting layer 61 and the second organic light-emitting layer 62, and the second light-emitting sub-circuit is used to control the light emission of the second organic light-emitting layer 62.

[0055] In some exemplary embodiments, Figures 3a to 3c As shown, the anode layer includes a first anode 51 and a second anode 52 , the first anode 51 is connected to the first organic light-emitting layer 61 , and the second anode 52 is connected to the electron-charge generation layer 97 and / or the hole-charge generation layer 98 .

[0056] In this embodiment, the electron-charge generation layer 97 and the hole-charge generation layer 98 form an NP structure, such as Figure 3a As shown, the second anode 52 may be connected to the electron-charge generating layer 97, as shown in FIG. Figure 3b As shown, the second anode 52 may also be connected to the hole-charge generating layer 98, or, as shown Figure 3c As shown, the second anode 52 may be connected to both the electron-charge generating layer 97 and the hole-charge generating layer 98 .

[0057] In other exemplary embodiments, Figure 3d As shown, the anode layer includes a first anode 51 and a second anode 52, and the light-emitting device layer also includes an electrode layer 63 arranged between the electron-charge generating layer 97 and the hole-charge generating layer 98. The first anode 51 is connected to the first organic light-emitting layer 61, and the second anode is connected to any one or more layers of the electron-charge generating layer 97, the electrode layer 63 and the hole-charge generating layer 98.

[0058] In some exemplary embodiments, the material of the electrode layer 63 may be a metal, such as molybdenum (Mo), silver (Ag), copper (Cu) or aluminum (Al), or the material of the electrode layer 63 may be a conductive oxide, such as indium tin oxide ITO or indium zinc oxide IZO.

[0059] In this embodiment, the electron-charge generating layer 97, the electrode layer 63 and the hole-charge generating layer 98 form an NMP structure. Figure 3d As shown, the second anode 52 can be connected to the electron-charge generating layer 97, or, in other exemplary embodiments, the second anode 52 can also be connected to the electrode layer 63 (not shown in the figure), or, the second anode 52 can also be connected to the hole-charge generating layer 98 (not shown in the figure), or, the second anode 52 can also be connected to any two or three layers of the electron-charge generating layer 97, the electrode layer 63 and the hole-charge generating layer 98 (not shown in the figure).

[0060] In some exemplary embodiments, the pixel definition layer 96 includes a first pixel opening K1 and a second pixel opening K2, the first pixel opening K1 exposes at least a portion of the first anode 51, the second pixel opening K2 exposes at least a portion of the second anode 52, and the electron-charge generation layer 97 and / or the hole-charge generation layer 98 have an orthographic projection on the substrate 10 covering the orthographic projection of the first pixel opening K1 and the second pixel opening K2 on the substrate 10.

[0061] In some exemplary embodiments, the first organic light-emitting layer 61 is located in the first pixel opening K1, and the first organic light-emitting layer 61 includes a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer stacked in sequence on the first anode 51;

[0062] The orthographic projection of the second organic light-emitting layer 62 on the substrate 10 covers the orthographic projections of the first pixel opening K1 and the second pixel opening K2 on the substrate 10, and the second organic light-emitting layer 62 includes a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer stacked in sequence on the hole-charge generation layer 98.

[0063] In some exemplary embodiments, an orthographic projection of the second organic light emitting layer 62 on the substrate 10 covers an orthographic projection of the electron-charge generation layer 97 and / or the hole-charge generation layer 98 on the substrate 10 .

[0064] In some exemplary embodiments, the driving circuit layer 102 further includes a current control subcircuit, the first light-emitting subcircuit includes a first transistor T1, and the second light-emitting subcircuit includes a second transistor T2, wherein:

[0065] The current control subcircuit is used to receive a data signal and a light-emitting control signal, control whether to generate a driving current according to the light-emitting control signal, and control the current intensity of the generated driving current according to the data signal;

[0066] The control electrode of the first transistor T1 is connected to the second scanning signal line, the source electrode of the first transistor T1 is connected to the output end of the current control sub-circuit, and the drain electrode of the first transistor T1 is connected to the first anode 51;

[0067] The control electrode of the second transistor T2 is connected to the third scan signal line, the source electrode of the second transistor T2 is connected to the output end of the current control sub-circuit, and the drain electrode of the second transistor T2 is connected to the second anode 52 .

[0068] Figure 5a FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 5a As shown, the pixel driving circuit includes a current control subcircuit, a first light-emitting subcircuit and a second light-emitting subcircuit, wherein the current control subcircuit includes a third transistor T3 to an eighth transistor T8 and a first capacitor C1, the first light-emitting subcircuit includes a first transistor T1, and the second light-emitting subcircuit includes a second transistor T2.

[0069] Among them, the control electrode of the first transistor T1 is connected to the second scanning signal line GateB(1), the first electrode of the first transistor T1 is connected to the first node N1, the second electrode of the first transistor T1 is connected to one side of the first light-emitting element EL1, the other side of the first light-emitting element EL1 is connected to one side of the second light-emitting element EL2, and the other side of the second light-emitting element EL2 is connected to the second power supply line VSS; the control electrode of the second transistor T2 is connected to the third scanning signal line GateB(2), the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to one side of the second light-emitting element EL2; the control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the fourth node N4; the control electrode of the fourth transistor T4 is connected to the first scanning signal line GateA, the first electrode of the fourth transistor T4 is connected to the second node N2, and the fourth transistor A second electrode of T4 is connected to a fourth node N4; one end of the first capacitor C1 is connected to the second node N2, and the other end of the first capacitor C1 is connected to the first power supply line VDD; a control electrode of the fifth transistor T5 is connected to the reset signal line Reset, a first electrode of the fifth transistor T5 is connected to the initial signal line Vinit, and a second electrode of the fifth transistor T5 is connected to the second node N2; a control electrode of the sixth transistor T6 is connected to the first scan signal line GateA, a first electrode of the sixth transistor T6 is connected to the data signal line Data, and a second electrode of the sixth transistor T6 is connected to the third node N3; a control electrode of the seventh transistor T7 is connected to the light emitting signal line EM, a first electrode of the seventh transistor T7 is connected to the first power supply line VDD, and a second electrode of the seventh transistor T7 is connected to the third node N3; a control electrode of the eighth transistor T8 is connected to the light emitting signal line EM, a first electrode of the eighth transistor T8 is connected to the fourth node N4, and a second electrode of the eighth transistor T8 is connected to the first node N1.

[0070] In this embodiment, the first transistor T1 to the eighth transistor T8 can all be N-type thin-film transistors or P-type thin-film transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In addition, considering that the leakage current of low-temperature polycrystalline silicon thin-film transistors is relatively low, it is preferred that all transistors in this embodiment of the present invention be low-temperature polycrystalline silicon thin-film transistors. Specifically, the thin-film transistors can be bottom-gate thin-film transistors or top-gate thin-film transistors, as long as they can achieve the switching function.

[0071] In some exemplary embodiments, the first scanning signal line GateA is the scanning signal line in the pixel driving circuit of the current display row, and the reset signal line Reset is the scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line GateA is GateA(n), and the reset signal line Reset is GateA(n-1). The reset signal line Reset of the current display row and the first scanning signal line GateA in the pixel driving circuit of the previous display row can be the same signal line, so as to reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0072] In some exemplary embodiments, the light-emitting element EL (including the first to nth light-emitting elements) may be an organic electroluminescent diode (OLED), or may be another type of light-emitting diode, such as a micro-LED or sub-millimeter LED. In practical applications, the specific structure of the light-emitting element EL needs to be designed and determined based on the actual application environment and is not limited here. The following description uses the light-emitting element EL as an example, wherein the light-emitting element EL is an organic electroluminescent diode.

[0073] It should be noted that the first capacitor C1 can be a liquid crystal capacitor formed by a pixel electrode and a common electrode, or an equivalent capacitor formed by a liquid crystal capacitor formed by a pixel electrode and a common electrode and a storage capacitor, which is not limited in this application.

[0074] The following further illustrates the technical solution of the embodiment of the present invention through the working process of the pixel driving circuit. It should be noted that the following description is based on the working process of the first-level pixel driving circuit as an example.

[0075] In the following, the pixel driving circuit provided by the embodiment of the present application is provided with the first transistor T1 to the eighth transistor T8 being a P-type thin film transistor as an example. Figure 5a The pixel driving circuit shown and Figure 5b The working timing diagram shown in FIG. 1 specifically describes the working process of a pixel driving circuit in a frame period. Figure 5a As shown, the pixel driving circuit provided in the embodiment of the present application includes 8 transistor units (T1~T8), 1 capacitor unit (C1) and 2 power lines (VDD, VSS), wherein the first power line VDD continuously provides a high-level signal and the second power line VSS continuously provides a low-level signal.

[0076] Its working process includes:

[0077] In the first stage t1, i.e., the reset stage, the voltage of the reset signal line Reset is pulled low, the fifth transistor T5 is turned on, and the gate electrode of the third transistor T3 and one end of the first capacitor C1 (i.e., the second node N2) are reset to the initial voltage of the initial signal line Vinit;

[0078] The second stage t2 is the threshold voltage compensation and display data reading stage. At this time, the voltage of the first scan signal line GateA is pulled low, the sixth transistor T6, the third transistor T3 and the fourth transistor T4 are turned on, the data signal of the data signal line Data is input, and the data signal and the threshold voltage (Vdata+Vth) are stored on the first capacitor C1.

[0079] In the third stage t3, i.e., the light-emitting sub-stage, the voltage of the light-emitting signal line EM is pulled low, the seventh transistor T7 and the eighth transistor T8 are in the on-state, and the light-emitting state of the first light-emitting element EL1 and the second light-emitting element EL2 is determined according to the switching state of the first transistor T1 and the second transistor T2. For example, when the second scanning signal line GateB(1) is at a low level, the first transistor T1 is turned on, and the first light-emitting element EL1 and the second light-emitting element EL2 are both in the light-emitting state; or, when the third scanning signal line GateB(2) is at a low level, the second transistor T2 is turned on, the first light-emitting element EL1 is not illuminated, and the second light-emitting element EL2 is illuminated.

[0080] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0081] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate 10, patterning the semiconductor film through a patterning process to form a first insulating layer 91 covering the substrate 10, and a semiconductor layer disposed on the first insulating layer 91.

[0082] In an exemplary embodiment, the semiconductor layer of each sub-pixel may include a first active layer of the first transistor T1 to an eighth active layer of the eighth transistor T8. In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0083] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first metal film through a patterning process to form a second insulating layer 92 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 92. The first conductive layer pattern may include: the gate electrode of the first transistor T1 to the gate electrode of the eighth transistor T8, a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first plate of a storage capacitor. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0084] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first and second areas of the first to seventh active layers are all conductorized.

[0085] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate having the aforementioned pattern formed thereon, patterning the second metal film using a patterning process to form a third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93. The second conductive layer pattern may include: an initial signal line and a second plate of a storage capacitor, etc. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0086] (4) Forming a pattern of the fourth insulating layer 94. In an exemplary embodiment, forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer 94 covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer 94.

[0087] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third metal film on the substrate having the aforementioned pattern formed thereon, patterning the third metal film using a patterning process to form a third conductive layer disposed on the fourth insulating layer 94. The third conductive layer may include: source electrodes of the first transistor T1 to the eighth transistor T8, drain electrodes of the first transistor T1 to the eighth transistor T8, a first power line, a data signal line, and a connection electrode. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0088] In an exemplary embodiment, the source electrodes of the first to eighth transistors T1 to T8 are connected to one end of the active layer of the first to eighth transistors T1 to T8 through vias, respectively, and the drain electrodes of the first to eighth transistors T1 to T8 are connected to the other end of the active layer of the first to eighth transistors T1 to T8 through vias, respectively.

[0089] (6) Forming a pattern of the first flat layer 95. In an exemplary embodiment, forming the pattern of the first flat layer 95 may include: coating a first flat film on the substrate on which the aforementioned pattern is formed, patterning the first flat film using a patterning process to form a first flat layer 95 covering the third conductive layer, wherein a plurality of vias are provided on the first flat layer 95, and the plurality of vias include at least a first via V1 and a second via V2, and the first flat layer 95 in the first via V1 is etched away to expose the surface of the drain electrode of the first transistor T1. The first via V1 is configured to allow a first anode formed subsequently to be connected to the drain electrode of the first transistor T1 through the via. The first flat layer 95 in the second via V2 is etched away to expose the surface of the drain electrode of the second transistor T2. The second via V2 is configured to allow a second anode formed subsequently to be connected to the drain electrode of the second transistor T2 through the via.

[0090] At this point, the substrate 10 is prepared as follows Figure 6In the plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a data signal line, a first power supply line, an initial signal line, etc. connected to the pixel driving circuit. In the plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer 91, a semiconductor layer, a second insulating layer 92, a first conductive layer, a third insulating layer 93, a second conductive layer, a fourth insulating layer 94, a third conductive layer, and a first planar layer 95, which are sequentially stacked on the base 10.

[0091] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations:

[0092] (7) Forming an anode layer pattern. In some exemplary embodiments, forming the anode pattern may include: depositing a transparent conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the transparent conductive film using a patterning process to form an anode layer disposed on the first planar layer.

[0093] In some exemplary embodiments, the anode layer includes a first anode 51 and a second anode 52, the first anode 51 is connected to the drain electrode of the first transistor T1 through a first via hole V1, and the second anode 52 is connected to the drain electrode of the second transistor T2 through a second via hole V2, thereby realizing that the pixel driving circuit can drive the first light-emitting element and / or the second light-emitting element to emit light.

[0094] (8) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film through a patterning process to form a pixel definition (PDL) layer 96 pattern, wherein a first pixel opening K1 and a second pixel opening K2 are formed on the pixel definition layer 96, the pixel definition layer 96 within the first pixel opening K1 is removed to expose a portion of the surface of the first anode 51, and the pixel definition layer 96 within the second pixel opening K2 is removed to expose a portion of the surface of the second anode 52.

[0095] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc. In a plane parallel to the display substrate, the shape of the first pixel opening K1 may be similar to that of the first anode 51, and the shape of the second pixel opening K2 may be similar to that of the second anode 52. In a plane perpendicular to the display substrate, the cross-sectional shape of the first pixel opening K1 and the second pixel opening K2 may be rectangular or trapezoidal, etc.

[0096] (9) Forming a first organic light-emitting layer pattern. In an exemplary embodiment, forming the first organic light-emitting layer pattern may include: evaporating a first organic light-emitting material on the substrate formed with the aforementioned pattern to form a first organic light-emitting layer 61 pattern, wherein the first organic light-emitting layer 61 is connected to the first anode 51 through the first pixel opening, as shown in FIG. Figure 7 shown.

[0097] In an exemplary embodiment, the first organic light-emitting layer 61 may include an emitting layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the first organic light-emitting layer 61 may be formed by evaporation using a fine metal mask (FMM).

[0098] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, with the doping ratio of the guest material in the light-emitting layer being between 1% and 20%. Within this doping ratio range, the host material in the light-emitting layer can effectively transfer exciton energy to the guest material in the light-emitting layer to stimulate the guest material to emit light. Furthermore, the host material in the light-emitting layer "dilutes" the guest material in the light-emitting layer, effectively improving the fluorescence quenching caused by collisions between guest material molecules and energy collisions, thereby improving the luminous efficiency and device life. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, i.e., the mass percentage. In an exemplary embodiment, the host material and the guest material can be co-evaporated using a multi-source evaporation process so that the host material and the guest material are uniformly dispersed in the light-emitting layer. The doping ratio can be controlled by controlling the evaporation rate of the guest material during the evaporation process, or by controlling the ratio of the evaporation rates of the host material and the guest material. In an exemplary embodiment, the thickness of the light-emitting layer can be approximately 10 nm to 50 nm.

[0099] In an exemplary embodiment, the hole injection layer may be made of an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or may be made of a p-type dopant of a strong electron-withdrawing system and a dopant of a hole transport material. In an exemplary embodiment, the hole injection layer may have a thickness of approximately 5 nm to 20 nm.

[0100] In an exemplary embodiment, the hole transport layer may be made of a material with high hole mobility, such as an aromatic amine compound, whose substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, or furan. In an exemplary embodiment, the hole transport layer may have a thickness of approximately 40 nm to 150 nm.

[0101] In an exemplary embodiment, the hole blocking layer and the electron transport layer may be made of aromatic heterocyclic compounds, such as imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, and benzimidazolephenanthridine derivatives; oxazine derivatives such as pyrimidine derivatives and triazine derivatives; and compounds containing a nitrogen-containing six-membered ring structure such as quinoline derivatives, isoquinoline derivatives, and phenanthroline derivatives (including compounds having a phosphine oxide-based substituent on the heterocyclic ring). In an exemplary embodiment, the hole blocking layer may have a thickness of approximately 5 nm to 15 nm, and the electron transport layer may have a thickness of approximately 20 nm to 50 nm.

[0102] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or a compound of these alkali metals or metals. In an exemplary embodiment, the electron injection layer may have a thickness of approximately 0.5 nm to 2 nm.

[0103] (10) Patterns of an N-charge generation layer (N-CGL) 97 and a P-charge generation layer (P-CGL) 98 are formed. In an exemplary embodiment, the N-charge generation layer 97 and the P-charge generation layer 98 are sequentially evaporated using a fine metal mask. The N-CGL layer 97 is connected to the second anode 52 through the second pixel opening K2.

[0104] In an exemplary embodiment, the N-CGL layer 97 comprises a host material and a guest material. The host material of the N-CGL layer 97 has a lowest unoccupied molecular orbital (LUMO) energy level less than or equal to -2.9 and a glass transition temperature greater than 130°C. This structure can effectively improve the high-temperature reliability of the stacked device.

[0105] In an exemplary embodiment, the guest material of the N-CGL layer 97 may be an implanted metal material, such as Yb (ytterbium), or may be other metals or metal compounds, such as Cs (cesium) or Li (lithium). In an exemplary embodiment, the doping concentration of the guest material of the N-CGL layer 97 is in the range of 0.8% to 1.2%.

[0106] In an exemplary embodiment, the P-CGL layer 98 may be a single material film layer, that is, the P-CGL layer 98 is made of only one material, for example, a P-doped material (PD-doped material).

[0107] In an exemplary embodiment, the P-CGL layer 98 may be a mixed material film layer, i.e., the P-CGL layer 98 is made of at least two materials, such as a host material and a guest material. In an exemplary embodiment, the host material of the P-CGL layer 98 is selected from any of triphenylamine-based and biphenyl-based hole transport materials. The P-doped material serving as the guest material may have a mass concentration of 5% or less.

[0108] In an exemplary embodiment, the thickness of the P-CGL layer 98 is between 50 angstroms and 120 angstroms.

[0109] (11) Forming a second organic light-emitting layer pattern. In an exemplary embodiment, forming the second organic light-emitting layer 62 pattern may include: evaporating a second organic light-emitting material on the substrate formed with the aforementioned pattern to form the second organic light-emitting layer 62 pattern, such as Figure 8 shown.

[0110] In an exemplary embodiment, the orthographic projection of the second organic light emitting layer 62 on the substrate covers the orthographic projection of the N-CGL layer 97 and / or the P-CGL layer 98 on the substrate, thereby preventing a device short circuit.

[0111] In an exemplary embodiment, the second organic light-emitting layer 62 may include an emitting layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the second organic light-emitting layer 62 may be formed by evaporation using a fine metal mask (FMM).

[0112] In an exemplary embodiment, the materials and thicknesses of the light-emitting layer, hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer can refer to those described in the aforementioned step (9) and are not repeated here.

[0113] (12) Forming a cathode 99 pattern. In an exemplary embodiment, forming the cathode 99 pattern may include: evaporating a cathode material on the substrate having the aforementioned pattern formed thereon to form the cathode 99 pattern, wherein the cathode 99 is connected to the second organic light-emitting layer 62. In an exemplary embodiment, the cathode 99 may be a connected integral structure.

[0114] (13) Forming a pattern of the light extraction layer 100. In an exemplary embodiment, forming a pattern of the light extraction layer 100 may include: evaporating a light extraction layer material on a substrate having the aforementioned pattern, to form a pattern of the light extraction layer 100, such as Figure 9 As shown, the light extraction layer 100 is connected to the cathode 99 .

[0115] At this point, the light-emitting structure layer pattern is completed on the driving circuit layer. The light-emitting structure layer includes an anode layer, a pixel definition layer, a first organic light-emitting layer, an N-charge generation layer, a P-charge generation layer, a cathode and a light extraction layer. The anode layer includes a first anode and a second anode. The first organic light-emitting layer is connected to the N-charge generation layer and the first anode respectively. The N-charge generation layer is connected to the P-charge generation layer and the second anode respectively. The second organic light-emitting layer is connected to the cathode and the P-charge generation layer respectively. Figures 10a to 10cAs shown, the first organic light-emitting layer includes a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer stacked in sequence on the first anode, and the second organic light-emitting layer includes a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer stacked in sequence on the hole-charge generating layer.

[0116] (14) Forming a pattern of the encapsulation layer 101. In an exemplary embodiment, forming a pattern of the encapsulation layer 101 may include: first using an open mask plate to deposit a first inorganic thin film by plasma enhanced chemical vapor deposition (PECVD) to form a first encapsulation layer. Subsequently, using an inkjet printing process to inkjet print an organic material on the first encapsulation layer, and after curing into a film, forming a second encapsulation layer. Subsequently, using an open mask plate to deposit a second inorganic thin film to form a third encapsulation layer. The first encapsulation layer, the second encapsulation layer, and the third encapsulation layer constitute the encapsulation layer 101, as shown in FIG. Figures 3a to 3d In an exemplary embodiment, the first and third encapsulation layers may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The second encapsulation layer may be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is disposed between the two inorganic material layers to prevent external moisture from entering the light-emitting structure layer.

[0117] In an exemplary embodiment, when preparing a flexible display substrate, the preparation process of the display substrate may include processes such as peeling off a glass carrier, attaching a back film, and cutting, which are not limited in the present disclosure.

[0118] In some exemplary embodiments, the substrate 10 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some exemplary embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0119] In some exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The anode layer may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is called a buffer (BUF) layer and is used to improve the substrate's resistance to water and oxygen. The second insulating layer is called a first gate insulating (GI1) layer, the third insulating layer is called a second gate insulating (GI2) layer, and the fourth insulating layer is called an interlayer insulating (ILD) layer. The first planarization (PLN1) layer may be made of an organic material. The semiconductor layer may be made of polysilicon (p-Si) or oxide.

[0120] The structure and fabrication process shown in this disclosure are merely exemplary. In exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or reduced as needed. For example, the display area may include three sub-pixels. Another example is a pixel driver circuit that may be a 5T1C or 7T1C circuit. Furthermore, other electrodes or leads may be provided within the film structure, and this disclosure does not specifically limit these.

[0121] When a display device is in high brightness, single-layer RGB light-emitting elements can only achieve high brightness by increasing the current. However, high current can significantly reduce the device's service life and affect its performance. The present disclosure achieves high brightness through RGB tandem light-emitting elements. These tandem light-emitting elements enable the display device to achieve high brightness at low current density. When the display device requires low brightness, the present disclosure disables one or more light-emitting elements through the light-emitting subcircuit, using a single light-emitting element to achieve low brightness. This ensures that the device still requires a relatively high current in the low brightness state, which facilitates grayscale setting and improves device performance.

[0122] Table 1 and Figures 11a to 11f The comparison test results of RGB tandem light emitting elements and RGB single layer light emitting elements in terms of luminous efficiency and service life are shown in Table 1 and Figures 11a to 11fAs shown in the figure, RGB tandem light-emitting elements have obvious advantages over RGB single-layer light-emitting elements in terms of luminous efficiency and service life, where 10mA / cm2 is the current density during the test, L is the brightness, CE is the current efficiency, EQE is the external quantum efficiency, CIEx and CIEy are the color coordinates, WP is the wavelength, and Lifetime is the service life.

[0123]

[0124] It can be seen from the structure and preparation process of the display substrate described above that the display substrate provided by the present disclosure is provided with a plurality of light-emitting sub-circuits on the driving circuit layer and a plurality of stacked light-emitting elements on the light-emitting device layer, such as Figure 12a and Figure 12b As shown, multiple stacked light-emitting elements are used for high-brightness display, and at least one of the stacked light-emitting elements is used for low-brightness display, achieving the technical effect of switching between high-brightness display and low-brightness display, while increasing the brightness of the display device and prolonging the life of the light-emitting elements. The present disclosure uses at least one of the multiple stacked light-emitting elements for low-brightness display, which can also improve the low-grayscale display quality of the display device, thereby improving display performance.

[0125] The preparation process disclosed herein can be realized using existing mature preparation equipment, with minor improvements to existing processes, and can be well compatible with existing preparation processes. The process is simple to realize, easy to implement, with high production efficiency, low production cost, and high yield rate.

[0126] The exemplary embodiments of the present disclosure further provide a method for preparing a display substrate, which may include:

[0127] forming a driving circuit layer on the substrate, wherein the driving circuit layer includes a plurality of light-emitting control circuits, and the plurality of light-emitting control circuits include a first light-emitting sub-circuit and a second light-emitting sub-circuit;

[0128] A light-emitting device layer is formed on the driving circuit layer, and the light-emitting device layer includes a plurality of light-emitting elements stacked in sequence on the driving circuit layer. The first light-emitting sub-circuit is used to control the emission of a first part of the plurality of light-emitting elements, and the second light-emitting sub-circuit is used to control the emission of a second part of the plurality of light-emitting elements. The number of light-emitting elements included in the first part is different from the number of light-emitting elements included in the second part.

[0129] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that: The invention comprises a driving circuit layer and a light-emitting device layer sequentially stacked on a substrate, wherein the driving circuit layer comprises a plurality of light-emitting control circuits, and the light-emitting device layer comprises a plurality of light-emitting elements sequentially stacked on the driving circuit layer, wherein: The multiple light-emitting control circuits include a first light-emitting sub-circuit and a second light-emitting sub-circuit, the multiple light-emitting elements include an anode layer, a pixel definition layer, a first organic light-emitting layer, an electron-charge generation layer, a hole-charge generation layer, a second organic light-emitting layer, and a cathode sequentially stacked on the drive circuit layer, the first light-emitting sub-circuit is used to control the first organic light-emitting layer and the second organic light-emitting layer to emit light, and the second light-emitting sub-circuit is used to control the second organic light-emitting layer to emit light; The anode layer includes a first anode and a second anode, the driving circuit layer also includes a current control subcircuit, the first light-emitting subcircuit includes a first transistor, and the second light-emitting subcircuit includes a second transistor, wherein: the current control subcircuit is used to receive a data signal and a light-emitting control signal, control whether to generate a driving current according to the light-emitting control signal, and control the current intensity of the generated driving current according to the data signal; the control electrode of the first transistor is connected to the second scanning signal line, the source electrode of the first transistor is connected to the output end of the current control subcircuit, and the drain electrode of the first transistor is connected to the first anode; the control electrode of the second transistor is connected to the third scanning signal line, the source electrode of the second transistor is connected to the output end of the current control subcircuit, and the drain electrode of the second transistor is connected to the second anode.

2. The display substrate according to claim 1, wherein: The light-emitting device layer also includes an electrode layer arranged between the electron-charge generating layer and the hole-charge generating layer, the first anode is connected to the first organic light-emitting layer, and the second anode is connected to any one or more layers of the electron-charge generating layer, the electrode layer and the hole-charge generating layer.

3. The display substrate according to claim 1, wherein The first anode is connected to the first organic light-emitting layer, and the second anode is connected to any one or more of the electron-charge generation layer and the hole-charge generation layer.

4. The display substrate according to claim 3, wherein: The pixel definition layer includes a first pixel opening and a second pixel opening, the first pixel opening exposes at least a portion of the first anode, the second pixel opening exposes at least a portion of the second anode, and the orthographic projection of the electron-charge generation layer on the substrate covers the orthographic projections of the first pixel opening and the second pixel opening on the substrate.

5. The display substrate according to claim 4, wherein: The first organic light-emitting layer is located in the first pixel opening, and the first organic light-emitting layer includes a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer stacked in sequence on the first anode; The orthographic projection of the second organic light-emitting layer on the substrate covers the orthographic projections of the first pixel opening and the second pixel opening on the substrate, and the second organic light-emitting layer includes a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer stacked in sequence on the hole-charge generating layer.

6. The display substrate according to claim 3, wherein: The orthographic projection of the second organic light-emitting layer on the substrate covers the orthographic projection of the electron-charge generation layer and / or the hole-charge generation layer on the substrate.

7. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 6.

8. A method for preparing a display substrate, characterized in that: include: A driving circuit layer is formed on a substrate, the driving circuit layer including a current control subcircuit and multiple light-emitting control circuits, the multiple light-emitting control circuits including a first light-emitting subcircuit and a second light-emitting subcircuit, the first light-emitting subcircuit including a first transistor, and the second light-emitting subcircuit including a second transistor, wherein: the current control subcircuit is configured to receive a data signal and a light-emitting control signal, control whether to generate a driving current based on the light-emitting control signal, and control the current intensity of the generated driving current based on the data signal; the control electrode of the first transistor is connected to a second scan signal line, and the source electrode of the first transistor is connected to an output end of the current control subcircuit; the control electrode of the second transistor is connected to a third scan signal line, and the source electrode of the second transistor is connected to the output end of the current control subcircuit; A light-emitting device layer is formed on the driving circuit layer, the light-emitting device layer includes a plurality of light-emitting elements stacked in sequence on the driving circuit layer, the plurality of light-emitting elements include an anode layer, a pixel definition layer, a first organic light-emitting layer, an electron-charge generation layer, a hole-charge generation layer, a second organic light-emitting layer and a cathode stacked in sequence on the driving circuit layer, the anode layer includes a first anode and a second anode, the drain electrode of the first transistor is connected to the first anode, and the drain electrode of the second transistor is connected to the second anode, the first light-emitting sub-circuit is used to control the light emission of the first organic light-emitting layer and the second organic light-emitting layer, and the second light-emitting sub-circuit is used to control the light emission of the second organic light-emitting layer.

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