Semiconductor device including a plurality of trenches

Abstract

A semiconductor device (100) is provided. The semiconductor device (100) includes a plurality of grooves (102) extending from a first main surface (106) into a semiconductor body (104). A first group of grooves (1021) of the plurality of grooves (102) includes a gate electrode (1081). A second group of grooves (1022) of the plurality of grooves (102) includes a source electrode (1082). A third group of grooves (1023) of the plurality of grooves (102) includes an auxiliary electrode (1083). The source electrode (1082) is electrically coupled to a source contact region (110) via a source wiring (112) and the auxiliary electrode (1083). The source wiring (112) and the auxiliary electrode (1083) are electrically connected in series between the source contact region (110) and the source electrode (1082).

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including a plurality of trenches. Background Art

[0002] In semiconductor switching devices such as insulated gate bipolar transistors (IGBTs), mobile charge carriers rush into a lowly doped drift region and form a charge carrier plasma that provides a low on-state resistance. When switching between the on-state and the off-state via a gate electrode in a trench, parasitic capacitances have an impact on the overall switching behavior of the device. Undesirable effects such as turn-on losses may result. Therefore, the development of semiconductor device technology is challenging to meet target requirements for the switching characteristics of semiconductor trench devices.

[0003] There is a need to improve the switching characteristics of semiconductor trench devices. Summary of the invention

[0004] An example of the present disclosure relates to a semiconductor device. The semiconductor device includes a plurality of grooves extending from a first main surface into a semiconductor body. A first group of grooves in the plurality of grooves includes a gate electrode. A second group of grooves in the plurality of grooves includes a source electrode. A third group of grooves in the plurality of grooves includes an auxiliary electrode. The source electrode is electrically coupled to a source contact region via a source wiring and an auxiliary electrode. The source wiring and the auxiliary electrode are electrically connected in series between the source contact region and the source electrode.

[0005] Another example of the present disclosure relates to another semiconductor device. The semiconductor device includes a plurality of grooves extending from a first main surface into a semiconductor body. A first group of grooves in the plurality of grooves includes a gate electrode. A second group of grooves in the plurality of grooves includes a source electrode. The source electrode is subdivided into at least a first portion and a second portion. The conductance per unit length of the first portion of the source electrode in an axial direction is less than the conductance per unit length of the second portion of the source electrode in an axial direction. The second portion is electrically coupled to a source contact region via the first portion. The semiconductor device also includes a mesa region defined by grooves in the first group of grooves and grooves in the second group of grooves. The mesa region includes a source region electrically connected to the source contact region.

[0006] Another example of the present disclosure relates to another semiconductor device. The semiconductor device includes a plurality of grooves extending from a first main surface into a semiconductor body. A first group of grooves in the plurality of grooves includes a gate electrode. A second group of grooves in the plurality of grooves includes a source electrode. The source electrodes in the second group of grooves are electrically coupled to a source contact region via a source wiring and a resistor placed on a substrate different from the semiconductor body. The source wiring and the resistor are connected in series between the source contact region and the source electrodes in the second group of grooves.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of semiconductor devices, such as vertical power semiconductor devices, and together with the description serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

[0009] Figures 1A to 1F are schematic plan views and cross-sectional views for illustrating an example of a semiconductor device including resistive coupling between a source electrode and a source contact region.

[0010] FIG. 2A to FIG. 2I is a schematic layout for illustrating an example of resistive coupling between a source electrode and a source contact region.

[0011] FIG. 3A to FIG. 3C , Figure 4 and Figure 5 are schematic plan views and cross-sectional views for illustrating other examples of semiconductor devices including resistive coupling between a source electrode and a source contact region. DETAILED DESCRIPTION

[0012] In the detailed description below, reference is made to the accompanying drawings, which form a part of the present invention and in which specific embodiments in which the present invention can be practiced are shown by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features shown or described for one embodiment may be used in other embodiments or in combination with other embodiments to produce yet another embodiment. The present invention is intended to include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The accompanying drawings are not drawn to scale but are for illustration purposes only. For clarity, the same elements are represented by corresponding reference numerals in different drawings unless otherwise specified.

[0013] The terms "having", "containing", "including", "comprising" and the like are open ended, and these terms indicate the presence of stated structures, elements or features, but do not exclude additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0014] The term "electrically connected" describes a permanent low resistance connection between electrically connected elements, such as direct contact between the associated elements or a low resistance connection via metal and / or heavily doped semiconductor materials. The term "electrically coupled" includes one or more intermediate elements suitable for signal and / or power transmission that can be connected between electrically coupled elements, such as elements that can be controlled to temporarily provide a low resistance connection in a first state and a high resistance connection in a second state. An ohmic contact is a non-rectifying electrical junction with a linear or nearly linear current-voltage characteristic.

[0015] Ranges given for physical dimensions include the bounding values. For example, a parameter y ranging from a to b is read as a≤y≤b. A parameter y with a value of at least c is read as c≤y, and a parameter y with a value of at most d is read as y≤d.

[0016] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is “on” another element (e.g., a layer is “on” another layer or “on” a substrate), additional components (e.g., additional layers) may be located between the two elements (e.g., if a layer is “on” a substrate, the additional layers may be located between the layer and the substrate).

[0017] An example of a semiconductor device may include a plurality of trenches extending from a first main surface into a semiconductor body. A first group of trenches in the plurality of trenches may include a gate electrode. A second group of trenches in the plurality of trenches may include a source electrode. A third group of trenches in the plurality of trenches may include an auxiliary electrode. The source electrode may be electrically coupled to a source contact region via a source wiring and an auxiliary electrode. The source wiring and the auxiliary electrode may be electrically connected in series between the source contact region and the source electrode.

[0018] The semiconductor device may be a vertical power semiconductor device having a load current flowing between a first load terminal at a first main surface and a second load terminal at a second main surface opposite to the first main surface. The semiconductor device may be a vertical power semiconductor IGBT (insulated gate bipolar transistor), or a power semiconductor reverse conduction (RC) IGBT or a power semiconductor transistor such as a power semiconductor IGFET (insulated gate field effect transistor, such as a metal oxide semiconductor field effect transistor). The vertical power semiconductor device may be configured to conduct a current exceeding 1A or exceeding 30A or even exceeding 100A, and may be further configured to block a voltage between load terminals, such as between the emitter and collector of an IGBT, or between the drain and source of a MOSFET, the voltage being in the range of several hundred volts up to several thousand volts, such as 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV. For example, the blocking voltage may correspond to a voltage level specified in a data sheet of the power semiconductor device.

[0019] The semiconductor body may include or consist of a semiconductor material from a group IV semiconductor, a IV-IV compound semiconductor material, a III-V compound semiconductor material, or a II-VI compound semiconductor material. Examples of semiconductor materials from group IV semiconductors include, in particular, silicon (Si) and germanium (Ge). Examples of IV-IV compound semiconductor materials include, in particular, silicon carbide (SiC) and silicon germanium (SiGe). Examples of III-V compound semiconductor materials include, in particular, gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). Examples of II-VI compound semiconductor materials include, in particular, cadmium telluride (CdTe), cadmium mercury telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe). For example, the semiconductor body may be a silicon semiconductor body of magnetic CZ, MCZ, or floating zone (FZ) or epitaxial deposition.

[0020] For example, the gate electrodes in the first group of trenches in the plurality of trenches may be electrically insulated from the surrounding portions of the semiconductor body (e.g., electrically insulated from the body region) by a dielectric, such as a gate dielectric. The dielectric may include a layer or a combination of layers, such as a layer stack of dielectric layers, such as an oxide layer such as a thermal oxide layer or a deposited oxide layer, such as an undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), a nitride layer, a high-k dielectric layer, or a low-k dielectric layer. The gate electrode may include an electrode material or a combination of electrode materials, such as a doped semiconductor material (e.g., a highly doped semiconductor material), such as doped polysilicon, a metal, or a metal compound. Similar to the gate electrodes in the first group of trenches, the source electrodes in the second group of trenches in the plurality of trenches may also be electrically insulated from the surrounding portions of the semiconductor body by a dielectric. The source electrode may include an electrode material or a combination of electrode materials, such as a doped semiconductor material (e.g., a highly doped semiconductor material), such as doped polysilicon, a metal, or a metal compound. Similar to the gate electrode in the first group of trenches and similar to the second electrode in the second group of trenches, the auxiliary electrode in the third group of trenches in the plurality of trenches may also be electrically insulated from the surrounding portion of the semiconductor body by a dielectric. The auxiliary electrode may include an electrode material or a combination of electrode materials, such as a doped semiconductor material (e.g., a highly doped semiconductor material), such as doped polysilicon, a metal, or a metal compound. Multiple trenches or portions thereof in the first group of trenches to the third group of trenches may be formed simultaneously, for example, by a common etching process. Similarly, the gate electrode, the source electrode, and the auxiliary electrode may also be formed at least partially simultaneously, for example, by a common layer deposition process.

[0021] All or some parts of each of the grooves in the first to third groups of grooves may be stripe-shaped. The stripe-shaped parts of the grooves in the first to third groups of grooves may extend in parallel along an axial direction, such as a first transverse direction.

[0022] The source wiring can be arranged at the edge of the active area. In the active area, the load current can enter the semiconductor body from the load terminal above the first main surface. For example, the load terminal can be a source contact area and the source wiring can be spaced laterally from the source contact area. Although the source in the second group of trenches can be at least partially arranged directly below the source contact area, the source in the second group of trenches can be electrically coupled to the source contact area via the source wiring and the auxiliary electrode in the third group of trenches, rather than being directly electrically connected to the source contact area through the contact portion above the source electrode. This can make it possible to reduce the shielding effect of the trenches in the second group of trenches by introducing a resistive coupling between the potential of the source electrode in the trenches in the second group of trenches and the potential of the source contact area. This resistive coupling can make it possible to suppress the turn-on voltage tailing and thus reduce the turn-on loss.

[0023] For example, the semiconductor device may include a drift region between the first main surface and the second main surface. The impurity concentration in the drift region may gradually or stepwise increase or decrease as the distance from the first main surface increases, at least in a vertically extending portion thereof. According to other examples, the impurity concentration in the drift region may be approximately uniform. For a silicon-based IGBT, the average impurity concentration in the drift region may be within 5×10 12 cm -3 With 1x10 15 cm -3 For example, from 1x10 13 cm -3 to 2x10 14 cm -3 In the case of a semiconductor device based on silicon carbide, the average impurity concentration in the drift region may be in the range of 5×10 14 cm -3 With 1x10 17 cm -3 For example, from 1x10 15 cm -3 to 2x10 16 cm -3 range. The vertical extension of the drift region may depend on the voltage blocking requirements of the vertical power semiconductor device, such as a specified voltage level. When the vertical power semiconductor device is operated in a voltage blocking mode, the space charge region may extend partially or completely vertically through the drift region depending on the blocking voltage applied to the vertical power semiconductor device. When the vertical power semiconductor device is operated at or near a specified maximum blocking voltage, the space charge region may reach or pass through the field termination region. The field termination region is configured to prevent the space charge region from further reaching the cathode or collector at the second main surface of the semiconductor body. In this way, the drift region or base region may be formed using a desired low doping level and with a desired thickness while achieving soft switching of the semiconductor device formed thereby.

[0024] For example, the source wiring and the source contact area can be separate parts of the patterned wiring layer. For example, the source wiring and the source contact area can correspond to a wiring level of the wiring area above the first main surface, wherein in the case of multiple wiring levels, a wiring level of the wiring area can be located closest to the first main surface. The wiring area can include one or more than one wiring level, such as two, three, four or even more wiring levels. Each wiring level can be formed by a stack of a single conductive layer or conductive layers, such as a metal layer. For example, the wiring level can be patterned by photolithography. An intermediate dielectric can be arranged between the stacked wiring levels. (Multiple) contact plugs or (multiple) contact lines can be formed in the openings in the intermediate dielectric to electrically connect parts of different wiring levels, such as metal lines or contact areas, to each other.

[0025] For example, the ratio between the number of trenches in the second group of trenches and the number of trenches in the third group of trenches may be in the range from 100 to 100000. For example, the ratio may enable adjusting the voltage drop of the resistive coupling between the source electrode and the source contact region.

[0026] For example, the source wiring may extend parallel to at least two sides of the source contact region. For example, some or all of the trenches in the second group of trenches may be electrically connected to the source wiring at opposite ends of the trenches. Some or all of the trenches in the second group of trenches may also be electrically connected to the source wiring at one end of the trenches.

[0027] For example, the source wiring may laterally surround at least one-quarter of the circumference of the source contact region. For this example, some or all of the trenches in the second set of trenches may be electrically connected to the source wiring at one end of the trench. For example, reducing the degree of looping of the source contact region by the source wiring may enable area-efficient resistive coupling between the source contact region and the source electrodes in the second set of trenches.

[0028] For example, the semiconductor device may further include a gate wiring. A source wiring may be arranged between the gate wiring and the source contact region. The gate wiring may extend parallel to at least two sides of the source wiring. The gate wiring and the source wiring may be separate parts of a patterned wiring layer. For example, the source wiring and the gate wiring may be formed in one wiring layer by photolithographically patterning one or more conductive layers of the wiring level.

[0029] For example, the semiconductor device may further include a second source wiring. The second source wiring may be connected in parallel to the source contact region. The source wiring may be arranged between the second source wiring and the source contact region. The source wiring may be completely or mainly (e.g., more than 50% of its circumference) laterally surrounded by the second source wiring and the source contact region. For example, the semiconductor device may include a plurality of contacts arranged between the second source wiring and the first main surface. The plurality of contacts may electrically connect a plurality of mesa regions to the second source wiring. Each of the plurality of mesa regions may be laterally defined by adjacent grooves. For example, electrically connecting the second source wiring to the mesa region may enable the commutation robustness of the semiconductor device to be improved.

[0030] The semiconductor device may further include a fourth group of trenches in the plurality of trenches. The trenches in the fourth group of trenches may include a second source electrode. In addition to being resistively coupled to the source electrode in the second group of trenches in the source contact region, the second source electrode in the trenches in the fourth group of trenches may be electrically connected to the source contact region via a contact arranged between the source contact region and the second source electrode and / or via a contact arranged between the second source wiring and the second source electrode.

[0031] For example, the auxiliary electrodes in the third group are connected in parallel between the source wiring and the source contact region. The total resistance of the auxiliary electrodes connected in parallel is 50 to 500 times the ratio of the resistance between the gate electrode and the gate terminal (e.g., gate pin or gate pad) multiplied by the sum of the axial extensions of all the grooves in the first group of grooves to the sum of the axial extensions of all the grooves in the second group of grooves.

[0032] For example, the semiconductor device may include a mesa region laterally defined by trenches in the first set of trenches and trenches in the second set of trenches, wherein the mesa region includes a source region. The source region in the mesa region may be electrically connected to the source contact region via a contact adjacent to a bottom side of the source contact region.

[0033] For example, the conductance per unit length of the auxiliary electrode along the axial direction of the plurality of grooves may be less than the conductance per unit length of the gate electrode along the axial direction of the plurality of grooves. For example, the material of the auxiliary electrode may have a resistivity greater than the resistivity of the material of the gate electrode. For example, the material or material combination of the auxiliary electrode and the gate electrode may be different. Alternatively or in addition, the auxiliary electrode and the gate electrode may use the same semiconductor material, such as polysilicon, but the doping concentration of the semiconductor material of the gate electrode may be greater than the doping concentration of the semiconductor material of the auxiliary electrode. Alternatively or in addition, the cross-sectional area of ​​the auxiliary electrode perpendicular to the axial direction of the grooves may be at least partially, for example, in at least some portions of the electrode along the axial direction, smaller than the cross-sectional area of ​​the gate electrode.

[0034] Another example of a semiconductor device may include a plurality of grooves extending from a first main surface into a semiconductor body. A first group of grooves in the plurality of grooves may include a gate electrode. A second group of grooves in the plurality of grooves may include a source electrode. The source electrode may be subdivided into at least a first portion and a second portion. The conductance per unit length of the first portion of the source electrode along the axial direction may be less than the conductance per unit length of the second portion of the source electrode along the axial direction. The second portion may be electrically coupled to a source contact region via the first portion. The semiconductor device may also include a mesa region defined by grooves in the first group of grooves and grooves in the second group of grooves. The mesa region may include a source region electrically connected to the source contact region.

[0035] Similar to the auxiliary electrodes in the trenches of the third group of trenches described in the above example, the first portion of the source electrode can enable resistive coupling between the second portion of the source electrode and the source contact region. Such resistive coupling can suppress turn-on voltage tailing and thus reduce turn-on losses.

[0036] For example, the material of the first portion of the source electrode may have a greater resistivity than the material of the second portion of the source electrode. For example, the material or material combination of the first portion of the source electrode and the second portion of the source electrode may be different. Alternatively or in addition, a semiconductor material may be used for the first portion of the source electrode and for the second portion of the source electrode, such as polysilicon, but the net doping concentration of the semiconductor material of the second portion of the source electrode may be greater than the net doping concentration of the semiconductor material of the first portion of the source electrode. Alternatively or in addition, the cross-sectional area of ​​the first portion of the source electrode perpendicular to the axial direction of the groove may be at least partially, for example in at least some segments of the first portion of the source electrode along the axial direction, for example due to a smaller lateral and / or vertical extent, smaller than the cross-sectional area of ​​the second portion of the source electrode.

[0037] For example, the lateral extent of the first portion of the source electrode in the axial direction may be smaller than the lateral extent of the second portion of the source electrode in the axial direction.For example, the second portion of the source electrode may be mainly, such as more than 50%, arranged below the source contact region.

[0038] For example, the vertical extent of the first portion of the source electrode may be smaller than the vertical extent of the second portion of the source electrode.

[0039] For example, the width of the first portion of the source electrode at the first major surface may be smaller than the width of the second portion of the source electrode at the first major surface.

[0040] Another example of a semiconductor device may include a plurality of grooves extending from a first main surface into a semiconductor body. A first group of grooves in the plurality of grooves may include a gate electrode. A second group of grooves in the plurality of grooves may include a source electrode. The source electrode in the second group of grooves may be electrically coupled to a source contact region via a source wiring and a resistor placed on a substrate different from the semiconductor body. The source wiring and the resistor may be connected in series between the source contact region and the source electrode in the second group. For example, the source wiring may be connected in parallel with an auxiliary source contact region. A first bonding wire may electrically connect an auxiliary source contact region above the semiconductor body to a first end of a resistor on the substrate. A second bonding wire may electrically connect an auxiliary source contact region on the semiconductor body to a second end of a resistor on the substrate.

[0041] Similar to the auxiliary electrodes in the trenches in the third group of trenches described in the above examples, and similar to the first portion of the source described in the above examples, a resistor placed on a substrate different from the semiconductor body can enable resistive coupling between the source electrode in the trenches in the second group of trenches and the source contact region. Such resistive coupling can enable suppression of turn-on voltage tailing and thus reduce turn-on losses.

[0042] Another example of a semiconductor device may include a plurality of trenches extending from a first main surface into a semiconductor body. The plurality of trenches may extend from the first main surface into the semiconductor body. A first group of trenches in the plurality of trenches may include a gate electrode. A second group of trenches in the plurality of trenches may include a source electrode. A mesa region may be laterally defined by a first trench in the first group of trenches and a second trench in the second group of trenches. The mesa region may include a source region. The source region may be electrically coupled to a source contact region, such as a first load terminal, via a first conductive path. A source electrode in a second group of trenches in the plurality of trenches may be electrically coupled to a source contact region, such as a first load terminal, via a second conductive path. A gate electrode in a first group of trenches in the plurality of trenches may be electrically coupled to a gate contact or gate terminal via a gate conductive path. The second conductive path may have a resistance at least five times or ten times higher than the gate conductive path. The second conductive path may have a resistance no more than one hundred times or no more than one thousand times higher than the gate conductive path. The gate conductive path may have a resistance at least one thousand times higher than the first conductive path.

[0043] For example, a fourth group of trenches in the plurality of trenches may include a second source electrode. The second source electrode in the fourth group of trenches in the plurality of trenches may be electrically coupled to a source contact region or a load terminal via a third conductive path. The third conductive path may have a resistance less than that of the gate conductive path.

[0044] Another example of a semiconductor device may be an IGBT including a semiconductor body electrically coupled to a first load terminal and electrically coupled to a second load terminal. The IGBT may include a drift region configured to conduct a load current between the first load terminal and the second load terminal. The drift region may have a first conductivity type. The IGBT may also include a gate trench having a gate trench electrode. The IGBT may also include a source trench having a source trench electrode electrically coupled to the first load terminal. The IGBT may also include a mesa region. The mesa region may include a source region of the first conductivity type electrically connected to the first load terminal. The source region may be arranged adjacent to the gate trench. The gate trench electrode may be configured to receive a control signal from the control terminal of the IGBT and control the load current in the mesa region. The source trench may be arranged on a side of the mesa region opposite to a side where the gate trench is located, for example, the mesa region may be laterally limited by the gate trench and the source trench. The source trench electrode may be electrically coupled to the first load terminal via a first resistance path. In the on-state of the IGBT, the IGBT may be configured to conduct a load current in a forward direction and the gate electrode is set to a first gate voltage, such as a gate on voltage. In the off-state of the IGBT, the IGBT is configured to block a load current in a forward direction and the gate electrode is set to a second gate voltage, such as a gate off voltage. In a switching state in which the IGBT switches from an off-state to an on-state during a switching time, the voltage of the source trench electrode may deviate from the voltage of the first load terminal by at least 30% of the gate voltage difference between the first gate voltage and the second gate voltage for at least 30% of the switching time.

[0045] The examples and features described above and below may be combined.

[0046] In the following, further examples of semiconductor devices are explained in conjunction with the figures. The functions and structural details described with respect to the above examples apply equally to the exemplary embodiments shown in the figures and described further below.

[0047] Figure 1A is a schematic plan view showing an example of the semiconductor device 100 . Figure 1B is along Figure 1A Schematic cross-sectional view of intersection line AA. Figure 1C is along Figure 1A Schematic cross-sectional view of intersection line BB.

[0048] Reference Figures 1A to 1E, the semiconductor device 100 includes a plurality of trenches 102 extending from a first main surface 106 into a semiconductor body 104. A first group of trenches 1021 of the plurality of trenches 102 includes a gate electrode 1081. A second group of trenches 1022 of the plurality of trenches 102 includes a source electrode 1082. A third group of trenches 1023 of the plurality of trenches 102 includes an auxiliary electrode 1083. Trench dielectrics 1091, 1092, 1093 electrically separate the electrodes 1081, 1082, 1083 from surrounding portions of the semiconductor body 104.

[0049] The source electrode 1082 is electrically coupled to the source contact region 110, for example, a first load terminal of the vertical power semiconductor device, via the source wiring 112 and the auxiliary electrode 1083. The source wiring 112 and the auxiliary electrode 1083 are electrically connected in series between the source contact region 110 and the source electrode 1082. In the figure, the contact 116 provides an electrical contact between the electrode in the region of the semiconductor body 104 or the trench 102 and the first wiring level (for example, the source wiring 112 or the source contact region 110). An intermediate dielectric 118 is arranged between the first wiring level and the semiconductor body 104.

[0050] Each mesa region 114 is defined by two adjacent trenches in the lateral direction x. Figures 1A to 1C For example, additional trenches may be arranged between the trenches 102 of the second group of trenches 1022 and the trenches 102 of the third group of trenches 1023 .

[0051] The trenches 102 in the first and second groups of trenches may be arranged adjacent to each other in a regular pattern as part of an active transistor cell within an active region.

[0052] As in Figure 1D As schematically shown in the cross-sectional view of , the mesa region 114 may be electrically connected to the source contact region 110 via a contact 116. For example, this enables electrical contact between the source contact region 110 and the active transistor cells (eg, source and body regions of the active transistor cells).

[0053] As in Figure 1E As schematically shown in the cross-sectional view of , the auxiliary electrode 1083 is electrically connected to the source contact region 110 via the contact portion 116 .

[0054] As in Figure 1F As schematically shown in the cross-sectional view of FIG. , the semiconductor device 100 may further include, for example Figure 1CA fourth group of trenches 1024 of the plurality of trenches 102 is shown between the trenches 102 of the second group of trenches 1022 and the trenches 102 of the third group of trenches 1023. The trenches 102 of the fourth group of trenches 1024 include second source electrodes 1084 and trench dielectrics 1094. In addition to the source electrodes 1082 of the second group of trenches 1022 of the trenches 122 of the source contact region 110 resistively coupled to the source electrodes 1084 through the auxiliary electrodes 1083 of the third group of trenches 1023 of the trenches 102 (see, for example, Figure 1A ), the second source electrode 1084 of the fourth group of trenches 1024 in the trenches 102 is electrically connected to the source contact region 110 through the contact portion 116 arranged between the source contact region 110 and the second source electrode 1084. In some examples, the trenches in the fourth group of trenches can be arranged between the trenches in the second group of trenches. For example, the trenches in the fourth group of trenches can be farther away from the trenches in the first group of trenches, such as the gate trenches, than the trenches in the second group of trenches.

[0055] The semiconductor device may further include additional trenches that do not belong to the first group of trenches, the second group of trenches, the third group of trenches, or the fourth group of trenches.

[0056] Various layouts of the trenches 102 may be implemented in an active region of the semiconductor device 100 , such as a transistor cell array.

[0057] For example, the mesa region 114 may be defined along the lateral direction x by one trench 102 in the first group of trenches 1021 of the plurality of trenches 102 and any one of the trenches 102 in the second group of trenches 1022 or the trenches 102 in the fourth group of trenches 1024. Likewise, the mesa region 114 may be defined along the lateral direction x by one trench 102 in the second group of trenches 1024 of the plurality of trenches 102 and any one of the trenches 102 in the third group of trenches 1023 or the trenches 102 in the fourth group of trenches 1024 or any of the additional trenches. Likewise, the mesa region 114 may be defined along the lateral direction x by one trench 102 in the third group of trenches 1023 of the plurality of trenches 102 and any one of the trenches 102 in the second group of trenches 1022 or the trenches 102 in the fourth group of trenches 1024. Similarly, the mesa region 114 may be defined along the lateral direction x by a trench 102 in the fourth group of trenches 1024 of the plurality of trenches 102 and any one of the trenches 102 in the first group of trenches 1021, the trenches 102 in the second group of trenches 1022, or the trenches 102 in the third group of trenches 1023. For example, in the mesa region, semiconductor regions such as source regions, body regions, body contact regions (in Figures 1A to 1F ), which is not shown in the figure, is used to form a transistor unit.

[0058] exist FIG. 2A to FIG. 2IAn exemplary layout is shown in the schematic top view of FIG.

[0059] exist FIG. 2A to FIG. 2C In the schematic top view of , the axial direction of the trench 102 is the transverse direction x. For the sake of clarity, only the auxiliary electrodes 1083 of some trenches 102 of the third group of trenches 1023 are shown. FIG. 2A to FIG. 2C Each of the exemplary semiconductor devices 100 includes a gate contact region 120 in a corner of a semiconductor body 104 or a chip. A gate wiring 122 surrounds the source contact region 110 and is connected to the gate contact region 120. The gate wiring 122 is connected to the source contact region 110 by contacting ( FIG. 2A to FIG. 2C The gate electrode 1081 of the first group of trenches 1021 in the trench 102 is electrically connected to the gate electrode 1081 of the first group of trenches 1021 in the trench 102. The source 1082 in the second group of trenches 1022 in the trench 102 is resistively coupled to the source contact region 110 through the source wiring 112 and the auxiliary electrode 1083 of the third group of trenches 1023 in the trench 102. The second source 1084 in the fourth group of trenches 1024 in the trench 102 can be directly electrically connected to the source contact region 110 through the contact therebetween. Figure 2B The semiconductor device 100 of the layout shown in FIG. 1 further includes a second source wiring 124 in parallel with the source contact region 110. The source wiring 112 is laterally arranged between the second source wiring 124 and the source contact region 110. The second source wiring 124 can support electrical shielding between the source wiring 112 and the gate contact region 120 / gate wiring 122. In addition, the second source wiring 124 can be electrically connected to at least some of the mesa regions 114 and / or to at least some of the second source electrodes 1084 of the trenches 102 in the fourth group of trenches 1024.

[0060] and Figure 2A Compared with the layout of Figure 2C The layout shown is beneficial in terms of area consumption of the source wiring 112 .

[0061] exist FIG. 2D to FIG. 2I In the schematic top view of FIG. 1 , the gate contact region 120 is arranged in the center of the edge of the chip or semiconductor body. Figure 2D to Figure 2G The schematic layout shown in FIG. 1 includes two source contact regions 110. For each source contact region 110, the source electrodes 1082 in the second set of trenches 1022 are electrically connected via portions of source wiring 112 arranged at opposite sides of the corresponding source contact region 110. Figure 2D Compared with the layout of Figure 2F The layout shown is beneficial for the area consumption of the source wiring 112. Figure 2E Compared with the layout of Figure 2G The layout shown is beneficial for the area consumption of the source wiring 112. Figure 2F Compared with the layout of Figure 2H The layout shown is beneficial for the area consumption of the source wiring 112. Figure 2G Compared with the layout of Fig.2I The layout shown is beneficial in terms of area consumption of the source wiring 112 .

[0062] exist Figure 3A , Figure 3B Schematic plan view and Figure 3C Another example of a semiconductor device 100 is shown in a schematic cross-sectional view of FIG.

[0063] Similar to the previous examples, the semiconductor device 100 includes a plurality of trenches 102 extending from the first main surface 106 into the semiconductor body 104 , wherein a first group 1021 of the plurality of trenches 102 includes a gate electrode 1081 and a second group 1022 of the plurality of trenches 102 includes a source electrode 1082 .

[0064] Source electrode 1082 is subdivided into at least first portion 1261 and second portion 1262. The conductance per unit length of first portion 1261 of source electrode 1082 along axial direction x is smaller than the conductance per unit length of second portion 1262 of source electrode 1082 along axial direction x.

[0065] The second portion 1262 of the source electrode 1082 is electrically coupled to the source contact region 110 via the first portion 1261. Figure 3A In the schematic diagram of FIG. 1 , the end schematically shows the source contact region 110 . For example, the first portion 1261 may be electrically connected to the source wiring 112 through the contact portion 116 , or may be directly connected to the source contact region 110 through the contact portion 116 .

[0066] The semiconductor device 100 further includes a mesa region 114 defined by the trenches 102 in the first set of trenches 1021 and the trenches 102 in the second set of trenches 1022. The mesa region 114 includes a source region 128 electrically connected to the source contact region 110.

[0067] Reference Figure 3B , at the first main surface 106, the width of the source electrode 1082 in the first portion 1261 is smaller than the width of the source electrode 1082 in the second portion 1262. This enables the conductance per unit length of the first portion 1261 of the source electrode 1082 along the axial direction x to be reduced compared to the second portion 1262.

[0068] Apart from Figure 3B Examples other than or as Figure 3B An alternative embodiment of the example of the source electrode 1082 is taken along the lateral direction x Figure 3CThe schematic cross-sectional view is an example of a semiconductor device having a smaller vertical extent of the source 1082 in the first portion 1261 than the vertical extent of the source 1082 in the second portion 1062 by forming the trenches 102 of the second group of trenches 1082 in the first portion 1261 shallower than the trenches 102 of the second group of trenches 1082 in the second portion 1262.

[0069] exist Figure 4 Another example of the semiconductor device 100 is shown in a schematic plan view of FIG.

[0070] Similar to the previous examples, the semiconductor device 100 includes a plurality of trenches 102 extending from the first main surface 106 into the semiconductor body 104 , wherein a first group 1021 of the plurality of trenches 102 includes a gate electrode 1081 and a second group 1022 of the plurality of trenches 102 includes a source electrode 1082 .

[0071] The source electrodes 1082 in the second set of trenches 1022 are electrically coupled to the source contact region 110 via source wiring 112 and a resistor 130 placed on a substrate 132 different from the semiconductor body 104. The source wiring 112 and the resistor are connected in series between the source contact region 110 and the source electrodes 1082 in the second set of trenches 1022. Bonding wires 1341, 1342 may provide electrical connections between the auxiliary source contact regions 136 in the wiring region above the semiconductor body 104 and the substrate 132. However, other interconnection technologies through silicon vias may be used, such as solder bonding.

[0072] Another example may include an additional connection pad, wherein the resistor is formed as a resistor wiring connected to the additional pad. The additional pad is electrically connected to the source contact region, for example, by a bonding wire. In this example, the resistor may be implemented as a source wiring.

[0073] Figure 5 The schematic cross-sectional view of shows a semiconductor device 100, such as an IGBT, having a mesa region 114 laterally defined by trenches 102 in a first set of trenches 1021 and trenches 102 in a second set of trenches 1022. The mesa region 114 includes an n+ doped source region 128 electrically connected to a source contact region 110 via a contact 116. The source region 128 adjoins a first trench dielectric 1091. The mesa region 114 also includes a p-doped body region 138 and a p+ doped body contact region 140 arranged between the body region 138 and the contact 116. The p+ doped body contact region 140 is intended to provide an ohmic contact between the body region 138 and the contact 116. The p+ doped body contact region 140 may be omitted in case the doping concentration of the body region 138 is high enough to ensure ohmic contact characteristics. Figure 5In the example shown, the contact is a trench contact 116 extending into the semiconductor body 104 and electrically connected to the body region 138 and electrically connected to the source region 128. As an alternative to the trench contact or in addition to the trench contact, a planar contact (not shown) can be formed. For example, the planar contact can be electrically connected to the source region 128 and electrically connected to the body region 138 or electrically connected to the body contact region 140 at the first main surface 104.

[0074] For example, the conductivity of the channel near the interface between the body region 138 and the trench dielectric 1091 may be controlled by a voltage applied to the gate electrode 1081 via the gate terminal G.

[0075] The source electrodes 1082 in the second group of trenches 1022 in the plurality of trenches may be electrically coupled to the source contact region 110, such as the first load terminal, via a first conductive path having a resistance R1. The gate electrodes 1081 in the first group of trenches in the plurality of trenches may be electrically coupled to the gate contact or gate terminal G via a second conductive path having a resistance R2. The resistance R2 may be at least five or ten times higher than the resistance R1, and may be no more than one hundred or one thousand times higher than the resistance R1.

[0076] The various aspects and features mentioned and described with one or more of the previously described examples and figures may also be combined with one or more of the other examples to replace the same features in the other examples or to additionally introduce features into the other examples.

[0077] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that various alternatives and / or equivalent implementations may be used to replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any changes or modifications to the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor device (100), comprising: A plurality of trenches (102) extending from a first main surface (106) into a semiconductor body (104), wherein A first group of trenches (1021) of the plurality of trenches (102) comprises a gate electrode (1081), a second group of trenches (1022) of the plurality of trenches (102) comprises a source electrode (1082), and a third group of trenches (1023) of the plurality of trenches (102) comprises an auxiliary electrode (1083); and The source electrode (1082) is electrically coupled to the source contact region (110) via the source wiring (112) and the auxiliary electrode (1083), and the source wiring (112) and the auxiliary electrode (1083) are electrically connected in series between the source contact region (110) and the source electrode (1082).

2. The semiconductor device (100) according to claim 1, wherein: The source wiring (112) and the source contact region (110) are separate parts of a patterned wiring layer.

3. The semiconductor device (100) according to any one of the preceding claims, wherein: The ratio of the number of grooves (102) in the second group of grooves (1022) to the number of grooves (102) in the third group of grooves (1023) is in the range of 100 to 100,000.

4. The semiconductor device (100) according to any one of claims 1 to 2, wherein: The source wiring (112) extends parallel to at least two sides of the source contact region (110).

5. The semiconductor device (100) according to any one of claims 1 to 2, wherein: The source wiring (112) laterally surrounds at least one quarter of the circumference of the source contact region (110).

6. The semiconductor device (100) according to any one of claims 1 to 2, further comprising a gate wiring (122), wherein: The source wiring (112) is arranged between the gate wiring (122) and the source contact region (110), and the gate wiring (122) extends parallel to at least two sides of the source wiring (112).

7. The semiconductor device (100) according to claim 6, Also included is a second source wiring (124), wherein: The second source wiring (124) is connected in parallel to the source contact region (110), and the source wiring (112) is arranged between the second source wiring (124) and the source contact region (110), and is completely or mainly laterally surrounded by the second source wiring (124) and the source contact region (110).

8. The semiconductor device (100) according to claim 7, further comprising a plurality of contacts (116) arranged between the second source wiring (124) and the first main surface (106), wherein: The plurality of contacts (116) electrically connect the plurality of mesa regions (114) to the second source wiring (124), and wherein each of the plurality of mesa regions (114) is laterally bounded by adjacent trenches of the plurality of trenches (102).

9. The semiconductor device (100) according to any one of claims 1 to 2, wherein: The auxiliary electrodes (1083) in the third group of grooves (1023) are connected in parallel between the source wiring (112) and the source contact area (110), and wherein the total resistance of the auxiliary electrodes (1083) connected in parallel is in the range of 50 to 500 times the ratio of the resistance between the gate electrode (1081) and the gate terminal multiplied by the sum of the axial extensions of all the grooves in the first group of grooves (1021) to the sum of the axial extensions of all the grooves in the second group of grooves (1022).

10. The semiconductor device (100) according to any one of claims 1 to 2, further comprising a mesa region (114) laterally defined by the trenches (102) in the first group of trenches (1021) and the trenches (102) in the second group of trenches (1022), wherein: The mesa region includes a source region (128).

11. The semiconductor device (100) according to any one of claims 1 to 2, wherein: The conductance per unit length of the auxiliary electrode (1083) along the axial direction of the plurality of grooves (102) is smaller than the conductance per unit length of the gate electrode (1081) along the axial direction of the plurality of grooves (102).

12. A semiconductor device (100), comprising: A plurality of trenches (102) extending from a first main surface (106) into a semiconductor body (104), wherein A first group of trenches (1021) of the plurality of trenches (102) comprises a gate electrode (1081), and a second group of trenches (1022) of the plurality of trenches (102) comprises a source electrode (1082), The source electrode (1082) is subdivided into at least a first portion (1261) and a second portion (1262), The conductance per unit length of the first portion (1261) of the source electrode (1082) in the axial direction is smaller than the conductance per unit length of the second portion (1262) of the source electrode (1082) in the axial direction, wherein the second portion (1262) is electrically coupled to the source contact region (110) via the first portion (1261), and further comprising A mesa region (114) defined by the trenches (102) in the first group of trenches (1021) and the trenches (102) in the second group of trenches (1022), wherein the mesa region (114) includes a source region (128) electrically connected to the source contact region (110).

13. The semiconductor device (100) according to claim 12, wherein: The width of the first portion of the source electrode (1082) along the axial direction is smaller than the width of the second portion of the source electrode (1082) along the axial direction.

14. The semiconductor device (100) according to any one of claims 12 to 13, wherein: The source electrode (1082) includes a semiconductor material, and a net doping concentration of the semiconductor material in the first portion (1261) is less than a net doping concentration of the semiconductor material in the second portion (1262).

15. The semiconductor device (100) according to any one of claims 12 to 13, wherein: The depth of the source electrode (1082) in the first portion (1261) is smaller than the depth of the source electrode (1082) in the second portion (1262).

16. The semiconductor device (100) according to any one of claims 12 to 13, wherein: At the first main surface (106), the width of the source electrode (1082) in the first portion (1261) is smaller than the width of the source electrode (1082) in the second portion (1262).

17. A semiconductor device (100), comprising: A plurality of trenches (102) extending from a first main surface (106) into a semiconductor body (104), wherein A first group of trenches (1021) of the plurality of trenches (102) comprises a gate electrode (1081), and a second group of trenches (1022) of the plurality of trenches (102) comprises a source electrode (1082), The source electrode (1082) in the second group of trenches (1022) is electrically coupled to the source contact region (110) via a source wiring (112) and a resistor (130) placed on a substrate (132) different from the semiconductor body (104), and the source wiring (112) and the resistor are connected in series between the source contact region (110) and the source electrode (1082) in the second group of trenches (1022).

18. The semiconductor device (100) according to claim 17, wherein: The source wiring (112) is incorporated into an auxiliary source contact region (136), and a first bonding wire (1341) electrically connects the auxiliary source contact region (136) on the semiconductor body (104) and a first end of the resistor (130) on the substrate (132).

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