High Electron Mobility Transistor

Abstract

The present invention discloses a high electron mobility transistor, comprising: a channel layer disposed on a substrate; a barrier layer disposed on the channel layer; a first compound semiconductor layer disposed on the barrier layer; and a second compound semiconductor layer disposed between the barrier layer and the first compound semiconductor layer. Wherein, the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of a metal dopant, the concentration distribution has a first peak in the first compound semiconductor layer, and the concentration distribution has a second peak in the second compound semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more particularly to a high electron mobility transistor. Background Art

[0002] In semiconductor technology, III-V semiconductor compounds can be used to form various integrated circuit devices, such as high-power field effect transistors, high-frequency transistors, or high electron mobility transistors (HEMTs). HEMT belongs to a type of transistor with a two-dimensional electron gas (2-DEG), and its 2-DEG is adjacent to the junction surface (i.e., the hetero-junction surface) between two materials with different energy gaps. Since HEMT does not use a doped region as the carrier channel of the transistor, but uses 2-DEG as the carrier channel of the transistor, HEMT has various attractive characteristics compared to the well-known metal-oxide-semiconductor field effect transistor (MOSFET), such as high electron mobility and the ability to transmit signals at high frequencies.

[0003] In order to switch the HEMT between the on-state and the off-state, a positive voltage or a negative voltage is usually applied to the gate of the HEMT. However, for existing HEMTs, due to the gate-lag effect, the threshold voltage (Vt) usually varies with the magnitude of the gate voltage. For example, the deviation degree (ΔVt) of the threshold voltage corresponding to the on-state and the off-state is usually different, which is not conducive to the rapid switching of the HEMT, thus affecting the performance of the semiconductor device. Summary of the Invention

[0004] In view of this, it is necessary to propose an improved high electron mobility transistor to improve the defects existing in the existing high electron mobility transistor.

[0005] According to an embodiment of the present invention, a high electron mobility transistor is provided, including: a channel layer disposed on a substrate; a barrier layer disposed on the channel layer; a first compound semiconductor layer disposed on the barrier layer; and a second compound semiconductor layer disposed between the barrier layer and the first compound semiconductor layer, wherein the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of a metal dopant, the concentration distribution has a first peak in the first compound semiconductor layer, and the concentration distribution has a second peak in the second compound semiconductor layer.

[0006] According to an embodiment of the present invention, since the second compound semiconductor layer is disposed between the first compound semiconductor layer and the barrier layer, by forming a peak in the concentration of metal dopants in the second compound semiconductor layer, the energy barrier between the highest valence band of the second compound semiconductor layer and the highest valence band (maximum Ev) of the barrier layer can be increased. Therefore, holes from the first compound semiconductor layer are less likely to be injected into the barrier layer, thus avoiding the generation of trapped charges in the barrier layer, thereby reducing the threshold voltage deviation of the high electron mobility transistor and avoiding the gate delay effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. is a cross-sectional schematic view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a second compound semiconductor layer;

[0008] Figure 2 FIG. is a graph showing the relationship between the dopant concentration and the depth in the semiconductor stack layer of the present invention;

[0009] Figure 3 FIG. is a graph showing the relationship between the threshold voltage deviation value and the gate voltage of Embodiment 1, Embodiment 2 and Comparative Example 1 of the present invention;

[0010] Figure 4 FIG. is a cross-sectional schematic view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a silicon capping layer;

[0011] Figure 5 FIG. is a cross-sectional schematic view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a second compound semiconductor layer and a P-type III-V capping layer;

[0012] Figure 6 FIG. is a cross-sectional schematic view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a second compound semiconductor layer and a P-type III-V barrier layer;

[0013] Figure 7 FIG. is a cross-sectional schematic view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a second compound semiconductor layer, a P-type III-V barrier layer and a P-type III-V capping layer.

[0014] DESCRIPTION OF REFERENCE NUMERALS:

[0015] 100-1, 100-2, 100-3, 100-4, 100-5 High electron mobility transistor

[0016] 102 Substrate

[0017] 104 Nitride layer

[0018] 106 First nitride layer

[0019] 108 Second nitride layer

[0020] 110 Superlattice layer

[0021] 112 First superlattice layer

[0022] 114 Second superlattice layer

[0023] 116 High-resistance layer

[0024] 118 III-V channel layer

[0025] 120 III-V barrier layer

[0026] 122 Second compound semiconductor layer

[0027] 124 First compound semiconductor layer

[0028] 126 Crystalline silicon compound semiconductor layer

[0029] 128 P-type III-V compound semiconductor layer

[0030] 130 Two-dimensional electron gas region

[0031] 132 Two-dimensional hole gas region

[0032] 134 P-type III-V barrier layer

[0033] 210, 212, 220, 222 Curves

[0034] ΔV1 First threshold voltage deviation

[0035] ΔV2 Second threshold voltage deviation

[0036] V g1 First gate voltage

[0037] V g2 Second gate voltage

[0038] D Drain

[0039] G Gate

[0040] S Source

[0041] P Concentration peak Detailed implementation manners

[0042] The present invention will be further described below in conjunction with the accompanying drawings and specific implementation manners.

[0043] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity in description, embodiments of specific components and arrangements are also described in the present invention. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description of "the first feature is formed on or above the second feature" hereinafter may mean that "the first feature is in direct contact with the second feature", or may mean that "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact.

[0044] In addition, for the descriptive terms related to space mentioned in the present invention, such as: "under", "low", "below", "above", "on", "beneath", "top", "bottom" and other similar terms, for the convenience of description, their usages are all to describe the relative relationship between one element or feature and another (or multiple) element or feature in the drawings. Except for the orientation shown in the drawings, these space-related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device changes (rotating 90 degrees or other orientations), the space-related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0045] Although the present invention uses terms such as first, second, third, etc. to describe various elements, components, regions, layers and / or sections, it should be understood that these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section, and they do not represent any previous ordinal number of the element itself, nor the arrangement order of one element and another element or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer or section discussed below may also be referred to as the second element, component, region, layer or section.

[0046] The terms "about" or "substantially" and other similar terms mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "about" or "substantially", the meaning of "about" or "substantially" may still be implied.

[0047] In the present invention, the "group III-V semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. Among them, the group III element can be boron (B), aluminum (Al), gallium (Ga), or indium (In), and the group V element can be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, the "group III-V semiconductor" can include: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), its analogs, or combinations of the above compounds, but not limited thereto. In addition, depending on the requirements, dopants may also be included in the group III-V semiconductor to form a group III-V semiconductor with a specific conductivity type, such as an N-type or P-type III-V semiconductor.

[0048] The present invention relates to a high-voltage semiconductor device or a high electron mobility transistor (HEMT), such as a power switching transistor that can be used as a voltage converter or for high-power telecommunications applications, but the present invention is not limited thereto. Compared with silicon power transistors, due to the wider bandgap of III-V HEMTs, they have the characteristics of low on-state resistance (R ON ) and low switching losses.

[0049] Figure 1 is a schematic cross-sectional view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, where the semiconductor stack layer at least includes a P-type group III-V intermediate layer. As Figure 1 shown, the high electron mobility transistor 100-1 includes a substrate 102, a semiconductor stack layer (such as at least including a group III-V channel layer 118, a group III-V barrier layer 120, a P-type group III-V intermediate layer 122, a first compound semiconductor layer 124), a source S, a drain D, and a gate G. Other layers, such as a nitride layer 104, a superlattice layer 110, and a high-resistance layer 116, can be selectively provided between the substrate 102 and the semiconductor stack layer.

[0050] According to an embodiment of the present invention, the substrate 102 may be a ceramic substrate such as silicon carbide (SiC), aluminum oxide (Al2O3), sapphire, aluminum nitride, etc. In one embodiment, a bonding layer may be provided on the surface of the substrate 102, and the bonding layer material may include, for example, silicon. According to an embodiment of the present invention, the substrate 102 further includes a core layer and a single or multiple layers of insulating material layers and / or other suitable material layers covering the core layer. The core layer may be aluminum nitride or aluminum oxide, and the insulating material layer may be an oxide, nitride, oxynitride, or other suitable insulating material.

[0051] The nitride layer 104 may be selectively provided on the substrate 102, which has fewer lattice defects, so as to improve the epitaxial quality of the semiconductor stack layer provided on the nitride layer 104. Among them, the nitride layer 104 may include a nitride stack layer, for example, including a first nitride layer 106 and a second nitride layer 108. According to an embodiment of the present invention, the first nitride layer 106 may be, for example, a low-temperature aluminum nitride layer (LT-AlN), and this low-temperature aluminum nitride layer may be formed by metal-organic chemical vapor deposition (MOCVD) at an ambient temperature of 800°C - 1100°C; the second nitride layer 108 may be, for example, a high-temperature aluminum nitride layer (HT-AlN), and this high-temperature aluminum nitride layer may be formed by metal-organic chemical vapor deposition at an ambient temperature of 1100°C - 1400°C, but it is not limited thereto.

[0052] The superlattice layer (SL) 110 may be selectively provided on the substrate 102, for example, provided on the nitride layer 104. The superlattice layer 110 can be used to reduce the degree of lattice mismatch between the substrate 102 and the semiconductor layer provided on the superlattice layer 110, and reduce the stress generated by the lattice mismatch. According to an embodiment of the present invention, the superlattice layer 110 may be a superlattice stack layer, for example, including a first superlattice layer 112 and a second superlattice layer 114. According to different requirements, the first superlattice layer 112 or the second superlattice layer 114 may each be a periodic alternating layer structure composed of at least two III-V (group III-V) compound semiconductors, such as a structure formed by alternately stacking AlN thin layers / GaN thin layers, or each may be a III-V compound semiconductor with a gradually changing composition ratio, such as aluminum gallium nitride (Al x Ga 1-x N, 0.15 ≦ x ≦ 0.9), but it is not limited thereto.

[0053] The high-resistance layer 116 can be selectively disposed on the substrate 102, for example, on the superlattice layer 110. The high-resistance layer 116 has a higher resistivity compared to other layers, thus avoiding leakage current between the semiconductor layer disposed on the high-resistance layer 116 and the substrate 102. According to an embodiment of the present invention, the high-resistance layer 116 can be a doped III-V semiconductor layer, such as carbon-doped gallium nitride (c-GaN), but is not limited thereto.

[0054] The channel layer (i.e., the III-V channel layer described in the following text) 118 can be disposed on the substrate 102, for example, on the high-resistance layer 116. The III-V channel layer 118 can include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layer can be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. According to an embodiment of the present invention, the III-V channel layer 118 is an undoped III-V semiconductor, such as undoped GaN (u-GaN). According to other embodiments of the present invention, the III-V channel layer 118 can also be one or more doped III-V semiconductor layers, such as a P-type III-V semiconductor layer. For the P-type III-V semiconductor layer, the dopant can be Cd, Fe, Mg, or Zn, but is not limited thereto.

[0055] The barrier layer (i.e., the III-V barrier layer described in the following text) 120 can be disposed on the III-V channel layer 118. The III-V barrier layer 120 can include one or more III-V semiconductor layers, and its composition will be different from that of the III-V semiconductor of the III-V main layer 104. For example, the III-V barrier layer 120 can include AlN, Al y Ga (1-y) N (0 < y < 1) or a combination thereof. According to an embodiment, the III-V barrier layer 120 can be an N-type III-V semiconductor, such as an essentially N-type AlGaN layer, but is not limited thereto.

[0056] Due to the discontinuous energy gap between the III-V channel layer 118 and the III-V barrier layer 120, by stacking the III-V channel layer 118 and the III-V barrier layer 120 on top of each other, electrons will accumulate in the III-V channel layer 118 due to the piezoelectric effect and near the heterointerface between the III-V channel layer 118 and the III-V barrier layer 120. This accumulated electrons can form a thin layer with a high carrier mobility, that is, a two-dimensional electron gas (2-DEG) region 130.

[0057] The first compound semiconductor layer 124 may be disposed on the III-V barrier layer 120 to deplete the two-dimensional electron gas (2-DEG) region 130, achieving a normally-off state of the semiconductor device. The first compound semiconductor layer 124 may be a p-type III-V semiconductor, such as a p-type GaN layer, but is not limited thereto. In addition, the energy gap of the first compound semiconductor layer 124 may be smaller than that of the III-V barrier layer 120, such that a discontinuous energy gap may exist between the first compound semiconductor layer 124 and the III-V barrier layer 120.

[0058] The p-type III-V intermediate layer 122 may be disposed between the III-V barrier layer 120 and the first compound semiconductor layer 124, and the thickness of the p-type III-V intermediate layer 122 is simultaneously thinner than the thickness of the III-V barrier layer 120 and the thickness of the first compound semiconductor layer 124. For example, the thickness of the p-type III-V intermediate layer 122 may be 20 nm, while the thicknesses of the III-V barrier layer 120 and the first compound semiconductor layer 124 may be 50 nm and 35 nm respectively, but are not limited thereto. According to an embodiment of the present invention, the p-type III-V intermediate layer 122 is a p-type III-V semiconductor, such as a p-type GaN layer, and the dopant may be a metal dopant selected from Mg, Cd, or Zn. According to an embodiment of the present invention, the peak dopant concentration range of the p-type III-V intermediate layer 122 is from 9E18 cm -3 to 2E19 cm -3 , and is lower than the peak dopant concentration range of the first compound semiconductor layer 124 (for example, from 1E19 cm -3 to 1E20 cm -3 ).

[0059] Due to the discontinuous energy gap between the p-type III-V intermediate layer 122 and the III-V barrier layer 120, by stacking the p-type III-V intermediate layer 122 and the III-V barrier layer 120 on each other, holes will accumulate in the p-type III-V intermediate layer 122 due to the piezoelectric effect and near the heterointerface between the p-type III-V intermediate layer 122 and the III-V barrier layer 120. This accumulated holes can form a thin layer with a high carrier mobility, that is, a two dimensional hole gas (2-DHG) region 132.

[0060] The source electrode S and the drain electrode D may be electrically connected to the III-V channel layer 118 respectively, and the gate electrode G may be electrically connected to the first compound semiconductor layer 124. Among them, the source electrode S and the drain electrode D may form an ohmic contact with the III-V channel layer 118, and the gate electrode G may form a Schottky contact with the first compound semiconductor layer 124, but is not limited thereto.

[0061] To analyze the concentration distribution in the semiconductor stack layer, secondary ion mass spectroscopy (SIMS) can be used to analyze Figure 1 the relationship between the metal component concentration and the depth of the semiconductor stack layer shown in Figure 2 . Figure 2 is a graph showing the relationship between the dopant concentration and the depth in the semiconductor stack layer according to an embodiment of the present invention. As Figure 2 shown, curve 210 and curve 212 are the concentration distributions of Mg and Al corresponding to different depths in the semiconductor stack layer of an embodiment of the present invention, respectively, and curve 220 and curve 222 are the concentration distributions of Mg and Al corresponding to different depths in the semiconductor stack layer of Comparative Example 1 (without the second compound semiconductor layer 122), respectively. Among them, Figure 2 in the depth range of 0 - 70 nm roughly corresponds to Figure 1 the first compound semiconductor layer 124, the depth range of 70 - 85 nm roughly corresponds to Figure 1 the second compound semiconductor layer 122, the depth range of 85 - 120 nm roughly corresponds to Figure 1 the group III - V barrier layer 120, and the depth range of 120 - 140 nm roughly corresponds to Figure 1 the group III - V channel layer 118. For curve 210, there is a concentration peak P in the depth range of 70 - 85 nm (i.e., corresponding to the second compound semiconductor layer). The full width at half maximum (FWHM) of this concentration peak P is approximately 5 nm to 15 nm, and the highest concentration (or peak concentration) is approximately up to 1.5E19 cm -3 ; while in the depth range of 0 - 70 nm (i.e., corresponding to the first compound semiconductor layer), the highest concentration is approximately 5E19 cm -3 (corresponding to the depth range of 2 - 5 nm), and the lowest concentration is approximately 7E18 cm -3 (corresponding to the depth of 70 nm). In contrast, there is no concentration peak in the Mg concentration of curve 220 in the depth range of 40 - 100 nm. It should be noted that Figure 2 the concentration distribution of the metal dopant shown is preferably measured using secondary ion mass spectroscopy or a detection device with higher resolution. If measured using a detection device with poor resolution, the concentration peak of the second compound semiconductor layer may not be measured.

[0062] To determine the influence of the second compound semiconductor layer on the gate delay effect in a high electron mobility transistor, the threshold voltage deviation under different gate stress voltages can be further analyzed. The measurement results are shown in Figure 3 . Figure 3Shows the relationship diagram between the threshold voltage deviation value and the gate voltage of Embodiments 1 and 2 of the present invention and Comparative Examples 1 and 2. Please refer to Figure 1 、 Figure 3 and Figure 4 as well. Among them, Figure 3 The structure of Embodiment 1 in Figure 1 is similar to the structure shown in Figure 3 The structure of Embodiment 2 in Figure 4 is similar to the structure shown in Figure 4 The main difference between the structure shown in Figure 1 and Figure 3 is that the semiconductor stack layer does not include the second compound semiconductor layer 122, but includes a crystalline silicon compound semiconductor layer 126 disposed on the first compound semiconductor layer 124;

[0063] As Figure 3 shown, when the gate voltages are the first gate voltage V g1 and the second gate voltage V g2 respectively, for example, corresponding to -6V and 6V respectively, the high electron mobility transistor can correspond to the cut-off state and the on-state respectively. For Embodiment 1, when the gate voltages are the first gate voltage V g1 and the second gate voltage V g2 respectively, the corresponding threshold voltage deviation values are approximately equal, and are between the first threshold voltage deviation value ΔV1 and the second threshold voltage deviation value ΔV2, indicating that the high electron mobility transistor of Embodiment 1 does not have an obvious gate delay effect. For Embodiment 2, when the gate voltage is the second gate voltage V g2 the corresponding threshold voltage deviation value will be slightly lower than the first threshold voltage deviation value ΔV1, rather than between the first threshold voltage deviation value ΔV1 and the second threshold voltage deviation value ΔV2, indicating that the high electron mobility transistor of Embodiment 2 has a gate delay effect in the on-state. In contrast, for Comparative Example 1, when the gate voltage is the first gate voltage V g1 the corresponding threshold voltage deviation value is much larger than the first threshold voltage deviation value ΔV1. Therefore, the gate delay effect of Comparative Example 1 is more significant than that of Embodiments 1 and 2.

[0064] Those with ordinary knowledge in the technical field should easily understand that, in order to meet the requirements of actual products, there may be other aspects of the high electron mobility transistor of the present invention, and it is not limited to the foregoing. The following will further describe other embodiments or variations of the high electron mobility transistor. And for the sake of simplicity, the following description mainly details the differences of each embodiment, and will not repeat the same parts. In addition, various embodiments in the present invention may use repeated reference symbols and / or markings. The use of these repeated reference symbols and markings is to make the description more concise and clear, rather than to indicate the relevance between different embodiments and / or configurations.

[0065] Figure 4 is a schematic cross-sectional view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a silicon compound semiconductor layer. As Figure 4 shown, Figure 4 the structure 100-2 shown is similar to Figure 1 the structure 100-1 shown, and the main difference is that Figure 4 there is no second compound semiconductor layer 122 between the ternary quaternary barrier layer 120 and the first compound semiconductor layer 124, but the compound semiconductor layer is disposed on the first compound semiconductor layer 124. According to an embodiment of the present invention, the compound semiconductor layer may be a crystalline silicon compound semiconductor layer 126. Since there is an energy gap discontinuity between the crystalline silicon compound semiconductor layer 126 and the first compound semiconductor layer 124, holes can be more easily transferred from the gate to the first compound semiconductor layer 124.

[0066] Figure 5 is a schematic cross-sectional view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a second compound semiconductor layer and a P-type ternary quaternary capping layer. As Figure 5 shown, Figure 5 the structure 100-3 shown is similar to Figure 1 the structure 100-1 shown, and the main difference is that Figure 5 between the ternary quaternary barrier layer 120 and the first compound semiconductor layer 124, in addition to including the second compound semiconductor layer 122, there is also a P-type III-V compound semiconductor layer 128 disposed on the first compound semiconductor layer 124. According to an embodiment of the present invention, the P-type ternary quaternary compound semiconductor layer 128 may be highly doped P + type GaN, which can be used to promote hole injection. Among them, the P-type ternary quaternary compound semiconductor layer 128 and the first compound semiconductor layer 124 may include the same metal dopant, such as Mg, and the doping concentration of the P-type ternary quaternary compound semiconductor layer 128 is higher than that of the first compound semiconductor layer 124.

[0067] Figure 6 is a cross-sectional schematic view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a second compound semiconductor layer and a P-type group III-V barrier layer. As Figure 6 shown, Figure 6 the structure 100-4 shown is similar to Figure 1 the structure 100-1 shown. The main difference is that Figure 6 between the group III-V barrier layer 120 and the first compound semiconductor layer 124 of - in addition to including the second compound semiconductor layer 122, it also includes a P-type group III-V barrier layer 134 disposed between the group III-V barrier layer 120 and the second compound semiconductor layer 122. According to an embodiment of the present invention, the P-type group III-V barrier layer 134 can be a P

[0068] Figure 7 is a cross-sectional schematic view of a semiconductor stack layer of a high-voltage semiconductor device according to an embodiment of the present invention, wherein the semiconductor stack layer at least includes a second compound semiconductor layer, a P-type group III-V barrier layer, and a P-type group III-V cap layer. As Figure 7 shown, Figure 7 the structure 100-5 shown is similar to Figure 1 the structure 100-1 shown. The main difference is that Figure 7 between the group III-V barrier layer 120 and the first compound semiconductor layer 124 of

[0069] According to the above embodiments, since the second compound semiconductor layer is disposed between the first compound semiconductor layer and the group III-V barrier layer, by forming a peak in the concentration of metal dopants in the second compound semiconductor layer, the energy barrier between the highest valence band of the second compound semiconductor layer and the highest valence band of the barrier layer can be increased. Therefore, holes from the first compound semiconductor layer are not easily injected into the barrier layer, thereby avoiding the generation of trapped charges in the group III-V barrier layer, and further reducing the threshold voltage deviation of the high electron mobility transistor. Therefore, the gate delay effect can be avoided, which is beneficial to the fast switching of the high electron mobility transistor.

[0070] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several equivalent substitutions or obvious variations can be made, and if the performance or use is the same, they should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A high electron mobility transistor, characterized in that, Comprising: A channel layer disposed on a substrate; A barrier layer disposed on the channel layer; A first compound semiconductor layer, which is a P-type semiconductor layer, disposed on the barrier layer; And, A second compound semiconductor layer, which is a P-type semiconductor layer, disposed between the barrier layer and the first compound semiconductor layer, wherein the first compound semiconductor layer includes a first concentration distribution of a metal dopant, and the second compound semiconductor layer includes a second concentration distribution of the metal dopant, the first concentration distribution has a first peak in the first compound semiconductor layer, and the second concentration distribution has a second peak in the second compound semiconductor layer.

2. The high electron mobility transistor according to claim 1, wherein: The metal dopant is magnesium, cadmium, carbon or zinc.

3. The high electron mobility transistor according to claim 1, characterized in that: The concentration of the metal dopant in the first compound semiconductor layer is greater than the concentration of the metal dopant in the second compound semiconductor layer.

4. The high electron mobility transistor according to claim 1, wherein: The concentration range of the first peak is 1E19 cm -3 to 1E20 cm -3 , and the concentration range of the second peak is 9E18 cm -3 to 2E19 cm -3 .

5. The high electron mobility transistor according to claim 1, characterized in that: The full width at half maximum of the second peak is 5 nm to 15 nm.

6. The high electron mobility transistor according to claim 1, wherein: The channel layer is an undoped III-V channel layer.

7. The high electron mobility transistor according to claim 1, characterized in that: A two-dimensional electron gas region can be formed in the channel layer, and the two-dimensional electron gas region is adjacent to the interface between the channel layer and the barrier layer.

8. The high electron mobility transistor as claimed in claim 1, wherein: The thickness of the second compound semiconductor layer is simultaneously less than the thickness of the barrier layer and the thickness of the first compound semiconductor layer.

9. The high electron mobility transistor according to claim 1, wherein: A two-dimensional hole gas region can be formed in the second compound semiconductor layer, and the two-dimensional hole gas region is adjacent to the interface between the barrier layer and the second compound semiconductor layer.

10. The high electron mobility transistor according to claim 1, characterized in that: Further comprising a semiconductor cap layer disposed on the second compound semiconductor layer.

11. The high electron mobility transistor according to claim 10, characterized in that: The semiconductor cap layer is a crystalline silicon cap layer.

12. The high electron mobility transistor according to claim 10, wherein: The semiconductor cap layer is a P-type cap layer, wherein the P-type cap layer and the first compound semiconductor layer include the metal dopant, and the doping concentration of the P-type cap layer is higher than the doping concentration of the first compound semiconductor layer.

13. The high electron mobility transistor according to claim 1, characterized in that: Further comprising a P-type barrier layer disposed between the barrier layer and the second compound semiconductor layer, and the P-type barrier layer includes the metal dopant.

14. The high electron mobility transistor according to claim 13, wherein: The doping concentration of the metal dopant in the P-type barrier layer is lower than the doping concentration of the metal dopant in the second compound semiconductor layer.

15. The high electron mobility transistor according to claim 1, wherein: The gate of the high electron mobility transistor is electrically connected to the first compound semiconductor layer, and the source and drain of the high electron mobility transistor are respectively electrically connected to the channel layer.

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