Neural network circuits that provide early integration before analog-to-digital conversion

Abstract

A neural network circuit is described that provides early integration before an ADC. A comparator is adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a bit vector indicating whether the plurality of analog voltages exceed the predetermined threshold, and transmit the bit vector via the network. At least one ADC is configured to convert the plurality of analog voltages into a vector of digital values, and transmit the vector of digital values ​​via the network. At least one modulator is configured to receive the bit vector from the network, provide a pulse to each of a plurality of input lines of a second synaptic array based on the bit vector, receive the digital value vector from the network, and provide a pulse to each of the plurality of input lines based on the digital value vector.

Description

Background Art

[0001] Embodiments of the present invention relate to neural network circuits and, more particularly, to circuits adapted to provide early integration prior to analog-to-digital conversion. Summary of the invention

[0002] According to an embodiment of the present invention, a neural network circuit is provided. A first synapse array is configured to output a plurality of analog voltages. A second synapse array has a plurality of input lines. A network is operably coupled to the first synapse array and the second synapse array. At least one comparator is operably coupled to the first synapse array. The at least one comparator is adapted to compare the plurality of analog voltages with a predetermined threshold to generate a bit vector, each bit of the bit vector indicating whether one of the plurality of analog voltages exceeds the predetermined threshold, and the bit vector is transmitted via the network. At least one analog-to-digital converter is operably coupled to the first synapse array and the network. At least one analog-to-digital converter is configured to convert the plurality of analog voltages into a digital value vector, and the digital value vector is transmitted via the network. At least one modulator is operably coupled to the second synapse array and the network. The at least one modulator is configured to receive the bit vector from the network, process the bit vector, the processing the bit vector comprising providing a pulse to each of the plurality of input lines of the second synapse array when a corresponding bit of the bit vector indicates that the predetermined threshold value is exceeded, receive the digital value vector from the network, and process the digital value vector comprising providing a pulse to each of the plurality of input lines of the second synapse array, each pulse having a duration proportional to a corresponding digital value of the digital value vector. Receiving the bit vector and / or processing the bit vector occurs in parallel with converting the plurality of analog voltages and / or transmitting the digital value vector.

[0003] According to an embodiment of the present invention, a method and a computer program product for operating a neural network circuit are provided. A plurality of analog voltages output from a first synaptic array are compared to a predetermined threshold to generate a bit vector. Each bit of the bit vector indicates whether one of the plurality of analog voltages exceeds the predetermined threshold. The bit vector is processed. Processing the bit vector includes providing a pulse to each of a plurality of input lines of a second synaptic array when a corresponding bit of the bit vector indicates that the predetermined threshold is exceeded. In parallel with said processing of the bit vector, the plurality of analog voltages are converted into a digital value vector. After said processing of the bit vector, a pulse is provided to each of a plurality of input lines of the second synaptic array, each pulse having a duration proportional to a corresponding digital value of the digital value vector. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1An exemplary non-volatile memory based crossbar array or crossbar memory according to an embodiment of the present invention is shown.

[0005] Figure 2 Exemplary synapses within a neural network are shown in accordance with an embodiment of the present invention.

[0006] Figure 3 An exemplary neural core array according to an embodiment of the present invention is shown.

[0007] Figure 4 An exemplary neural network according to an embodiment of the present invention is shown.

[0008] Figure 5 An exemplary multi-core neural network according to an embodiment of the present invention is shown.

[0009] Fig. 6A - B is a timeline showing integration according to an embodiment of the present invention.

[0010] Figure 7 A method of operating a neural network according to an embodiment of the present invention is shown.

[0011] Figure 8 A computing node according to an embodiment of the invention is described. DETAILED DESCRIPTION

[0012] Artificial neural networks (ANNs) are distributed computing systems that consist of multiple neurons interconnected by connection points called synapses. Each synapse encodes the strength of the connection between the output of one neuron and the input of another neuron. The output of each neuron is determined by the collective input received from other neurons connected to it. Therefore, the output of a given neuron is based on the output of the connected neurons from the previous layer and the strength of the connection determined by the synaptic weights. ANNs are trained to solve specific problems (e.g., pattern recognition) by adjusting the weights of the synapses so that a specific class of inputs produces the desired output.

[0013] ANNs can be implemented on a variety of hardware, including crossbar arrays, also known as crosspoint arrays or crosswire arrays. A basic crossbar array configuration includes a set of conductive row lines and a set of conductive column lines formed to cross the set of conductive row lines. The intersection between the two sets of wires is separated by a crosspoint device. The crosspoint device serves as the ANN weighted connection between neurons.

[0014] In various embodiments, a crossbar array or crossbar memory based on non-volatile memory is provided. A plurality of junctions are formed by crossing row lines with column lines. At each junction located between one of the row lines and one of the column lines coupled, a resistive memory element, such as a non-volatile memory, is connected in series with a selector. The selector may be a volatile switch or a transistor, various types of which are known in the art. It will be appreciated that various resistive memory elements are suitable for use as described herein, including memristors, phase change memories, conductive bridge RAMs, and spin transfer torque RAMs.

[0015] A fixed number of synapses may be provided on a core, and then multiple cores may be connected to provide a complete neural network. In such an embodiment, interconnectivity between cores is provided to communicate the output of a neuron on one core to another core, for example via a packet-switched or circuit-switched network. In a packet-switched network, greater flexibility of interconnection may be achieved at the expense of power and speed due to the need to transmit, read, and act on address bits. In a circuit-switched network, address bits are not required, so flexibility and reconfigurability must be achieved by other means.

[0016] In various exemplary networks, multiple cores are arranged in an array on a chip. In such embodiments, the relative positions of the cores can be referred to by cardinal directions (right, south, east, west). The data carried by the neural signals can be encoded in the pulse duration carried by each wire using digital voltage levels suitable for buffering or other forms of digital signal recovery.

[0017] One approach to routing is to provide an analog-to-digital converter at the output edge of each core, paired with an on-chip digital network for quickly routing packets to any other core, and a digital-to-analog converter at the input edge of each core.

[0018] In various computing applications including implementations of deep neural networks (DNNs) using analog resistive memory elements, it is often necessary to perform analog-to-digital conversion (ADC) at the bottom edge of one array before transferring data to the edge of the next array, where the data will be used to drive pulse modulated data. In such implementations, the large size of each ADC results in the need to time-multiplex the use of shared ADC resources. This then significantly prolongs the total operating time required to complete the final time-multiplexed use of each shared ADC. Due to the low area efficiency of the ADC circuit, a large amount of time is required to perform ADC operations using shared ADC resources, transfer data, prepare new data to modulate input pulses at the next array, and wait for the longest possible pulse to complete at the next array.

[0019] There remains a need in the art for a method of performing pulse modulation integration faster in a subsequent array. Therefore, various embodiments of the present invention provide for transmitting the most significant bit (MSB) for early integration before the ADC (analog-to-digital conversion) for neural network calculations.

[0020] refer to Figure 1 , an exemplary non-volatile memory-based crossbar array or crossbar memory is shown. A plurality of junctions 101 are formed by the intersection of row lines 102 and column lines 103. At each of the junctions 101 coupled between one of the row lines 102 and one of the column lines 103, a resistive memory element 104 (e.g., non-volatile memory) is connected in series with a selector 105. The selector may be a volatile switch or a transistor, various types of which are known in the art.

[0021] It will be appreciated that a variety of resistive memory elements are suitable for use as described herein, including memristors, phase change memories, conductive bridge RAM, spin-transfer torque RAM.

[0022] refer to Figure 2 , shows an exemplary synapse in a neural network. Multiple inputs x1...x from node 201 n With the corresponding weight w ij Multiply. The sum of the weights ∑x i w 2j Provided to the function f(·) at node 202 to obtain the value It will be appreciated that a neural network will include multiple such connections between layers and that this is merely exemplary.

[0023] Reference now Figure 3 , shows an exemplary neural core array according to an embodiment of the present invention. Array 300 includes a plurality of cores 301. The cores in array 300 are interconnected by lines 302, as further described below. In this example, the array is two-dimensional. However, it should be understood that the present invention can be applied to cores of one-dimensional or three-dimensional arrays. Core 301 includes a non-volatile memory array 311 that implements synapses as described above. Core 301 includes a west side and a south side, each of which can be used as an input and the other as an output. It should be understood that the west / south nomenclature is used merely for ease of reference to relative positioning and is not intended to limit the direction of input and output.

[0024] In various exemplary embodiments, the west side includes support circuits 312 dedicated to the entire side of core 301, shared circuits 313 dedicated to a subset of rows, and per-row circuits 314 dedicated to a single row. In various embodiments, the south side also includes support circuits 315 dedicated to the entire side of core 301, shared circuits 316 dedicated to a subset of columns, and per-column circuits 317 dedicated to a single column.

[0025] refer to Figure 4 , shows an exemplary neural network. In this example, a plurality of input nodes 401 are interconnected with a plurality of intermediate nodes 402. The intermediate nodes 402 are in turn interconnected with output nodes 403. It should be understood that this simple feedforward network is only for illustrative purposes, and the application of the present invention is not related to a specific neural network scheme.

[0026] refer to Figure 5 , shows an exemplary multi-core neural network. In this example, two cores are depicted, which may be implemented as described above. Input row 501 (e.g., which may correspond to input node 401) passes through crossbar switch array 510 to provide an output voltage (given as V N =∑x i w ij ). Applying the transfer function produces an activation y, which is provided to one of the input rows 504. In this example, y = f(V N ), where f is an arbitrary transfer function. Regardless of the transfer function chosen, a comparator is required at the analog voltage that causes exactly half of the total integration time as shown by threshold 503.

[0027] In an embodiment of the present invention, within a given neural network, a single bit for each neuron is transferred from a first synaptic array (e.g., crossbar 510) to the next synaptic array (e.g., crossbar 520). If the bit is 1 (high), a pulse of half the maximum duration is immediately modulated onto the next array. This integration can occur at the next array in parallel with the process of performing a precise ADC operation, transferring the N bits for each neuron from one array to the next, and performing any necessary squeezing operations.

[0028] In various embodiments, the analog comparator threshold used to calculate the MSB of the original transmission is designed so that the level corresponds exactly to the transition between just below and just above half of the maximum resulting modulated pulse. This idea is thus independent of any squeezing function applied to the N bits of data. When the N bits of data for each neuron are finally transmitted and squeezed, the second array only needs to apply the N-1 lowest bits to modulate the pulse. The same exact total pulse modulation duration is applied to the second array, but through the early and efficient transmission of the MSB information, an overall saving of approximately half of the maximum duration has been achieved.

[0029] Referring to FIG6 , a timeline for integration according to an embodiment of the present invention is provided. Fig. 6A and 6B In the example, the timeline runs from T = 0 to T = t. At T = 0, any previous integration ends, leaving a charge on the capacitor and a final value V N Get ready for ADC conversion.

[0030] Fig. 6A Operation of a set of shared ADC resources without early integration is shown. At 601, the first ADC conversion of N bits / column is performed by the source core. At 602, the result is transmitted and / or squeezed to the subsequent core. At this stage, the transmitted values ​​total to N bits / ready columns. At 603, these first received N bits / columns are prepared for integration at the destination core. Then, at 604, integration of the first available stimulus begins. When all columns are ready, the process is repeated for them. Thus, the last ADC conversion occurs at 605. At 606, these last bits are transmitted and / or squeezed. At 607, the associated received bits are prepared at the destination core, allowing integration of the last stimulus at 608. Integration of all received stimuli is completed at T=t.

[0031] Figure 6BThe operation of a set of shared ADC resources with early integration according to an embodiment of the present invention is shown. Here, the most significant bit is measured at 611, and then the most significant bit is transmitted for each column at 612. Then, at 613, the integration of the first half of all stimuli can be performed on the destination core. In parallel with the integration at the destination core, the first ADC conversion of N bits / column is performed by the source core at 614. At 615, the result is transmitted and / or squeezed to the destination core. At this stage, the transmitted values ​​total to N bits / ready columns. At 616, the received N bits / column are prepared at the destination core. Then, at 617, integration of the first available stimulus outside the most significant bit can be started. When all columns are ready, the process is repeated for them. Therefore, the final ADC conversion occurs at 618. At 619, the resulting bits are transmitted and / or squeezed. At 620, the received bits are prepared at the destination core, allowing integration of the final stimulus at 621. The early integration of the most significant bits (at 613) allows the remaining integrations (at 617 and 621) to be completed before T=t. The total time savings is shown at 622.

[0032] refer to Figure 7 , a method for operating a neural network according to an embodiment of the present invention is shown. At 701, a plurality of analog voltages output from a first synaptic array are compared with a predetermined threshold value to generate a bit vector. Each bit of the bit vector indicates whether one of the plurality of analog voltages exceeds the predetermined threshold value. At 702, the bit vector is processed. Processing the bit vector includes providing a pulse to each of a plurality of input lines of a second synaptic array when a corresponding bit of the bit vector indicates that the predetermined threshold value is exceeded. At 703, in parallel with the processing of the bit vector, the plurality of analog voltages are converted into a digital value vector. At 704, after the processing of the bit vector, a pulse is provided to each of a plurality of input lines of the second synaptic array, each pulse having a duration proportional to a corresponding digital value of the digital value vector.

[0033] In various embodiments, a set of circuits is provided for converting a vector of analog voltages at the edge of a first array into a vector of durations at the edge of a second array. A comparator compares each analog voltage with a common analog threshold, thereby generating a most significant amplitude bit of each analog voltage, generating a vector of most significant amplitude bits. A transmission system transmits the vector of most significant amplitude bits from the edge of the first array to the edge of the second array. Considering the value of the most significant amplitude bit, the circuit injects a vector of constant duration pulse signals into the second array. A plurality of A / D converters convert the analog voltages at the edge of the first array into a vector of high-resolution residual digital data representations, which accommodates the vector of the most significant amplitude bits that have been calculated. The transmission system transmits the vector of high-resolution residual digital data from the edge of the first array to the edge of the second array. Considering the value of the high-resolution residual digital data vector, the circuit introduces a vector of variable duration pulse signals. The operations performed on the most significant amplitude bits (comparison, transmission of the vector of most significant amplitude bits, and injection of a constant duration signal into the second array) occur in parallel with the operations of the A / D converters (conversion, transmission of the vector of high-resolution residual digital data, and injection of a variable duration signal into the second array).

[0034] In some embodiments, the analog voltage represents a signed quantity for which the most significant magnitude bit is turned on only for positive analog voltages exceeding a common threshold. In some embodiments, the analog voltage represents a signed quantity and two comparators (with respective common analog thresholds) are used.

[0035] In some embodiments, the analog voltage is stored on a capacitor.

[0036] Reference now Figure 8 , a schematic diagram of an example of a computing node is shown. Computing node 10 is only one example of a suitable computing node and is not intended to impose any limitations on the scope of use or functionality of the embodiments described herein. Regardless, computing node 10 can be implemented and / or perform any of the functions set forth above.

[0037] In computing node 10, there is a computer system / server 12, which can operate with many other general or special computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, fat clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, etc.

[0038] Computer system / server 12 may be described in the general context of computer system executable instructions, such as program modules, executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. Computer system / server 12 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in local and remote computer system storage media including memory storage devices.

[0039] like Figure 8 As shown, the computer system / server 12 in the computing node 10 is shown in the form of a general-purpose computing device. The components of the computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including the system memory 28 to the processor 16.

[0040] Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, these architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, Peripheral Component Interconnect (PCI) bus, Peripheral Component Interconnect Express (PCIe), and Advanced Microcontroller Bus Architecture (AMBA).

[0041] Computer system / server 12 typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 12, and it includes volatile and nonvolatile media, removable and non-removable media.

[0042] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, and commonly referred to as a "hard drive"). Although not shown, a disk drive for reading from and writing to a removable, non-volatile disk (e.g., a "floppy disk") may be provided, as well as an optical drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media. In this case, each may be connected to the bus 18 via one or more data media interfaces. As will be further depicted and described below, the memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of an embodiment of the present invention.

[0043] By way of example and not limitation, a program / utility 40 having a set (at least one) of program modules 42, as well as an operating system, one or more application programs, other program modules, and program data, may be stored in memory 28. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. Program modules 42 generally perform the functions and / or methods of the embodiments described herein.

[0044] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, etc.; one or more devices that enable a user to interact with the computer system / server 12; and / or any device that enables the computer system / server 12 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 22. However, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0045] The present invention may be implemented as a system, method, and / or computer program product. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0046] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0047] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0048] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as "C" programming language or similar programming languages). The computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider through the Internet). In certain embodiments, in order to perform various aspects of the present invention, the electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA) can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0049] Various aspects of the present invention are described herein with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to embodiments of the present invention. It will be understood that each frame of the flow chart and / or block diagram and the combination of frames in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0050] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0051] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0052] Flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, each frame in flow chart or block diagram can represent the module, segment or part of instruction, and it comprises one or more executable instructions for realizing the logical function of appointment.In some alternative embodiments, the function mentioned in the frame may not occur in the order mentioned in the figure.For example, two frames shown continuously can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the function involved.It will also be noted that the combination of the frame in each frame of block diagram and / or flow chart illustration and block diagram and / or flow chart illustration can be realized by the dedicated hardware-based system of performing specified function or action or performing the combination of special hardware and computer instruction.

[0053] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: a first synapse array configured to output a plurality of analog voltages; a second synapse array having a plurality of input lines; a network operably coupled to the first synapse array and the second synapse array; at least one comparator operably coupled to the first synapse array, the at least one comparator adapted to compare the plurality of analog voltages with a predetermined threshold to generate a bit vector, each bit of the bit vector indicating whether one of the plurality of analog voltages exceeds the predetermined threshold, and transmit the bit vector via the network; at least one analog-to-digital converter operably coupled to the first synaptic array and the network, the at least one analog-to-digital converter configured to convert the plurality of analog voltages into a vector of digital values ​​and transmit the vector of digital values ​​via the network; at least one modulator operatively coupled to the second synapse array and the network, the at least one modulator configured to receive the bit vector from the network, processing the bit vector, the processing the bit vector comprising providing a pulse to each of the plurality of input lines of the second synapse array when a corresponding bit indication of the bit vector exceeds the predetermined threshold, receiving the digital value vector from the network, and processing the vector of digital values, the processing the vector of digital values ​​comprising providing a pulse to each of the plurality of input lines of the second synapse, each pulse having a duration proportional to a corresponding digital value of the vector of digital values; in The receiving the bit vector and / or processing the bit vector occurs in parallel with the converting the plurality of analog voltages and / or transmitting the digital value vector.

2. The apparatus according to claim 1, wherein: Each of the first and second synapse arrays includes a plurality of ordered input lines, a plurality of ordered output lines, and a plurality of synapses, each synapse operably coupled to one of the plurality of input lines and one of the plurality of output lines.

3. The device according to claim 2, wherein: Each of the plurality of synapses includes a resistive element configured to store a weight of a neural network.

4. The device according to claim 1, wherein: The synaptic array is configured as a trained neural network.

5. The device according to claim 1, wherein: Each of the plurality of analog voltages corresponds to an unsigned value.

6. The device according to claim 1, wherein: Each of the plurality of analog voltages corresponds to a signed value.

7. The device according to claim 6, wherein: The at least one comparator includes at least two comparators, and wherein comparing the multiple analog voltages with the predetermined threshold includes applying a first comparator to the analog voltage to determine a sign and applying a second comparator to the analog voltage to determine whether the analog voltage exceeds the predetermined threshold.

8. The device according to claim 1, wherein: The first synapse array includes a plurality of capacitors, each of the plurality of capacitors being configured to store and output one of the plurality of analog voltages.

9. A method comprising: comparing a plurality of analog voltages output from the first synapse array with a predetermined threshold to generate a bit vector, each bit of the bit vector indicating whether one of the plurality of analog voltages exceeds the predetermined threshold; processing the bit vector, the processing the bit vector comprising providing a pulse to each of a plurality of input lines of a second synapse array when a corresponding bit indication of the bit vector exceeds the predetermined threshold; In parallel with said processing said bit vector, converting said plurality of analog voltages into a vector of digital values; as well as Subsequent to said processing said bit vector, providing a pulse to each of said plurality of input lines of said second synapse, each pulse having a duration proportional to a corresponding digital value of said vector of digital values.

10. The method according to claim 9, wherein: Each of the first and second synapse arrays includes a plurality of ordered input lines, a plurality of ordered output lines, and a plurality of synapses, each synapse operably coupled to one of the plurality of input lines and one of the plurality of output lines.

11. The method according to claim 10, wherein: Each of the plurality of synapses includes a resistive element configured to store a weight of a neural network.

12. The method according to claim 9, wherein: The synaptic array is configured as a trained neural network.

13. The method according to claim 9, wherein: Each of the plurality of analog voltages corresponds to an unsigned value.

14. The method according to claim 9, wherein: Each of the plurality of analog voltages corresponds to a signed value.

15. The method according to claim 14, wherein: The at least one comparator includes at least two comparators, and wherein comparing the multiple analog voltages with the predetermined threshold includes applying a first comparator to the analog voltage to determine a sign and applying a second comparator to the analog voltage to determine whether the analog voltage exceeds the predetermined threshold.

16. The method according to claim 9, wherein: The first synapse array includes a plurality of capacitors, each of the plurality of capacitors being configured to store and output one of the plurality of analog voltages.

17. A computer program product for operating a neural network circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: comparing a plurality of analog voltages output from the first synapse array with a predetermined threshold to generate a bit vector, each bit of the bit vector indicating whether one of the plurality of analog voltages exceeds the predetermined threshold; processing the bit vector, the processing the bit vector comprising providing a pulse to each of a plurality of input lines of a second synapse array when a corresponding bit indication of the bit vector exceeds the predetermined threshold; In parallel with said processing said bit vector, converting said plurality of analog voltages into a vector of digital values; as well as Subsequent to said processing said bit vector, providing a pulse to each of said plurality of input lines of said second synapse, each pulse having a duration proportional to a corresponding digital value of said vector of digital values.

18. The computer program product of claim 17, wherein: Each of the first and second synapse arrays includes a plurality of ordered input lines, a plurality of ordered output lines, and a plurality of synapses, each synapse operably coupled to one of the plurality of input lines and one of the plurality of output lines.

19. The computer program product of claim 18, wherein: Each of the plurality of synapses includes a resistive element configured to store a weight of a neural network.

20. The computer program product of claim 17, wherein the synaptic array is configured as a trained neural network.

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