Semiconductor device

Abstract

A semiconductor device includes a conductive member including first, second, and third conductors that are separated from each other, a first semiconductor element having a first main surface on which a first drain electrode, a first source electrode, and a first gate electrode are provided, and a second semiconductor element having a second main surface on which a second drain electrode, a second source electrode, and a second gate electrode are provided. The first conductor is in conduction with the first source electrode and the second drain electrode. The second conductor is in conduction with the second source electrode and is adjacent to the second conductor in a second direction orthogonal to a first direction orthogonal to the first main surface. The third conductor is in conduction with the first drain electrode and is adjacent to the first and second conductors in the first direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device in which a plurality of semiconductor elements are mounted. BACKGROUND

[0002] Conventionally, a semiconductor device in which a plurality of semiconductor elements are molded with one resin member is known. The semiconductor device is called a system-in-package. In Patent Literature 1, a semiconductor device in which two switching elements and a control IC are single packaged is disclosed. The control IC is a semiconductor element that controls each switching element. Each switching element performs a switching operation in accordance with a signal from the control IC. Such a semiconductor device is mounted in a circuit substrate of an electronic device or the like, for example, and is used for a power supply circuit such as a DC / DC converter.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2003-218309 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In recent years, with energy saving and high performance of electronic devices, it is required that a semiconductor device reduce power consumption, improve responsiveness of a switching operation, and the like. In terms of achieving reduction of power consumption and improvement of responsiveness of a switching operation, reduction of a parasitic inductance and reduction of a parasitic resistance are effective.

[0008] In view of the above, an object of the present disclosure is to provide a semiconductor device in which a plurality of semiconductor elements are single packaged, and reduction of a parasitic inductance and reduction of a parasitic resistance are achieved.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] A semiconductor device provided by the present disclosure is characterized in that it comprises: a conductive component, which includes a first conductor, a second conductor and a third conductor separated from each other; a first semiconductor element, which has a first main surface, on which a first drain electrode, a first source electrode and a first gate electrode are arranged; a second semiconductor element, which has a second main surface, on which a second drain electrode, a second source electrode and a second gate electrode are arranged, the first conductor is electrically connected to the first source electrode and the second drain electrode, the second conductor is electrically connected to the second source electrode, and when viewed in a first direction orthogonal to the first main surface, the second conductor is adjacent to the first direction orthogonal to the first direction, the third conductor is electrically connected to the first drain electrode, and when viewed in the first direction, the third conductor is adjacent to the first conductor and the second conductor, respectively.

[0011] Effects of the Invention

[0012] According to the semiconductor device of the present disclosure, parasitic inductance and parasitic resistance can be reduced in a semiconductor device in which a plurality of semiconductor elements are packaged in a single package. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view showing the semiconductor device according to the first embodiment.

[0014] Figure 2 is Figure 1 A diagram showing a sealing component with imaginary lines in the perspective view of FIG.

[0015] Figure 3 It is a perspective view showing the semiconductor device according to the first embodiment (seen from the bottom side).

[0016] Figure 4 It is a plan view showing the semiconductor device according to the first embodiment.

[0017] Figure 5 It will Figure 4 A partial enlarged view in which a portion of the top view is enlarged.

[0018] Figure 6 It is along Figure 4 A cross-sectional view taken along line VI-VI.

[0019] Figure 7 It is along Figure 4 A cross-sectional view taken along line VII-VII.

[0020] Figure 8 It is along Figure 4 A cross-sectional view taken along line VIII-VIII.

[0021] Figure 9 is a circuit configuration view of the power conversion device of the first embodiment.

[0022] Figure 10 is a perspective view of the power conversion device of the first embodiment.

[0023] Figure 11 is a plan view of the power conversion device of the first embodiment.

[0024] Figure 12 is a plan view of the power conversion device of the second embodiment.

[0025] Figure 13 is a circuit configuration view of the power conversion device of the second embodiment.

[0026] Figure 14 is a plan view of the power conversion device of the third embodiment.

[0027] Figure 15 is a plan view of the power conversion device of the modification of the third embodiment.

[0028] Figure 16 is a plan view of the power conversion device of the fourth embodiment.

[0029] Figure 17 is a plan view of the power conversion device of the modification of the fourth embodiment.

[0030] Figure 18 is a plan view of the power conversion device of the fifth embodiment.

[0031] Figure 19 is a plan view of the power conversion device of the sixth embodiment.

[0032] Figure 20 is a sectional view along the line XX-XX of Figure 19

[0033] Figure 21 is a plan view of the power conversion device of the seventh embodiment.

[0034] Figure 22 is a plan view of the power conversion device of the eighth embodiment.

[0035] Figure 23 is a sectional view along the line XXIII-XXIII of Figure 22 DETAILED DESCRIPTION

[0036] ​​Hereinafter, a preferred embodiment of the semiconductor device of the present disclosure will be described with reference to the drawings. Further, the same or similar structural elements are denoted by the same reference numerals, and description thereof will be omitted.

[0037] In the present disclosure, "something A overlaps something B in a certain direction" includes "something A overlaps all of something B in a certain direction" and "something A overlaps a part of something B in a certain direction" unless otherwise specified. In addition, the terms "first", "second", "third" and the like in the present disclosure are used only as labels and do not mean that the objects need to be arranged in the order.

[0038] Reference Signs List Figures 1-11 A semiconductor device Al of the first embodiment will be described. The semiconductor device Al is used, for example, for a power conversion device such as an inverter or a converter.

[0039] Figures 1-8 A module configuration of the semiconductor device Al of the first embodiment is shown. The semiconductor device Al has, in its module configuration, two semiconductor elements 1 and 2, a control element 3, a lead frame 4, a plurality of lead wires 5A to 5L, and a sealing member 6. In addition, in the semiconductor device Al, the lead frame 4 includes a plurality of leads 4A to 4H that are separated from each other.

[0040] Figure 1 is a perspective view that shows the semiconductor device Al. Figure 2 is a perspective view that shows the semiconductor device Al. Figure 1 is a view that shows the sealing member 6 with a broken line (double-dot chain line) in the perspective view of Figure 3 is a perspective view that shows the semiconductor device Al, and shows a case where it is viewed from the bottom surface side. Figure 4 is a plan view that shows the semiconductor device Al, and shows the sealing member 6 with a broken line (double-dot chain line). Figure 5 is a partially enlarged view that enlarges a part of Figure 4 . Figure 6 is a cross-sectional view along the VI-VI line of Figure 4 . Figure 7 is a cross-sectional view along the VII-VII line of Figure 4 . Figure 8 is a cross-sectional view along the VIII-VIII line of Figure 4 .

[0041] For convenience of explanation, three directions that are orthogonal to each other are defined as an x direction, a y direction, and a z direction. The z direction is a thickness direction of the semiconductor device Al. The x direction is a left-right direction in a plan view (see Figure 4 ) of the semiconductor device Al. The y direction is a front-rear direction in the plan view (see Figure 4directions. Also, one of the x directions is set as an x1 direction, and the other of the x directions is set as an x2 direction. Similarly, one of the y directions is set as a y1 direction, and the other of the y directions is set as a y2 direction, and one of the z directions is set as a z1 direction, and the other of the z directions is set as a z2 direction. In the present disclosure, there are also cases where the z1 direction is referred to as down, and the z2 direction is referred to as up. The z direction corresponds to the “first direction” recited in the claims, the x direction corresponds to the “second direction” recited in the claims, and the y direction corresponds to the “third direction” recited in the claims.

[0042] The semiconductor device Al is mounted on a circuit substrate of an electronic device or the like. The semiconductor device Al is, for example, a surface-mounted package configuration, and in the present embodiment, is, for example, a package form called a SON (Small Outline Non-lead).

[0043] The two semiconductor elements 1 and 2 are elements that exert an electrical function of the semiconductor device Al. Each semiconductor element 1 and 2 is a switching element, and in the present disclosure, is a MOSFET. Further, each semiconductor element 1 and 2 is not limited to a MOSFET, and can be another transistor such as a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET), a HEMT (High Electron Mobility Transistor), a bipolar transistor, or an IGBT (Insulated Gate Bipolar Transistor). In addition, each semiconductor element 1 and 2 can be an n-type MOSFET, or a p-type MOSFET. Each semiconductor element 1 and 2 is preferably a trench gate type, but can also be a planar gate type.

[0044] As shown in FIG. 1, each semiconductor element 1 and 2 is, for example, a rectangular shape in plan view (viewed in the z direction). As shown in FIG. 2, each semiconductor element 1 and 2 is, for example, a rectangular shape in plan view (viewed in the x direction). Figure 4 Figure 2 Figure 4 As shown in FIG. 1, each semiconductor element 1 and 2 is, for example, a rectangular shape in plan view (viewed in the z direction). As shown in FIG. 2, each semiconductor element 1 and 2 is, for example, a rectangular shape in plan view (viewed in the x direction).

[0045] As shown in FIG. 1, each semiconductor element 1 and 2 is, for example, a rectangular shape in plan view (viewed in the z direction). As shown in FIG. 2, each semiconductor element 1 and 2 is, for example, a rectangular shape in plan view (viewed in the x direction). Figure 6 ​​As shown, the semiconductor element 1 has an element front surface la and an element back surface lb. The element front surface la and the element back surface lb are separated in the z direction. The element front surface la faces the z2 direction, and the element back surface lb faces the zl direction. In the present example, the element front surface la and the element back surface lb are orthogonal to the z direction. The element back surface lb faces the lead 4A. The element front surface la corresponds to the "first front surface" recited in the claims, and the element back surface lb corresponds to the "first back surface" recited in the claims.

[0046] The semiconductor element 1 is a 3-terminal element having 3 electrodes. In the present embodiment, as shown in FIG. 1, the semiconductor element 1 includes a drain electrode 11, a source electrode 12, and a gate electrode 13. As shown in FIG. 1, the drain electrode 11, the source electrode 12, and the gate electrode 13 are disposed on the element front surface la. The drain electrode 11 corresponds to the "first drain electrode" recited in the claims, the source electrode 12 corresponds to the "first source electrode" recited in the claims, and the gate electrode 13 corresponds to the "first gate electrode" recited in the claims. Figure 4 Figure 5 Figure 6 As shown in FIG. 1, the drain electrode 11 includes a plurality of pad portions 111. Each pad portion 111 is a band shape extending in a first extension direction. In the example shown in FIG. 1, each pad portion 111 extends in the y direction, and the first extension direction is substantially identical to the y direction. Each pad portion 111 is in conduction with a drain region inside the semiconductor element 1. The pad portion 111 corresponds to the "first drain pad portion" recited in the claims. Figure 6

[0047] As shown in FIG. 1, the source electrode 12 includes a plurality of pad portions 121. Each pad portion 121 is a band shape extending in the first extension direction, like each pad portion 111. In the example shown in FIG. 1, each pad portion 121 extends in the y direction. Each pad portion 121 is in conduction with a source region inside the semiconductor element 1. The pad portion 121 corresponds to the "first source pad portion" recited in the claims. Figure 5 Figure 5

[0048] The plurality of pad portions 111 and the plurality of pad portions 121 are arranged and alternately disposed in a first arrangement direction. The first arrangement direction is a direction substantially orthogonal to the first extension direction, and when the first extension direction is substantially identical to the y direction, the first arrangement direction is substantially identical to the x direction. Figure 5 Figure 5

[0049] The plurality of pad portions 111 and the plurality of pad portions 121 are arranged and alternately disposed in a first arrangement direction. The first arrangement direction is a direction substantially orthogonal to the first extension direction, and when the first extension direction is substantially identical to the y direction, the first arrangement direction is substantially identical to the x direction.

[0050] As shown in FIG. 1, the source electrode 12 includes a plurality of pad portions 121. Each pad portion 121 is a band shape extending in the first extension direction, like each pad portion 111. In the example shown in FIG. 1, each pad portion 121 extends in the y direction. Each pad portion 121 is in conduction with a source region inside the semiconductor element 1. The pad portion 121 corresponds to the "first source pad portion" recited in the claims. Figure 5 ​​​​​​​As shown, the gate electrode 13 includes two pads 131 and 132. Each pad 131 and 132 is electrically connected to the gate region (channel region) inside the semiconductor element 1. The two pads 131 and 132 are arranged near the edge of the element main surface 1a on the y1 side and are separated from each other in the x direction. Figure 5 In the example shown, pad portion 131 is located at a corner on the x2 and y1 sides in a top view. Pad portion 132 is located at a corner on the x1 and y1 sides in a top view. Both pad portions 131 and 132 have the same potential. Gate electrode 13 may also not include pad portion 132.

[0051] The semiconductor element 1 receives a drive signal from the control element 3 and switches between an on state and an off state (performs a switching operation) in accordance with the drive signal. The drive signal is input to the gate electrode 13 (pad portion 131) via the wire 5E.

[0052] like Figure 7 As shown, semiconductor element 2 has a principal surface 2a and a rear surface 2b. The principal surface 2a and rear surface 2b are separated in the z-direction. The principal surface 2a faces the z2 direction, while the rear surface 2b faces the z1 direction. In this example, the principal surface 2a and rear surface 2b are perpendicular to the z-direction. The rear surface 2b faces the lead 4B. The principal surface 2a corresponds to the "second principal surface" in the claims, and the rear surface 2b corresponds to the "second rear surface" in the claims.

[0053] The semiconductor element 2 is a three-terminal element having three electrodes. Figure 4 、 Figure 5 as well as Figure 7 As shown in FIG, the semiconductor element 2 includes a drain electrode 21, a source electrode 22, and a gate electrode 23. Figure 7 As shown, the drain electrode 21, source electrode 22, and gate electrode 23 are arranged on the device main surface 2a. The drain electrode 21 corresponds to the "second drain electrode" described in the claims, the source electrode 22 corresponds to the "second source electrode" described in the claims, and the gate electrode 23 corresponds to the "second gate electrode" described in the claims.

[0054] like Figure 5 As shown, the drain electrode 21 includes a plurality of pad portions 211. Each pad portion 211 is in the shape of a strip extending in the second extension direction. The second extension direction is inclined at an angle of 10° to 170° relative to the first extension direction. That is, the angle formed by the first extension direction and the second extension direction is 10° to 170°. Figure 5 In the example shown, each pad portion 211 extends in the x-direction, and the second extension direction is substantially consistent with the x-direction. Figure 5In the illustrated example, the first extension direction and the second extension direction form an angle of substantially 90°. Each pad portion 211 is in conduction with a drain region inside the semiconductor element 2. The pad portion 211 corresponds to the "second drain pad portion" recited in the claims.

[0055] As Figure 5 illustrated, the source electrode 22 includes a plurality of pad portions 221. Each pad portion 221, like each pad portion 211, is a strip extending in the second extension direction. In Figure 5 the illustrated example, each pad portion 221 extends in the x direction. Each pad portion 221 is in conduction with a source region inside the semiconductor element 2. The pad portion 221 corresponds to the "second source pad portion" recited in the claims.

[0056] The plurality of pad portions 211 and the plurality of pad portions 221 are arranged in the first arrangement direction and are alternately arranged. The second arrangement direction is a direction substantially orthogonal to the second extension direction, and when the second extension direction substantially coincides with the x direction, the second arrangement direction substantially coincides with the y direction.

[0057] As Figure 5 illustrated, the gate electrode 23 includes two pad portions 231, 232. Each pad portion 231, 232 is in conduction with a gate region (channel region) inside the semiconductor element 2. The two pad portions 231, 232 are arranged near the end edge on the x2 direction side in the element main surface 2a and are separated from each other in the y direction. In Figure 5 the illustrated example, the pad portion 231 is arranged at a corner on the x2 direction side and the yl direction side in a plan view. The pad portion 232 is arranged at a corner on the x2 direction side and the y2 direction side in a plan view. Both of the two pad portions 231, 232 are at the same potential. Furthermore, the gate electrode 23 can not include the pad portion 232.

[0058] The semiconductor element 2 inputs a drive signal from the control element 3, and switches between the conduction state and the cut-off state (performs a switching operation) in accordance with the drive signal. The drive signal is input to the gate electrode 23 (pad portion 231) via the lead wire 5F.

[0059] The control element 3 controls each switching operation of the two semiconductor elements 1, 2. The control element 3 generates a drive signal for driving each semiconductor element 1, 2, and outputs the generated drive signal to each semiconductor element 1, 2, respectively. The control element 3 is, for example, an IC (integrated circuit). The control element 3 is a semiconductor element configured to include a semiconductor material. As Figure 2 and Figure 4 illustrated, the control element 3 is mounted to the lead wire 4D. In Figure 4 the illustrated example, the control element 3 overlaps each portion of each semiconductor element 1, 2, respectively, when viewed in the y direction.

[0060] As shown in Figure 8 , the control element 3 has an element front face 3a and an element back face 3b. The element front face 3a and the element back face 3b are separated in the z direction. The element front face 3a faces the z2 direction, and the element back face 3b faces the z1 direction. The element back face 3b opposes the lead 4D.

[0061] As shown in Figure 4 , the control element 3 includes a plurality of element electrodes 31 to 38. The plurality of element electrodes 31 to 38 are respectively arranged on the element front face 3a. The element electrodes 31 to 38 are respectively an input terminal or an output terminal in the control element 3. The arrangement of each of the element electrodes 31 to 38 in the plan view is not limited to the example shown in Figure 4 .

[0062] As shown in Figure 4 , the element electrode 31 is joined to one end of the lead wire 5J and is conducted with the lead wire 5J and the lead 4F.

[0063] As shown in Figure 4 , the element electrode 32 is joined to one end of the lead wire 5H and is conducted with the lead wire 5H and the lead 4D.

[0064] As shown in Figure 4 , the element electrode 33 is joined to one end of the lead wire 5K and is conducted with the lead wire 5K and the lead 4G.

[0065] As shown in Figure 4 , the element electrode 34 is joined to one end of the lead wire 5L and is conducted with the lead wire 5L and the lead 4H.

[0066] As shown in Figure 4 , the element electrode 35 is joined to one end of the lead wire 5E and is conducted with the lead wire 5E and the gate electrode 13 (pad portion 131) of the semiconductor element 1. A drive signal (first drive signal) that controls the switching operation of the semiconductor element 1 is output from the element electrode 35. The element electrode 35 corresponds to the "first element electrode" recited in the claims.

[0067] As shown in Figure 4 , the element electrode 36 is joined to one end of the lead wire 5F and is conducted with the lead wire 5F and the gate electrode 23 (pad portion 231) of the semiconductor element 2. A drive signal (second drive signal) that controls the switching operation of the semiconductor element 2 is output from the element electrode 36. The element electrode 36 corresponds to the "second element electrode" recited in the claims.

[0068] As shown in Figure 4 , the element electrode 37 is connected to one end of the lead wire 5I and is conducted with the lead wire 5I and the lead 4E.

[0069] As shown in Figure 4As shown, the element electrode 38 is bonded to one end of a wire 5G and is electrically connected to the lead 4A via the wire 5G.

[0070] The lead frame 4 carries two semiconductor elements 1 and 2 and a control element 3. The lead frame 4 and a plurality of wires 5A to 5L together form a conductive path in the semiconductor device A1. The lead frame 4 is made of a conductive material. The constituent material of the lead frame 4 is, for example, a metal containing Cu (copper). In addition, the constituent material may also be other metals other than Cu. In addition, the surface of the lead frame 4 may be plated as appropriate. Figure 4 As shown, the lead frame 4 includes a plurality of leads 4A to 4H separated from each other. Figure 3 As shown, each portion is exposed from the sealing member 6 , and the exposed portion serves as a terminal when the semiconductor device A1 is mounted on an external circuit board (eg, a circuit board B1 described later).

[0071] like Figure 4 As shown, lead 4A carries semiconductor element 1. Lead 4A is bonded to one end of each of a plurality of wires 5B, and is electrically connected to source electrode 12 of semiconductor element 1 via the plurality of wires 5B. Furthermore, lead 4A is bonded to one end of each of a plurality of wires 5C, and is electrically connected to drain electrode 21 of semiconductor element 2 via the plurality of wires 5C. Furthermore, lead 4A is bonded to one end of wire 5G, and is electrically connected to element electrode 38 of control element 3 via the wire 5G.

[0072] like Figure 4 As shown, the lead 4B carries the semiconductor element 2. The lead 4B is bonded to one end of each of a plurality of wires 5D, and is electrically connected to the source electrode 22 of the semiconductor element 2 via the plurality of wires 5D.

[0073] like Figure 4 As shown, the lead 4C is joined to one end of each of the plurality of wires 5A, and is electrically connected to the drain electrode 11 of the semiconductor element 1 via the plurality of wires 5A.

[0074] like Figure 4 As shown, the control element 3 is mounted on the lead 4D. The lead 4D is joined to one end of a wire 5H and is electrically connected to the element electrode 32 of the control element 3 via the wire 5H.

[0075] like Figure 4 As shown, the lead 4E is joined to one end of a wire 5I and is electrically connected to the element electrode 37 of the control element 3 via the wire 5I.

[0076] like Figure 4 As shown, the lead 4F is joined to one end of a wire 5J and is electrically connected to the element electrode 31 of the control element 3 via the wire 5J.

[0077] like Figure 4As shown, the lead wire 4G is connected to one end of the lead wire 5K, and is connected to the element electrode 33 of the control element 3 via the lead wire 5K.

[0078] As shown, the lead wire 4H is connected to one end of the lead wire 5L, and is connected to the element electrode 34 of the control element 3 via the lead wire 5L. Figure 4 In the lead wire frame 4, as shown in

[0079] Figure 4 The lead wire 4A and the lead wire 4B are adjacent in the x direction in a plan view. An insulating region 49A is interposed between the lead wire 4A and the lead wire 4B (indicated by a dot in for the sake of easy understanding). The lead wire 4A and the lead wire 4B overlap when viewed in the x direction. The insulating region 49A corresponds to the "second insulating region" recited in the claims.

[0080] Figure 4 The lead wire 4A and the lead wire 4C are adjacent in the y direction in a plan view. An insulating region 49B is interposed between the lead wire 4A and the lead wire 4C (indicated by a dot in for the sake of easy understanding). The lead wire 4A and the lead wire 4C overlap when viewed in the y direction. The insulating region 49B corresponds to the "first insulating region" recited in the claims.

[0081] Figure 4 The lead wire 4B and the lead wire 4C are adjacent in the x direction in a plan view. An insulating region 49C is interposed between the lead wire 4B and the lead wire 4C (indicated by a dot in for the sake of easy understanding). The lead wire 4B and the lead wire 4C overlap when viewed in the x direction.

[0082] Figure 4 The lead wire 4C is arranged in the first direction of extension with respect to the semiconductor element 1, and the lead wire 4A is arranged in the second direction of extension with respect to the semiconductor element 2.

[0083] The lead wire 4A and the lead wire 4B are both arranged at positions further in the y2 direction than the lead wire 4D. The lead wire 4A and the lead wire 4B both overlap the lead wire 4D when viewed in the y direction, and do not overlap the lead wire 4D when viewed in the x direction.

[0084] The lead wire 4E, the lead wire 4F, the lead wire 4G, and the lead wire 4H each overlap the lead wire 4D when viewed in the x direction. The lead wire 4E and the lead wire 4F overlap the lead wire 4A and the lead wire 4C when viewed in the y direction, and the lead wire 4G and the lead wire 4H overlap the lead wire 4B when viewed in the y direction. The lead wire 4E and the lead wire 4G overlap when viewed in the x direction, and the lead wire 4F and the lead wire 4H overlap when viewed in the x direction. The lead wire 4D has a protruding portion protruding in the x2 direction, and the protruding portion is positioned between the lead wire 4G and the lead wire 4H in the y direction.

[0085] The lead wire 4E, the lead wire 4F, the lead wire 4G, and the lead wire 4H each overlap the lead wire 4D when viewed in the x direction. The lead wire 4E and the lead wire 4F overlap the lead wire 4A and the lead wire 4C when viewed in the y direction, and the lead wire 4G and the lead wire 4H overlap the lead wire 4B when viewed in the y direction. The lead wire 4E and the lead wire 4G overlap when viewed in the x direction, and the lead wire 4F and the lead wire 4H overlap when viewed in the x direction. The lead wire 4D has a protruding portion protruding in the x2 direction, and the protruding portion is positioned between the lead wire 4G and the lead wire 4H in the y direction.

[0086] ​In the lead frame 4, the leads 4C, 4A, 4E, and 4F are arranged in order along the edge on the x1 side, and the leads 4B, 4G, the protruding portion of the lead 4D, and the lead 4H are arranged in order along the edge on the x2 side. Furthermore, in the lead frame 4, the leads 4F, 4D, and 4H are arranged in order along the edge on the y1 side, and the leads 4C and 4B are arranged in order along the edge on the y2 side.

[0087] In this embodiment, the lead frame 4 corresponds to the "conductive member" described in the claims. Lead 4A corresponds to the "first conductor" described in the claims. Lead 4B corresponds to the "second conductor" described in the claims. Lead 4C corresponds to the "third conductor" described in the claims. Lead 4D corresponds to the "fourth conductor" described in the claims. Lead 4E corresponds to the "fifth conductor" described in the claims. Lead 4F corresponds to the "sixth conductor" described in the claims. Lead 4G corresponds to the "seventh conductor" described in the claims. Lead 4H corresponds to the "eighth conductor" described in the claims.

[0088] The plurality of wires 5A to 5L respectively connect the two separated components. Each wire 5A to 5L is a so-called bonding wire. Each wire 5A to 5L is made of a conductive material. The constituent material of each wire 5A to 5L can be, for example, a metal containing Au (gold), a metal containing Al (aluminum), or a metal containing Cu. Figure 2 In the example shown, the wire diameters (thickness) of the plurality of conductors 5A to 5D are larger than the wire diameters (thickness) of the plurality of conductors 5E to 5L, but they may be the same or smaller. Figure 4 The numbers shown can also be appropriately changed taking into account the structures (top-view area, configuration and number, etc.) of each pad portion 111, 121, 131, 132, 211, 221, 231, 232 and each element electrode 31 to 38, the wire diameter of each wire 5A to 5L, and the amount of current flowing through each wire 5A to 5L.

[0089] like Figure 5 as well as Figure 4 As shown, one end of each of the plurality of wires 5A is bonded to the drain electrode 11 (any one of the plurality of pads 111) of the semiconductor element 1, and the other end is bonded to the lead 4C. Figure 5 and Figure 4 In the example shown, three wires 5A are bonded to each of the three pads 111. Each wire 5A electrically connects the drain electrode 11 (each pad 111) to the lead 4C. Figure 4 As shown, each conductor 5A overlaps with the insulating region 49B in a plan view.

[0090] like Figure 5 as well as Figure 4 As shown, each of the plurality of wires 5B has one end bonded to the source electrode 12 (any one of the plurality of pads 121) of the semiconductor element 1 and the other end bonded to the lead 4A. Figure 5 and Figure 4 In the example shown, three wires 5B are bonded to each of the two pads 121. Each wire 5B establishes electrical continuity between the source electrode 12 (each pad 121) and the lead 4A.

[0091] like Figure 5 as well as Figure 4 As shown, each of the plurality of wires 5C has one end bonded to the drain electrode 21 (any one of the plurality of pads 211) of the semiconductor element 2 and the other end bonded to the lead 4A. Figure 5 and Figure 4 In the example shown, three wires 5C are bonded to each of the three pads 211. Each wire 5C electrically connects the drain electrode 21 (each pad 211) to the lead 4A. Figure 4 As shown, each conductor 5C overlaps with the insulating region 49A in a plan view.

[0092] like Figure 5 as well as Figure 4 As shown, each of the plurality of wires 5D has one end bonded to the source electrode 22 (any one of the plurality of pads 221) of the semiconductor element 2 and the other end bonded to the lead 4B. Figure 5 and Figure 4 In the example shown, three wires 5D are bonded to each of the two pads 221. Each wire 5D establishes electrical continuity between the source electrode 22 (each pad 221) and the lead 4B.

[0093] like Figure 4 As shown, one end of the wire 5E is connected to the element electrode 35 of the control element 3, and the other end is connected to the gate electrode 13 (pad portion 131) of the semiconductor element 1. The wire 5E makes the element electrode 35 and the gate electrode 13 (pad portion 131) conductive. Figure 4 As shown, the wire 5E overlaps only the lead 4A and the lead 4D in the lead frame 4 in a plan view. That is, the wire 5E does not overlap the leads 4B, 4C, 4E to 4H in a plan view.

[0094] like Figure 4 As shown, one end of the wire 5F is connected to the element electrode 36 of the control element 3, and the other end is connected to the gate electrode 23 (pad portion 231) of the semiconductor element 2. The wire 5F makes the element electrode 36 and the gate electrode 23 (pad portion 231) conductive. Figure 4As shown, the lead wire 5F overlaps only the lead wire 4B and the lead wire 4D in the lead frame 4 in a plan view. That is, the lead wire 5F does not overlap the lead wires 4A, 4C, 4E to 4H in the plan view.

[0095] As shown, the lead wire 5G is joined at one end to the element electrode 38 of the control element 3 and at the other end to the lead wire 4A. The lead wire 5G electrically connects the element electrode 38 and the lead wire 4A. Figure 4

[0096] As shown, the lead wire 5H is joined at one end to the element electrode 32 of the control element 3 and at the other end to the lead wire 4D. The lead wire 5H electrically connects the element electrode 32 and the lead wire 4D. Figure 4

[0097] As shown, the lead wire 5I is joined at one end to the element electrode 37 of the control element 3 and at the other end to the lead wire 4E. The lead wire 5I electrically connects the element electrode 37 and the lead wire 4E. Figure 4

[0098] As shown, the lead wire 5J is joined at one end to the element electrode 31 of the control element 3 and at the other end to the lead wire 4F. The lead wire 5J electrically connects the element electrode 31 and the lead wire 4F. Figure 4

[0099] As shown, the lead wire 5K is joined at one end to the element electrode 33 of the control element 3 and at the other end to the lead wire 4G. The lead wire 5K electrically connects the element electrode 33 and the lead wire 4G. Figure 4

[0100] As shown, the lead wire 5L is joined at one end to the element electrode 34 of the control element 3 and at the other end to the lead wire 4H. The lead wire 5L electrically connects the element electrode 34 and the lead wire 4H. Figure 2 In the present embodiment, the lead wire 5A corresponds to the "first connecting member" recited in the claims. The lead wire 5B corresponds to the "second connecting member" recited in the claims. The lead wire 5C corresponds to the "third connecting member" recited in the claims. The lead wire 5D corresponds to the "fourth connecting member" recited in the claims. The lead wire 5E corresponds to the "fifth connecting member" recited in the claims. The lead wire 5F corresponds to the "sixth connecting member" recited in the claims.

[0101] The sealing member 6 is a protective member for the semiconductor elements 1, 2 and the control element 3. As shown, the sealing member 6 covers each of the semiconductor elements 1, 2, the control element 3, a portion of the lead frame 4, and the plurality of lead wires 5A to 5L. The material constituting the sealing member 6 is a resin material that is electrically insulating, for example, an epoxy resin. The sealing member 6 is, for example, rectangular in a plan view. Further, the shape of the sealing member 6 is not limited to

[0102] Figures 1-4 Figure 1 ​​​​​​​The example shown. As Figure 3 , Figure 4 and Figure 1 The sealing member 6 has a resin front surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634.

[0103] The resin front surface 61 and the resin back surface 62 are separated in the z direction. As Figure 3 shown, the resin front surface 61 faces the z2 direction, and as Figure 4 shown, the resin back surface 62 faces the z1 direction. A portion of each of the lead wires 4A to 4J (a surface facing the z1 direction) is exposed from the resin back surface 62. The plurality of resin side surfaces 631 to 634 are respectively sandwiched by the resin front surface 61 and the resin back surface 62 in the z direction, and are continuous with both. As Figure 4 shown, the resin side surfaces 631 and 632 are separated in the x direction, the resin side surface 631 faces the x1 direction, and the resin side surface 632 faces the x2 direction. As Figures 9-11 shown, the resin side surfaces 633 and 634 are separated in the y direction, the resin side surface 633 faces the y1 direction, and the resin side surface 634 faces the y2 direction.

[0104] Next, the power conversion device W1 having the semiconductor device Al will be described with reference to Figure 9 . Furthermore, in the following description, the reference potential will be sometimes referred to as a ground voltage V GND .

[0105] Figure 9 is a circuit configuration diagram of the power conversion device W1. Figure 9 The power conversion device W1 shown in is a step-down DC / DC converter of a synchronous rectification type. Furthermore, the power conversion device W1 can be any one of a circuit configuration that performs constant current control, a circuit configuration that performs constant voltage control, or a circuit configuration that performs constant power control. The power conversion device W1 is a power supply circuit that steps down an input voltage Vin to generate a desired output voltage Vout. The output voltage Vout is supplied to a load LO. Furthermore, Figure 9 is an example.

[0106] As Figure 9 shown, the power conversion device W1 includes the semiconductor device Al, two external power supplies PS1 and PS2, and a plurality of discrete components (a plurality of capacitors C11 to C14 and an inductor L1) in its circuit configuration. In addition, as Figure 9 shown, the semiconductor device Al has a plurality of external terminals T1 to T8, two semiconductor elements 1 and 2, and a control element 3 in its circuit configuration. Furthermore, one or more of the plurality of discrete components can be built into the semiconductor device Al.

[0107] The external power supply PS1 generates a power supply voltage VCC for driving the control element 3. The terminal on the high potential side of the external power supply PS1 is connected to the external terminal T1. The terminal on the low potential side of the external power supply PS1 is connected to the first ground terminal GND1, and is connected to the reference potential ground. The external power supply PS1 is connected in parallel to the capacitor C11. The capacitor C11 is a bypass capacitor for stabilizing the power supply voltage VCC.

[0108] The external power supply PS2 generates an input voltage Vin. The terminal on the high potential side of the external power supply PS2 is connected to the external terminal T3. The terminal on the low potential side of the external power supply PS2 is connected to the second ground terminal GND2, and is connected to the reference potential ground. Also, the case where the first ground terminal GND1 and the second ground terminal GND2 are both ground terminals with respect to the same reference potential is shown, but the reference potential of the first ground terminal GND1 and the reference potential of the second ground terminal GND2 can be made different. The external power supply PS2 is connected in parallel to the capacitor C12. The capacitor C12 is a bypass capacitor for stabilizing the input voltage Vin.

[0109] The inductor L1 has two terminals, one of which is connected to the external terminal T7, and the other of which is connected to the load LO and the capacitor C13. The first terminal of the capacitor C13 is connected to the inductor L1, and the second terminal is connected to the second ground terminal GND2. The inductor L1 and the capacitor C13 constitute an LC filter circuit. The first terminal of the capacitor C14 is connected to the external terminal T7, and the second terminal is connected to the external terminal T8. The capacitor C14 constitutes a bootstrap circuit together with the diode D1 described later. The capacitor C14 generates a start-up voltage VB.

[0110] The external terminal T1 is an input terminal for the power supply voltage VCC. The external terminal T1 is connected to the terminal on the high potential side of the external power supply PS1. The external terminal T1 is connected to the control element 3 (connection terminal TC1 described later) inside the semiconductor device Al. The external terminal T1 corresponds to the lead 4F in the module configuration of the semiconductor device Al, for example.

[0111] The external terminal T2 is connected to the first ground terminal GND1, and is connected to the reference potential ground. The external terminal T2 is connected to the control element 3 (connection terminal TC2 described later) inside the semiconductor device Al. The external terminal T2 corresponds to the lead 4D in the module configuration of the semiconductor device Al, for example.

[0112] The external terminal T3 is an input terminal for the input voltage Vin. The external terminal T3 is connected to the terminal on the high potential side of the external power supply PS2. The external terminal T3 is connected to the drain of the semiconductor element 1 inside the semiconductor device Al. The external terminal T3 corresponds to the lead 4C in the module configuration of the semiconductor device Al, for example.

[0113] The external terminal T4 is connected to the second ground GND2 and to the reference potential ground. The external terminal T4 is connected to the source of the semiconductor element 2 within the semiconductor device A1. The external terminal T4 corresponds to the lead 4B in the module structure of the semiconductor device A1, for example.

[0114] External terminal T5 is an input terminal for control signal SH. Control signal SH is a signal used to control the switching operation of semiconductor element 1. Control signal SH is, for example, a rectangular pulse wave that alternates between high and low levels. External terminal T5 is connected to control element 3 (connection terminal TC3, described later) within semiconductor device A1. External terminal T5 corresponds to lead 4G in the module structure of semiconductor device A1, for example.

[0115] External terminal T6 is the input terminal for control signal SL. Control signal SL is a signal used to control the switching operation of semiconductor element 2. Control signal SL is, for example, a rectangular pulse wave that alternates between high and low levels. The high and low periods of control signal SL and control signal SH are reversed. External terminal T6 is connected to control element 3 (connection terminal TC4, described later) within semiconductor device A1. External terminal T6 corresponds to lead 4H in the module structure of semiconductor device A1, for example.

[0116] External terminal T7 is the output voltage V SW Output voltage V SW This is a voltage signal generated by the switching operations of semiconductor element 1 and semiconductor element 2. External terminal T7 is connected to the connection point between the source of semiconductor element 1 and the drain of semiconductor element 2 within semiconductor device A1. External terminal T7 corresponds to lead 4A in the module structure of semiconductor device A1, for example.

[0117] External terminal T8 is an input terminal for startup voltage VB. Startup voltage VB is a voltage signal generated by capacitor C14 and diode D1 (described later). External terminal T8 is connected to the second end of capacitor C14. External terminal T8 is connected to control element 3 (connection terminal TC7, described later) within semiconductor device A1. External terminal T8 corresponds to lead 4E in the module structure of semiconductor device A1, for example.

[0118] like Figure 10 As shown, two semiconductor elements 1 and 2 are MOSFETs. Each semiconductor element 1 and 2 switches between a conducting state (on state) and a blocking state (off state) based on drive signals GH and GL input to the gate. The two semiconductor elements 1 and 2 form a half-bridge switching circuit, with semiconductor element 1 serving as the upper arm and semiconductor element 2 serving as the lower arm.

[0119] The drain of the semiconductor element 1 is connected to the external terminal T3, and the source of the semiconductor element 1 is connected to the drain of the semiconductor element 2. The gate of the semiconductor element 1 is connected to the control element 3 (connection terminal TC5 described later).

[0120] The semiconductor element 1 performs switching operation in accordance with a drive signal GH (first drive signal) inputted from the control element 3 to the gate. The semiconductor element 1 is in an on state when the drive signal GH inputted to the gate is at a high level, and is in an off state when the drive signal GH inputted to the gate is at a low level. Further, the semiconductor element 1 is of a normally-off type, but can be of a normally-on type.

[0121] The drain of the semiconductor element 2 is connected to the source of the semiconductor element 1, and the source of the semiconductor element 2 is connected to the external terminal T4. The gate of the semiconductor element 2 is connected to the control element 3 (connection terminal TC6 described later).

[0122] The semiconductor element 2 performs switching operation in accordance with a drive signal GL (second drive signal) inputted from the control element 3 to the gate. The semiconductor element 2 is in an on state when the drive signal GL inputted to the gate is at a high level, and is in an off state when the drive signal GL inputted to the gate is at a low level. Further, the semiconductor element 2 is of a normally-off type, but can be of a normally-on type.

[0123] The connection point of the source of the semiconductor element 1 and the drain of the semiconductor element 2 is connected to the external terminal T7, and is connected to the control element 3 (connection terminal TC8 described later). By the switching operation of the semiconductor element 1 and the switching operation of the semiconductor element 2, the output voltage V SW .

[0124] The control element 3 mainly controls the switching operations of the two semiconductor elements 1, 2. The control element 3 generates the respective drive signals GH, GL in accordance with the respective control signals SH, SL inputted, and inputs the generated respective drive signals GH, GL to the respective semiconductor elements 1, 2. The control element 3 includes a plurality of connection terminals TC1 to TC8, two drive circuits DR1, DR2, and a diode D1 in its internal circuit. The control element 3 is an IC in which the two drive circuits DR1, DR2 and the diode D1 are one-chip-ized.

[0125] The connection terminal TC1 is connected to the external terminal T1, and is an input terminal of the power supply voltage VCC in the control element 3. The connection terminal TC1 corresponds to the element electrode 31 in the module configuration of the semiconductor device Al. Therefore, the power supply voltage VCC is inputted to the element electrode 31.

[0126] The connection terminal TC2 is connected to the external terminal T2 and is connected to the first ground terminal GND1. The connection terminal TC2 corresponds to the element electrode 32 in the module configuration of the semiconductor device Al. Therefore, the element electrode 32 is connected to the first ground terminal GND1.

[0127] The connection terminal TC3 is connected to the external terminal T5 and is an input terminal of the control signal SH in the control element 3. The connection terminal TC3 corresponds to the element electrode 33 in the module configuration of the semiconductor device Al. Therefore, the control signal SH is input to the element electrode 33.

[0128] The connection terminal TC4 is connected to the external terminal T6 and is an input terminal of the control signal SL in the control element 3. The connection terminal TC4 corresponds to the element electrode 34 in the module configuration of the semiconductor device Al. Therefore, the control signal SL is input to the element electrode 34.

[0129] The connection terminal TC5 is an output terminal of the drive signal GH. The connection terminal TC5 is connected to the gate of the semiconductor element 1. The connection terminal TC5 corresponds to the element electrode 35 in the module configuration of the semiconductor device Al. Therefore, the drive signal GH is output from the element electrode 35.

[0130] The connection terminal TC6 is an output terminal of the drive signal GL. The connection terminal TC6 is connected to the gate of the semiconductor element 2. The connection terminal TC6 corresponds to the element electrode 36 in the module configuration of the semiconductor device Al. Therefore, the drive signal GL is output from the element electrode 36.

[0131] The connection terminal TC7 is connected to the external terminal T8 and is an input terminal of the start voltage VB in the control element 3. The connection terminal TC7 corresponds to the element electrode 37 in the module configuration of the semiconductor device Al. Therefore, the start voltage VB is input to the element electrode 37.

[0132] The connection terminal TC8 is connected to the connection point of the semiconductor element 1 (source) and the semiconductor element 2 (drain) and is an input terminal of the output voltage V SW . The connection terminal TC8 corresponds to the element electrode 38 in the module configuration of the semiconductor device Al. Therefore, the output voltage V SW is input from the element electrode 38.

[0133] Drive circuit DR1 generates drive signal GH based on input control signal SH. Drive signal GH is a signal used to cause semiconductor element 1 to switch, and is a signal that raises control signal SH to the level required for switching of semiconductor element 1. Drive circuit DR1 outputs the generated drive signal GH from connection terminal TC5. Connection terminal TC5 is connected to the gate of semiconductor element 1, so drive signal GH is input to the gate of semiconductor element 1. Drive signal GH is a signal that causes startup voltage VB to be high and the source voltage of semiconductor element 1 to be low. The source voltage of semiconductor element 1 is input to drive circuit DR1 via connection terminal TC8. The gate voltage of semiconductor element 1 is referenced by the source voltage of semiconductor element 1. Alternatively, drive circuit DR1 can be configured external to control element 3.

[0134] The drive circuit DR2 generates a drive signal GL based on the input control signal SL. The drive signal GL is a signal for switching the semiconductor element 2 and is a signal that increases the control signal SL to the level required for the switching operation of the semiconductor element 2. The drive circuit DR2 outputs the generated drive signal GL from the connection terminal TC6. The connection terminal TC6 is connected to the gate of the semiconductor element 2, so the drive signal GL is input to the gate of the semiconductor element 2. The drive signal GL is a signal that increases the power supply voltage VCC to a high level and the ground voltage V GND The gate voltage of the semiconductor element 2 is provided with the ground voltage V GND In addition, the drive circuit DR2 may be arranged outside the control element 3 .

[0135] The anode of diode D1 is connected to connection terminal TC1, and the cathode is connected to connection terminal TC7. Diode D1 and capacitor C14 together form a bootstrap circuit. The bootstrap circuit generates a startup voltage VB and supplies it to drive circuit DR1. Alternatively, diode D1 can be located external to control element 3.

[0136] Next, an operation example of the semiconductor device A1 will be described.

[0137] The semiconductor device Al generates drive signals GH, GL through the control element 3 when inputting control signals SH, SL from the external terminals T5, T6 to the control element 3. Further, each drive signal GH, GL is inputted from the control element 3 to each gate of the semiconductor elements 1, 2. The semiconductor device Al alternately repeats a first period in which the semiconductor element 1 is in an on state and the semiconductor element 2 is in an off state, and a second period in which the semiconductor element 1 is in an off state and the semiconductor element 2 is in an on state, through each drive signal GH, GL. At this time, in the first period, the input voltage Vin is applied to the external terminal T7. On the other hand, in the second period, the external terminal T7 is connected to the reference potential ground (the ground voltage V GND is applied to the external terminal T7). Thus, the output voltage V SW from the external terminal T7 is a pulse wave in which the high level is the input voltage Vin and the low level is the ground voltage V GND . Further, the output voltage V SW is smoothed through the inductor LI and the capacitor C13, and thus, is converted into a direct-current voltage, the output voltage Vout. The semiconductor device Al operates as described above, and thus, converts (steps down) the input voltage Vin into the output voltage Vout.

[0138] The first period and the second period are alternately repeated at a prescribed period, and the step-down ratio can be changed according to the ratio of the first period to the second period in 1 period. For example, when the first period is 25% of 1 period (the second period is 75% of 1 period), the output voltage Vout is stepped down to 1 / 4 of the input voltage Vin (Vout = Vin x (25 / 100)). Further, a dead time in which both the semiconductor elements 1, 2 are in an off state can be provided between the first period and the second period.

[0139] Figure 11 and Figure 10 is a structure example of the power conversion device Wl, and shows a state in which electronic components including the semiconductor device Al are mounted on the circuit substrate Bl. Figure 11 is a perspective view showing the power conversion device Wl. Figure 10 is a plan view showing the power conversion device Wl. In Figure 11 and Figure 10 , the semiconductor device Al is shown by a virtual line (double-dot chain line). Further, in Figure 11 and Figure 10 , a part of the power conversion device Wl is shown, and all of the electronic components and the wiring pattern are not described. For example, the inductor LI, the capacitor C13, and the like are omitted.

[0140] The circuit substrate B1 is, for example, a printed substrate such as a glass epoxy substrate. The circuit substrate B1 can be any one of a single-sided substrate having one layer, a double-sided substrate having two layers, and a multilayer substrate having three or more layers. The circuit substrate B1 mounts the respective electronic components in the power conversion device W1. In Figure 11 and Figure 9 In the example shown in FIG. 9, a plurality of capacitors C11, C12, and C14 are mounted in the circuit substrate B1 in addition to the semiconductor device A1. A plurality of wiring patterns 91 to 98 are formed in the circuit substrate B1. The constituent material of each of the wiring patterns 91 to 98 is, for example, a metal including copper. The plurality of wiring patterns 91 to 98 are part of the wiring in the circuit diagram shown in FIG. 9. The plurality of wiring patterns 91 to 98 are separated from each other. Figure 9

[0141] The wiring pattern 91 is joined to the lead 4A and is in conduction with the lead 4A. The output voltage V SW (voltage generated by the respective switching operations of the semiconductor element 1 and the semiconductor element 2) is applied to the wiring pattern 91 via the lead 4A.

[0142] The wiring pattern 92 is joined to the lead 4B and is in conduction with the lead 4B. The wiring pattern 92 is grounded to the second ground terminal GND2 (reference potential). Therefore, the lead 4B, the plurality of conductive lines 5D, and the source electrode 22 are also grounded to the second ground terminal GND2 (reference potential).

[0143] The wiring pattern 93 is joined to the lead 4C and is in conduction with the lead 4C. The wiring pattern 93 is connected to the terminal of the high potential side of the external power supply PS2 and is applied with the input voltage Vin. The input voltage Vin applied to the wiring pattern 93 is transmitted to the lead 4C and is input to the drain electrode 11 via the plurality of conductive lines 5A.

[0144] The wiring pattern 94 is joined to the lead 4D and is in conduction with the lead 4D. The wiring pattern 94 is grounded to the first ground terminal GND1 (reference potential). Therefore, the lead 4D, the conductive line 5H, and the element electrode 32 are also grounded to the first ground terminal GND1 (reference potential).

[0145] The wiring pattern 95 is joined to the lead 4E and is in conduction with the lead 4E. The start voltage VB is applied to the wiring pattern 95. The start voltage VB input to the wiring pattern 95 is transmitted to the lead 4E and is input to the element electrode 37 of the control element 3 via the conductive line 51.

[0146] The wiring pattern 96 is joined to the lead 4F and is in conduction with the lead 4F. The wiring pattern 96 is connected to the terminal of the high potential side of the external power supply PS1 and is applied with the power supply voltage VCC. The power supply voltage VCC applied to the wiring pattern 96 is transmitted to the lead 4F and is input to the element electrode 31 of the control element 3 via the conductive line 5J. ​

[0147] The wiring pattern 97 is joined to the lead 4G and is in conduction with the lead 4G. The wiring pattern 97 is input with a control signal SH. The control signal SH input to the wiring pattern 97 is transmitted to the lead 4G and is input to the element electrode 33 of the control element 3 via the lead 5K.

[0148] The wiring pattern 98 is joined to the lead 4H and is in conduction with the lead 4H. The wiring pattern 98 is input with a control signal SL. The control signal SL input to the wiring pattern 98 is transmitted to the lead 4H and is input to the element electrode 34 of the control element 3 via the lead 5L.

[0149] Each of the above-mentioned joining of each of the wiring patterns 91 to 98 to each of the leads 4A to 4H is achieved, for example, by solder (omitted from the drawing).

[0150] The capacitor C11 spans the wiring pattern 94 and the wiring pattern 96 in a plan view. The capacitor C11 includes two terminals, one of which is joined to the wiring pattern 94 and the other of which is joined to the wiring pattern 96. These joining is achieved, for example, by solder (omitted from the drawing). The lead 4D and the lead 4F are in conduction via the capacitor C11. Thus, as shown in the circuit diagram of FIG. 6, the capacitor C11 is connected between the external terminal Tl and the external terminal T2 (the first ground terminal GNDl). Figure 9

[0151] The capacitor C12 spans the wiring pattern 92 and the wiring pattern 93 in a plan view. The capacitor C12 includes two terminals, one of which is joined to the wiring pattern 92 and the other of which is joined to the wiring pattern 93. These joining is achieved, for example, by solder (omitted from the drawing). The lead 4B and the lead 4C are in conduction via the capacitor C12. Thus, as shown in the circuit diagram of FIG. 7, the capacitor C12 is connected between the external terminal T3 and the external terminal T4 (the second ground terminal GND2). Figure 9

[0152] The capacitor C14 spans the wiring pattern 91 and the wiring pattern 95 in a plan view. The capacitor C14 includes two terminals, one of which is joined to the wiring pattern 91 and the other of which is joined to the wiring pattern 95. These joining is achieved, for example, by solder (omitted from the drawing). The lead 4A and the lead 4E are in conduction via the capacitor C14. Thus, as shown in the circuit diagram of FIG. 8, the capacitor C14 is connected between the external terminal T7 and the external terminal T8. Figure 12

[0153] The semiconductor device Al configured as described above has the following effects.

[0154] ​​​The semiconductor device Al has a lead 4A, a lead 4B, and a lead 4C. The lead 4C is in conduction with the drain electrode 11 of the semiconductor element 1, the lead 4A is in conduction with the source electrode 12 of the semiconductor element 1 and the drain electrode 21 of the semiconductor element 2, and the lead 4B is in conduction with the source electrode 22 of the semiconductor element 2. The lead 4A and the lead 4B are adjacent to each other in the x direction as viewed in the z direction, and the lead 4C is adjacent to each of the lead 4A and the lead 4B as viewed in the z direction. According to this structure, the lead 4A, the lead 4B, and the lead 4C can be arranged in close proximity. Therefore, the wiring of the path (power system current path) of the current flowing from the lead 4C via the drain electrode 11-source electrode 12 of the semiconductor element 1, the lead 4A, and the drain electrode 21-source electrode 22 of the semiconductor element 2 to the lead 4B can be shortened. Therefore, the semiconductor device Al can achieve reduction of parasitic inductance and parasitic resistance, and thus, can achieve high efficiency and energy saving.

[0155] With regard to the semiconductor device Al, in the semiconductor element 1, the plurality of pad portions 111 (drain electrodes 11) and the plurality of pad portions 121 (source electrodes 12) respectively extend in the first extension direction. In addition, in the semiconductor element 2, the plurality of pad portions 211 (drain electrodes 21) and the plurality of pad portions 221 (source electrodes 22) respectively extend in the second extension direction. Further, the second extension direction is inclined with respect to the first extension direction. The inclination angle is, for example, 10° or more and 170° or less. Assume that the first extension direction and the second extension direction are the same, and the semiconductor element 1 and the semiconductor element 2 are arranged in the same direction as these extension directions. At this time, when the wiring is shortened to a plurality of leads 5A to 5D, the lead 4C and the lead 4B are located on opposite sides of each other with the lead 4A therebetween in the above extension direction. On the other hand, in the semiconductor device Al, the second extension direction is inclined with respect to the first extension direction, and thus, the lead 4B can be arranged in the vicinity of the lead 4C. Therefore, the wiring of the above power system current path can be shortened.

[0156] Semiconductor device A1 includes: lead 4A for mounting semiconductor element 1, lead 4B for mounting semiconductor element 2, and lead 4D for mounting control element 3. Lead 4A and lead 4B overlap when viewed in the x-direction, while lead 4D overlaps both lead 4A and lead 4B when viewed in the y-direction. This structure allows the separation distance between semiconductor element 1 and semiconductor element 2 to be shortened compared to the semiconductor device described in Patent Document 1. Specifically, in the semiconductor device described in Patent Document 1, two semiconductor elements (switching elements) are arranged on opposite sides of each other with a control element (control IC) sandwiched between them in a top view. Therefore, wiring must be performed to connect the two semiconductor elements, avoiding the control element, and the wiring distance tends to be longer. On the other hand, in semiconductor device A1, no control element 3 is arranged between semiconductor element 1 and semiconductor element 2. Therefore, the wiring distance connecting semiconductor element 1 and semiconductor element 2 can be shortened (in this embodiment, the lengths of each wire 5B, 5C and a portion of lead 4A). Therefore, the semiconductor device A1 can achieve reductions in parasitic inductance and parasitic resistance, thereby achieving improved efficiency and energy saving.

[0157] Regarding semiconductor device A1, leads 4A and 4B are both arranged closer to lead 4D in the y2 direction and overlap with lead 4D when viewed in the y direction. Therefore, semiconductor element 1 and semiconductor element 2 can be arranged on one side in the y direction, and control element 3 can be arranged on the other side in the y direction. When semiconductor device A1 is powered on, semiconductor elements 1, 2 and control element 3 generate heat. The heat generated by semiconductor elements 1, 2 is greater than the heat generated by control element 3. When the heat from semiconductor elements 1, 2 is transferred to control element 3, the transferred heat may cause malfunction or performance degradation of control element 3. However, semiconductor device A1 arranges leads 4A, 4B on one side of lead 4D in the y direction (y2 direction side), thereby separating semiconductor elements 1, 2 and control element 3. As a result, semiconductor device A1 can suppress the heat transferred from semiconductor elements 1, 2 to control element 3, thereby suppressing malfunction and performance degradation of control element 3.

[0158] Semiconductor device A1 includes a wire 5E that, when viewed from above, overlaps only with leads 4A and 4D of leadframe 4. This structure eliminates the need for other leads between semiconductor element 1 and control element 3, reducing the distance between them. Consequently, the length of wire 5E can be shortened, minimizing parasitic inductance and resistance in wire 5E. In particular, wire 5E transmits a drive signal (drive signal GH) that controls the switching operation of semiconductor element 1. This reduces the likelihood of malfunctioning or reducing the responsiveness of the switching operation of semiconductor element 1.

[0159] The semiconductor device Al has a wire 5F that overlaps only the lead 4A and the lead 4D in the lead frame 4 in a plan view. According to this structure, no other lead is arranged between the semiconductor element 2 and the control element 3, and thus the separation distance between the semiconductor element 2 and the control element 3 can be reduced. Thus, the length of the wire 5F can be shortened, and thus the parasitic inductance and the parasitic resistance of the wire 5F can be suppressed. In particular, the wire 5F is a transmission line of a drive signal (a drive signal GL) that controls the switching operation of the semiconductor element 2, and thus the reduction in responsiveness of the switching operation of the semiconductor element 2 and the malfunction of the switching operation can be suppressed.

[0160] In the first embodiment, the case where both the first ground terminal GND1 and the second ground terminal GND2 are ground terminals with respect to the same reference potential is shown, but the reference potential of the first ground terminal GND1 can be made different from the reference potential of the second ground terminal GND2. In the semiconductor device Al, the potential of the second ground terminal GND2 can fluctuate due to the respective switching operations of the semiconductor element 1 and the semiconductor element 2. At this time, assume a case where the potential of the first ground terminal GND1 also fluctuates in accordance with the fluctuation in the potential of the second ground terminal GND2 when the first ground terminal GND1 and the second ground terminal GND2 are the same potential. This fluctuation in the first ground terminal GND1 is a cause of the malfunction of the control element 3. Thus, by making the potential of the first ground terminal GND1 different from the potential of the second ground terminal GND2, even if the potential of the second ground terminal GND2 fluctuates, the fluctuation in the potential of the first ground terminal GND1 can be suppressed. Thus, in this modified example, the malfunction of the control element 3 can be suppressed. For example, in the semiconductor device Al, the lead 4D that is grounded to the first ground terminal GND1 and the lead 4B that is grounded to the second ground terminal GND2 are separated, and thus the potentials of the first ground terminal GND1 (the lead 4D) and the second ground terminal GND2 (the lead 4B) can be made different.

[0161] Next, the semiconductor device A2 of the second embodiment will be described with reference to Figure 13 and Figure 12 . Figure 13 is a plan view that shows a power conversion device W2 having the semiconductor device A2, and a sealing member 6 is shown by a broken line (double-dot chain line). Figure 12 is a circuit configuration diagram of the power conversion device W2.

[0162] As shown in Figure 13 and Figure 12 , the semiconductor device A2 further has a plurality of capacitors C21, C22, C24, C25, C26, C27 compared to the semiconductor device Al. In addition, the power conversion device W2 further has a plurality of resistors R15, R16 compared to the power conversion device W1.

[0163] Capacitor C21 has two terminals, such as Figure 13 As shown, one terminal is connected to the lead 4D, and the other terminal is connected to the lead 4F. Thus, the lead 4D and the lead 4F are connected via the wiring patterns 94, 96 and the capacitor C11 as in the first embodiment, and are also connected via the capacitor C21. Figure 12 As shown, capacitor C21 is connected in parallel with capacitor C11. The capacitor C21 is connected by solder (not shown), for example. Capacitor C21 is covered by sealing member 6 and is built into semiconductor device A2. Figure 12 In the example shown, there is one capacitor C21, but it is also possible to have multiple capacitors C21. At this time, multiple capacitors C21 are respectively joined to lead 4D and lead 4F. The capacity of capacitor C21 (their combined capacity in the case of multiple capacitors C21) is less than the capacity of capacitor C11 (their combined capacity in the case of multiple capacitors C11), and the top-view area of ​​capacitor C21 is less than the top-view area of ​​capacitor C11. In addition, the structure (capacity, top-view area, etc.) of capacitor C21 is not limited to this. Capacitor C21 is equivalent to the "third capacitor" described in the claims.

[0164] Capacitor C22 has two terminals, such as Figure 13 As shown, one terminal is connected to the lead 4B, and the other terminal is connected to the lead 4C. Thus, the lead 4B and the lead 4C are connected via the wiring patterns 92, 93 and the capacitor C12 as in the first embodiment, and are also connected via the capacitor C22. Figure 12 As shown, capacitor C22 is connected in parallel with capacitor C12. In addition, the connection of capacitor C22 is realized by solder (omitted from the figure). Capacitor C22 is covered by sealing member 6 and built into semiconductor device A2. Figure 12 In the example shown, there is one capacitor C22, but it is also possible to have multiple capacitors C22. At this time, multiple capacitors C22 are respectively engaged with lead 4B and lead 4C. The capacity of capacitor C22 (their combined capacity in the case of multiple capacitors C22) is less than the capacity of capacitor C12 (their combined capacity in the case of multiple capacitors C12), and the top view area of ​​capacitor C22 is less than the top view area of ​​capacitor C12. In addition, the structure (capacity, top view area, etc.) of capacitor C22 is not limited to this. Capacitor C22 is equivalent to the "first capacitor" described in the claims.

[0165] Capacitor C24 has two terminals, such as Figure 13 As shown, one terminal is connected to the lead 4A, and the other terminal is connected to the lead 4E. As a result, the lead 4A and the lead 4E are connected through the wiring patterns 91, 95 and the capacitor C14 as in the first embodiment, and are also connected through the capacitor C24.Figure 12 As shown, capacitor C24 is connected in parallel with capacitor C14. In addition, the connection of capacitor C24 is realized by solder (omitted from the figure). Capacitor C24 is covered by sealing member 6 and built into semiconductor device A2. Figure 12 In the example shown, there is one capacitor C24, but it is also possible to have multiple capacitors C24. At this time, multiple capacitors C24 are respectively joined to lead 4A and lead 4E. The capacity of capacitor C24 (their combined capacity in the case of multiple capacitors C24) is less than the capacity of capacitor C14 (their combined capacity in the case of multiple capacitors C14), and the top view area of ​​capacitor C24 is less than the top view area of ​​capacitor C14. In addition, the structure (capacity, top view area, etc.) of capacitor C24 is not limited to this. Capacitor C24 is equivalent to the "second capacitor" described in the claims.

[0166] Capacitor C25 has two terminals, such as Figure 12 As shown, one terminal is connected to the lead 4D, and the other terminal is connected to the lead 4G. Thus, the lead 4D and the lead 4G are connected via the capacitor C25. In addition, the connection of the capacitor C25 is achieved by solder (omitted from the figure). The capacitor C25 is covered by the sealing component 6 and is built into the semiconductor device A2. Figure 12 In the example shown, there is one capacitor C25, but multiple capacitors C25 may be provided. In this case, the multiple capacitors C25 are connected to the lead 4D and the lead 4G respectively. The capacitor C25 corresponds to the "fourth capacitor" described in the claims.

[0167] Capacitor C26 includes two terminals, such as Figure 12 As shown, one terminal is connected to the lead 4D, and the other terminal is connected to the lead 4H. Thus, the lead 4D and the lead 4H are connected via the capacitor C26. In addition, the connection of the capacitor C26 is achieved by solder (omitted from the figure). The capacitor C26 is covered by the sealing component 6 and is built into the semiconductor device A2. Figure 12 In the example shown, there is one capacitor C26, but multiple capacitors C26 may be provided. In this case, the multiple capacitors C26 are connected to the lead 4D and the lead 4H respectively. The capacitor C26 corresponds to the "fifth capacitor" described in the claims.

[0168] Capacitor C27 has two terminals, such as Figure 12 As shown, one terminal is connected to the lead 4B, and the other terminal is connected to the lead 4D. Thus, the lead 4B and the lead 4D are connected via the capacitor C27. In addition, the connection of the capacitor C27 is achieved by solder (omitted from the figure). The capacitor C27 is covered by the sealing component 6 and is built into the semiconductor device A2. Figure 12In the illustrated example, one capacitor C27 is provided, but a plurality of capacitors C27 can also be provided. In this case, the plurality of capacitors C27 are respectively connected to the lead 4B and the lead 4D. The capacitor C27 corresponds to the "sixth capacitor" recited in the claims.

[0169] The resistor R15 includes two terminals, as Figure 13 As illustrated, one terminal is connected to the wiring pattern 97, and the other terminal is connected to a wiring pattern 971 separated from each of the wiring patterns 91 to 98. Thereby, the wiring pattern 97 and the wiring pattern 971 are conducted via the resistor R15. Further, the connection of the resistor R15 is achieved by, for example, solder (omitted from illustration). As Figure 12 As illustrated, the resistor R15 and the capacitor C25 constitute an RC filter. This RC filter suppresses noise contained in the control signal SH inputted from the outside. Further, an inductor can be used instead of the resistor R15 to constitute an LC filter.

[0170] The resistor R16 includes two terminals, as Figure 13 As illustrated, one terminal is connected to the wiring pattern 98, and the other terminal is connected to a wiring pattern 981 separated from each of the wiring patterns 91 to 98. Thereby, the wiring pattern 98 and the wiring pattern 981 are conducted via the resistor R16. Further, the connection of the resistor R16 is achieved by, for example, solder (omitted from illustration). As Figure 14 As illustrated, the resistor R16 and the capacitor C26 constitute an RC filter. This RC filter suppresses noise contained in the control signal SL inputted from the outside. Further, an inductor can be used instead of the resistor R16 to constitute an LC filter.

[0171] The semiconductor device A2 configured as described above has the following effects.

[0172] The semiconductor device A2 is the same as the semiconductor device Al in that the lead 4A and the lead 4B are adjacent to each other in the x direction when viewed in the z direction, and the lead 4C is adjacent to each of the lead 4A and the lead 4B when viewed in the z direction. Thereby, the semiconductor device A2 is the same as the semiconductor device Al in that the wiring of the above-described power system current path can be shortened. Therefore, the semiconductor device A2 can achieve reduction of parasitic inductance and parasitic resistance, and thus, can achieve high efficiency and energy saving.

[0173] The semiconductor device A2 has the capacitor C21. In the semiconductor device Al, the lead 4D and the lead 4F are conducted via the circuit substrate Bl (the wiring patterns 94, 96, and the capacitor C11), but in the semiconductor device A2, the lead 4D and the lead 4F are also conducted via the capacitor C21. According to this structure, the current path between the gate electrode 23 and the source electrode 22 of the semiconductor element 2 is smaller than the power conversion device Wl. Therefore, the semiconductor device A2 can suppress a surge voltage applied to the semiconductor element 2, and can suppress a problem caused by the surge voltage.

[0174] The semiconductor device A2 has the capacitor C22. In the semiconductor device Al, the lead 4B and the lead 4C are conducted via the circuit substrate Bl (the wiring patterns 92, 93, and the capacitor C12), but in the semiconductor device A2, the lead 4B and the lead 4C are also conducted via the capacitor C22. According to this structure, the above-described power system current path is smaller than the power conversion device Wl. Therefore, the semiconductor device A2 can reduce a parasitic inductance and a parasitic resistance in the power system current path compared with the semiconductor device Al, and can suppress generation of a surge voltage.

[0175] The semiconductor device A2 has the capacitor C24. In the semiconductor device Al, the lead 4A and the lead 4E are conducted via the circuit substrate Bl (the wiring patterns 91, 95, and the capacitor C14), but in the semiconductor device A2, the lead 4A and the lead 4E are also conducted via the capacitor C24. According to this structure, the current path between the gate electrode 13 and the source electrode 12 of the semiconductor element 1 is smaller than the power conversion device W2. Therefore, the semiconductor device A2 can suppress a surge voltage applied to the semiconductor element 1, and can suppress a problem caused by the surge voltage.

[0176] The semiconductor device A2 has the capacitor C25, and the circuit substrate Bl has the resistor R15. According to this structure, in the power conversion device W2, an RC filter is formed by the capacitor C25 and the resistor R15. As described above, the RC filter can reduce noise contained in the drive signal GH input to the semiconductor element 1. Therefore, the semiconductor device A2 can stabilize the switching operation of the semiconductor element 1 compared with the semiconductor device Al.

[0177] The semiconductor device A2 has the capacitor C26, and the circuit substrate Bl has the resistor R16. According to this structure, in the power conversion device W2, an RC filter is formed by the capacitor C26 and the resistor R16. As described above, the RC filter can reduce noise contained in the drive signal GL input to the semiconductor element 2. Therefore, the semiconductor device A2 can stabilize the switching operation of the semiconductor element 2 compared with the semiconductor device Al.

[0178] Semiconductor device A2 includes capacitor C27. If, without capacitor C27, lead 4B and lead 4D were to be electrically conductive, wiring would be necessary through circuit board B1. In this case, wiring would need to avoid other wiring patterns, which would tend to increase the length of the wiring. However, in semiconductor device A2, capacitor C27 provides electrical conductivity between lead 4B and lead 4D, shortening the current path between leads 4B and 4D. Consequently, semiconductor device A2 can shorten the current path between leads 4B and 4D, thereby preventing mis-conduction of semiconductor elements 1 and 2.

[0179] Furthermore, the semiconductor device A2 has the same components as those of the semiconductor device A1 and thus achieves the same effects as those of the semiconductor device A1.

[0180] In the second embodiment, the semiconductor device A2 includes all of the capacitors C21, C22, C24, C25, C26, and C27, but it does not need to include all of them. In other words, the semiconductor device A2 may have a structure including at least one of the capacitors C21, C22, C24, C25, C26, and C27.

[0181] In the second embodiment, the power conversion device W2 includes a capacitor C11. However, if the capacitance of the capacitor C21 of the semiconductor device A2 (or the combined capacitance of multiple capacitors C21 if multiple capacitors C21 are included) is appropriately large, the capacitor C11 may not be mounted on the circuit board B1. Similarly, if the capacitance of the capacitor C22 of the semiconductor device A2 (or the combined capacitance of multiple capacitors C22 if multiple capacitors C22 are included) is appropriately large, the capacitor C12 may not be mounted on the circuit board B1. Furthermore, if the capacitance of the capacitor C24 of the semiconductor device A2 (or the combined capacitance of multiple capacitors C24 if multiple capacitors C24 are included) is appropriately large, the capacitor C14 may not be mounted on the circuit board B1.

[0182] Next, refer to Figure 14 A semiconductor device A3 according to the third embodiment will be described. Figure 14 FIG is a top view showing a power conversion device W3 having a semiconductor device A3, and a sealing member 6 is shown by an imaginary line (two-dot chain line). Figure 14 In the semiconductor device A3 shown, the number and wire diameters of the plurality of wires 5A, 5B, 5C, and 5D are different from those of the semiconductor device A1, but these may be configured similarly to the semiconductor device A1.

[0183] The semiconductor element 1 of the semiconductor device A3 has higher performance (e.g., lower on-resistance) than the semiconductor element 2 of the semiconductor device A3, and has higher performance (e.g., lower on-resistance) than the semiconductor element 1 of the semiconductor device A1. Figure 14As shown, the top view area of ​​semiconductor element 1 of semiconductor device A3 is larger than that of semiconductor element 2 of semiconductor device A3 and larger than that of semiconductor element 1 of semiconductor device A1. Furthermore, semiconductor element 2 of semiconductor device A3 is identical to semiconductor element 2 of semiconductor device A1.

[0184] like Figure 14 As shown, the semiconductor element 1 of the semiconductor device A3 differs from the semiconductor element 1 of the semiconductor device A1 in the structure of each electrode (drain electrode 11 and source electrode 12). Specifically, the planar shape of each pad portion 111, 121 is different.

[0185] like Figure 14 As shown, each pad portion 111 of the semiconductor device A3 has a tapered shape. Specifically, each pad portion 111 extends from the end edge of the y2 direction side toward the end edge of the y1 direction side in the y direction, and the size in the x direction is small. Each pad portion 111 is roughly triangular in a top view. Similar to each pad portion 111, each pad portion 121 also has a tapered shape. Specifically, each pad portion 121 extends from the end edge of the y1 direction side toward the end edge of the y2 direction side in the y direction, and the size in the x direction is small. Each pad portion 121 is roughly triangular in a top view. In addition, in the semiconductor device A3, the plurality of pad portions 111 and 121 are also respectively extended in the first extension direction (in Figure 14 y direction in the middle) and extends in the first arrangement direction (in the Figure 15 They are arranged alternately in the x direction).

[0186] The semiconductor device A3 constructed as described above has the following effects.

[0187] Similar to semiconductor device A1, semiconductor device A3 has leads 4A and 4B adjacent to each other in the x-direction when viewed in the z-direction, and lead 4C adjacent to each of leads 4A and 4B when viewed in the z-direction. Consequently, similar to semiconductor device A1, semiconductor device A3 can shorten the wiring of the power system current path. Consequently, semiconductor device A3 can reduce parasitic inductance and parasitic resistance, thereby achieving improved efficiency and energy savings.

[0188] The on-resistance of semiconductor element 1 in semiconductor device A3 is lower than that of semiconductor element 2, and lower than that of semiconductor element 1 in semiconductor device A1. Due to this structure, the conduction loss in semiconductor element 1 is lower than that in semiconductor element 2, and lower than that in semiconductor element 1 in semiconductor device A1. Therefore, semiconductor device A3 can reduce the conduction loss in semiconductor element 1 compared to semiconductor device A1. This reduction in conduction loss is particularly effective when semiconductor device A3 is used in a boost circuit.

[0189] The planar area of the semiconductor element 1 of the semiconductor device A3 is larger than that of the semiconductor device Al. According to this configuration, the semiconductor device A3 has a larger area of the element main surface la of the semiconductor element 1 than the semiconductor device Al, and thus, heat dissipation from the element main surface la can be improved. That is, the semiconductor device A3 can reduce the thermal resistance of the semiconductor element 1 compared to the semiconductor device Al.

[0190] Further, the semiconductor device A3 has the same effects as the semiconductor device Al through the portions configured similarly to the semiconductor device Al. Further, in the semiconductor device A3, similarly to the semiconductor device A2, the same effects as the semiconductor device A2 can be obtained by additionally providing the plurality of capacitors C21, C22, C24, C25, C26, and C27.

[0191] Figure 15 A modification of the semiconductor device A3 of the third embodiment is shown. The semiconductor device A31 of this modification has a larger planar area of the lead 4A than the semiconductor device A3. Specifically, the lead 4A (see Figure 14 ) of the semiconductor device A31 has, for example, an expanded region ER1 (indicated by a dot in Figure 15 ) added compared to the lead 4A (see Figure 15 ) of the semiconductor device A3. Further, with the addition of this expanded region ER1, the lead 4B is also expanded in plan view.

[0192] According to the semiconductor device A31, the planar area of the lead 4A is larger than that of the semiconductor device A3. Thereby, the heat conduction efficiency from the lead 4A to the wiring pattern 91 of the circuit substrate Bl can be improved. That is, in the semiconductor device A31, heat from the semiconductor element 1 can be dissipated from both the element main surface la and the element back surface lb. In particular, by setting the planar area of the lead 4A to be 1.1 times or more and 5 times or less of the planar area of the semiconductor element 1, the suppression of the increase in size of the semiconductor device A31 can be achieved, and the improvement of the heat conduction efficiency from the lead 4A to the wiring pattern 91 can be achieved.

[0193] In addition, as shown in Figure 16 , in plan view, the distance between the center of the semiconductor element 1 and the center of the control element 3 is smaller than the distance between the center of the lead 4A and the center of the control element 3. For ease of understanding, in Figure 16In the center of the plan view of the semiconductor element 1, the center of the plan view of the lead 4A, and the center of the plan view of the control element 3, respectively, a cross (cross mark) is marked. That is, in the plan view, the semiconductor element 1 is arranged in the vicinity of the control element 3. According to this structure, the length of the lead wire 5E can be shortened, and thus the parasitic inductance and the parasitic resistance of the lead wire 5E can be reduced.

[0194] Next, the semiconductor device A4 according to the fourth embodiment will be described with reference to Figure 16 to FIG. 14. Figure 16 is a plan view of a power conversion device W4 including the semiconductor device A4, and a sealing member 6 is indicated by a broken line (double-dot chain line). Further, in Figure 16 the semiconductor device A4, the number and the wire diameter of the plurality of lead wires 5A, 5B, 5C, and 5D are different from those of the semiconductor device Al, but these can be configured similarly to the semiconductor device Al.

[0195] The semiconductor element 2 of the semiconductor device A4 is higher in performance (for example, smaller in on-resistance) than the semiconductor element 1 of the semiconductor device A4, and is higher in performance (for example, smaller in on-resistance) than the semiconductor element 2 of the semiconductor device Al. Further, as shown in Figure 16 , the planar area of the semiconductor element 2 of the semiconductor device A4 is larger than the planar area of the semiconductor element 1 of the semiconductor device A4, and is larger than the planar area of the semiconductor element 2 of the semiconductor device Al. Further, the semiconductor element 1 of the semiconductor device A4 is the same as the semiconductor element 1 of the semiconductor device Al.

[0196] As shown in Figure 16 , the structure of each electrode (drain electrode 21 and source electrode 22) of the semiconductor element 2 of the semiconductor device A4 is different from that of the semiconductor element 2 of the semiconductor device Al. Specifically, the planar shape of each pad portion 211, 221 is different.

[0197] As shown in Figure 16 , each pad portion 211 of the semiconductor device A4 has a taper shape. Specifically, each pad portion 211 is smaller in the y direction from the end edge on the x2 direction side toward the end edge on the xl direction side. Each pad portion 211 is substantially triangular in the plan view. Similarly to each pad portion 211, each pad portion 221 also has a taper shape. Specifically, each pad portion 221 is smaller in the y direction from the end edge on the xl direction side toward the end edge on the x2 direction side. Each pad portion 221 is substantially triangular in the plan view. Further, in the semiconductor device A4, the plurality of pad portions 211, 221 also respectively extend in the second extension direction (x direction in Figure 16 ) and are alternately arranged in the second arrangement direction (y direction in Figure 16 ).

[0198] Further, in the semiconductor device A4, the structure (arrangement, planar size, shape, and the like) of each of the leads 4A to 4H of the lead frame 4 is appropriately changed. For example, the planar area of the semiconductor element 2 is made large, and thus the size of the lead 4B on which the semiconductor element 2 is mounted is made large. As shown in FIG. 6, the lead 4B of the semiconductor device A4 is connected from the end edge on the y2 direction side to the end edge on the yl direction side, and overlaps all of the other leads 4A, 4C to 4H when viewed in the x direction. Figure 17

[0199] The semiconductor device A4 configured as described above has the following effects.

[0200] The semiconductor device A4, like the semiconductor device Al, has the lead 4A and the lead 4B adjacent to each other in the x direction when viewed in the z direction, and has the leads 4C adjacent to the leads 4A and 4B, respectively, when viewed in the z direction. Thus, like the semiconductor device Al, the semiconductor device A4 can shorten the wiring of the above-described power system current path. Therefore, the semiconductor device A4 can achieve reduction of parasitic inductance and parasitic resistance, and thus can achieve high efficiency and energy saving.

[0201] The on-resistance of the semiconductor element 2 of the semiconductor device A4 is smaller than the on-resistance of the semiconductor element 1, and is smaller than the on-resistance of the semiconductor element 2 of the semiconductor device Al. According to this structure, the conduction loss in the semiconductor element 2 is smaller than the conduction loss in the semiconductor element 1, and is smaller than the conduction loss in the semiconductor element 2 of the semiconductor device Al. Therefore, the semiconductor device A4 can reduce the conduction loss in the semiconductor element 2, as compared with the semiconductor device Al. In particular, the semiconductor device A4 is effective for reduction of the conduction loss of the semiconductor device A4 in the case of being used for a step-down circuit.

[0202] The planar area of the semiconductor element 2 of the semiconductor device A4 is larger than the planar area of the semiconductor element 2 of the semiconductor device Al. According to this structure, the semiconductor device A4 has a large area of the element main surface 2a of the semiconductor element 2, as compared with the semiconductor device Al, and thus can improve the heat dissipation from the element main surface 2a. That is, the semiconductor device A4 can reduce the thermal resistance of the semiconductor element 1, as compared with the semiconductor device Al.

[0203] Further, the semiconductor device A4 obtains the same effects as the semiconductor device A4 through the portions configured similarly to the semiconductor device Al. Further, in the semiconductor device A4, like the semiconductor device A2, by additionally providing the plurality of capacitors C21, C22, C24, C25, C26, C27, the same effects as the semiconductor device A2 can be obtained.

[0204] Figure 17 ​A modification of the semiconductor device A4 of the fourth embodiment is shown. The semiconductor device A41 of this modification has a larger top view area of ​​the lead 4B than the semiconductor device A4. Specifically, the lead 4B of the semiconductor device A41 (see Figure 16 ) and the lead 4B of the semiconductor device A4 (refer to Figure 17 ) is compared, for example, an expansion region ER2 is added (for ease of understanding, Figure 17 (indicated by a dot in the middle).

[0205] In semiconductor device A41, the top-view area of ​​lead 4B is larger than that of lead 4B in semiconductor device A4. This improves the efficiency of heat conduction from lead 4B to wiring pattern 92 on circuit board B1. Specifically, in semiconductor device A41, heat from semiconductor element 2 can be dissipated from both element main surface 2a and element back surface 2b. In particular, by setting the top-view area of ​​lead 4B to between 1.1 and 5 times the top-view area of ​​semiconductor element 2, the size of semiconductor device A41 can be suppressed while improving the efficiency of heat conduction from lead 4B to wiring pattern 92.

[0206] In addition, if Figure 17 As shown, in the top view, the distance between the center of the semiconductor element 2 and the center of the control element 3 is smaller than the distance between the center of the lead 4B and the center of the control element 3. Figure 18 In the diagram, an x ​​(cross mark) is marked at the center of the top view of the semiconductor element 2, the center of the top view of the lead 4B, and the center of the top view of the control element 3. That is, in the top view, the semiconductor element 2 is arranged near the control element 3. This structure can shorten the length of the wire 5F, thereby reducing the parasitic inductance and parasitic resistance of the wire 5F.

[0207] Next, refer to Figure 18 A semiconductor device A5 according to the fifth embodiment will be described. Figure 18 It is a plan view showing a power conversion device W5 including a semiconductor device A5 , in which the sealing member 6 is indicated by an imaginary line (two-dot chain line).

[0208] like Figure 14 As shown, the semiconductor device A5 is equipped with the semiconductor element 1 of the semiconductor device A3 (see Figure 16 ) and the semiconductor element 2 of the semiconductor device A4 (refer to Figure 19 ). That is, the semiconductor elements 1 and 2 of semiconductor device A5 have higher performance (e.g., lower on-resistance) than the semiconductor elements 1 and 2 of semiconductor device A1, and each has a larger top view area. Furthermore, in semiconductor device A5, the structure (arrangement, top view dimensions, shape, etc.) of each lead 4A to 4H of lead frame 4 is appropriately modified.

[0209] In semiconductor device A5, similar to semiconductor device A1, leads 4A and 4B are adjacent in the x-direction when viewed in the z-direction, and lead 4C is adjacent to leads 4A and 4B, respectively, when viewed in the z-direction. Consequently, similar to semiconductor device A1, semiconductor device A5 can shorten the wiring of the power system current path. Consequently, semiconductor device A5 can reduce parasitic inductance and parasitic resistance, thereby achieving improved efficiency and energy savings.

[0210] Compared to semiconductor device A1, semiconductor device A5 includes high-performance (lower on-resistance) semiconductor elements 1 and 2. Therefore, semiconductor device A5 can reduce conduction loss in each semiconductor element 1 and 2 compared to semiconductor device A1.

[0211] Next, refer to Figure 20 as well as Figure 19 , a semiconductor device A6 according to a sixth embodiment is described. Figure 20 It is a plan view showing a power conversion device W6 including a semiconductor device A6, in which the sealing member 6 is indicated by an imaginary line (two-dot chain line). Figure 19 It is along Figure 19 Cross-sectional view of line XX-XX.

[0212] like Figure 20 As shown, the semiconductor device A6 differs from the semiconductor device A1 in that clips 7A, 7B, 7C, and 7D are used instead of the plurality of wires 5A, 5B, 5C, and 5D.

[0213] like Figure 20 As shown in FIG. 1 , the clips 7A to 7D are formed by bending a plate-shaped metal member. The constituent material of the clips 7A to 7D is, for example, a metal containing Cu or a metal containing Al. Alternatively, it can be a cladding material such as CIC (Copper-Invar-Copper). Figure 19 In the illustrated example, each of the clips 7A to 7D is bent perpendicularly to the upper surface of the lead frame 4 , but may be inclined with respect to the z direction.

[0214] One side of the clip 7A in the y direction (at Figure 19 The y1 direction side of the clip 7B is in the shape of comb teeth, and the comb teeth are respectively connected to the plurality of pads 111. Figure 19 The y2 direction side of the clip 7C is in the shape of comb teeth, and the comb teeth are respectively connected to the plurality of pads 121. Figure 19 The x2 direction side of the clip 7D is in the shape of a comb, and the comb-shaped parts are respectively connected to the plurality of pads 211. Figure 19The portion of the clip 7A that is in the x1 direction side (the side of the x1 direction in the middle) is comb-tooth shaped, and this comb-tooth shaped portion is joined to the plurality of pad portions 221, respectively. Further, the shape of each of the clips 7A to 7D is not limited to Figure 20 and Figure 21 the example shown in FIG. 17.

[0215] In the semiconductor device A6, as with the semiconductor device Al, the lead 4A and the lead 4B are adjacent in the x direction when viewed in the z direction, and the lead 4C is adjacent to each of the leads 4A and 4B when viewed in the z direction. Thus, as with the semiconductor device Al, the semiconductor device A6 can shorten the wiring of the power system current path described above. Therefore, the semiconductor device A6 can achieve a reduction in parasitic inductance and parasitic resistance, and thus can achieve high efficiency and energy saving.

[0216] The semiconductor device A6 has the clip 7A in place of the lead 5A. The clip 7A can reduce the wiring resistance compared to the lead 5A. In particular, the clip 7A is part of the power system current path described above, and thus the semiconductor device A6 can suppress power loss in power conversion compared to the semiconductor device Al. Similarly, the semiconductor device A6 has the clips 7B, 7C, and 7D in place of the leads 5B, 5C, and 5D. Each of the clips 7B, 7C, and 7D can reduce the wiring resistance compared to each of the leads 5B, 5C, and 5D. In particular, each of the clips 7B, 7C, and 7D is part of the power system current path described above, and thus the semiconductor device A6 can suppress power loss in power conversion compared to the semiconductor device Al.

[0217] In the sixth embodiment, a case where each of the clips 7A to 7D is in a partially bent configuration is shown, but is not limited thereto. For example, each of the clips 7A to 7D can be in a configuration where the thickness (the dimension in the z direction) of a portion thereof is changed. At this time, the portion of each of the clips 7A to 7D that is joined to the semiconductor element 1 or the semiconductor element 2 is thin, and the portion that is joined to any one of the leads 4A, 4B, and 4C is thick.

[0218] In the sixth embodiment, a case where the clip 7A has a comb-tooth shaped portion that is joined to the plurality of pad portions 111 (the drain electrode 11) is shown, but is not limited thereto. For example, a plurality of clips 7A each having a strip shape can be provided, and one clip 7A can be joined to each of the plurality of pad portions 111, respectively. The same applies to the other clips 7B to 7D.

[0219] Next, the semiconductor device A7 of the seventh embodiment will be described with reference to Figure 21 to FIG. 18. Figure 21 is a plan view of a power conversion device W7 having the semiconductor device A7, and a sealing member 6 is indicated by a broken line (double-dot chain line).

[0220] AsFigure 21 As shown, semiconductor device A7 differs from semiconductor device A1 in that semiconductor elements 1 and 2 are flip-chip mounted. That is, semiconductor element 1 is mounted with element principal surface 1a facing lead frame 4, and semiconductor element 2 is mounted with element principal surface 2a facing lead frame 4.

[0221] The lead frame 4 of the semiconductor device A7 has leads 4A to 4C of different shapes in order to perform flip-chip mounting on the semiconductor elements 1 and 2, and also includes leads 4I and 4J. Figure 21 As shown, comb-tooth-shaped portions (hereinafter referred to as "comb-tooth portions") are formed on each of the leads 4A to 4C. Furthermore, two comb-tooth portions are formed on the lead 4A.

[0222] like Figure 21 As shown, the drain electrode 11 (plurality of pads 111) of semiconductor element 1 is conductively bonded to the comb-teeth of lead 4C. The source electrode 12 (plurality of pads 121) of semiconductor element 1 is conductively bonded to one comb-teeth of lead 4A. The gate electrode 13 (either of the two pads 131 and 132) of semiconductor element 1 is conductively bonded to lead 4I. The drain electrode 21 (plurality of pads 211) of semiconductor element 2 is conductively bonded to the other comb-teeth of lead 4A. The source electrode 22 (plurality of pads 221) of semiconductor element 2 is conductively bonded to the comb-teeth of lead 4B. The gate electrode 23 (either of the two pads 231 and 232) of semiconductor element 2 is conductively bonded to lead 4J.

[0223] like Figure 22 As shown, wire 5E is bonded to lead 4I. Gate electrode 13 of semiconductor element 1 and device electrode 35 are electrically connected via lead 4I and wire 5E. Wire 5F is bonded to lead 4J. Gate electrode 23 of semiconductor element 2 and device electrode 36 of control element 3 are electrically connected via lead 4J and wire 5F.

[0224] In semiconductor device A7, leads 4A and 4B are adjacent to each other in the x-direction when viewed in the z-direction, and lead 4C is also adjacent to leads 4A and 4B when viewed in the z-direction. Consequently, similar to semiconductor device A1, semiconductor device A7 can shorten the wiring of the power system current path. Consequently, semiconductor device A7 can reduce parasitic inductance and parasitic resistance, thereby achieving improved efficiency and energy conservation.

[0225] Next, refer to Figure 23 as well as Figure 22 , a semiconductor device A8 according to an eighth embodiment is described. Figure 23 1 is a plan view showing the semiconductor device A8, in which the sealing member 6 is indicated by an imaginary line (two-dot chain line). Figure 22 It is alongFigure 22 Cross-sectional view of the XXIII-XXIII line.

[0226] As Figure 23 and Figure 22 shown, the semiconductor device A8 differs from the semiconductor device Al and has a conductive substrate 8 in place of the lead frame 4.

[0227] The conductive substrate 8 includes a base material 81 and a plurality of wiring portions 82A to 82H.

[0228] The base material 81 is composed of an insulating material. The material composing the base material 81 is, for example, a ceramic excellent in thermal conductivity. As such a ceramic, for example, AlN (aluminum nitride), SiN (silicon nitride), AI2O3 (aluminum oxide), or the like is used. The base material 81 is, for example, a flat plate. Further, the material composing the base material 81 is not limited to a ceramic, but can be various resin materials used in a printed board or the like, or silicon or the like.

[0229] The wiring portions 82A to 82H are formed on the base material 81. Each of the wiring portions 82A to 82H is composed of a conductive material. The material composing each of the wiring portions 82A to 82H is, for example, a metal including copper. Further, the material can not be copper, but can be aluminum or the like. The plurality of wiring portions 82A to 82H are arranged separately from each other.

[0230] The wiring portion 82A corresponds to the lead 4A. The wiring portion 82B corresponds to the lead 4B. The wiring portion 82C corresponds to the lead 4C. The wiring portion 82D corresponds to the lead 4D. The wiring portion 82E corresponds to the lead 4E. The wiring portion 82F corresponds to the lead 4F. The wiring portion 82G corresponds to the lead 4G. The wiring portion 82H corresponds to the lead 4H. ​ Each of the wiring portions 82A to 82H shown is arranged similarly to each of the leads 4A to 4H of the semiconductor device Al, and the positional relationship and the like of each are also the same.

[0231] In the present embodiment, the conductive substrate 8 corresponds to the "conductive member" recited in the claims. The wiring portion 82A corresponds to the "first electrically conductive body" recited in the claims. The wiring portion 82B corresponds to the "second electrically conductive body" recited in the claims. The wiring portion 82C corresponds to the "third electrically conductive body" recited in the claims. The wiring portion 82D corresponds to the "fourth electrically conductive body" recited in the claims. The wiring portion 82E corresponds to the "fifth electrically conductive body" recited in the claims. The wiring portion 82F corresponds to the "sixth electrically conductive body" recited in the claims. The wiring portion 82G corresponds to the "seventh electrically conductive body" recited in the claims. The wiring portion 82H corresponds to the "eighth electrically conductive body" recited in the claims.

[0232] The semiconductor device A8 has the wiring portions 82A, 82B, 82C configured similarly to the respective leads 4A, 4B, 4C in the semiconductor device Al. According to this configuration, the semiconductor device A8, like the semiconductor device Al, the wiring portion 82A is adjacent to the wiring portion 82B in the x direction when viewed in the z direction, and the wiring portion 82C is adjacent to each of the wiring portion 82A and the wiring portion 82B when viewed in the z direction. Thus, the semiconductor device A8, like the semiconductor device Al, can shorten the wiring of the power system current path. Therefore, the semiconductor device A8 can achieve reduction of parasitic inductance and parasitic resistance, and thus, can achieve high efficiency and energy saving.

[0233] In the first to eighth embodiments, the semiconductor devices Al to A8 are shown as being in a package form of the SON type, but are not limited thereto and can be configured by other package forms. For example, the semiconductor devices Al to A8 can be configured by a package form of a BGA (Ball Grid Array) type, an LGA (Land Grid Array) type, a QFP (Quad Flat Package) type, a QFN (Quad Flat Non-lead) type, or the like. Further, these package forms are one example and are not limited thereto.

[0234] The semiconductor device of the present disclosure is not limited to the above-described embodiments. The specific configuration of each portion of the semiconductor device of the present disclosure can be freely designed variously.

[0235] The semiconductor device of the present disclosure includes the following embodiments related to the notes.

[0236] [Note 1]

[0237] A semiconductor device characterized by comprising:

[0238] a conductive member including a first conductor, a second conductor, and a third conductor that are separated from each other;

[0239] a first semiconductor element having a first main surface on which a first drain electrode, a first source electrode, and a first gate electrode are disposed; and

[0240] a second semiconductor element having a second main surface on which a second drain electrode, a second source electrode, and a second gate electrode are disposed,

[0241] the first conductor is in conduction with the first source electrode and the second drain electrode,

[0242] the second conductive body is in conduction with the second source electrode, and when viewed in a first direction orthogonal to the first main surface, the second conductive body is adjacent to the first conductive body in a second direction orthogonal to the first direction,

[0243] the third conductive body is in conduction with the first drain electrode, and when viewed in the first direction, the third conductive body is adjacent to the first conductive body and the second conductive body, respectively.

[0244] [Note 2]

[0245] The semiconductor device according to Note 1,

[0246] The semiconductor device further includes:

[0247] a first connection member that puts the third conductive body in conduction with the first drain electrode;

[0248] a second connection member that puts the first source electrode in conduction with the first conductive body;

[0249] a third connection member that puts the first conductive body in conduction with the second drain electrode; and

[0250] a fourth connection member that puts the second source electrode in conduction with the second conductive body,

[0251] the first semiconductor element is mounted on the first conductive body, and the first main surface faces the opposite side to the direction in which the first conductive body faces in the first direction,

[0252] the first semiconductor element is mounted on the second conductive body, and the second main surface faces the opposite side to the direction in which the second conductive body faces in the first direction.

[0253] [Note 3]

[0254] The semiconductor device according to Note 2,

[0255] the first conductive body and the third conductive body are adjacent to each other in a third direction orthogonal to both the first direction and the second direction when viewed in the first direction.

[0256] [Note 4]

[0257] The semiconductor device according to Note 3,

[0258] the first connection member overlaps with a first insulating region that insulates the first conductive body and the third conductive body from each other when viewed in the first direction.

[0259] [Note 5]

[0260] The semiconductor device according to any one of the above 3 to 4,

[0261] The third connection member overlaps a second insulating region that insulates the first conductive body and the second conductive body when viewed in the first direction.

[0262] [Note 6]

[0263] The semiconductor device according to any one of the above 3 to 5,

[0264] The first conductive body and the second conductive body overlap when viewed in the second direction,

[0265] The first conductive body and the third conductive body overlap when viewed in the third direction.

[0266] [Note 7]

[0267] The semiconductor device according to Note 6,

[0268] The second conductive body and the third conductive body overlap when viewed in the second direction.

[0269] [Note 8]

[0270] The semiconductor device according to any one of the above 3 to 7,

[0271] The semiconductor device further comprises:

[0272] a control element including a first element electrode and a second element electrode;

[0273] a fifth connection member that electrically connects the first gate electrode and the first element electrode; and

[0274] a sixth connection member that electrically connects the second gate electrode and the second element electrode,

[0275] The control element outputs a first drive signal that controls switching operation of the first semiconductor element from the first element electrode, and outputs a second drive signal that controls switching operation of the second semiconductor element from the second element electrode.

[0276] [Note 9]

[0277] The semiconductor device according to Note 8,

[0278] The conductive member further includes a fourth conductive body that is separate from the first conductive body, the second conductive body, and the third conductive body and supports the control element,

[0279] The fourth conductive body overlaps the first conductive body and the third conductive body when viewed in the third direction, and is located on the opposite side of the third conductive body from the first conductive body with the first conductive body interposed therebetween in the third direction.

[0280] [Note 10]

[0281] The semiconductor device according to Note 9,

[0282] The fifth connection member overlaps only the first conductive body and the fourth conductive body among the conductive members when viewed in the first direction.

[0283] [Note 11]

[0284] The semiconductor device according to Note 9 or 10,

[0285] The sixth connection member overlaps only the second conductive body and the fourth conductive body among the conductive members when viewed in the first direction.

[0286] [Note 12]

[0287] The semiconductor device according to any one of Notes 9 to 11,

[0288] The semiconductor device further comprises a first capacitor having two terminals,

[0289] One terminal of the first capacitor is connected to the second conductive body, and the other terminal is connected to the third conductive body.

[0290] [Note 13]

[0291] The semiconductor device according to any one of Notes 9 to 12,

[0292] The semiconductor device further comprises a second capacitor having two terminals,

[0293] The conductive member further comprises a fifth conductive body that is separate from the first conductive body, the second conductive body, the third conductive body, and the fourth conductive body and is in conduction with the control element,

[0294] One terminal of the second capacitor is connected to the first conductive body, and the other terminal is connected to the fifth conductive body.

[0295] [Note 14]

[0296] The semiconductor device according to any one of Notes 9 to 13,

[0297] The semiconductor device further comprises a third capacitor having two terminals,

[0298] The conductive member further includes a sixth conductor which is separate from the first conductor, the second conductor, the third conductor, and the fourth conductor and is in conduction with the control element,

[0299] One terminal of the third capacitor is joined to the fourth conductor, and the other terminal is joined to the sixth conductor.

[0300] [Para 15]

[0301] The semiconductor device according to any one of Paras 9 to 14, wherein

[0302] The semiconductor device further has a fourth capacitor and a fifth capacitor each having two terminals,

[0303] The conductive member further includes a seventh conductor and an eighth conductor each of which is separate from the first conductor, the second conductor, the third conductor, and the fourth conductor,

[0304] The seventh conductor and the eighth conductor are separate from each other and are each in conduction with the control element,

[0305] One terminal of the fourth capacitor is joined to the fourth conductor, and the other terminal is joined to the seventh conductor,

[0306] The fifth capacitor is joined to the fourth conductor, and the other terminal is joined to the eighth conductor.

[0307] [Para 16]

[0308] The semiconductor device according to any one of Paras 9 to 15, wherein

[0309] The semiconductor device further has a sixth capacitor having two terminals,

[0310] One terminal of the sixth capacitor is joined to the second conductor, and the other terminal is joined to the fourth conductor.

[0311] [Para 17]

[0312] The semiconductor device according to any one of Paras 9 to 16, wherein

[0313] The first semiconductor element has a smaller on-resistance than the on-resistance of the second semiconductor element.

[0314] [Para 18]

[0315] The semiconductor device according to any one of Paras 9 to 16, wherein

[0316] The on-resistance of the second semiconductor element is smaller than the on-resistance of the first semiconductor element.

[0317] [Para 19]

[0318] The semiconductor device according to any one of Paras 9 to 18, wherein

[0319] The distance between the center of the first semiconductor element and the center of the control element is smaller than the distance between the center of the first electrically-conductive body and the center of the control element when viewed in the first direction.

[0320] [Para 20]

[0321] The semiconductor device according to any one of Paras 9 to 19, wherein

[0322] The distance between the center of the second semiconductor element and the center of the control element is smaller than the distance between the center of the second electrically-conductive body and the center of the control element when viewed in the first direction.

[0323] [Para 21]

[0324] The semiconductor device according to any one of Paras 9 to 20, wherein

[0325] The second electrically-conductive body overlaps the fourth electrically-conductive body when viewed in the second direction.

[0326] [Para 22]

[0327] The semiconductor device according to any one of Paras 1 to 21, wherein

[0328] The first drain electrode includes a plurality of first drain pad portions each extending in a first extension direction orthogonal to the first direction,

[0329] The first source electrode includes a plurality of first source pad portions each extending in the first extension direction,

[0330] The plurality of first drain pad portions and the plurality of first source pad portions are alternately arranged in a first arrangement direction orthogonal to both the first direction and the first extension direction.

[0331] [Para 23]

[0332] The semiconductor device according to Para 22, wherein

[0333] The second drain electrode includes a plurality of second drain pad portions each extending in a second extension direction orthogonal to the first direction,

[0334] The second source electrode includes: a plurality of second source pad portions each extending in the second extension direction,

[0335] The plurality of second drain pad portions and the plurality of second source pad portions are alternately arranged in a second arrangement direction orthogonal to both the first direction and the second extension direction,

[0336] The second extension direction is inclined with respect to the first extension direction.

[0337] [Para 24]

[0338] The semiconductor device according to Para 23, wherein

[0339] The inclination of the second extension direction with respect to the first extension direction is 10° or more and 170° or less.

[0340] [Para 25]

[0341] The semiconductor device according to any one of Paras 1 to 24, wherein

[0342] Each constituent material of the first semiconductor element and the second semiconductor element is gallium nitride.

[0343] Symbol Explanation

[0344] A1 to A8, A31, A41: Semiconductor device

[0345] 1, 2: Semiconductor element

[0346] 1a, 2a: Element front surface

[0347] 1b, 2b: Element back surface

[0348] 11, 21: Drain electrode

[0349] 111, 211: Pad portion

[0350] 12, 22: Source electrode

[0351] 121, 221: Pad portion

[0352] 13, 23: Gate electrode

[0353] 131, 132, 231, 232: Pad portion

[0354] 3: Control element

[0355] 3a: Element front surface

[0356] 3b: Element back surface

[0357] 31 to 38: Element electrode

[0358] 4: lead frame

[0359] 4A to 4J: leads

[0360] 49A, 49B, 49C: insulating regions

[0361] 5A to 5L: wires

[0362] 6: sealing member

[0363] 61: resin main surface

[0364] 62: resin back surface

[0365] 631 to 634: resin side surfaces

[0366] 7A to 7D: clips

[0367] 8: conductive substrate

[0368] 81: base material

[0369] 82A to 82H: wiring portions

[0370] W1 to W7: power conversion devices

[0371] B1: circuit substrate

[0372] 91 to 98, 971, 981: wiring patterns

[0373] C11 to C14, C21, C22, C24 to C27: capacitors

[0374] R15, R16: resistors

[0375] D1: diode

[0376] DR1, DR2: drive circuits

[0377] ER1, ER2: expansion regions

[0378] GND1: first ground terminal

[0379] GND2: second ground terminal

[0380] L1: inductor

[0381] LO: load

[0382] PS1, PS2: external power supplies

[0383] T1 to T8: external terminals

[0384] TC1 to TC8: connection terminals

Claims

1. A semiconductor device, characterized in that: have: a conductive component comprising a first conductive body, a second conductive body, and a third conductive body that are separated from each other; a first semiconductor element having a first main surface on which a first drain electrode, a first source electrode, and a first gate electrode are arranged; as well as a second semiconductor element having a second main surface on which a second drain electrode, a second source electrode, and a second gate electrode are arranged; The first conductor is electrically connected to the first source electrode and the second drain electrode. The second conductor is electrically connected to the second source electrode, and when viewed in a first direction perpendicular to the first main surface, the second conductor is adjacent to the first conductor in a second direction perpendicular to the first direction. The third conductor is electrically connected to the first drain electrode and is adjacent to the first conductor. The first semiconductor element and the second semiconductor element are connected in series to form a half-bridge switching circuit. The semiconductor device further comprises: a first connecting member for electrically connecting the third electrical conductor to the first drain electrode; a second connecting member for electrically connecting the first source electrode to the first conductor; a third connecting member for electrically connecting the first conductor to the second drain electrode; as well as a fourth connecting member for electrically connecting the second source electrode to the second conductor; The first semiconductor element is mounted on the first conductor, and the first main surface faces the opposite side of the direction facing the first conductor in the first direction. The second semiconductor element is mounted on the second conductor, and the second main surface faces the opposite side of the direction facing the second conductor in the first direction.

2. The semiconductor device according to claim 1, wherein The first conductor and the third conductor are adjacent to each other in a third direction that is orthogonal to both the first direction and the second direction when viewed in the first direction.

3. The semiconductor device according to claim 2, wherein The first connecting member overlaps with a first insulating region that insulates the first conductor from the third conductor when viewed in the first direction.

4. The semiconductor device according to claim 2, wherein The third connecting member overlaps with a second insulating region that insulates the first conductor from the second conductor when viewed in the first direction.

5. The semiconductor device according to claim 2, wherein The first conductor and the second conductor overlap when viewed in the second direction, The first conductive body and the third conductive body overlap when viewed in the third direction.

6. The semiconductor device according to claim 5, wherein The second conductive body and the third conductive body overlap when viewed in the second direction.

7. The semiconductor device according to any one of claims 2 to 6, wherein The semiconductor device further comprises: a control element comprising a first element electrode and a second element electrode; a fifth connecting member for electrically connecting the first gate electrode to the first element electrode; as well as a sixth connecting member that electrically connects the second gate electrode to the second element electrode, The control element outputs a first drive signal for controlling a switching operation of the first semiconductor element from the first element electrode, and the control element outputs a second drive signal for controlling a switching operation of the second semiconductor element from the second element electrode.

8. The semiconductor device according to claim 7, wherein The conductive component further includes a fourth conductor that is separated from the first conductor, the second conductor, and the third conductor and carries the control element. The fourth conductor overlaps the first conductor and the third conductor when viewed in the third direction, and is located on the opposite side of the third conductor across the first conductor in the third direction.

9. The semiconductor device according to claim 8, wherein The fifth connecting member overlaps only the first conductor and the fourth conductor in the conductive member when viewed in the first direction.

10. The semiconductor device according to claim 8, wherein The sixth connecting member overlaps only the second conductor and the fourth conductor in the conductive member when viewed in the first direction.

11. The semiconductor device according to claim 8, wherein The semiconductor device further includes: a first capacitor having two terminals; One terminal of the first capacitor is connected to the second conductor, and the other terminal is connected to the third conductor.

12. The semiconductor device according to claim 8, wherein The semiconductor device further includes: a second capacitor having two terminals, The conductive component further includes a fifth conductor that is separated from the first conductor, the second conductor, the third conductor, and the fourth conductor and is electrically connected to the control element. One terminal of the second capacitor is connected to the first conductor, and the other terminal is connected to the fifth conductor.

13. The semiconductor device according to claim 8, wherein The semiconductor device further includes: a third capacitor having two terminals, The conductive component further includes a sixth conductor, which is separated from the first conductor, the second conductor, the third conductor, and the fourth conductor and is electrically connected to the control element. One terminal of the third capacitor is connected to the fourth conductor, and the other terminal is connected to the sixth conductor.

14. The semiconductor device according to claim 8, wherein The semiconductor device further includes: a fourth capacitor and a fifth capacitor, each of which has two terminals. The conductive component further includes a seventh conductor and an eighth conductor, which are separated from the first conductor, the second conductor, the third conductor, and the fourth conductor, respectively. The seventh conductor and the eighth conductor are separated from each other and are respectively connected to the control element. One terminal of the fourth capacitor is connected to the fourth conductor, and the other terminal is connected to the seventh conductor. The fifth capacitor is connected to the fourth conductor, and the other terminal thereof is connected to the eighth conductor.

15. The semiconductor device according to claim 8, wherein The semiconductor device further includes: a sixth capacitor having two terminals, One terminal of the sixth capacitor is connected to the second conductor, and the other terminal is connected to the fourth conductor.

16. The semiconductor device according to claim 8, wherein The on-resistance of the first semiconductor element is smaller than the on-resistance of the second semiconductor element.

17. The semiconductor device according to claim 8, wherein The on-resistance of the second semiconductor element is smaller than the on-resistance of the first semiconductor element.

18. The semiconductor device according to claim 8, wherein When viewed in the first direction, a distance between a center of the first semiconductor element and a center of the control element is smaller than a distance between a center of the first conductor and a center of the control element.

19. The semiconductor device according to claim 8, wherein When viewed in the first direction, a distance between a center of the second semiconductor element and a center of the control element is smaller than a distance between a center of the second conductor and a center of the control element.

20. The semiconductor device according to claim 8, wherein The second conductive body does not overlap with the fourth conductive body when viewed in the second direction.

21. The semiconductor device according to any one of claims 1 to 6, wherein The first drain electrode includes: a plurality of first drain pad portions, each extending in a first extension direction perpendicular to the first direction; The first source electrode includes: a plurality of first source pad portions, each extending in the first extension direction; The plurality of first drain pad portions and the plurality of first source pad portions are alternately arranged in a first arrangement direction perpendicular to both the first direction and the first extending direction.

22. The semiconductor device according to claim 21, wherein The second drain electrode includes: a plurality of second drain pad portions, each extending in a second extension direction perpendicular to the first direction; The second source electrode includes: a plurality of second source pad portions, each extending in the second extension direction; The plurality of second drain pad portions and the plurality of second source pad portions are alternately arranged in a second arrangement direction orthogonal to both the first direction and the second extending direction. The second extending direction is inclined relative to the first extending direction.

23. The semiconductor device according to claim 22, wherein The inclination of the second extending direction with respect to the first extending direction is not less than 10° and not more than 170°.

24. The semiconductor device according to any one of claims 1 to 6, wherein The first semiconductor element and the second semiconductor element are each made of gallium nitride.

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