III-V Semiconductor Device with Integrated Protection Function

Abstract

Disclosed is a heterojunction power device based on group-III nitride semiconductors, which includes a first heterojunction transistor (19) formed on a substrate. The first heterojunction transistor includes: a first group-III nitride semiconductor region formed on the substrate, wherein the first group-III nitride semiconductor region includes a first heterojunction, and the first heterojunction includes at least one two-dimensional carrier gas of a second conductivity type; a first terminal (8) operatively connected to the group-III nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first group-III nitride semiconductor region; a first gate terminal (10) formed on the first group-III nitride semiconductor region between the first terminal and the second terminal. The device also includes a second heterojunction transistor (14) formed on the substrate. The second heterojunction transistor includes: a second group-III nitride semiconductor region formed on the substrate, wherein the second group-III nitride semiconductor region includes a second heterojunction, and the second heterojunction includes at least one two-dimensional carrier gas of a second conductivity type; a third terminal operatively connected to the second group-III nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second group-III nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and a second gate terminal formed on the second group-III nitride semiconductor region between the third terminal and the fourth terminal, and wherein the second heterojunction transistor is used for sensing and protection functions of the first power heterojunction transistor. The device also includes at least one monolithic integrated current sensing transistor (16) having a structure substantially the same as that of the first heterojunction transistor, and wherein the third transistor is scaled to a smaller area or a shorter gate width compared to the first heterojunction transistor by a scaling factor X, where X is greater than 1. Other embodiments include both internal sensing and external sensing, sensing loads and feedback circuits to provide overcurrent, gate overvoltage or overtemperature protection.

Description

Technical Field

[0001] This disclosure relates to power semiconductor devices. Specifically, but not exclusively, this disclosure relates to the use of heterostructure AlGaN / GaN high electron mobility transistors or rectifiers.

Background Art

[0002] Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic devices. Power semiconductor devices are commonly used in a "commutation mode" (i.e., they are turned on or off), and thus have a design optimized for this use.

[0003] Silicon bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs) are common types of power semiconductor switching devices. Their application areas range from switched-mode power supplies for consumer electronics, electric vehicles, motor control, and power supplies to RF and microwave circuits and telecommunications systems.

[0004] Gallium nitride (GaN) is a wide-bandgap material with properties that make it a candidate for several application areas that require solid-state devices, such as radio frequency electronics, optoelectronic devices, and power electronics.

[0005] GaN technology allows the design of transistors with high electron mobility and high saturation velocity. These properties of GaN have made it a good candidate for high-power and high-temperature microwave applications, such as radar and cellular communication systems. As the users and required capabilities of the systems expand, the interest in increasing their operating frequency and power correspondingly grows. Higher frequency signals can carry more information (bandwidth) and allow for smaller antennas with very high gain.

[0006] In addition, GaN and its wide bandgap provide the possibility of emitting light at higher frequencies, such as in the green, blue, violet, and ultraviolet parts of the electromagnetic spectrum.

[0007] In the last decade, gallium nitride (GaN) has increasingly been regarded as a very promising material for the field of power devices. The application areas cover portable consumer electronics, solar inverters, electric vehicles, and power supplies. The wide bandgap of the material (Eg = 3.39 eV) results in a high critical electric field (Ec = 3.3 MV / cm), which can lead to: compared with silicon-based devices with the same breakdown voltage, the design of this device has a shorter drift region and thus a lower on-state resistance.

[0008] The use of aluminum gallium nitride (AlGaN) / GaN heterostructures also allows for a very high mobility (μ = 2000 cm 2A two-dimensional electron gas (2DEG) is formed at the heterointerface of the / (Vs) value. In addition, the piezoelectric polarization charges present in the AlGaN / GaN heterostructure result in a high electron density in the 2DEG layer (e.g., 1e 13 cm -2 ). These properties allow the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters. A large number of studies have focused on the development of power devices using AlGaN / GaN heterostructures.

[0009] However, when attempting to design enhancement-mode devices rather than depletion-mode devices, the inherently present 2DEG at the AlGaN / GaN heterointerface poses challenges. However, several methods that can lead to enhancement-mode devices have been proposed, including using a metal-insulator-semiconductor structure, using fluorine treatment, a recessed gate structure, and using a p-type capping layer. Attributed to the relatively mature and controllable epitaxial growth of the pGaN layer compared to other technologies, pGaN / AlGaN / GaN HEMTs are the current state-of-the-art structures for commercialization.

[0010] Figure 1 The cross-section of the active region of a prior art pGaN HEMT is shown. The device includes an AlGaN layer 1, a GaN layer 2, a transition layer 3, a silicon substrate 4, a substrate terminal 5, an SiO2 passivation 6, a source terminal 8, a drain terminal 9, a gate terminal 10, and a highly p-doped GaN 11. The device shown is a lateral three-terminal device with an AlGaN / GaN heterostructure epitaxially grown on a standard silicon wafer. The transition layer is used to allow the growth of a high-quality GaN layer despite the significant lattice mismatch between GaN and Si. Carbon p-type doping is typically added to the GaN layer. Finally, a thin GaN capping layer is usually added to form a gate with a magnesium (Mg) p-type doping density greater than 1×10 19 cm -3 . A typical pGaN gate device has a threshold voltage of about 1.5 V to about 2 V and a gate turn-on bias voltage of about 8 V.

[0011] Although enhancement-mode devices are used as main power switches in many power electronics applications, there are other applications where depletion-mode devices may be more suitable. Generally, a depletion-mode AlGaN / GaN transistor is fabricated by directly placing a Schottky metal contact 12 that serves as the gate terminal on the AlGaN layer (excluding the p-GaN capping layer present in enhancement-mode devices), as Figure 2 seen in.

[0012] In existing technology devices, there is a trend to integrate more functions and more devices (such as transistors) into a single chip to make smaller, smarter, and more powerful systems. The combination and integration of enhancement-mode and depletion-mode transistors are key enabling technologies for advanced logic, analog, and digital circuits.

[0013] In power electronic devices, it is often necessary to monolithically integrate protection and sensing circuitry (such as current sensing, overvoltage protection, temperature sensing) with the main (usually enhancement-mode) power switch. This monolithic integration of functionality rather than discrete implementation will allow for a reduction in total system size / cost, streamlining of the bill of materials, and will result in improved performance by reducing parasitic components associated with the interconnections between discrete devices. In this sensing and protection circuitry, it is often necessary to use depletion-mode or normally-on devices.

[0014] The prior art does not provide the ability to form the gate terminals of both enhancement-mode and depletion-mode devices within the same manufacturing step. In prior art devices, Schottky contacts are formed in a separate manufacturing step.

[0015] In prior art depletion-mode Schottky gate devices, the threshold voltage of the device (i.e., the gate bias voltage at which the device is considered to move from the off state to the on state and vice versa) depends on process parameters such as but not limited to the AlGaN layer thickness, aluminum mole fraction, and the gate metal stack. Therefore, adjusting the threshold voltage to a level most suitable for a particular application requires changing the epitaxial growth and / or gate metal processing, which is both time-consuming and cost-ineffective. In contrast, the ability to reliably adjust the device threshold voltage through layout modification would be significantly less time-consuming and more cost-effective. The prior art currently does not have this ability.

[0016] Prior art depletion-mode devices in the on state have a limitation in terms of the maximum positive gate bias voltage that can be applied to the gate terminal before the main on-state conduction path (i.e., the low-resistance path) changes from drain-source to gate-source. This maximum bias voltage depends on the Schottky barrier height present at the gate contact and does not exceed 2V. There are no depletion-mode HEMT devices in the prior art that can be biased beyond this voltage level. SUMMARY OF THE INVENTION

[0017] This disclosure is directed to semiconductor structures and devices formed in group III nitrides, and more particularly, the present invention is directed to GaN and Al x GaN 1-x structures.

[0018] According to the present disclosure, a monolithic integrated current sensing transistor and preferably at least one depletion device are used to provide protection and sensing circuitry for a main (usually enhancement-mode) power switch. The ability to sense the current through the main power HEMT via the current sensing transistor and use it to adjust the gate bias or gate pulse width / frequency of the main power HEMT can be used to avoid drain overcurrent events on the load side or provide a longer hold time during short circuit conditions. The configuration can also provide self-protection based on a monolithic integrated (internal) feedback circuit and / or sense pads that allow external sensing of the current and process this through a controller / microprocessor and a marl driver unit to provide external feedback to the gate of the main power HEMT to optimize its operation and / or provide self-protection. Furthermore, if the integrated sense load has a reproducible temperature dependence, it can be used to provide both overcurrent and overtemperature protection. This is especially useful when excessive self-heating occurs. The monolithic integration rather than discrete implementation of this functionality allows for a reduction in the total system size / cost, streamlining of the bill of materials, and can result in improved performance by reducing parasitic components associated with the interconnections between discrete devices.

[0019] According to the present disclosure, a semiconductor device with integrated sensing and protection circuitry is provided in GaN technology, where the main power transistor and the transistors for sensing and protection can be fabricated using the same gate technology. The drain and gate terminals of the current sensing transistor are connected to the drain and gate terminals of the main power HEMT, respectively. The drain terminal of at least one of the other transistors in the sensing and protection circuitry can be connected to the gate terminal of the main power transistor. Different embodiments including other sensing and protection circuitry are provided to mitigate overcurrent and overtemperature events.

[0020] According to the present disclosure, a depletion transistor can include a gate structure based on a discontinuous p-GaN layer that contains islands within a strip or closed shape surrounding a cell for modulating the conduction path between a high voltage terminal and a low voltage terminal when a gate voltage is provided and can be used in a protection circuit. All of these islands can be connected to the same gate electrode. The so-called discontinuous islands mean that there is no p-GaN layer between adjacent islands. Thus, there is a direct unobstructed conduction path between the source and drain terminals through a 2DEG layer formed at the heterojunction between GaN and AlGaN (between the islands). However, adjacent islands can be placed closely together across (orthogonal to) the current path such that the potential applied to the p-GaN gate islands modulates the conductive region between the islands (2DEG layer) and thus modulates the direct path between the source and drain. The p-GaN layers in the continuous and discontinuous gate structures can be fabricated in the same process step, and the difference between continuous and discontinuous is achieved by a change in the layout of the same mask.

[0021] According to one aspect of the present disclosure, there is provided a sensing and protection circuit that may preferably use the depletion-mode transistors described above. The depletion-mode transistors sense a specific intrinsic gate voltage or / and drain current and are used to reduce or limit the gate voltage on the main power transistor when an over-drain current (or over-temperature) condition is detected in the main power transistor. The specific on-state gate voltage is equal to the voltage at which a two-dimensional electron gas (2DEG) forms under the p-GaN island and causes a steep increase in the current of the normally-on sensing device (i.e., a decrease in the on-state resistance).

[0022] According to a first aspect of the present invention, there is provided a heterojunction power device based on group-III nitride semiconductors, comprising:

[0023] A first power heterojunction transistor formed on a substrate, the first heterojunction transistor comprising:

[0024] A first group-III nitride semiconductor region formed on the substrate, wherein the first group-III nitride semiconductor region includes a first heterojunction, the first heterojunction including at least one two-dimensional carrier gas of a second conductivity type;

[0025] A first terminal operatively connected to the first group-III nitride semiconductor region;

[0026] A second terminal laterally spaced from the first terminal and operatively connected to the first group-III nitride semiconductor region;

[0027] A first gate region formed on the first group-III nitride semiconductor region between the first terminal and the second terminal;

[0028] A first gate terminal contacting the first gate region;

[0029] A second heterojunction transistor formed on a substrate, the second heterojunction transistor comprising:

[0030] A second group-III nitride semiconductor region formed on the substrate, wherein the second group-III nitride semiconductor region includes a second heterojunction, the second heterojunction including at least one two-dimensional carrier gas of a second conductivity type;

[0031] A third terminal operatively connected to the second group-III nitride semiconductor region;

[0032] A fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second group-III nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and

[0033] A second gate region formed on the second group-III nitride semiconductor region between the third terminal and the fourth terminal;

[0034] A second gate terminal that contacts the second gate region;

[0035] A third heterojunction transistor formed on a substrate, the third heterojunction transistor comprising:

[0036] A third group-III nitride semiconductor region formed on the substrate, wherein the third group-III nitride semiconductor region includes a third heterojunction that includes at least one two-dimensional carrier gas of a second conductivity type;

[0037] A fifth terminal operatively connected to the third group-III nitride semiconductor region;

[0038] A sixth terminal that is laterally spaced from the fifth terminal in a first dimension and operatively connected to the third group-III nitride semiconductor region, wherein the sixth terminal is operatively connected to the second terminal; and

[0039] A third gate region formed on the third group-III nitride semiconductor region between the fifth terminal and the sixth terminal;

[0040] A third gate terminal that contacts the third gate region, wherein the third gate terminal is operatively connected to the first gate terminal; and

[0041] wherein the third heterojunction transistor is monolithically integrated with the first heterojunction transistor and has a substantially identical structure to the first heterojunction transistor, and wherein the third transistor is scaled to a smaller area or a shorter gate width compared to the first heterojunction transistor by a scaling factor X, where X is greater than 1, and

[0042] wherein the third heterojunction transistor is used for current sensing of the first power heterojunction transistor and the second heterojunction transistor is configured for sensing and / or protection functions of the first power heterojunction transistor.

[0043] According to a second aspect of the present invention, there is provided a heterojunction power device based on a group-III nitride semiconductor as in Technical Solution 1,

[0044] wherein the heterojunction transistor further includes one or more highly doped semiconductor regions of a first conductivity type formed on the first group-III nitride semiconductor region, and wherein the first gate terminal is formed on the one or more highly doped semiconductor regions; and

[0045] wherein the second heterojunction transistor includes at least two highly doped semiconductor regions of a first conductivity type formed on the second group-III nitride semiconductor region, and wherein the second gate terminal is formed on the at least two highly doped semiconductor regions, and wherein the at least two highly doped semiconductor regions are laterally spaced from each other in a second dimension.

[0046] The second heterojunction transistor may be a normally-on transistor based on a discontinuous p-GaN layer, the discontinuous p-GaN layer containing islands within a strip or closed shape surrounding a cell for modulating the conduction path between a high voltage terminal and a low voltage terminal when a gate voltage is provided.

[0047] According to a third aspect of the present disclosure, the sensing and protection function may refer to both sensing current through a current sensing transistor (third transistor) and sensing the first gate terminal voltage of the power heterojunction transistor using a second transistor and limiting the voltage applied to the first gate of the power heterojunction transistor due to either of the sensing functions.

[0048] According to a fourth aspect of the present disclosure, the sensing and protection function may be both internal and external. In this aspect of the invention, at least one current sensing transistor is provided. The at least one current sensing transistor provides dual sensing (internal and external). The internal current sensing is accomplished through an integrated sensing load further connected to an integrated feedback circuit for over-current self-protection. The feedback circuit may include transistors such as the second transistor described in a previous aspect of the invention. The sensing load may include an integrated resistor made of (for example) 2DEG or metal or other active components such as depletion or enhancement transistors. If the sensing load has a reproducible temperature dependence, the feedback circuit may also provide over-heat self-protection. The external sensing is provided as an output (via an integrated sensing pad) in the form of a current or voltage ideally proportional to the current flowing through the main power HEMT to a controller / microprocessor for further processing. The controller / microprocessor may instruct the internal / external gate driver unit to provide external feedback to the gate of the main power HEMT to optimize its operation and / or provide self-protection. The internal feedback circuit may further include amplification components to enhance its sensing and protection performance.

[0049] The object of the present disclosure is to preferably use GaN technology to provide a semiconductor device with an integrated sensing and protection circuit, wherein a main power transistor with a gate structure based on a continuous p-GaN layer is preferably used and the transistors for sensing are fabricated using the same gate technology preferably characterized by a continuous or discontinuous p-GaN layer. Different embodiments of the protection circuit are described to mitigate drain over-current, over-heat or over-gate voltage events. This contributes to durable operation and an increased safe operating area.

[0050] A second heterojunction transistor, the sense load, and / or other portions of the feedback circuit may be formed on the same substrate and use a GaN base layer that is almost exactly the same as that of the first heterojunction power transistor, but placed in different regions of the integrated chip. In this case, the first heterojunction transistor may be monolithically integrated with the second heterojunction transistor and the third heterojunction transistor and may also include some other monolithically integrated components, such as resistors, capacitors, transistors, or diodes that belong to the sense load or the feedback circuit. The monolithic integration of the above components allows for a reduction in the total system size / cost. It also results in improved performance by reducing the parasitic components associated with the interconnections between discrete devices.

[0051] Preferably, the starting substrate may be silicon. However, any other substrate that combines silicon with another semiconductor material compatible with prior art processes may be used. The use of a silicon substrate facilitates the availability of etching techniques, low cost, high reproducibility, and the foundry of supporting processes. Alternative substrate materials may include sapphire, silicon carbide (SiC), gallium nitride (GaN), and gallium arsenide (GaAs). Other alternatives are also possible. Additionally, the present disclosure encompasses the possibility of growing a group III nitride semiconductor region including a heterojunction (or heterostructure) on a first substrate suitable for the purpose and then transferring the heterostructure to a second substrate. The second substrate may be any of the above substrates or a different substrate (e.g., polydimethylsiloxane (PDMS), flexible substrate, diamond). Silicon as the substrate material will be used in the following examples and figures for illustration.

[0052] The first heterojunction transistor may further include one or more first highly doped semiconductor regions of the first conductivity type formed on the first group III nitride semiconductor region, and the first gate terminal is formed on the one or more first highly doped semiconductor regions. The second heterojunction transistor may include one or more second highly doped semiconductor regions of the first conductivity type formed on the second group III nitride semiconductor region, and the second gate terminal may be formed on the one or more second highly doped semiconductor regions. It should be understood that both the first highly doped region and the second highly doped region may be a continuous region or multiple discrete regions. The present disclosure encompasses both scenarios. The third heterojunction transistor (current sensing transistor) or at least one current sensing transistor may have a structure substantially the same as that of a heterojunction transistor, and wherein the third transistor is scaled to a smaller area or a shorter gate width compared to the first heterojunction transistor by a scaling factor X, where X is greater than 1. All transistors (but preferably, the first power transistor and the third transistor (or at least the current sensing transistor)) may be based on the finger shape of a finger-forked design.

[0053] The first gate terminal may be formed on the first plurality of highly doped semiconductor regions. The second gate terminal may be formed on the second plurality of highly doped semiconductor regions. The first gate terminal and / or the second gate terminal may include an ohmic contact. Alternatively, the first gate terminal and / or the second gate terminal may include a Schottky contact.

[0054] The first heterojunction of the first group-III nitride semiconductor region may include: a first group-III nitride semiconductor layer having a first bandgap formed on the substrate; a second group-III nitride semiconductor layer having a second bandgap different from the first bandgap disposed on the first group-III nitride semiconductor layer; and at least one two-dimensional carrier gas of a second conductivity type formed at the interface between the first group-III nitride semiconductor layer and the second group-III nitride semiconductor layer to provide a channel. The second heterojunction of the second group-III nitride semiconductor region may include: a third group-III nitride semiconductor layer having a first bandgap formed on the substrate; a fourth group-III nitride semiconductor layer having a second bandgap different from the first bandgap disposed on the first group-III nitride semiconductor layer; and at least one two-dimensional carrier gas of a second conductivity type formed at the interface between the third group-III nitride semiconductor layer and the fourth group-III nitride semiconductor layer to provide a channel.

[0055] Each of the first group-III nitride semiconductor layer, the second group-III nitride semiconductor layer, the third group-III nitride semiconductor layer, and the fourth group-III nitride semiconductor layer may include any one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN).

[0056] The heterostructure may include an elemental semiconductor (e.g., Si, Ge), a binary compound from group III and group IV (e.g., GaAs) or group II and group VI (e.g., ZnS) or group III and group V (e.g., GaN), a binary alloy semiconductor (e.g., SiGe), a ternary alloy (e.g., AlGaAs), a quaternary alloy (e.g., InGaAsP), or even a quinary material (e.g., GaInPSbAs). Thus, some examples of possible heterostructures are as follows: AlGaAs / GaAs, InGaP / GaAs, InP / InGaAs, InAlAs / InGaAs, SiGe / Si, AlGaAs / InGaAs, InAlAs / InGaAs, and InAlN / GaN, AlGaN / GaN. Preferably, the heterostructure will be an AlGaN / GaN heterostructure including a two-dimensional electron gas (2DEG); this will be used for illustration in the following examples and figures. GaN and AlGaN technologies allow the design of transistors with high electron mobility and high saturation velocity.

[0057] At least one two-dimensional carrier gas can be a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG), with the former being preferred due to the very high electron mobility.

[0058] The first plurality of highly doped semiconductor regions can include a single continuous highly doped region having a p-type conductivity corresponding to a device characterized by a 2DEG or an n-type conductivity corresponding to a device characterized by a 2DHG. Alternatively, the first plurality of highly doped regions can include at least two discrete highly doped semiconductor regions having a p-type conductivity corresponding to a device characterized by a 2DEG or an n-type conductivity corresponding to a device characterized by a 2DHG.

[0059] The second plurality of highly doped semiconductor regions can include a single continuous highly doped region. Alternatively, the second plurality of highly doped semiconductor regions can include at least two highly doped semiconductor regions that are laterally spaced from each other in the second dimension.

[0060] The highly doped semiconductor regions (islands) can be placed on the semiconductor surface of the heterojunction and at zero gate-source terminal bias, which create depletion of the conductive channel (2D carrier gas) directly beneath them. At zero gate-source bias, an uninterrupted channel exists between the third (source) terminal and the fourth (drain) terminal along a path where there is no highly doped layer (on the 2D carrier gas formed under the region between the islands). As long as the gate-source bias is greater than a first threshold voltage, this uninterrupted channel exists.

[0061] As a more negative bias is applied to the gate terminal relative to the source terminal, the carrier gas concentration in the conductive channel (region) between the drain terminal and the source terminal decreases due to the electric field extending from the highly doped islands to the region between the islands. This lateral field depletion forms the 2D carrier gas under the region between the highly doped semiconductor islands and thus blocks the current path through the 2D carrier gas resistance between the source (third terminal) and the drain (fourth terminal). The critical gate bias at which the device is considered to move from the on state (low resistance) to the off state is defined as the first threshold voltage or the device threshold voltage. It should be noted that instead of applying a negative potential to the gate relative to the source terminal, the gate can also be kept grounded and a positive potential can be applied to the source, with the same result.

[0062] Each of the highly doped semiconductor regions can be spaced from the nearest other highly doped semiconductor regions. The threshold voltage can be controlled by the spacing between adjacent highly doped islands, the layer thickness, and the doping fraction. The specific on-state resistance of the depletion-mode transistor can be controlled by the number of spacings between the highly doped islands and the width (in the second dimension) of the highly doped islands relative to the spacing between the islands (i.e., the pitch).

[0063] At least two highly doped semiconductor regions may include discrete regions, where each of the at least two highly doped semiconductor discrete regions may be separated from the nearest other highly doped semiconductor region by a predetermined distance (i.e., pitch). The discrete regions (or discontinuous islands) may be formed such that there is no highly doped semiconductor layer between adjacent islands. Thus, there is a direct and unobstructed conduction path between the third terminal (source) and the fourth terminal (drain) provided by the non-depleted 2D carrier gas layer. Adjacent islands may be closely placed together in rows across (and orthogonal to) the current path such that the potential applied to the gate modulates the conductive region between the islands (i.e., a portion of the 2D carrier gas layer) and thus modulates the direct path between the source and the drain.

[0064] At least two highly doped semiconductor regions may be aligned in a first dimension. In other words, at least two highly doped semiconductor regions may form rows of highly doped semiconductor regions extending in a second dimension (in a direction different from the direction of the current between the first and second terminals).

[0065] The second heterojunction transistor may be configured as a depletion-mode field-effect transistor. In other words, the second heterojunction transistor may be configured as a normally-on transistor, as described above.

[0066] The depletion-mode transistor may have two threshold voltages. The first threshold voltage may be negative and may be equivalent to a classical normally-on transistor to indicate the transition from the cut-off state to the on state. Preferably, the second threshold voltage may be positive and may be characterized by a steep increase in current. The second threshold voltage may have a value equal to that of an integrated normally-off device characterized by a continuous highly doped semiconductor gate.

[0067] When the gate voltage of the depletion-mode transistor is very negative, the adjacent highly doped semiconductor gate islands deplete the portion of the 2D carrier gas between them to block the path for electrons or holes to flow from the source to the drain. Once the gate-source voltage is equal to or greater than the first threshold voltage, a 2D carrier gas begins to form at the middle of the pitch between adjacent p islands. At this stage, a conduction path is established between the source and the drain. The value of the first threshold voltage may be adjusted by controlling the pitch between adjacent highly doped semiconductor islands. As the gate-source voltage increases above the first threshold voltage but remains below the second threshold voltage, the formation of the 2D carrier gas channel spreads from the middle of the pitch between adjacent highly doped semiconductor islands towards the edges of the highly doped semiconductor gate islands. The current continuously increases as the on-state resistance decreases. When the second threshold voltage (which is preferably positive) is reached, a steep increase in current is seen because the 2D carrier gas diffuses under the p gate islands to allow current to flow through this region, thus resulting in an increased conduction area. This is characterized by a steep increase in current and thus a sharp drop in the on-state resistance. The rate of increase of the current depends on the ratio between the width of the highly doped semiconductor gate islands and the pitch between the highly doped semiconductor gate islands.

[0068] A depletion transistor (which may include a gate structure based on a discontinuous p-GaN layer around an island within a strip or closed shape of a cell) senses a specific intrinsic gate voltage or / and drain current and is used to reduce or limit the gate voltage on a main power transistor when an over-drain current and / or an over-temperature condition or an over-current and / or an over-gate voltage condition is detected in the main power transistor. The specific on-state gate voltage is equal to the voltage at which a two-dimensional electron gas (2DEG) is formed under the p-GaN island and causes a sharp drop in the on-state resistance of the normally-on depletion transistor.

[0069] At least two highly doped semiconductor regions may include p-type gallium nitride (p-GaN) material. The pGaN forms a barrier with the underlying AlGaN material. The high doping of pGaN promotes the depletion region to penetrate the AlGaN layer to reach the 2DEG, which is the function of applying a potential to the gate terminal relative to the source terminal. When the potential on the gate increases, holes tunnel from the gate terminal into the semiconductor. During dynamic high voltage stress, a specific amount of hole current through the gate has a positive effect on the stability of the device, but if the gate current is too high, this is regarded as leakage in the control terminal that affects the total losses of the driver and the device. Obviously, using a pGaN gate creates depletion of the 2DEG thereunder at zero gate bias and thus allows the design of normally-off (enhancement-mode) devices. (n-doped regions do not function in the same way).

[0070] The device may further include a transition layer formed between the substrate and the first group-III nitride semiconductor region or the second group-III nitride semiconductor region. The transition layer may be present between the heterostructure and the bulk substrate to minimize lattice mismatch or accommodate mechanical stress in the heterostructure. The transition layer may include a nucleation layer. The nucleation layer may be made of aluminum nitride (AlN) or any other suitable material and may be placed on the substrate. The nucleation layer may form the first sub-layer of a transition layer made of different sub-layers containing materials (such as AlGaN or GaN materials) that are the same as the first semiconductor layer and the second semiconductor layer of the heterostructure device. This helps to release mechanical stress and accommodate the lattice mismatch between the substrate (such as silicon) and the heterostructure formed on top.

[0071] In an embodiment of the present disclosure where the substrate is silicon and the heterostructure is based on a group-III nitride compound (such as GaN), the transition layer may include a single layer of AlxGaN1-xN (x is the aluminum mole fraction of the compound) or any composition of AlxGaN1-xN / AlyGaN1-yN (y is the aluminum mole fraction of the compound) that produces a multi-layer stack (also known as a superlattice).

[0072] The heterojunction power device may further include an isolation layer formed between the first heterojunction transistor and the second heterojunction transistor. Other isolation layers may be used to isolate different components in the integrated heterojunction chip. These components may be part of a sense load or a feedback circuit.

[0073] The second heterojunction transistor may form part of the sensing and protection circuit of the first heterojunction transistor. The second heterojunction transistor may be integrated with the first heterojunction transistor, while the remaining part of the sensing and protection circuit may not be monolithically integrated with the first heterojunction transistor, but provided within the same package or a separate package. Alternatively, the entire sensing and protection circuit may be monolithically integrated with the first heterojunction transistor.

[0074] According to a first aspect of the present disclosure, the sensing and protection function refers to sensing the current flowing through the first power heterojunction transistor and limiting or adjusting the gate signal supplied to the gate of the first power heterojunction transistor by using a third transistor.

[0075] In the prior art, sensing the current in the main power transistor can be accomplished by using a resistor attached to the first terminal (source) and monitoring the voltage developed across this resistor. However, this results in an increased potential in the source of the power device, leading to both a lower effective gate-to-source voltage applied to the main transistor and an additional loss of power dissipated in the resistor.

[0076] Conversely, as described in the present invention, it is preferably to use a current sensing device monolithically integrated with the power switch. The current sensing transistor has an area (or gate width) much smaller than that of the first power heterojunction transistor. In this case, the current flowing in the current sensing transistor is proportional to but significantly smaller than the current flowing in the first power heterojunction transistor.

[0077] According to a first aspect of the present disclosure, the current sensing transistor (third transistor) may be structurally the same as the main power transistor, but the main power transistor has a much larger active area or gate width (e.g., 10 times, 100 times, 1000 times) than the current sensing transistor. The two transistors may have their drains connected together and their gates connected together but separate source terminals. The current sensing transistor may be used to sense the current flowing through the source of the main power transistor.

[0078] The second gate terminal of the second heterojunction transistor described in the first aspect of the present disclosure is operatively connected to the source terminal of the current sensing transistor. In other words, the source of the current sensing transistor and the gate of the second heterojunction transistor may be connected. As described in the first aspect of the present disclosure, the gate of the first power transistor is connected to the drain of the second heterojunction transistor.

[0079] The device may further include a first resistor (current sensing resistor) or a sense load. The second gate terminal (gate of the second transistor) is operatively connected to the source of the current sensing transistor and the first terminal of the resistor or sense load. The second terminal of the first resistor or sense load is operatively connected to the source terminal of the main power transistor. Alternatively, the second terminal of the first resistor or sense load is operatively connected to a ground terminal.

[0080] The first resistor or sense load may be monolithically integrated with, for example, the first power transistor and the second transistor, and the first resistor may include a 2DEG layer or a metal layer. Alternatively, the first resistor may be located external to the first power transistor and the second transistor. The sense load may include an integrated resistor or other low voltage heterojunction transistors, such as depletion or enhancement mode HEMTs.

[0081] As the current through the first resistor (or sense load) increases, the second gate voltage of the second transistor rises and the equivalent on-resistance of the second transistor may decrease to provide a reduced resistance for the path between the first gate terminal and the source terminal of the main power transistor. This limits the potential at the first gate terminal. Subsequently, the circuit may act as a protection against drain overcurrent events in the first power device.

[0082] The device may further include a sense pad and the second terminal of the first resistor or sense load may be connected to the sense pad such that the current through the current sensing transistor can be measured. This can be used to determine the current in the main power transistor internally or externally by using the scaling factor of the active regions of the two transistors and the size of the first transistor.

[0083] The device may further include a second resistor. The second resistor may form a voltage divider with the first resistor. The selection of the resistances of the two resistors allows for easy adjustment of the possible maximum current level between the drain and source terminals of the main power transistor.

[0084] The second heterojunction transistor may be configured as an enhancement mode transistor. The potential at the gate terminal of the enhancement mode transistor may increase as the current through the current sensing (first) resistor increases to raise the potential on the gate of the second enhancement mode transistor and thus adjust its resistance. The critical current through the first power transistor may turn on the second enhancement mode transistor to limit the potential on the gate of the main power transistor. The described circuit may act as a protection against drain overcurrent events in the first power device.

[0085] The second heterojunction transistor can be configured as a depletion-mode transistor. When there is no current in the first power device, the gate of the second transistor is grounded, but due to the normally-on property, current still flows through the depletion-mode transistor. In this mode, the second heterojunction transistor acts as a resistive load between the gate and the source of the first main power device. The potential at the gate terminal of the second heterojunction transistor can increase as the current through the current sensing (first) resistor increases, thereby increasing the potential on the gate of the second heterojunction transistor. The critical current through the first power transistor can result in a potential higher than the second threshold voltage of the normally-on transistor. This causes a steep increase in the on-resistance of the second heterojunction transistor, which in turn limits the potential on the gate of the main power transistor. The circuit described herein can act as protection against drain overcurrent events in the first power device.

[0086] According to a third aspect of the present disclosure, the sensing and protection function can refer to sensing both the current through the first terminal of the first power heterojunction transistor and the voltage of the first gate terminal of the power heterojunction transistor and limiting the voltage applied to the first gate of the power heterojunction transistor due to either of the sensing functions.

[0087] In this aspect of the present disclosure, the second transistor configured as a normally-on device can further include a third gate terminal (such that the second transistor itself has two gates). The second gate terminal can be connected to the midpoint of a voltage divider; and the device can further include a first resistor, and wherein the third gate terminal is connected to the first terminal of the resistor. In other words, the second transistor can be a dual-gate transistor.

[0088] The second heterojunction transistor can include at least two sets of a plurality of highly doped semiconductor regions of a first conductivity type, and the second gate terminal can be formed on the plurality of highly doped semiconductor regions, wherein the third gate terminal can be formed on another plurality of highly doped semiconductor regions. Each of the plurality of highly doped semiconductor regions can include at least two highly doped semiconductor regions that are laterally spaced from each other in a second dimension. In other words, the dual-gate transistor can have two gates including discontinuous p-GaN gate islands, as described above.

[0089] A normally-on (depletion-mode) transistor having two gates can be used as the second transistor, wherein the first gate is connected to the midpoint of the voltage divider described above and the second gate is connected to a resistor / resistive load attached to a current sensor device. In this case, if a condition or another condition (overcurrent detection in the first main power device or over-gate voltage detection in the first main power device) occurs, the on-state resistance of the second heterojunction transistor is triggered to drop sharply to pull down the gate potential until neither of the conditions (overcurrent detection or over-gate voltage detection) is detected. This results in limiting the gate voltage to a desired level to increase the safe operating area and robustness.

[0090] According to a third aspect of the present disclosure, the device may further include a voltage divider. Terminals of the voltage divider may be connected to a first gate terminal (of the main power transistor) and a midpoint of the voltage divider may be connected to a portion of a second gate terminal of a second heterojunction transistor, in which case the second heterojunction transistor is configured as a normally-on (depletion-mode) transistor and has two gate control terminals. The voltage divider may be integrated with the first power transistor and the second transistor into, for example, a 2DEG layer. Alternatively, the voltage divider may be formed by an external resistor or a resistive load. A second portion of the gate terminal may be connected to a sense resistor or a sense load and a source of a third heterojunction transistor (a current sense transistor).

[0091] When a condition of overcurrent or over-gate voltage is detected in the main power transistor, the second transistor may be used to reduce or limit the gate voltage on the main power (first) transistor.

[0092] The voltage divider may include at least two series resistors. At least two resistors of the voltage divider may each include a two-dimensional electron gas (2DEG).

[0093] The heterojunction power device may include a voltage limiting circuit formed by two resistors forming the voltage divider and an active-switching low-voltage depletion-mode (second) transistor. A drain-source path of the active-switching low-voltage depletion-mode transistor may be connected between a gate and a source of the main power transistor and is connected in parallel with the voltage divider. A midpoint of the voltage divider may be connected to a gate terminal of the second (low-voltage) depletion-mode transistor. In this embodiment, when the potential of the gate terminal of the main power device increases, the resistance of the depletion-mode transistor may decrease and thus adjust the resistance between the gate terminal of the main power device and the source terminal of the main power device. The voltage divider formed by the resistors may determine the potential on the gate terminal of the depletion-mode transistor. The described circuit may protect the main power gate terminal (of the first power device) from over-gate voltage events.

[0094] According to a fourth aspect of the present disclosure, there is provided a heterojunction chip including a first power heterojunction transistor (as a main transistor) and at least one current sense transistor, wherein the at least one current sense transistor provides dual current sensing: current sensing for internal use for overcurrent or over-temperature self-protection and current sensing for external use for optimizing the drive / control of the first power heterojunction transistor or for additional protection against overcurrent or over-temperature.

[0095] At least one current sensing transistor may be a third transistor, as described in a previous aspect of the present invention. The at least one current sensing transistor has the same structure as the first power heterojunction transistor, but is scaled to a much smaller active region or gate width (by a factor X, where X is much greater than 1) respectively compared to the active region or gate width of the first power heterojunction transistor. The at least one current sensing transistor is monolithically integrated with the heterojunction chip. The at least one current sensing transistor has its drain and gate terminals connected to the drain and gate terminals of the first power heterojunction transistor respectively.

[0096] The at least one current sensing transistor can be used for:

[0097] (i) Using an internal protection of a resistor load or a sense load connected to its source terminal and an additional monolithically integrated feedback circuit to locally provide a signal to the gate to reduce or limit the gate voltage amplitude or the pulse width of the switching frequency in the first power heterojunction transistor when a specific current limit is reached in the first power heterojunction transistor, and

[0098] (ii) Sending a signal (in the form of current or voltage) to an external controller / microprocessor to optimize the drive / control of the first power heterojunction transistor and / or to additionally protect the first power heterojunction transistor by controlling the provision of the gate signal through a driver circuit.

[0099] The feedback circuit may include a second transistor, as described in a previous aspect of the present invention.

[0100] "External device / circuit / component" should be understood as a device / circuit / component that is not monolithically integrated with the heterojunction chip but may be located in a different package or co-packaged with the heterojunction chip. This device / circuit / component can be fabricated from silicon or standard materials. The driver circuit (gate driver) may be located externally or may be monolithically integrated within the heterojunction chip. Alternatively, part of the gate driver may be located internally to provide an interface with the first power heterojunction transistor and part of the gate driver may be located externally and fabricated from (for example) a cheaper material such as silicon. Advantageously, the controller / microprocessor may be located externally as this allows high performance to be achieved at very low cost.

[0101] According to an embodiment of the fourth aspect of the present disclosure, dual current sensing is performed by two or more separately integrated current sensing transistors, each of the current sensing transistors providing an internal current sensing and protection function or an external current sensing and / or protection function. The two or more current sensing transistors may be the same or different. The two or more current sensing transistors may include multiple finger-like device layouts or several fingers. For example, the current sensing transistor may include one finger, the second current sensing transistor may include a two-finger structure, and the first power heterojunction transistor may include several fingers (1 to 3 orders of magnitude greater than the number of these fingers, for example 100 fingers or 1000 fingers).

[0102] In this embodiment, a current sensing transistor designed to provide external current sensing and / or protection can be connected to an external precision resistor. The precision resistor will not be affected by the manufacturing tolerances of the process used to fabricate the heterojunction device and will be less or almost not affected by temperature variations of the first power heterojunction transistor or the surrounding environment. The voltage drop across this precision resistor can provide a more accurate estimate of the true current in the first power heterojunction transistor. The voltage across this external resistor designed to provide external current sensing and / or protection or the current directly through the current sensing transistor can be fed into a controller / microprocessor unit, which can further analyze it and instruct the gate driver to limit or adjust (in amplitude or time or pulse width or frequency or duty cycle) the signal applied to the gate driver to optimize system operation and protect the first power heterojunction transistor or a system in which part of it is a heterojunction chip.

[0103] A current sensing transistor designed to provide internal current sensing and protection can have its source terminal connected to an internal (integrated) resistor or the first terminal of a sense load. The sense load can be formed by a resistor or a resistive load or a monolithically integrated low-voltage transistor or a series and / or parallel combination of a resistor and at least one monolithically integrated low-voltage transistor. The gate of the low-voltage transistor can be connected to its drain or source or the source of the first power heterojunction transistor or any other node of the sense load. Alternatively, the gate of the low-voltage transistor of the sense load can be connected to the gate of the first power heterojunction transistor. The use of a combination of series and / or parallel resistors in the sense load connected to a low-voltage normally-on or normally-off transistor can provide some compensation for the loss of linearity of the current in the current sensing transistor divided from the current in the first power heterojunction transistor due to the large current flowing in the heterojunction chip. This loss of linearity can be attributed to the temperature increase caused by the self-heating effect in the first power heterojunction transistor. For example, the equivalent on-state resistance of a low-voltage normally-on or normally-off device can decrease as the gate voltage increases (i.e., high current in the first power heterojunction transistor). This decrease in the equivalent resistance through which the current flows in the current sensing transistor can (partially) compensate for the increase in the resistance of the resistor in the sense load of the low-voltage transistor or the 2DEG (for example) attributed to the temperature increase.

[0104] Any of the monolithic integrated (internal) resistors or the resistors in the sense load can be made of 2DEG or a metal layer used in the program. Alternatively, it can be made of one of the existing layers in the program (such as the pGaN layer) or a custom resistor layer (such as CrSi). If, for example, several metal layers are used to fabricate ohmic or Schottky contacts to provide a field plate effect or conduct current, any of these metal layers can be used to fabricate the (several) resistors in the sense load to provide a voltage drop across them, which is proportional to the current flowing through the current sensing transistor and thus proportional to the measurement of the current flowing through the first power heterojunction transistor.

[0105] The (several) resistors in the sense load described above can have a temperature-dependent resistance. For example, it is known that 2DEG and metal layers have a higher resistance at higher temperatures and this behavior is replicated relatively well from device to device. Therefore, the resistors in the sense load can be used as a relative temperature sensor. The reference resistance can be measured at a reference temperature. The variation in resistance can be correlated with the temperature variation. For example, if the temperature increases due to self-heating during the operation of the first power heterojunction transistor or due to an increase in the ambient temperature, the 2DEG resistance or the metal resistance of the internal resistor increases. Therefore, the voltage drop across this resistor will depend not only on the current flowing through the current sensing structure (and is proportional to the current in the first power heterojunction transistor), but also on the resistance variation with temperature. When the temperature increases (due to, for example, the self-heating effect), the voltage across the resistor load (or sense load) connected to the source terminal of the current sensing transistor increases. Therefore, the voltage drop across this resistor load varies not only with the current, but also with the temperature. The signal can be used to provide internal or external protection against both overcurrent and / or over-temperature conditions. In this way, over-temperature protection and overcurrent protection are provided by the action of the current sensing transistor described above and the internal resistor made of 2DEG or a metal layer or the internal sense load.

[0106] In this embodiment, the protection function can be achieved by reducing the resistance of the second heterojunction transistor (as part of the feedback circuit) that can be connected between the source and the gate of the main power transistor. The voltage drop across the current sense load increases with current and temperature, which can directly or by using other components in the integrated feedback circuit increase the gate voltage of the second heterojunction transistor and thus reduce the resistance between the gate and the source of the main power transistor.

[0107] In a second embodiment of the fourth aspect of the present disclosure, a single current sensing transistor provides dual current sensing in the form of a single monolithic integrated current sensing transistor characterized by an additional sense pad connected to its source terminal to provide a voltage signal to an external circuit.

[0108] In this embodiment, the current sensing transistor can provide dual current sensing (both external and internal). A single current sensing transistor has its source terminal connected to an integrated resistor or a sensing load. The internal circuit including a second heterojunction transistor uses the voltage drop across this load to provide feedback to the gate such that when an overcurrent is detected, the gate voltage can be adjusted to limit or reduce the current. An additional sensing pad connected to the source of the current sensing transistor can be connected to a controller / microprocessor unit which will perform external current reading and / or current protection and provide appropriate control through an external driver to limit or adjust the amplitude, pulse width, or switching frequency of the gate signal of the first power heterojunction transistor.

[0109] As in the previous case, in this embodiment, an internal sensing resistor or sensing can also be used to provide overtemperature protection based on the variation of the voltage drop across the resistive or sensing load with temperature. A feedback circuit can be used to provide either or both overcurrent or overtemperature protection by limiting or adjusting (in amplitude or time or frequency or duty cycle) the signal applied to the gate driver to optimize system operation and protect the first power heterojunction transistor or a system where part of it is a heterojunction chip. As in the previous case, the protection function can be achieved by reducing the resistance of the second heterojunction transistor connected between the source and the gate of the main power transistor, as described in a previous aspect of the present disclosure.

[0110] Alternatively, an external sensing load can be connected to the sensing pad for accurately reading the current of the first power heterojunction transistor. The voltage across this external sensing load or the current directly through a current sensor can be fed into a controller / microprocessor unit which can further analyze it and instruct the gate driver to limit or adjust (in amplitude or time or frequency or duty cycle) the signal applied to the gate driver to optimize system operation and protect the first power heterojunction transistor or a system where part of it is a heterojunction chip.

[0111] In a third embodiment of the fourth aspect of the present disclosure, current flows through a metal resistor by at least one current sensing transistor, and at least part of the current in the first power heterojunction transistor also flows through the metal resistor simultaneously. This metal resistor can be part of an existing metallization that connects the internal source contact of the multi-finger structure to the source pad (source terminal). The fingers are connected to a distributed metal track / bus, and the distributed metal track / bus is connected to the source pad. The fingers can be connected to the track / bus further away from the source pad, in which case it will see a larger metallization resistance than the fingers closer to the source pad (because the current from the fingers flows through a longer path of the source metallization track). At least one current sensing transistor can be further away from the metal pad to encounter a larger resistance of the metallization track and the voltage drop generated by the multiple and distributed currents passing through this resistance by other fingers belonging to the first power heterojunction transistor.

[0112] At least one current sensing transistor can be characterized by a monolithic integrated sensing load as described above. The terminals of this sensing load can be connected to the source of at least one current sensing transistor and the other terminal can be connected to the metal resistor associated with the metal track as described above. Alternatively, the metal resistor described above can include an additional 2DEG or a metal resistor in series with the resistor of the metal track or a sensing load (as described above). The source terminal of at least one current sensing transistor can be connected to a sensing pad for external current sensing and / or protection and / or connected to an internal feedback circuit to exert an effect on the gate as described above. The sensitivity and linearity of the voltage potential at the source terminal of at least one current sensing transistor can be enhanced by using this additional metal transistor that can include a source track and through which at least part of the current of the first power heterojunction transistor flows.

[0113] In another embodiment of the fourth aspect of the present disclosure, the internal feedback circuit includes a common-source, common-drain, or common-gate amplifier stage and the voltage drop across the sensing pad as an input. The circuit can further use a voltage divider. The voltage divider can be composed of integrated devices (such as Schottky diodes, resistors, capacitors, diodes, transistors that connect the gate to the source or drain, or transistors whose gate is controlled by a similar voltage divider). The output of the amplifier stage can be used for overcurrent or over-temperature protection by turning on a second heterojunction transistor whose drain is attached to the gate terminal of the first power heterojunction transistor as described in the first aspect of the present disclosure. Alternatively, the output of the amplifier stage can be used as an external output or fed back to components of an integrated circuit other than for overcurrent protection. Embodiments of this configuration will be further given in the present disclosure (refer to the detailed description in the figure part).

[0114] According to another aspect of the present disclosure, there is provided a method of manufacturing a heterojunction power device based on group III nitride semiconductors, the method comprising:

[0115] Form a first group-III nitride semiconductor region formed on a substrate, wherein the first group-III nitride semiconductor region includes a first heterojunction, and the first heterojunction includes at least one two-dimensional carrier gas of a second conductivity type;

[0116] Form a first terminal operatively connected to the first group-III nitride semiconductor region;

[0117] Form a second terminal that is laterally spaced apart from the first terminal and operatively connected to the first group-III nitride semiconductor region;

[0118] Form a first gate terminal formed on the first group-III nitride semiconductor region between the first terminal and the second terminal;

[0119] Form a second group-III nitride semiconductor region formed on the substrate, wherein the second group-III nitride semiconductor region includes a second heterojunction, and the second heterojunction includes at least one two-dimensional carrier gas of the second conductivity type;

[0120] Form a third terminal operatively connected to the second group-III nitride semiconductor region;

[0121] Form a fourth terminal that is laterally spaced apart from the third terminal in a first dimension and operatively connected to the second group-III nitride semiconductor region, wherein the fourth terminal is connected to the first gate terminal;

[0122] Form a second gate region formed on the second group-III nitride semiconductor region between the third terminal and the fourth terminal;

[0123] Form a second gate terminal contacting the second gate region,

[0124] Form a third group-III nitride semiconductor region formed on the substrate, wherein the third group-III nitride semiconductor region includes a third heterojunction, and the third heterojunction includes at least one two-dimensional carrier gas of the second conductivity type;

[0125] Form a fifth terminal operatively connected to the third group-III nitride semiconductor region;

[0126] Form a sixth terminal that is laterally spaced apart from the fifth terminal in a first dimension and operatively connected to the third group-III nitride semiconductor region, wherein the sixth terminal is operatively connected to the second terminal; and

[0127] Form a third gate region formed on the third group-III nitride semiconductor region between the fifth terminal and the sixth terminal;

[0128] Form a third gate terminal that contacts the third gate region, where the third gate terminal is operatively connected to the first gate terminal, and

[0129] where the third heterojunction transistor is used for current sensing of the first power heterojunction transistor and the second power heterojunction transistor is configured for sensing and / or protection functions of the first power heterojunction transistor.

[0130] The first plurality of highly doped semiconductor regions (in the first transistor) and the second plurality of highly doped semiconductor regions (in the second transistor) can be fabricated in the same process step. The difference between continuous and discontinuous highly doped semiconductor regions can be achieved by changing the layout of the same mask.

[0131] Finally, in the overview discussed above, the present disclosure describes the following:

[0132] The present disclosure is directed to a semiconductor device using GaN technology having integrated sensing and protection circuitry, where a main power transistor using a gate structure based on a continuous p-GaN layer and a transistor for sensing are fabricated using the same gate technology characterized by continuous or discontinuous p-GaN layers. The drain terminal of at least one of the sensing transistors (the second heterojunction transistor) can be connected to the gate terminal of the main power transistor. At least one current sensing transistor having the same structure as the main power switch but having a reduced area (or gate width) relative to the main power switch is monolithically integrated with the first power transistor (the main power transistor). At least one current sensing can be connected to a sense resistor or a sense load and can provide internal or external current sensing. A feedback circuit can be monolithically integrated to provide internal protection. Different embodiments of the feedback and protection circuitry are described to mitigate gate events of drain overcurrent or over-temperature and overcurrent or gate overvoltage. This contributes to durable operation and an increased safe operating area. In a main embodiment, a normally-on depletion-mode transistor (which includes a gate structure based on a discontinuous p-GaN layer, the discontinuous p-GaN layer including islands within a strip or closed shape surrounding the cell) senses a specific intrinsic gate voltage or / and drain current of the main power transistor and is used to reduce or limit the gate voltage on the main power transistor when a condition of over-gate voltage or over-drain current is detected in the main power transistor. The specific on-state gate voltage (as mentioned above) is equal to the voltage at which a two-dimensional electron gas (2DEG) forms under the p-GaN islands and results in a sharp drop in the on-state resistance of the normally-on depletion-mode transistor.

[0133] In other embodiments of the present disclosure, a heterojunction chip is provided, which includes a main power transistor, at least one current sensing transistor, a sensing load, and a feedback circuit, wherein the at least one current sensing transistor provides dual current sensing: the current sensing is for internal use by the current feedback circuit for overcurrent or over-temperature self-protection and the current sensing is for external use for optimizing the drive / control of the first power heterojunction transistor or for additional protection against overcurrent or over-temperature. The protection can be accomplished by reducing the resistance of the second heterojunction transistor between the gate and the source of the main power transistor. The external microprocessor can analyze and process the external current sensing signal and instruct the external / internal gate driver to limit or adjust (in amplitude or time or pulse width or frequency or duty cycle) the signal applied to the gate driver to optimize the system operation and protect the first power heterojunction transistor or a system of which it is a part of the heterojunction chip. The sensing load can be made of an internal or external resistor, and the internal or external resistor is made of 2DEG or other materials or layers and / or low-voltage transistors. It can also contain a resistance contribution from the source metallization track, and at least a part of the current in the main power device flows through the source metallization track.

[0134] The internal feedback circuit can include a common-source, common-drain, or common-gate amplifier stage and the voltage drop across the sensing pad as an input. The circuit can further use a voltage divider, a Schottky diode, a resistor, a capacitor, a diode, a transistor. The output of the amplifier stage can be used for overcurrent or over-temperature protection by turning on the second heterojunction transistor whose drain is attached to the gate of the main power device.

Description of the Drawings

[0135] The present disclosure will be more fully understood with reference to the drawings. However, the drawings should not be considered as limiting the present disclosure to the specific embodiments shown, but are for illustration and understanding only.

[0136] Figure 1 A schematic cross-section of the active region of a prior art p-GaN HEMT is shown;

[0137] Figure 2 A schematic cross-section of the active region of a prior art depletion-mode HEMT with a Schottky gate terminal is shown;

[0138] Figure 3 A schematic circuit diagram of an overcurrent protection circuit according to an embodiment of the present disclosure is shown, wherein the overcurrent protection is constituted by a resistor and an active-switching low-voltage depletion-mode transistor (the second transistor) to control the potential on the gate terminal of the first power transistor;

[0139] Figure 4 A schematic perspective view of a depletion-mode transistor that can be used in an embodiment device according to the present disclosure is shown;

[0140] Figure 5 Shows a schematic circuit diagram of another embodiment of the present disclosure, wherein the device further includes a resistor or a resistive load;

[0141] Figure 6 Shows a schematic circuit diagram of another embodiment of the present disclosure, wherein an overcurrent protection circuit composed of a resistor and an active switching low-voltage enhancement-type transistor (second transistor) is implemented to control the potential on the gate terminal of the first power transistor;

[0142] Figure 7 Shows a schematic circuit diagram of another embodiment of the present disclosure, wherein an overcurrent protection circuit is implemented and an additional external terminal is provided;

[0143] Figure 8 Shows a schematic circuit diagram of another embodiment of the present disclosure, wherein an overcurrent protection circuit is implemented and the current sensing resistor is replaced by a properly scaled normally-on transistor;

[0144] Figure 9 Shows a schematic circuit diagram of a voltage limiting circuit, wherein the voltage limiting circuit is composed of two resistors forming a voltage divider and an active switching low-voltage depletion-type transistor (second transistor) to control the potential on the gate terminal of the first power transistor;

[0145] Figure 10 Shows a schematic circuit diagram, wherein the Figure 3 overcurrent protection circuit shown in Figure 9 and the overvoltage protection circuit shown in

[0146] Figure 11 are combined into a single integrated (or discrete) circuit having the same functionality; Figure 10 Shows a schematic perspective view of a double-gate terminal normally-on transistor that can be used in the circuit shown in

[0147] Figure 12 Shows an alternative schematic circuit diagram of a combined protection circuit according to an embodiment of the present disclosure; and

[0148] Figure 13 Shows a schematic top view of the layout design of the monolithic integration of a current sensing transistor, a main power transistor, and a sensing resistor.

[0149] Figure 14 Illustrates a block diagram of an additional embodiment of the present disclosure, which shows a heterojunction chip incorporating a main power transistor block, a current sensing block, and feedback current to provide both an internal sensing signal and an external sensing signal.

[0150] Figure 15A and Figure 15BDisclosed is a schematic circuit diagram of a heterojunction chip characterized by a main power transistor, two current sensing transistors, a feedback circuit, at least one sensing resistor, and a controller unit and a gate driver unit.

[0151] Figure 16 Disclosed is a schematic circuit diagram of a heterojunction chip characterized by a main power transistor, current sensing transistors designed to provide both internal current sensing and external current sensing, a sensing resistor, a feedback circuit, and a controller unit and a gate driver unit.

[0152] Figure 17 Disclosed is a schematic circuit diagram of a heterojunction chip characterized by a main power transistor, current sensing transistors designed to provide both internal current sensing and external current sensing, a low voltage depletion transistor that is part of the sensing load, a feedback circuit, and a controller unit and a gate driver unit.

[0153] Figure 18A Disclosed is a schematic circuit diagram of a heterojunction chip characterized by a plurality of fingers of a main power transistor, two current sensing transistors, and a metallization resistor that carries current from both a part of the main transistor and a part of the sensing load.

[0154] Figure 18B Disclosed is Figure 18A a schematic top view of an example of the layout design of the heterojunction chip described in

[0155] Figures 19A to 25 Disclosed is Figures 14 to 17 different possible schematic implementations of the internal feedback circuit block shown in

Detailed Description

[0156] The present disclosure will be more fully understood in light of the accompanying drawings. However, the drawings should not be considered as limiting the present disclosure to the specific embodiments shown, but are for illustration and understanding only.

[0157] Figure 3 Disclosed is a schematic circuit diagram of an overcurrent protection circuit according to an embodiment of the present disclosure, wherein the disclosed solution consists of a resistor and an actively switched low voltage depletion transistor (second transistor) to control the potential at the gate terminal of the main power transistor. The overcurrent protection circuit includes a first power transistor 19 formed by a current sensing transistor 16 and a main power transistor 19, a depletion transistor (second transistor) 14, and a current sensing resistor 15.

[0158] In this embodiment, the current sensing transistor 16 has the same structure as the main power device 19 but is scaled to a much smaller known area compared to the main power device 19 (by a factor X, where X is much larger than 1). The depletion transistor (second transistor) 14 is monolithically integrated with the first power transistor. The current sensing transistor 16 has its drain terminal and gate terminal connected to the gate terminal and drain terminal of the main power transistor 19, respectively. The source of the current sensing transistor 16 is connected to the terminal of a resistor 15 or a resistive load (which can be formed by a normally-on transistor). The resistor 15 or the resistive load can be monolithically integrated with the first power devices 16, 19 and the second transistor 14 (by, for example, using a 2DEG layer). Alternatively, the resistor 15 or the resistive load can be external. The second terminal of the resistor 15 can be connected to the source of the main power device 19 (as shown in Figure 3 a) or can be connected to ground. Alternatively, the second terminal of the resistor 15 can be connected to an independent pad to externally measure the current through the current sensing device 16 and thus determine the current in the main power device 19. The role of the resistor / resistive load 15 is to convert the current from the current sensing transistor 16 into a voltage drop across it. The first terminal of the resistor 15 can be connected to the gate terminal of the second heterojunction transistor, which can be a normally-on (depletion) device 14 (as shown in Figure 3 and described above) using either discontinuous or continuous p-GaN gate technology, or alternatively to a normally-off device. The circuit is used to reduce or limit the gate voltage on the first power transistors 16, 19 by using the above-mentioned depletion device 14 and resistor 15 or resistive element when an over-drain current condition is detected in the current sensing transistor 16. If an over-current condition is detected, the voltage drop across the current sensing resistor 15 increases and thus the voltage bias on the gate terminal of the transistor 14 increases to cause a sharp drop in the resistance of the transistor 14. This provides a reduced resistance for the path between the gate and source of the first power devices 16, 19 to thus limit the potential on the first gate terminal. The described circuit can act as protection against drain over-current events.

[0159] Figure 4 A schematic perspective view of the depletion device for the proposed protection circuit is shown.

[0160] The depletion transistor also includes a high voltage drain terminal 9 arranged to make physical contact with the AlGaN layer 1. The high voltage drain terminal 9 forms an ohmic contact with the 2DEG. The low voltage source terminal 8 is also arranged to make physical contact with the AlGaN layer 1 and also forms an ohmic contact with the 2DEG. The drain terminal 9 and the source terminal 8 consist of ohmic metal contacts on the surface of the AlGaN layer 1 or make direct contact with a good electrical connection to the 2DEG.

[0161] Regions of high p-doped III-V semiconductors 11 are formed in contact with the AlGaN semiconductor layer 1. These have the function of reducing the 2DEG carrier gas concentration under the highly doped region 11 when the device is unbiased, and are formed of p-GaN material in this embodiment. The p-GaN regions 11 are discrete regions and are spaced from each other in the second dimension (x-direction). The p-GaN regions 11 - also referred to as p-GaN islands - extend along a discontinuous line in the x-direction. The discontinuous layer of the p-type GaN gate is made of islands placed within a strip or closed shape. The highly p-doped GaN regions 11 can be doped with magnesium (Mg). The highly p-doped GaN regions 11 through which current flows extend along an axis perpendicular to the axis connecting the source terminal 8 and the drain terminal 9.

[0162] The highly doped layer 11 in the discontinuous gate structure of the depletion-mode device can be fabricated in the same process step as the highly doped layer of the main power transistor. All p-GaN layers (continuous or discontinuous) can be completed in the same process step. The difference between the continuous layer and the discontinuous layer is achieved by changing the layout of the same mask.

[0163] The gate control terminal 10 is configured above the highly doped region 11 to control the carrier gas density of the 2DEG at the interface of the semiconductor layers 1, 2. All the p-GaN islands 11 of the depletion-mode device are connected to the same gate electrode 10. The gate terminal 10 consists of metal contacts placed on the intermittent regions between the p-GaN islands 11. The electrical connection between the high voltage terminal (drain) 9 and the low voltage terminal (source) 8 is determined by the voltage signal applied to the third terminal (gate) 10. The gate control terminal 10 can be an ohmic contact or a Schottky contact.

[0164] The depletion-mode device described in the embodiment can be Figure 4 the depletion-mode AlGaN / GaN HEMT shown in. The proposed structure is superior to the depletion-mode AlGaN / GaN HEMT using prior art Schottky gates such as Figure 2 shown in.

[0165] The proposed depletion-mode device is capable of controlling the device threshold voltage by adjusting the layout design of the transistor rather than adjusting the epitaxial growth or the gate metal stack. The layout redesign results in an optimized device with much lower cost / effort than other currently available methods.

[0166] The depletion-type device used as a component can be a normally-on depletion-type device, where an increasing positive gate bias voltage (> 7V) can be applied before the conduction channel changes from drain-source to gate-source in the main on-state. Currently, in prior art devices, the voltage at which gate turn-on occurs is typically between 0.7V and 2V. At a higher positive gate terminal bias, the proposed depletion-type device can achieve an increase in the carrier gas density in the channel under the gate terminal to reduce the total on-state resistance of the device.

[0167] This gate structure of the depletion-type device allows for the fabrication of the depletion-type device in a fabrication process that cannot be used to directly form a depletion-type device with a Schottky contact on top of the AlGaN layer. In prior art devices, the gate of the depletion-type device would have to be fabricated using additional process steps.

[0168] Therefore, the use of this depletion-type device enables enhanced integration of protecting electronic devices and the main power switch. The monolithic integration of the above electronic devices allows for: reducing the total system size and cost, streamlining the BOM (Bill of Materials), and improving reliability. It can also lead to performance improvement by reducing parasitic components associated with the interconnections between discrete devices.

[0169] Figure 5 A schematic circuit diagram of another embodiment of the present disclosure proposed is shown. This is similar to Figure 3 the embodiment shown in and provides similar functionality; however, in this embodiment, the circuit includes another resistor 20.

[0170] A second resistor 20 is added in series with the current sensing transistor 16. The second resistor and the first resistor 15 form a voltage divider. The resistances of the two resistors 15, 20 are selected to allow easy adjustment of the maximum possible current level between the drain terminal and the source terminal of the main power transistor 19 in this arrangement.

[0171] Figure 6 A schematic circuit diagram of another embodiment of the present disclosure proposed is shown, where an overcurrent protection circuit composed of a resistor 15 and an active-switching low-voltage enhancement-type transistor (second transistor) 21 is implemented to control the potential on the gate terminals of the first power transistors 16, 19. This is similar to Figure 3 the embodiment shown in and provides similar functionality; however, the enhancement-type transistor 21 replaces the depletion-type transistor of the previous embodiment.

[0172] The heterojunction power device may include the overcurrent protection circuit described above, where the low-voltage depletion transistor is replaced by a low-voltage enhancement transistor 21. Similar to the previous embodiment, the potential at the gate terminal of the enhancement transistor 21 increases as the current through the current sensing resistor 15 increases. As the current through the high-resistance transistor 16 increases, the potential drop across the current sensing resistor 15 increases. This raises the potential on the gate of the low-voltage enhancement transistor 21 and thus adjusts its resistance. The critical current through the high-resistance transistor 16 can turn on the low-voltage enhancement transistor 21 to limit the potential on the gates of the first power transistors 16, 19. The described circuit can act as protection against drain overcurrent events.

[0173] Figure 7 A schematic circuit diagram showing another embodiment of the present disclosure is presented, where an overcurrent protection circuit is implemented, and an additional external terminal is provided. This is similar to Figure 3 the embodiment shown in and provides similar functionality; however, in this embodiment, an external terminal 22 and an external terminal 23 are included.

[0174] In this embodiment, the second terminal of the resistor 15 is used as the external terminal 22 instead of being connected to the source of the main power transistor 19. Additionally, another external terminal 23 is added to measure the current through the current sensing transistor 16.

[0175] Figure 8 A schematic circuit diagram showing another embodiment of the present disclosure is presented, where an overcurrent protection circuit is implemented and the current sensing resistor is replaced by a properly scaled normally-on transistor 24, where the drain terminal of the normally-on transistor 24 is connected to the gate terminal of the normally-on transistor 24. This is similar to Figure 3 the embodiment shown in and provides similar functionality. In this configuration, the normally-on transistor 24 will act as a resistive component. The source terminal of the transistor 24 can be connected to the source terminal of the main power transistor 19 or can be an external terminal.

[0176] Figure 9 A schematic circuit diagram of a voltage limiting circuit is shown, where the voltage limiting circuit consists of two series resistors 17, 18 forming a voltage divider and an active switching low-voltage depletion transistor (second transistor) 14 to control the potential on the gate terminal of the first power transistor. In this figure, the current sensing transistor is not explicitly shown, but the power transistor device incorporating the current sensing transistor is shown as a single transistor 26.

[0177] In this embodiment of the present disclosure, when a condition of over-gate voltage is detected in the first power transistor 26, the normally-on transistor 14 is used to reduce or limit the gate voltage on the first power transistor 26. The depletion-mode transistor 14 can be a normally-on transistor or, alternatively, a normally-off transistor. The gate voltage detection is accomplished by using voltage dividers 17, 18 attached to the gate of the first power device 26, where the midpoint is connected to the gate of the depletion-mode transistor 14. The voltage dividers 17, 18 can be integrated with the main power transistor 26 and the depletion-mode transistor 14 (e.g., by using a 2DEG layer). Alternatively, the voltage divider can include resistors or resistive loads (e.g., normally-on transistors) located outside the transistors 14, 26.

[0178] Figure 10 A schematic circuit diagram of an embodiment of the present disclosure that is proposed is shown, where the Figure 3 overcurrent protection circuit shown in Figure 9 and the overvoltage protection circuit shown in

[0179] are combined into a single integrated (or discrete) circuit having the same functionality. In this embodiment, the depletion-mode transistor of the previous embodiment is a dual-gate terminal normally-on transistor (second transistor) 25.

[0180] Figure 11 A schematic perspective view of the dual-gate terminal normally-on transistor in the circuit schematic shown in Figure 10 is shown. In this embodiment, there are two sets of multiple highly doped regions 11. The first gate contact 10 is connected to the first multiple highly doped regions, and the second gate contact 27 is connected to the second multiple highly doped regions.

[0181] Figure 12Shows an alternative schematic circuit diagram of a combined protection circuit according to an embodiment of the present disclosure. In this embodiment, the combined protection circuit can be used in an integrated (or discrete) circuit having an auxiliary gate circuit, such as the integrated circuit described in the PCT application "WO2019012293A1: A power semiconductor device with an auxiliary gate structure", and the entire content of this application is incorporated herein by reference.

[0182] Figure 13 Shows a schematic top view of a layout design of a monolithic integration of a current sensing transistor 16, a main power transistor 19, and a sensing resistor 15. In this embodiment, the current sensing transistor 16 and the main power transistor 19 share the same active region 29, the same drain pad 28, and the same gate pad 33, but do not have the same source metallization / pad. The sensing resistor 15 (2DEG resistor 30) is formed in the active region 31, isolated from the active regions of the current sensing transistor 16 and the main power transistor 19, and is connected in series with the two source terminals of the transistors 16, 19.

[0183] Figure 14 Illustrates a block diagram of an additional embodiment of the present disclosure. In this embodiment, a main power transistor block (first power heterojunction transistor) 34, a current sensing transistor block 35, and a feedback circuit block 40 are monolithically integrated on a heterojunction (GaN) chip 100. In operation, an internal sensing signal from the current sensing transistor block 35 can be applied to the feedback circuit block 40, where the signal can be modified in a suitable form or (for example) inverted and / or amplified. The output of the feedback circuit 40 can be supplied to the main power transistor 34 to reduce or limit the amplitude of its gate voltage or the pulse width of the switching frequency when a specific current limit is reached in the main power transistor. Additionally, the current sensing circuit can provide an external sensing signal to an external controller / microprocessor (which is not monolithically integrated but can be co-packaged) to optimize the drive / control of the main power transistor and / or to additionally protect the main power transistor by controlling the provision of gate signals through a driver circuit. Additionally (or alternatively), the feedback signal to the external controller / microprocessor can be provided by the feedback block 40.

[0184] Figure 15A Schematically illustrates an additional embodiment of the present disclosure. This is a device with Figure 14An example of a circuit for the functionality of the embodiments described herein. This embodiment includes a main power transistor 19 and two current sensing transistors 16, 44 monolithically integrated on a heterojunction chip 110a. Transistors 16 and 44 may be or multiple finger structures placed side by side with the main power transistor 19 made of multiple fingers. Transistors 16, 44, and 19 share the same drain terminal, and transistors 16, 44, and 19 are driven by the same gate signal but have different source terminals. The first current sensing transistor 16 is connected to an integrated resistor 15. The internal sensing signal at the source of transistor 16 is applied to a monolithic feedback circuit 43. The feedback circuit 43 may include a second heterojunction transistor (not shown in the figure). The output of the internal feedback circuit is applied to the gate terminal of the main power transistor 19 and is operable to Figure 14 the feedback circuit block 40 described in. An external sensing signal is provided at the source of transistor 44. In this example, the external sensing signal is the voltage drop across an external precision resistor 46. This signal is fed into a controller / microprocessor unit 41, which may further analyze this signal and instruct the gate driver 42 to limit or adjust (in amplitude or time or frequency or duty cycle) the signal applied to the gate driver to optimize system operation and protect the main power transistor or a system where a part of it is the heterojunction chip 110a. The controller / microprocessor unit 41, the gate driver 42, and the precision resistor 46 may be co-packaged or provided on a common printed circuit board. Alternatively, the gate driver 42 may be monolithically integrated within the heterojunction chip 110a (not shown in the figure). Another alternative is to combine 42 and 43 in a single unit and monolithically integrate it in the heterojunction chip 110a (not shown in the figure).

[0185] Figure 15B Schematically illustrates an operation similar to Figure 15A the example shown in. In this embodiment, the current through the sensing transistor 44 is directly fed into the controller / microprocessor unit 41.

[0186] Figure 16 Schematically illustrates a similar to Figure 15BAdditional embodiments of the present disclosure of the embodiments shown herein. In the example shown in this embodiment, a single current sensing transistor 16 is used to provide both an internal sensing signal and an external sensing signal provided at the source terminal of the current sensing transistor. This embodiment also includes an integrated resistor 15, an integrated feedback circuit 43, a controller / microprocessor unit 41, and a gate driver 42. In this embodiment, for example, the controller / microprocessor unit 41 can accurately detect the voltage drop across the resistor 15, which is proportional to the current flowing through the current sensing transistor 16, which in turn is proportional (largely proportional) to the current flowing in the main transistor 19. This signal is further processed to instruct the gate driver 42 to limit or adjust (in amplitude or time or frequency or duty cycle) the signal applied to the gate driver to optimize system operation and / or protect a system where the first power heterojunction transistor or a part thereof is the heterojunction chip 110a.

[0187] Figure 17 An additional embodiment of the present disclosure is schematically illustrated. In this embodiment, the transistor 36 is used as a sensing load instead of the resistor 15 as in previous similar embodiments. In this example, the transistor 36 is a low voltage depletion type transistor. This transistor can have a structure similar to the structure of the transistor shown in Figure 4 herein. The gate terminal of the transistor 36 is connected to the gate terminal of the main power transistor 19. This configuration can provide some compensation for the loss of linearity of the current signal of the current sensing transistor 16 that varies according to the current of the main transistor 19. This loss of linearity can be attributed to the temperature increase caused by the self-heating effect in the main transistor 19. In this example, the equivalent on-state resistance of the low voltage normally-on device 36 can decrease as the gate voltage increases (i.e., high current in the first power heterojunction transistor). This decrease in the equivalent resistance through which current flows in the transistor 36 can (partially) compensate for the increase in the resistance of the 2DEG of the transistor 16, for example, attributed to the temperature increase. The current sensing signal can also be used internally (connected to the feedback circuit 43) or externally (terminal 37).

[0188] In other examples (not shown here), a combination of series and / or parallel resistors in the sensing load connected to a low voltage normally-on or normally-off device can be used. The combination of these transistors and low voltage normally-on or normally-off transistors can provide an improved equivalent sensing load to improve the accuracy of current sensing.

[0189] Figure 18A An additional embodiment of the present disclosure is schematically illustrated. In this embodiment, the equivalent circuit of the main power transistor 19 is drawn as a plurality of parallel transistors (50, 51, 52), which represent having based on Figure 18BThe different fingers in the device with a layout of a multi-finger structure in an angled configuration as shown. Resistors (59, 60, 61) represent the track metallization resistance in series with each finger of the device. Resistor 58 is similar to the integrated resistor 15 described in the previous embodiment, and resistor 57 is similar to the external resistor 46 described in the previous embodiment. Figure 18B The drain terminal 47, source terminal 48, and gate terminal 49 are also marked therein. This embodiment can also provide different current sensing signals 55, 56 that can be used internally or externally. In this embodiment, by sensing the current flowing through the metal resistor 59 of the HEMT 58, while at least a part of the current of the first power heterojunction transistor also flows through the metal resistor 59 (the current through the transistor 52). This metal resistor 59 can be a part of the existing metallization that connects the individual source contact regions of the multi-finger structure to the source pad (source terminal 48). The fingers are connected to a distributed metal track / bus, which is connected to the source pad, as Figure 18B shown. The current sensing finger of the transistor 53 can be connected to the track / bus further away from the source pad. In this case, it will see a larger metallization resistance than the fingers closer to the source pad (because the current from it flows through a longer path of the source metallization track). The sensitivity and linearity of the voltage potential at the source terminal of the sensing transistor 53 can be improved by using this additional metal resistor 59 that can include the source track resistance as described above and through which at least a part of the current of the first power heterojunction transistor flows.

[0190] Figure 19A , Figure 19B and Figure 19C illustrate additional embodiments of the present disclosure proposed. In this embodiment, a possible implementation of the internal feedback circuit 43 is given. The output of the current sensing signal at the source of the sensing transistor 16 can be amplified by a depletion-type (normally-on) D-HEMT 63 (or in different instances, an enhancement-type E-HEMT) in a common-gate configuration with a low supply voltage VDD. The circuit also includes additional integrated resistors 62, 64. The output signal of the illustrated common-gate amplifier can be supplied to the second heterojunction transistor 14 shown in the previous embodiments of the present disclosure proposed (as Figure 19A shown) or another transistor 65 ( Figure 19B and Figure 19C ), but having a function similar to that of the transistor 14. The drain terminal of the second transistor 14 can be connected to the gate terminal of the main power transistor, as Figure 19A shown. As Figure 19BAs shown, the drain terminal of transistor 65 can be connected to an integrated auxiliary gate circuit. The auxiliary gate circuit can include an auxiliary transistor (not shown in the figure), which connects one of its terminals to the gate of the first power transistor. The gate of this auxiliary transistor can be connected to the drain terminal of transistor 65. Alternatively, Figure 19C the drain of transistor 65 shown can be connected to an external circuit (not shown in the figure). Capacitors, such as those in parallel with resistor 15 or between the supply voltage VDD and the source of the current sensing HEMT 16, can be added to improve the dynamic behavior of the circuit.

[0191] In different embodiments, the additional resistors 62, 64, and resistor 15 can be replaced by other integrated devices - such as current sources using HEMTs, diodes, HEMTs with the gate connected to the source, or HEMTs with the gate controlled by a voltage divider. Depending on the specific embodiment, linear amplification of the current signal or a non-linear over-current signal can be achieved for control or protection applications. The output (terminal 90) of the amplifier circuit can be used internally or externally for control purposes.

[0192] Figure 20 An additional embodiment of the present disclosure is illustrated. In this other embodiment, an additional transistor 66 is added in series with the amplifying transistor 63. This can result in an improvement in the linearity, gain input, or output impedance of the amplifier. Alternatively, this can increase the desired non-linearity of the over-current protection circuit and can maintain the over-current signal and protect the device after the current in the sensing HEMT 16 collapses due to the over-current protection circuit. This latter function is achieved by, for example, a common-gate amplifier HEMT 63 coupled to an E-HEMT 66 with the gate connected to a positive bias. In this case, increasing the current sensing signal will increase the resistance in the common-gate HEMT 63. Therefore, when the amplifying transistor 63 is less conductive, both the drain and source of the additional HEMT 66 reach a higher potential, so the gate-source voltage of HEMT 66 is reduced and an immediate pull-down of the over-current signal after the HEMT current collapse is avoided.

[0193] Figure 21 An additional embodiment showing different possible implementations of an internal feedback circuit 43 is illustrated. In this embodiment, the feedback circuit includes an amplifier that includes a HEMT 70 in a common-source arrangement. The amplifying HEMT can be a D-HEMT, and the resistive loads 15 and 69 can be designed such that the output of the amplifier produces a signal that increases as the reverse current from source to drain increases in the main power HEMT 19. Detecting the reverse current can be used to control the main gate 10 to reduce conduction losses.

[0194] Figure 22An additional embodiment showing different possible implementations of the internal feedback circuit 43 is illustrated. The amplifying HEMT 74 can be a HEMT in a common-source configuration, where the output voltage from the source of the current-sensing HEMT 16 is shifted towards the supply voltage. The voltage shift can be achieved by an integrated element such as the diode 71 shown here. Alternatively, a resistor or a HEMT with its gate controlled by a voltage divider can be used. The voltage shift brings the input of the common-source amplifier circuit to an optimized level to achieve different design objectives, such as maximum linearity or maximum gain. The output (terminal 90) of the amplifier circuit can be used internally or externally for control purposes.

[0195] Figure 23 An additional embodiment of the present disclosure is illustrated. This embodiment shows another example of an amplifying HEMT 78 in a common-source arrangement. This arrangement is commonly referred to as a current mirror. In this example, the current-sensing load is a HEMT 76 whose gate terminal is connected to its drain terminal. Connecting the resulting output voltage as the input of the common-source amplifier forms a current mirror circuit.

[0196] Figure 24 An additional embodiment is illustrated, where the amplifying circuit can be a common-drain circuit. Similar to the common-source amplifying circuit described in Figure 22 , the output of the current-sensing HEMT 16 can be shifted towards the supply voltage to increase the amplification factor. The output (terminal 90) of the amplifier circuit can be connected to a second heterojunction transistor (65 / 14), or can be used internally or externally for control purposes.

[0197] Figure 25 An additional example is illustrated, where the amplifying circuit can consist of more than one amplification stage. Different embodiments can be proposed including multiple amplification stages of the same type (e.g., two common-source stages) or different types (e.g., a common-source stage followed by a common-drain stage). The output (terminal 90) of the amplifier circuit can be connected to a second heterojunction transistor (65 / 14), or can be used internally or externally for control purposes.

[0198] In addition, more than one amplifying / feedback circuit can be connected to the same current-sensing HEMT. This can be used to generate: an optimized linear signal for current measurement, and an optimized non-linear signal for current protection. The outputs of the two types of amplifying / feedback circuits can be connected to the gate of the second heterojunction transistor to act on the gate voltage of the main power transistor. In another example, one amplifier circuit can be optimized for reverse current, and one amplifier circuit is optimized for forward current.

[0199] List of reference numerals

[0200] 1: AlGaN layer

[0201] 2: GaN layer

[0202] 3: Transition layer

[0203] 4: Silicon substrate

[0204] 5: Substrate terminal

[0205] 6: SiO2 passivation

[0206] 7: Surface passivation dielectric

[0207] 8: Source terminal / Metallization

[0208] 9: Drain terminal / Metallization

[0209] 10: Gate terminal / Metallization

[0210] 11: Highly doped pGaN cap

[0211] 12: Schottky gate terminal

[0212] 13: Continuous conduction channel at zero gate-source bias

[0213] 14: Depletion-mode transistor

[0214] 15: Current sensing resistor

[0215] 16: High-resistance transistor

[0216] 17, 18: Divider resistors

[0217] 19: Low-resistance transistor

[0218] 20: Resistor

[0219] 21: Low-voltage enhancement-mode transistor

[0220] 22, 23: External terminals

[0221] 24: Additional normally-on transistor

[0222] 25: Dual-gate depletion-mode transistor

[0223] 26: Main power transistor

[0224] 27: Additional gate of dual-gate transistor

[0225] 28: Drain pad metal

[0226] 29: Transistor active region

[0227] 30: 2DEG resistor

[0228] 31: 2DEG resistor active region

[0229] 32: Source pad metal

[0230] 33: Gate pad metal

[0231] 34: Main power transistor frame

[0232] 35: Current sensing transistor frame

[0233] 36: Depletion-type transistor as sensing load

[0234] 37: External sensing terminal

[0235] 40: Feedback circuit block

[0236] 41: Controller / Microprocessor unit

[0237] 42: Gate driver

[0238] 43: Feedback circuit

[0239] 44: Current sensing transistor

[0240] 46: Sensing resistor

[0241] 47: Drain terminal / pad

[0242] 48: Source terminal / pad

[0243] 49: Gate terminal / pad

[0244] 50: Main power transistor

[0245] 51, 52: Main power transistor

[0246] 53, 54: Current sensing transistor

[0247] 55, 56: Sensing terminal

[0248] 57, 58: Sensing transistor

[0249] 59, 60, 61: Source rail metallization resistor

[0250] 62, 64, 67, 69, 72, 73, 75, 77, 80, 81, 82, 86: Resistor

[0251] 63, 70, 76, 78: Depletion-type transistor

[0252] 65, 66, 74, 83, 85: Enhancement-type transistor

[0253] 68, 71, 79: Diode

[0254] 90: Amplifier circuit output terminal

[0255] 100: Heterojunction chip block

[0256] 110a, 110b, 130, 140: Heterojunction chips

[0257] In the present disclosure, unless explicitly specified, a heterojunction transistor may be any known transistor based on a heterojunction (such as a p-gate HEMT transistor) or a Schottky gate transistor or an insulated gate transistor (such as a MISFET (metal-insulator-semiconductor field effect transistor)). A diode may be a Schottky diode, a Zener diode, or a pn diode or a diode made by connecting the source terminal and the drain terminal of a transistor. The heterojunction chips or heterojunction power devices described in the present disclosure may refer to heterojunction intelligent power devices or heterojunction intelligent chips or heterojunction power integrated circuits or heterojunction integrated circuits.

[0258] Those skilled in the art should understand that in the above description and the appended claims, positional terms such as "top", "above", "overlap", "under", "lateral", etc. refer to the conceptual diagrams of the device, such as the conceptual diagrams showing a standard cross-sectional perspective and the conceptual diagrams shown in the drawings. These terms are used for convenience of reference but are not intended to be limiting. Therefore, these terms should be understood to refer to the device in the orientation shown in the drawings.

[0259] Although the present disclosure has been described in terms of the preferred embodiments set forth above, it should be understood that these embodiments are for illustrative purposes only and the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and substitutions that are expected to fall within the scope of the appended claims in view of the present disclosure. Each feature disclosed or illustrated in this specification may be incorporated into the present disclosure alone or in any suitable combination with any other feature disclosed or illustrated herein.

[0260] Those skilled in the art can think of other effective alternatives. It should be understood that the present disclosure is not limited to the described embodiments, but covers all modifications that fall within the spirit and scope of the present disclosure.

Claims

1. A heterojunction power device based on group-III nitride semiconductors, comprising: A first power heterojunction transistor formed on a substrate, the first power heterojunction transistor comprising: A first group-III nitride semiconductor region formed on the substrate, wherein the first group-III nitride semiconductor region includes a first heterojunction, and the first heterojunction includes at least one two-dimensional carrier gas of a second conductivity type; A first terminal operatively connected to the first group-III nitride semiconductor region; A second terminal laterally spaced from the first terminal and operatively connected to the first group-III nitride semiconductor region; A first gate region formed on the first group-III nitride semiconductor region between the first terminal and the second terminal; A first gate terminal contacting the first gate region, A second heterojunction transistor formed on a substrate, the second heterojunction transistor comprising: A second group-III nitride semiconductor region formed on the substrate, wherein the second group-III nitride semiconductor region includes a second heterojunction, and the second heterojunction includes at least one two-dimensional carrier gas of a second conductivity type; A third terminal operatively connected to the second group-III nitride semiconductor region; A fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second group-III nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and A second gate region formed on the second group-III nitride semiconductor region between the third terminal and the fourth terminal; A second gate terminal contacting the second gate region, A third heterojunction transistor formed on a substrate, the third heterojunction transistor comprising: A third group-III nitride semiconductor region formed on the substrate, wherein the third group-III nitride semiconductor region includes a third heterojunction, and the third heterojunction includes at least one two-dimensional carrier gas of a second conductivity type; A fifth terminal operatively connected to the third group-III nitride semiconductor region; A sixth terminal laterally spaced from the fifth terminal in a first dimension and operatively connected to the third group-III nitride semiconductor region, wherein the sixth terminal is operatively connected to the second terminal; and A third gate region formed on the third group-III nitride semiconductor region between the fifth terminal and the sixth terminal; A third gate terminal contacting the third gate region, wherein the third gate terminal is operatively connected to the first gate terminal, and wherein the third heterojunction transistor is monolithically integrated with the first power heterojunction transistor and has a structure substantially the same as that of the first power heterojunction transistor, and wherein the third heterojunction transistor is scaled by a scaling factor X to an area smaller or a gate width shorter than that of the first power heterojunction transistor, where X is greater than 1, and Wherein, the third heterojunction transistor is used for current sensing of the first power heterojunction transistor, and the second heterojunction transistor is configured for the sensing and / or protection function of the first power heterojunction transistor.

2. The heterojunction power device based on group-III nitride semiconductor according to claim 1, Among them, The first power heterojunction transistor further includes one or more first highly doped semiconductor regions of a first conductivity type formed on the first group-III nitride semiconductor region, and wherein, the first gate terminal is formed on the one or more first highly doped semiconductor regions; and Wherein, the second heterojunction transistor includes at least two highly doped semiconductor regions of the first conductivity type formed on the second group-III nitride semiconductor region, and wherein, the second gate terminal is formed on the at least two highly doped semiconductor regions, and wherein, the at least two highly doped semiconductor regions are laterally spaced apart from each other in a second dimension.

3. The heterojunction power device based on group-III nitride semiconductor according to claim 1 or 2, wherein, The second heterojunction transistor is configured as a depletion-mode field effect transistor or a normally-on field effect transistor.

4. The heterojunction power device based on group-III nitride semiconductors according to claim 1 or 2, wherein, The sensing and / or protection function is performed by sensing the current passing through the third heterojunction transistor and / or by adjusting the gate voltage or the pulse width or frequency of the gate signal applied to the gate of the first power heterojunction transistor.

5. The heterojunction power device based on group-III nitride semiconductor according to claim 1 or 2, wherein The sensing and / or protection function is performed by sensing both the current passing through the third heterojunction transistor and the voltage of the first gate terminal of the first power heterojunction transistor, and by limiting the voltage applied to the first gate of the first power heterojunction transistor or adjusting the pulse width or frequency of the gate signal applied to the first gate of the first power heterojunction transistor due to any one of the sensing and / or protection functions.

6. The heterojunction power device based on group-III nitride semiconductors according to claim 1 or 2, wherein, The first power heterojunction transistor, the second heterojunction transistor and the third heterojunction transistor are monolithically integrated on the same substrate.

7. The heterojunction power device based on group-III nitride semiconductors according to claim 1 or 2, wherein, The device further includes a first resistor, and wherein, the fifth terminal of the third heterojunction transistor is operatively connected to the first terminal of the first resistor; the third heterojunction transistor serves as a current sensing transistor.

8. The heterojunction power device based on group III nitride semiconductors according to claim 7, wherein, The second terminal of the first resistor is operatively connected to the first terminal of the first power heterojunction transistor.

9. The heterojunction power device based on group-III nitride semiconductor according to claim 8 further includes a sense pad, and wherein, The fifth terminal of the third heterojunction transistor is connected to the sensing pad so that the current passing through the third heterojunction transistor can be measured.

10. The heterojunction power device based on group-III nitride semiconductors according to claim 8 further includes a second resistor, and wherein, One terminal of the second resistor is connected to one terminal of the first resistor.

11. The heterojunction power device based on group III nitride semiconductors according to claim 10, wherein, The second heterojunction transistor is configured as an enhancement-mode transistor or a normally-off transistor.

12. The heterojunction power device based on group-III nitride semiconductors according to claim 1 or 2, wherein, The device further includes a voltage divider, wherein, the terminals of the voltage divider are connected to the first gate terminal, and wherein, the midpoint of the voltage divider is connected to the second gate terminal.

13. The heterojunction power device based on group-III nitride semiconductors according to claim 12, wherein, The second heterojunction transistor includes a split gate terminal, and a part of the split gate terminal is connected to the midpoint of the divider; and the device further includes a first resistor, and the other part of the gate terminal is connected to the first terminal of the first resistor.

14. The heterojunction power device based on group III nitride semiconductors according to claim 2, wherein, The second heterojunction transistor includes at least two sets of a plurality of highly doped semiconductor regions of a first conductivity type, and a part of the gate terminal is formed over one set of the plurality of highly doped semiconductor regions, and another part of the gate terminal is formed over another set of the plurality of highly doped semiconductor regions, and each set of the plurality of highly doped semiconductor regions includes at least two highly doped semiconductor regions that are laterally spaced apart from each other in a second dimension.

15. A method of manufacturing a heterojunction power device based on group-III nitride semiconductors, the method comprising: forming a first power heterojunction transistor on a substrate, wherein forming the first power heterojunction transistor includes the steps of: forming a first group-III nitride semiconductor region on the substrate, wherein the first group-III nitride semiconductor region includes a first heterojunction, and the first heterojunction includes at least one two-dimensional electron gas of a second conductivity type; forming a first terminal operatively connected to the first group-III nitride semiconductor region; forming a second terminal that is laterally spaced apart from the first terminal and operatively connected to the first group-III nitride semiconductor region; forming a first gate terminal formed over the first group-III nitride semiconductor region between the first terminal and the second terminal; forming a second power heterojunction transistor on the substrate, wherein forming the second power heterojunction transistor includes the steps of: forming a second group-III nitride semiconductor region on the substrate, wherein the second group-III nitride semiconductor region includes a second heterojunction, and the second heterojunction includes at least one two-dimensional electron gas of the second conductivity type; forming a third terminal operatively connected to the second group-III nitride semiconductor region; forming a fourth terminal that is laterally spaced apart from the third terminal in a first dimension and operatively connected to the second group-III nitride semiconductor region, wherein the fourth terminal is connected to the first gate terminal; forming a second gate region over the second group-III nitride semiconductor region between the third terminal and the fourth terminal; forming a second gate terminal in contact with the second gate region, forming a third heterojunction transistor on the substrate, wherein forming the third heterojunction transistor includes the steps of: forming a third group-III nitride semiconductor region on the substrate, wherein the third group-III nitride semiconductor region includes a third heterojunction, and the third heterojunction includes at least one two-dimensional electron gas of a second conductivity type; forming a fifth terminal operatively connected to the third group-III nitride semiconductor region; Form a sixth terminal that is laterally spaced from the fifth terminal in a first dimension and operatively connected to the third group-III nitride semiconductor region, wherein the sixth terminal is operatively connected to the second terminal; and Form a third gate region that is formed over the third group-III nitride semiconductor region between the fifth terminal and the sixth terminal; Form a third gate terminal that contacts the third gate region, wherein the third gate terminal is operatively connected to the first gate terminal, and wherein the third heterojunction transistor is used for current sensing of the first power heterojunction transistor, and the second power heterojunction transistor is configured for sensing and / or protection functions of the first power heterojunction transistor.

16. A heterojunction chip, comprising: A first power heterojunction transistor formed on a substrate; The first power heterojunction transistor includes: A first group-III nitride semiconductor region formed over the substrate, wherein the first group-III nitride semiconductor region includes a first heterojunction that includes at least one two-dimensional carrier gas of a second conductivity type; A first terminal operatively connected to the first group-III nitride semiconductor region; A second terminal that is laterally spaced from the first terminal and operatively connected to the first group-III nitride semiconductor region; A first gate region formed over the first group-III nitride semiconductor region between the first terminal and the second terminal; A first gate terminal that contacts the first gate region, At least one current sensing transistor; and A feedback circuit; wherein the at least one current sensing transistor is configured to provide a first current sensing output and a second current sensing output; wherein the first current sensing output is generated for internal use by the feedback circuit for self-protection against overcurrent and / or over-temperature, and wherein the second current sensing output is generated for external use for optimizing the drive / control of the first power heterojunction transistor and / or for additional protection against overcurrent and / or over-temperature, and wherein the at least one current sensing transistor is monolithically integrated with the first power heterojunction transistor and has a substantially the same structure as the first power heterojunction transistor, and wherein the at least one current sensing transistor is scaled by a scaling factor X to a smaller area or shorter gate width compared to the first power heterojunction transistor, where X is greater than 1.

17. The heterojunction chip according to claim 16, further comprising a sensing load attached to the at least one current sensing transistor, wherein, The sensing load includes any one or more of the following: An integrated resistor made of a two-dimensional electron gas (2DEG), An integrated resistor made of a metal layer or other layer available in the heterojunction chip, An integrated enhancement-mode or depletion-mode low-voltage heterojunction transistor, An external precision resistor.

18. The heterojunction chip according to claim 17, wherein, The sensing load includes the contribution of the resistance of a metallization track disposed between the first terminal or an electrical contact to the first terminal and the first terminal pad, and at least a portion of the current in the first power heterojunction transistor flows through the metallization track.

19. The heterojunction chip according to claim 18, wherein, The at least one current sensing transistor is positioned away from the first terminal pad to increase the resistance and the voltage drop across the resistance of the metallization track, which is part of the sense load.

20. The heterojunction chip according to any one of claims 16 to 19, further comprising at least two separate current sensing transistors, wherein, One current sensing transistor is configured for internal current sensing and / or protection, and another current sensing transistor is configured for external use for external current sensing and / or protection and / or optimizing switching of the first power heterojunction transistor.

21. The heterojunction chip according to claim 16, wherein, The first power heterojunction transistor and the at least one current sensing transistor are made of fingers and arranged in an interleaved configuration, and wherein the first power heterojunction transistor has a greater number of fingers than the at least one current sensing transistor.

22. The heterojunction chip according to any one of claims 16 to 19, wherein, The at least one current sensing transistor is a single current sensing transistor, and one of the terminals of the single current sensing transistor is attached to a sense pad to perform both internal current sensing operations and external current sensing operations.

23. The heterojunction chip according to claim 22, wherein, At least one of the current sensing transistors is the same as a third heterojunction transistor formed on the substrate.

24. The heterojunction chip according to any one of claims 17 to 19, wherein, The feedback circuit includes a common source, common drain, or common gate amplifier, each of which provides amplification of the current through the current sensing transistor or the voltage drop across the sense load.

25. The heterojunction chip according to claim 24, wherein The feedback circuit includes a second heterojunction transistor.

26. The heterojunction chip according to claim 24, wherein the feedback circuit includes an amplifier stage, and the amplifier stage includes one or any of a divider, a Schottky diode, a resistor, a capacitor, a diode, or a transistor.

27. The heterojunction chip according to claim 26, wherein, The output of the amplifier stage is configured for overcurrent or overtemperature protection by controlling the gate of the second heterojunction transistor of the feedback circuit.

28. The heterojunction chip according to claim 26, wherein, The output of the amplifier stage is configured for overcurrent or overtemperature protection by directly or indirectly controlling the gate of an auxiliary transistor, and one of the terminals of the auxiliary transistor is connected to the gate of the first power heterojunction transistor.

29. A system including a heterojunction chip, comprising: The heterojunction chip according to any one of claims 16 to 28; A controller, located outside the heterojunction chip, the controller being configured to analyze and process an external current sensing signal and being configured to instruct an external gate driver or an internal gate driver to limit or adjust a signal applied to the gate of the first power heterojunction transistor to optimize the operation of the system and protect the first power heterojunction transistor or the system.

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