Display substrate, manufacturing method and display device

Abstract

The present invention provides a display substrate, a manufacturing method, and a display device. The display substrate includes a scanning drive circuit; the scanning drive circuit includes multiple shift register units, at least one shift register unit includes a signal output line and an output circuit, and the output circuit includes an output transistor and an output reset transistor; the signal output line includes a first output line portion extending along a first direction; the first output line portion is coupled to a second electrode of the output transistor via multiple first signal line vias provided in a signal line overlapping region, and the first output line portion is coupled to the second electrode of the output reset transistor via multiple second signal line vias provided in the signal line overlapping region; the multiple first signal line vias are arranged sequentially along the first direction, and the multiple second signal line vias are arranged sequentially along the first direction.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a manufacturing method and a display device. Background Art

[0002] Active-Matrix Organic Light-Emitting Diode (AMOLED) display panels are widely used in various fields due to their advantages such as low power consumption, low production cost, and wide color gamut.

[0003] An AMOLED display panel includes pixel circuits located in the display area and scan driver circuits located in the edge areas. The pixel circuits include multiple sub-pixel circuits arranged in an array. The scan driver circuits include multiple shift register units, each of which provides a light-emission control signal to a corresponding sub-pixel circuit. Because the scan driver circuits are located in the edge areas of the AMOLED display panel, the arrangement of the scan driver circuits determines the width of the AMOLED display panel's border. Summary of the Invention

[0004] In one aspect, an embodiment of the present invention provides a display substrate, comprising a scan drive circuit and a display area disposed on a substrate; the scan drive circuit comprises a plurality of shift register units, at least one of the plurality of shift register units comprises a signal output line and an output circuit, the output circuit comprises an output transistor and an output reset transistor;

[0005] The signal output line includes a first output line portion extending along a first direction;

[0006] The first output line portion is coupled to the second electrode of the output transistor through a plurality of first signal line vias provided in the signal line overlapping region, and the first output line portion is coupled to the second electrode of the output reset transistor through a plurality of second signal line vias provided in the signal line overlapping region; the plurality of first signal line vias are arranged sequentially along a first direction, and the plurality of second signal line vias are arranged sequentially along the first direction;

[0007] The signal line overlapping region includes a first signal line overlapping region and a second signal line overlapping region, the first signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a first source-drain metal pattern included in the second electrode of the output transistor on the substrate, and the second signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a second source-drain metal pattern included in the second electrode of the output reset transistor on the substrate;

[0008] The ratio of the maximum distance between any two first signal line vias arranged sequentially along the first direction in the first direction to the third length is a first predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance; the third length is the length of the overlapping area of ​​the first signal lines in the first direction;

[0009] The ratio of the maximum distance between any two second signal line vias arranged sequentially along the first direction in the first direction to the fourth length is a second predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance; and the fourth length is the length of the overlapping region of the second signal line in the first direction;

[0010] The first predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0011] The first predetermined distance is greater than or equal to 1.5 μm and less than or equal to 45 μm;

[0012] The second predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0013] The second predetermined distance is greater than or equal to 1.5 um and less than or equal to 65 um.

[0014] Optionally, the active layer of the output transistor and the active layer of the output reset transistor are arranged along a first direction, the length of the active layer of the output transistor in the first direction is a first length, the length of the active layer of the output reset transistor in the first direction is a second length, and the sum of the first length and the second length is the output active length;

[0015] The smaller of the minimum width of the active layer of the output transistor along the second direction and the minimum width of the active layer of the output reset transistor along the second direction is the output active width; the first direction intersects the second direction.

[0016] Optionally, a ratio of the output active length to the output active width is within a predetermined ratio range;

[0017] The predetermined ratio range is greater than or equal to 3 and less than or equal to 11.

[0018] Optionally, the output active width is within a predetermined width range;

[0019] The predetermined width range is greater than or equal to 12 um and less than or equal to 45 um.

[0020] Optionally, the active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer; the first semiconductor layer extends along a first direction;

[0021] The length of the first semiconductor layer in the first direction is the output active length;

[0022] A minimum length of the first semiconductor layer in the second direction is the output active length.

[0023] Optionally, the at least one shift register unit further includes a first transistor;

[0024] The first transistor includes a first active pattern, and the first active pattern extends along a second direction;

[0025] The first transistor is located on a side of the output circuit away from the display area.

[0026] Optionally, the at least one shift register unit further includes a second transistor and a third transistor; the second electrode of the second transistor is coupled to the second electrode of the third transistor;

[0027] a maximum distance in the second direction between an orthographic projection of the gate of the second transistor on the substrate and an orthographic projection of the gate of the third transistor on the substrate is a third predetermined distance;

[0028] The second transistor and the third transistor are located on a side of the output circuit away from the display area.

[0029] Optionally, the third predetermined distance is greater than or equal to 14 um and less than or equal to 50 um.

[0030] Optionally, the at least one shift register unit further includes a first transistor, a second transistor and a first capacitor, wherein:

[0031] The second electrode of the first transistor and the first electrode of the second transistor are respectively coupled to the second plate of the first capacitor, and the gate of the first transistor is coupled to the first plate of the first capacitor;

[0032] The first transistor, the first capacitor and the second transistor are arranged in sequence along a first direction;

[0033] The first transistor, the first capacitor, and the second transistor are located on a side of the output circuit away from a display area.

[0034] Optionally, the scan drive circuit further includes a first voltage signal line, and the at least one shift register unit further includes an output reset capacitor; a first plate of the output reset capacitor is coupled to the gate of the output reset transistor, and a second plate of the output reset capacitor is coupled to the first voltage signal line;

[0035] The maximum width of the second plate of the output reset capacitor in the second direction is a first predetermined width, and the maximum length of the second plate of the output reset capacitor in the first direction is a second predetermined length;

[0036] The output reset capacitor is located on a side of the output circuit away from the display area;

[0037] The orthographic projection of the second plate of the output reset capacitor on the substrate is within the orthographic projection of the first plate of the output reset capacitor on the substrate.

[0038] Optionally, the first predetermined width is greater than or equal to 3 um and less than or equal to 60 um, and the second predetermined length is greater than or equal to 3 um and less than or equal to 20 um.

[0039] Optionally, the first voltage signal line extends along a first direction, and the first voltage signal line is located on a side of the output reset capacitor away from the display area.

[0040] Optionally, the output transistor and the output reset transistor are arranged along a first direction; the scan drive circuit further includes a second voltage signal line; and the at least one shift register unit further includes an output reset capacitor;

[0041] The second plate of the output reset capacitor is coupled to the first voltage signal line;

[0042] The first electrode of the output transistor is coupled to the second voltage signal line, and the first electrode of the output reset transistor is coupled to the second plate of the output reset capacitor;

[0043] The output transistor and the output reset transistor are located on a side of the second voltage signal line away from the display area.

[0044] Optionally, the gate of the output transistor includes at least one output gate pattern, the first electrode of the output transistor includes at least one first electrode pattern, and the second electrode of the output transistor includes at least one second electrode pattern;

[0045] The output gate pattern is located between the adjacent first electrode pattern and the second electrode pattern;

[0046] The first electrode pattern, the output gate pattern, and the second electrode pattern all extend along a second direction.

[0047] Optionally, the gate of the output reset transistor includes at least one output reset gate pattern, the first electrode of the output reset transistor includes at least one third electrode pattern, and the second electrode of the output reset transistor includes at least one fourth electrode pattern;

[0048] The output reset gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern;

[0049] The third electrode pattern, the output reset gate pattern and the fourth electrode pattern all extend along the second direction;

[0050] The fourth electrode pattern of the output reset transistor that is closest to the gate of the output transistor is multiplexed as the second electrode pattern of the output transistor.

[0051] Optionally, the active layer of the output transistor includes at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each first channel portion is arranged between two adjacent first conductive portions;

[0052] The first channel portions correspond to the output gate patterns one by one, and the orthographic projection of each first channel portion on the substrate is located inside the orthographic projection of the corresponding output gate pattern on the substrate;

[0053] A portion of the first conductive portions of the output transistor corresponds to the first electrode pattern one-to-one, an orthographic projection of the first electrode pattern on the substrate and an orthographic projection of the corresponding first conductive portion on the substrate having a first overlapping region, and the first electrode pattern is coupled to the corresponding first conductive portion via at least one first via provided in the first overlapping region;

[0054] Another part of the first conductive portion in the output transistor corresponds one-to-one to the second electrode pattern, and an orthographic projection of the second electrode pattern on the substrate has a second overlapping area with an orthographic projection of the corresponding first conductive portion on the substrate, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via provided in the second overlapping area.

[0055] Optionally, the active layer of the output reset transistor includes at least two second conductive portions arranged opposite to each other along the first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions;

[0056] The second channel portions correspond to the output reset gate patterns one by one, and the orthographic projection of each second channel portion on the substrate is located inside the orthographic projection of the corresponding output reset gate pattern on the substrate;

[0057] A portion of the second conductive portions of the output reset transistor corresponds one-to-one to the third electrode pattern, an orthographic projection of the third electrode pattern on the substrate and an orthographic projection of the corresponding second conductive portion on the substrate form a third overlapping region, and the third electrode pattern is coupled to the corresponding second conductive portion via at least one third via provided in the third overlapping region;

[0058] Another part of the second conductive portion in the output reset transistor corresponds one-to-one to the fourth electrode pattern, and the orthographic projection of the fourth electrode pattern on the substrate has a fourth overlapping area with the orthographic projection of the corresponding second conductive portion on the substrate. The fourth electrode pattern is coupled to the corresponding second conductive portion through at least one fourth via provided in the fourth overlapping area.

[0059] Optionally, the scan driving circuit further includes a second voltage signal line; the at least one shift register unit further includes a fourth transistor;

[0060] The second voltage signal line is coupled to the electrode conductive connection portion, and the electrode conductive connection portion extends along the second direction; the at least one first electrode pattern is arranged in sequence along the first direction;

[0061] The electrode conductive connection portion is coupled to a first first electrode pattern included in the first electrode of the output transistor;

[0062] The first electrode of the fourth transistor is coupled to the electrode conductive connection portion;

[0063] A minimum distance in the first direction between an orthographic projection of the gate of the fourth transistor on the substrate and an orthographic projection of the electrode conductive connection portion on the substrate is a fourth predetermined distance.

[0064] Optionally, the fourth predetermined distance is greater than or equal to 1 um and less than or equal to 5 um.

[0065] Optionally, the at least one shift register unit further includes a fourth transistor and a fifth transistor;

[0066] The gate of the fourth transistor is coupled to the gate of the fifth transistor;

[0067] The gate of the fourth transistor and the gate of the fifth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along a second direction.

[0068] Optionally, the scan driving circuit further includes a first clock signal line, and the gate of the fifth transistor is coupled to the first clock signal line;

[0069] The first clock signal line extends along a first direction, and the first clock signal line is located on a side of the five transistors away from the display area.

[0070] Optionally, the at least one shift register unit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor and an output capacitor;

[0071] A first electrode of the fifth transistor is coupled to the input signal terminal; a second electrode of the fifth transistor is coupled to the gate of the sixth transistor;

[0072] The gate of the sixth transistor includes a first gate pattern and a second gate pattern coupled to each other;

[0073] The first gate pattern and the second gate pattern are respectively coupled to a first plate of the output capacitor, and the first plate of the output capacitor is coupled to a gate of the output transistor;

[0074] A first electrode of the sixth transistor is coupled to the gate of the fourth transistor, a second electrode of the sixth transistor is coupled to the second electrode of the fourth transistor, and a second plate of the output capacitor is coupled to the first electrode of the first transistor;

[0075] The fourth transistor, the sixth transistor and the first transistor are arranged in sequence along the first direction;

[0076] The fifth transistor, the sixth transistor and the first transistor are arranged in sequence along the first direction;

[0077] The output capacitor is located between the sixth transistor and the output circuit.

[0078] Optionally, the at least one shift register unit further includes a second transistor, a first transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein:

[0079] The active layer of the seventh transistor and the active layer of the eighth transistor are formed by a continuous second semiconductor layer, and the second semiconductor layer extends along the first direction;

[0080] The active layer of the seventh transistor includes a first ninth conductive portion, a ninth channel portion, and a second ninth conductive portion sequentially arranged along the first direction;

[0081] The second ninth conductive portion is multiplexed as the first tenth conductive portion;

[0082] The active layer of the eighth transistor includes a first tenth conductive portion, a tenth channel portion, and a second tenth conductive portion sequentially arranged along the first direction;

[0083] The first ninth conductive portion is used as the second electrode of the seventh transistor, the second ninth conductive portion is used as the first electrode of the seventh transistor, the second tenth conductive portion is used as the first electrode of the eighth transistor, and the first electrode of the seventh transistor is multiplexed as the second electrode of the eighth transistor;

[0084] The gate of the seventh transistor is coupled to the second plate of the output capacitor, and the second electrode of the seventh transistor is coupled to the gate of the sixth transistor;

[0085] A gate of the eighth transistor is coupled to the gate of the first transistor, and a first electrode of the eighth transistor is coupled to a first voltage signal line;

[0086] The first voltage signal line extends along a first direction;

[0087] The sixth transistor, the seventh transistor, the eighth transistor and the second transistor are arranged in sequence along a first direction.

[0088] Optionally, the scan driving circuit further includes a second clock signal line, and the gate of the second transistor and the gate of the seventh transistor are respectively coupled to the second clock signal line;

[0089] The second clock signal line extends along a first direction, and the second clock signal line is located on a side of the second transistor away from the display area.

[0090] Optionally, the scan driving circuit further includes a second voltage signal line and a signal output line;

[0091] The signal output line includes a first output line portion and at least one second output line portion;

[0092] The second voltage signal line and the first output line portion both extend along a first direction, and the first output line portion is located between the second voltage signal line and the output circuit;

[0093] The second output line portion extends along a second direction;

[0094] The second output line portion is used to provide a light emitting control signal to the pixel circuit in the display area;

[0095] The first output line portion and the output circuit are located on a side of the second voltage signal line away from the display area.

[0096] Optionally, the scan driving circuit further includes a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line;

[0097] The first voltage signal line, the second voltage signal line, the first clock signal line and the second clock signal line all extend along a first direction;

[0098] The orthographic projection of the first voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate, and the orthographic projection of the second clock signal line on the substrate are all located on a side of the orthographic projection of the shift register unit on the substrate away from the display area;

[0099] The orthographic projection of the second voltage signal line on the substrate is located on a side of the shift register unit close to the display area.

[0100] Optionally, the signal output line further includes at least one second output line portion, which is coupled to the first output line portion; the second output line portion extends to the display area and is used to provide a light-emitting control signal to the pixel circuit located in the display area.

[0101] Optionally, the scan drive circuit further includes a first voltage signal line, a second voltage signal line, a first clock signal line, a second clock signal line, and a signal output line; the at least one shift register unit further includes a first capacitor, an output capacitor, an output reset capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and the signal output line further includes at least one second output line portion;

[0102] The gate of the output transistor is coupled to the first plate of the output capacitor, the first electrode of the output transistor is coupled to the second voltage signal line, and the second electrode of the output transistor is coupled to the signal output line;

[0103] The gate of the output reset transistor is coupled to the first plate of the output reset capacitor, the first electrode of the output reset transistor is coupled to the second plate of the output reset capacitor, and the second electrode of the output reset transistor is coupled to the signal output line;

[0104] The second plate of the output reset capacitor is coupled to the first voltage signal line; the second plate of the output capacitor is coupled to the gate of the seventh transistor;

[0105] The first electrode of the first transistor is coupled to the second plate of the output capacitor, the second electrode of the first transistor and the first electrode of the second transistor are respectively coupled to the second plate of the first capacitor, and the gate of the first transistor is coupled to the first plate of the first capacitor;

[0106] A gate of the second transistor and a gate of the seventh transistor are respectively coupled to the second clock signal line, and a second electrode of the second transistor is coupled to the second electrode of the third transistor;

[0107] The gate of the third transistor is coupled to the gate of the output transistor, and the first electrode of the third transistor is coupled to the first plate of the output reset capacitor;

[0108] A gate of the fourth transistor is coupled to a gate of the fifth transistor, a first electrode of the fourth transistor is coupled to a first electrode of the output transistor, and a second electrode of the fourth transistor is coupled to a second electrode of the sixth transistor;

[0109] The gate of the fifth transistor is coupled to the first clock signal line, the first electrode of the fifth transistor is coupled to the input signal terminal, and the second electrode of the fifth transistor is coupled to the gate of the sixth transistor;

[0110] A first electrode of the sixth transistor is coupled to the gate of the fourth transistor, and a second electrode of the sixth transistor is coupled to the second electrode of the fourth transistor;

[0111] The gate of the seventh transistor is coupled to the second plate of the output capacitor, the first electrode of the seventh transistor is multiplexed as the second electrode of the eighth transistor, and the second electrode of the seventh transistor is coupled to the gate of the sixth transistor;

[0112] A gate of the eighth transistor is coupled to the gate of the first transistor, and a first electrode of the eighth transistor is coupled to a first voltage signal line;

[0113] The second output line portion is coupled to the first output line portion; the second output line portion extends to the display area and is used to provide a light emitting control signal to a pixel circuit located in the display area.

[0114] Optionally, the second voltage signal line is provided on a side of the shift register unit close to the display area;

[0115] The first voltage signal line, the first clock signal line and the second clock signal line are arranged on a side of the shift register unit away from the display area;

[0116] Along the direction close to the display area, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence; or, along the direction close to the display area, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence.

[0117] Optionally, the scan driving circuit further includes a first start signal line and a second start signal line;

[0118] Along a direction close to the display area, the second start signal line, the first start signal line, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence;

[0119] Along a direction close to the display area, the first start signal line, the second start signal line, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence;

[0120] Along a direction close to the display area, the second start signal line, the first start signal line, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence;

[0121] Along a direction close to the display area, the first start signal line, the second start signal line, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence.

[0122] Optionally, the output transistor and the output reset transistor are located between the output capacitor and the first output line portion; along the first direction, the output transistor and the output reset transistor are arranged in sequence;

[0123] a first capacitor, an output capacitor, an output reset capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0124] Along a first direction, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the first transistor, the first capacitor, the second transistor and the output reset transistor are arranged in sequence;

[0125] The fifth transistor, the fourth transistor, the sixth transistor, the seventh transistor and the eighth transistor are located between the output capacitor and the first voltage signal line;

[0126] The gate of the fifth transistor and the gate of the fourth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along the second direction.

[0127] Optionally, the display substrate further comprises a plurality of rows of pixel circuits provided on the base; the pixel circuits comprise light emitting control terminals;

[0128] The shift register unit corresponds to at least one row of pixel circuits;

[0129] The signal output line of the shift register unit is coupled to the light emitting control terminal of the at least one row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control terminal of the at least one row of pixel circuits.

[0130] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a display substrate, the method comprising manufacturing a scan drive circuit on a substrate; the scan drive circuit comprises a plurality of shift register units, at least one of the plurality of shift register units comprises an output circuit; the output circuit comprises an output transistor and an output reset transistor;

[0131] The method for manufacturing the display substrate further includes:

[0132] Fabricating a semiconductor layer on the substrate, and performing a patterning process on the semiconductor layer to form an active layer of an output transistor and an active layer of an output reset transistor;

[0133] forming a first gate metal layer on a side of the semiconductor layer facing away from the substrate, and patterning the first gate metal layer to form a gate of the output transistor and a gate of the output reset transistor;

[0134] Using the gates of the output transistor and the output reset transistor as masks, doping portions of the semiconductor layer not covered by the gates, so that the portions of the semiconductor layer not covered by the gates form conductive portions, and the portions of the semiconductor layer covered by the gates form channel portions;

[0135] Disposing a second gate metal layer on a side of the first gate metal layer facing away from the semiconductor layer, and patterning the second gate metal layer to form a signal output line; the signal output line includes a first output line portion extending along a first direction;

[0136] Disposing a first insulating layer on a side of the second gate metal layer facing away from the first gate metal layer;

[0137] A plurality of first signal line via holes and a plurality of second signal line via holes are formed in an area where the first insulating layer partially overlaps with the first output line; the first signal line via holes and the second signal line via holes pass through the first insulating layer;

[0138] forming a source-drain metal layer on a side of the first insulating layer facing away from the second gate metal layer, and patterning the source-drain metal layer to form a first source-drain metal pattern and a second source-drain metal pattern, wherein the first source-drain metal pattern includes the second electrode of the output transistor, and the second source-drain metal pattern includes the second electrode of the output reset transistor, so that the first output line portion is coupled to the second electrode of the output transistor through the plurality of first signal line vias, and the first output line portion is coupled to the second electrode of the output reset transistor through the plurality of second signal line vias;

[0139] The signal output line includes a first output line portion extending along a first direction;

[0140] The plurality of first signal line vias are sequentially arranged along the first direction, and the plurality of second signal line vias are sequentially arranged along the first direction;

[0141] The ratio of the maximum distance between any two first signal line vias arranged in sequence along the first direction and the third length is a first predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance;

[0142] The ratio of the maximum distance between any two second signal line vias arranged in sequence along the first direction in the first direction to the fourth length is a second predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance;

[0143] The third length is the length of the first signal line overlapping area in the first direction, and the fourth length is the length of the second signal line overlapping area in the first direction;

[0144] The first predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0145] The first predetermined distance is greater than or equal to 1.5 μm and less than or equal to 45 μm;

[0146] The second predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0147] The second predetermined distance is greater than or equal to 1.5 um and less than or equal to 65 um.

[0148] Optionally, the length of the active layer of the output transistor in the first direction is a first length, the length of the active layer of the output reset transistor in the first direction is a second length, and the sum of the first length and the second length is the output active length;

[0149] The smaller of the minimum width of the active layer of the output transistor along the second direction and the minimum width of the active layer of the output reset transistor along the second direction is the output active width; the first direction intersects the second direction.

[0150] Optionally, a ratio of the output active length to the output active width is within a predetermined ratio range;

[0151] The predetermined ratio range is greater than or equal to 3 and less than or equal to 11.

[0152] Optionally, the output active width is within a predetermined width range;

[0153] The predetermined width range is greater than or equal to 12 um and less than or equal to 45 um.

[0154] In a third aspect, an embodiment of the present invention further provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0155] Figure 1 is a circuit diagram of at least one embodiment of at least one shift register unit included in the display substrate according to an embodiment of the present invention;

[0156] Figure 2A yes Figure 1 An operation timing diagram of at least one embodiment of the shift register unit shown;

[0157] Figure 2B is a schematic diagram of the area division of a display substrate according to at least one embodiment of the present invention;

[0158] Figure 2C is a schematic diagram of the connection relationship between the scan driving circuit and the pixel circuit included in the display substrate according to at least one embodiment of the present invention;

[0159] Figure 2D is a schematic diagram of a layout of a shift register unit provided by at least one embodiment of the present invention;

[0160] Figure 3A A schematic diagram of another layout of a shift register unit provided by at least one embodiment of the present invention;

[0161] Figure 3B is another schematic diagram of a layout of a shift register unit provided by at least one embodiment of the present invention;

[0162] Figure 4 is Figure 3A, a schematic diagram showing a maximum distance K1 between a first first signal line via and a last first signal line via arranged sequentially along the first direction, and a schematic diagram showing a maximum distance K2 between a first second signal line via and a last second signal line via arranged sequentially along the first direction;

[0163] Figure 5 is a schematic diagram of an active layer in a shift register unit provided by at least one embodiment of the present invention;

[0164] Figure 6 is a schematic diagram of a first gate metal layer in a shift register unit provided by at least one embodiment of the present invention;

[0165] Figure 7 is a schematic diagram of a second gate metal layer in a shift register unit provided by at least one embodiment of the present invention;

[0166] Figure 8 is a schematic diagram of a via used in a shift register unit provided in at least one embodiment of the present invention;

[0167] Figure 9 A schematic diagram of a source and drain metal layer in a shift register unit provided by at least one embodiment of the present invention;

[0168] Figure 10 yes Figure 3A Schematic diagram of the source and drain metal layers in FIG;

[0169] Figure 11 This is another layout diagram of a shift register unit provided by at least one embodiment of the present invention. DETAILED DESCRIPTION

[0170] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0171] like Figure 1 As shown, at least one embodiment of the present invention provides a display substrate, the display substrate including a scan driving circuit located in an edge region of the display substrate, the scan driving circuit including a first voltage signal line VGH, a second voltage signal line VGL, a first clock signal line CK, a second clock signal line CB, and a signal output line E0; the scan driving circuit further includes a plurality of shift register units;

[0172] like Figure 1As shown, at least one embodiment of at least one shift register unit among the plurality of shift register units includes a first capacitor C1, an output capacitor C2, an output reset capacitor C3, an output transistor T10, an output reset transistor T9, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8;

[0173] The gate G10 of the output transistor T10 is coupled to the first plate C2a of the output capacitor C2, the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL, and the second electrode D10 of the output transistor T10 is coupled to the signal output line E0;

[0174] The gate G9 of the output reset transistor T9 is coupled to the first plate C3a of the output reset capacitor C3, the first electrode S9 of the output reset transistor T9 is coupled to the second plate C3b of the output reset capacitor C3, and the second electrode D9 of the output reset transistor T9 is coupled to the signal output line E0;

[0175] The second plate C3b of the output reset capacitor C3 is coupled to the first voltage signal line VGH; the second plate C2b of the output capacitor C2 is coupled to the second clock signal line CB;

[0176] A first electrode S1 of the first transistor T1 is coupled to the second clock signal line CB, a second electrode D1 of the first transistor T1 and a first electrode S2 of the second transistor T2 are respectively coupled to the second plate C1b of the first capacitor C1, and a gate G1 of the first transistor T1 is coupled to the first plate C1a of the first capacitor C1;

[0177] A gate G2 of the second transistor T2 and a gate G7 of the seventh transistor T7 are coupled to the first clock signal line CB respectively. A second electrode D2 of the second transistor T2 is coupled to a second electrode D3 of the third transistor T3. A first electrode S2 of the second transistor T2 is coupled to the second plate C1b of the first capacitor.

[0178] The gate G3 of the third transistor T3 is coupled to the gate G10 of the output transistor T10, and the first electrode S3 of the third transistor T3 is coupled to the first voltage signal line VGH;

[0179] A gate G4 of the fourth transistor T4 and a gate G5 of the fifth transistor T5 are coupled to the first clock signal line CK, a first electrode S4 of the fourth transistor T4 and a first electrode S10 of the output transistor T10 are coupled to the second voltage signal line VGL, and a second electrode D4 of the fourth transistor T4 is coupled to the second electrode D6 of the sixth transistor T6;

[0180] A gate electrode G5 of the fifth transistor T5 is coupled to the first clock signal line CK, a second electrode D5 of the fifth transistor T5 is coupled to a gate electrode G6 of the sixth transistor T6; a first electrode S5 of the fifth transistor T5 is coupled to an input signal terminal E1;

[0181] The first electrode S1 of the sixth transistor T6 and the gate G4 of the fourth transistor T4 are coupled to the first clock signal line CK, the second electrode D6 of the sixth transistor T6 is coupled to the second electrode D4 of the fourth transistor T4; the gate G6 of the sixth transistor T6 is coupled to the second electrode D1 of the fifth transistor;

[0182] A gate G7 of the seventh transistor T7 and a second plate C2b of the output capacitor C2 are coupled to the second clock signal line CB, a first electrode S7 of the seventh transistor T7 is coupled to the second electrode D8 of the eighth transistor T8, and the second electrode D7 of the seventh transistor T7 is coupled to the gate G6 of the sixth transistor T6;

[0183] A gate G8 of the eighth transistor T8 is coupled to the gate G1 of the first transistor T1 , and a first electrode S8 of the eighth transistor T8 is coupled to a first voltage signal line VGH.

[0184] exist Figure 1 In at least one embodiment of the shift register unit shown, all transistors are p-type transistors, but the present invention is not limited thereto.

[0185] In at least one embodiment of the present invention, Figure 1 At least one embodiment of the shift register unit shown may be a light emitting control scan driving circuit, but the present invention is not limited thereto.

[0186] In at least one embodiment of the present invention, the first electrode of the transistor may be a source, and the second electrode of the transistor may be a drain; or the first electrode of the transistor may be a drain, and the second electrode of the transistor may be a source.

[0187] exist Figure 1 , the node labeled N1 is the first node, the node labeled N2 is the second node, the node labeled N3 is the third node, and the node labeled N4 is the fourth node.

[0188] exist Figure 1In at least one embodiment shown, the first voltage signal line VGH may provide a high voltage Vgh, and the second voltage signal line VGL may provide a low voltage Vgl, but the present invention is not limited thereto.

[0189] like Figure 2A As shown, the present invention is as Figure 1 At least one embodiment of the shift register unit shown in FIG.

[0190] In the first time period P1, E1 provides a high level, CK provides a low level, CB provides a high level, T5 and T4 are turned on, the potential of N1 is high, T6 is turned off, the potential of N2 is low, so T7, T3 and T10 are turned off, and T8 and T1 are turned on; at this time, the potential of N3 is high, CB provides a high level, so T2 is turned off; because the voltage across the capacitor does not change suddenly, the potential of N4 remains at the high level of the previous frame, T9 is turned off, and the potential of the light-emitting control signal output by E0 remains at the low level of the previous frame;

[0191] In the second time period P2, E1 and CK both provide a high level, CB provides a low level, T5, T6, and T4 are all turned off, the potential of N1 remains at a high level, the potential of N2 remains at a low level, T7, T8, and T1 are all turned on, the potential of N3 changes from a high level to a low level, T2 is turned on, the potential of N4 is at a low level, T9 is turned on, E0 outputs a high level; T3 and T10 are both turned off;

[0192] In the third time period P3, E1 and CB both provide a high level, CK provides a low level, T5 and T4 are both turned on, the potential of N1 is high, the potential of N2 is low, T6 and T7 are both turned off, T8 and T1 are both turned on, the potential of N3 changes from the low level of the previous time period to a high level, T2 is turned off, the potential of N4 remains at a low level, T9 is turned on, E0 outputs a high level; T3 and T10 are both turned off;

[0193] In the fourth time period P4, E1 and CB both provide a low level, CK provides a high level, T5 and T4 are both turned off, the potential of N1 is high, T6 is turned off, the potential of N2 remains low, T7, T8 and T1 are all turned on, the voltage of N3 jumps to a low level, T2 is turned on, the potential of N4 is low, T9 is turned on, E0 outputs a high level; T3 and T10 are both turned off;

[0194] In the fifth time period P5, E1 and CK both provide a low level, CB provides a high level, T5, T6, and T4 are all turned on, the potentials of N1 and N2 are both low, T7 is turned off, T7 and T1 are both turned on, the voltage of N3 becomes high, T2 is turned off, T3 is turned on, the voltage of N4 becomes high, T9 is turned off, T10 is turned on, and E0 outputs a low level;

[0195] In the sixth time period P6, the E1 and CB signals are low, CK is high, T1 and T3 are turned off, node N1 maintains a low level, T2 is turned on, the N2 node voltage is high, T4 and T5 are turned on, T6 is turned off, the N3 node is high, T7 and T8 are turned on, the N4 node is high, T9 is turned off, T10 is turned on, and the Eout output is a low level.

[0196] In the seventh time period P7, E1 and CK both provide a low level, CB provides a high level, T5, T6 and T4 are all turned on, the potentials of N1 and N2 are both low, T7 is turned off, T8 and T1 are both turned on, the potential of N3 is high, T2 is turned off, T3 is turned on, the potential of N4 is high, T9 is turned off, T10 is turned on, and E0 outputs a low level;

[0197] In the eighth time period P8, E1 and CB both provide a low level, CK provides a high level, T5 and T4 are both turned off, the potential of N1 remains at a low level, T6 is turned on, the potential of N2 is at a high level, T7 is turned on, T8 and T1 are both turned off, the potential of N3 is at a high level, T2 and T3 are both turned on, the voltage of N4 is at a high level, T9 is turned off, T10 is turned on, and E0 outputs a low level;

[0198] After the sixth time period, T3 is continuously turned on, T9 is continuously turned off, T5 periodically charges C2, the potential of N1 remains at a low level, T10 is continuously turned on, and E0 outputs a low level until E1 receives an input signal in the next frame.

[0199] like Figure 2B As shown, the display substrate is labeled J1, the display area is labeled A0, the first edge area is labeled B1, and the second edge area is labeled B2.

[0200] A plurality of light emitting control lines, a plurality of gate lines and a plurality of data lines, as well as a plurality of sub-pixels defined by the intersection of the plurality of gate lines and the plurality of data lines, may be provided in the display area A0 of the display substrate J1;

[0201] A scan driving circuit may be provided in the first edge region B1 and / or the second edge region B2, wherein the scan driving circuit includes a plurality of shift register units;

[0202] The signal output line of each of the plurality of shift register units included in the scan driving circuit can be coupled to A light emitting control lines respectively, so as to provide a light emitting control signal to the corresponding light emitting control line.

[0203] Wherein, A can be a positive integer. In actual operation, A can be equal to 1, 2, 3, 4 or other positive integers, and the value of A can be selected according to actual conditions.

[0204] In a specific implementation, the light emitting control line is coupled to the light emitting control terminal of the pixel circuit in the corresponding row.

[0205] Optionally, the display substrate further comprises a plurality of rows of pixel circuits provided on the base; the pixel circuits comprise light emitting control terminals;

[0206] The shift register unit included in the scan driving circuit corresponds to at least one row of pixel circuits;

[0207] The signal output line of the shift register unit is coupled to the light emitting control terminal of the at least one row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control terminal of the at least one row of pixel circuits.

[0208] In at least one embodiment of the present invention, the pixel circuit may be disposed in an effective display area of ​​the display substrate, and the scan driving circuit may be disposed in an edge area of ​​the display substrate.

[0209] like Figure 2C As shown, the unit labeled Y1 is a scan driving circuit, the unit labeled S11 is a first-stage shift register unit included in the scan driving circuit S1, the unit labeled S12 is a second-stage shift register unit included in the scan driving circuit S1, the unit labeled S1N-1 is an N-1th-stage shift register unit included in the scan driving circuit S1, and the unit labeled S1N is an Nth-stage shift register unit included in the scan driving circuit S1, where N is an integer greater than 3;

[0210] exist Figure 2C , the pixel circuit labeled R1 is the first row, the pixel circuit labeled R2 is the second row, the pixel circuit labeled R3 is the third row, the pixel circuit labeled R4 is the fourth row, the pixel circuit labeled R2N-3 is the 2N-3 row, the pixel circuit labeled R2N-2 is the 2N-2 row, the pixel circuit labeled R2N-1 is the 2N-1 row, and the pixel circuit labeled R2N is the 2N row;

[0211] S11 provides a light-emitting control signal for R1 and R2, S12 provides a light-emitting control signal for R3 and R4, S1N-1 provides a light-emitting control signal for R2N-3 and R2N-2, and S1N provides a light-emitting control signal for R2N-1 and R2N;

[0212] like Figure 2C As shown, in the edge area, the display substrate may further include a gate driving circuit, the gate driving circuit including a multi-stage gate driving unit, the gate driving unit may correspond one-to-one to a pixel row, and be used to provide a corresponding gate driving signal for the pixels in the corresponding row;

[0213] exist Figure 2CIn the figure, the gate driving circuit is labeled Y2, the gate driving unit labeled S21 is the first row of gate driving units included in the gate driving circuit, the gate driving unit labeled S22 is the second row of gate driving units included in the gate driving circuit, the gate driving unit labeled S23 is the third row of gate driving units included in the gate driving circuit, the gate driving unit labeled S24 is the fourth row of gate driving units included in the gate driving circuit, the gate driving unit labeled S2N-3 is the 2N-3 row of gate driving units included in the gate driving circuit, the gate driving unit labeled S2N-2 is the 2N-2 row of gate driving units included in the gate driving circuit, the gate driving unit labeled S2N-1 is the 2N-1 row of gate driving units included in the gate driving circuit, and the gate driving unit labeled S2N is the 2N row of gate driving units included in the gate driving circuit.

[0214] exist Figure 2D In at least one embodiment shown, the first voltage signal line VGH provides a high voltage signal Vgh, and the second voltage signal line VGL provides a low voltage signal Vgl;

[0215] like Figure 2D As shown, VGL, VGH, CK and CB are arranged in a direction away from the display area; VGH, VGL, CK and CB extend in the first direction;

[0216] like Figure 1 and Figure 2D As shown, at least one embodiment of the shift register unit includes a first capacitor C1, an output capacitor C2, an output reset capacitor C3, an output transistor T10, an output reset transistor T9, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8; this embodiment of the shift register unit is arranged between VGH and VGL;

[0217] T10 and T9 are arranged along the first direction;

[0218] C2 is set on the side of T10 away from VGL, and T5, T6 and T4 are set between C2 and VGH;

[0219] T1 and T3 are set on the side of T9 away from VGL, C1 is set on the side of T3 away from T9, and T8 and T2 are set on the side of C1 away from T8;

[0220] T5, T7, T8, T2 and C3 are arranged in sequence along the first direction, T6, C1 and C3 are arranged in sequence along the first direction, and C2, T1, T3 and C3 are arranged in sequence along the first direction;

[0221] T1 includes a first active pattern, and the first active pattern of T1 is arranged vertically, which is not conducive to the compact arrangement between T2 and T3;

[0222] The second electrode plate C3b of C3 is relatively wide in the transverse direction, which is not conducive to narrowing the width of the shift register unit in the second direction.

[0223] exist Figure 2D In the figure, the first output line portion of the signal output line is labeled E01, the first second output line portion of the signal output line is labeled E021, and the second second output line portion of the signal output line is labeled E022. E01 is arranged along the first direction, and E021 is arranged along the second direction. E01, E021, and E022 are coupled to each other, and the first direction and the second direction intersect. E01 is arranged between VGL and the output circuit (the output circuit includes the output transistor T10 and the output reset transistor T9), and E021 and E022 extend toward the display area along the second direction to provide a light-emitting control signal for the pixel circuit located in the display area.

[0224] like Figure 2D As shown, S7 is multiplexed into D8.

[0225] exist Figure 2D and Figure 3A In the figure, G1 is the gate of T1, S1 is the first electrode of T1, and D1 is the second electrode of T1; G2 is the gate of T2, S2 is the first electrode of T2, and D2 is the second electrode of T2; G3 is the gate of T3, S3 is the first electrode of T3, and D3 is the second electrode of T3; G4 is the gate of T4, S4 is the first electrode of T4, and D4 is the second electrode of T4; G5 is the gate of T5, S5 is the first electrode of T5, and D5 is the second electrode of T5 The second electrode of T6 is labeled G6; the gate of T6 is labeled S6; the first electrode of T6 is labeled D6; the gate of T7 is labeled G7, the first electrode of T7 is labeled S7, and the second electrode of T7 is labeled D7; the gate of T8 is labeled G8, the first electrode of T8 is labeled S8; the gate of T9 is labeled G9, the first electrode of T9 is labeled S9, and the second electrode of T9 is labeled D9; the gate of T10 is labeled G10, the first electrode of T10 is labeled S10, and the second electrode of T10 is labeled D10.

[0226] exist Figure 2DIn at least one embodiment shown, the first direction may be a vertical direction from top to bottom, and the second direction may be a horizontal direction from right to left, but the present invention is not limited thereto. In actual operation, the first direction may also be a vertical direction from bottom to top, and the second direction may also be a horizontal direction from left to right; alternatively, the first direction may also be other directions, and the second direction may also be other directions.

[0227] exist Figure 2D In the layout of the gate drive circuit shown, the active layer of T9 and the active layer of T9 are formed by a continuous first semiconductor layer. The length of the first semiconductor layer in the first direction is small, so the vertical space of the entire shift register unit is small, which will cause the width of the shift register unit to be larger in the horizontal direction, which is not conducive to the close arrangement of the devices in the shift register unit in the horizontal direction, and is not conducive to the development of narrow borders of the display substrate.

[0228] Figure 2D The shift register unit shown may be an n-th stage shift register unit included in the scan driving circuit, where n is a positive integer.

[0229] Based on the above problems, the inventors of the present invention have discovered that the layout of the transistors in the shift register unit can be adjusted to reduce the occupied area of ​​the shift register unit, thereby reducing the border width of the display substrate.

[0230] exist Figure 3A In the illustrated layout, the first voltage signal line VGH provides a high voltage signal Vgh, and the second voltage signal line VGL provides a low voltage signal Vgl. In at least one embodiment of the present invention, the shift register unit is disposed between VGH and VGL.

[0231] exist Figure 3A In the figure, E01 is the first output line portion of the signal output line, E021 is the first second output line portion of the signal output line, and E022 is the second second output line portion of the signal output line. E01 is arranged along the first direction, and E021 is arranged along the second direction. E01, E021, and E022 are coupled to each other, and the first direction and the second direction intersect. Figure 3A As shown, E01 is disposed between VGL and the output circuit, and E021 and E022 extend toward the display area along the second direction to provide light emitting control signals for the pixel circuits located in the display area.

[0232] For example, in Figure 3A In the layout shown, the first direction may be a vertical direction from top to bottom, and the second direction may be a horizontal direction from right to left, but the present invention is not limited thereto.

[0233] Figure 3AThe shift register unit shown may be an n-th stage shift register unit included in the scan driving circuit, where n is a positive integer.

[0234] like Figure 1 and Figure 3A As shown, at least one embodiment of the shift register unit includes a first capacitor C1, an output capacitor C2, an output reset capacitor C3, an output transistor T10, an output reset transistor T9, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8; Figure 3A As shown, the output circuit O1 includes the output transistor T10 and the output reset transistor T9;

[0235] The gate G10 of the output transistor T10 is coupled to the first plate C2a of the output capacitor C2, the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL, and the second electrode D10 of the output transistor T10 is coupled to the first output line portion E01 included in the signal output line;

[0236] The gate G9 of the output reset transistor T9 is coupled to the first plate C3a of the output reset capacitor C3, the first electrode S9 of the output reset transistor T9 is coupled to the second plate C3b of the output reset capacitor C3, and the second electrode D9 of the output reset transistor T9 is coupled to the first output line portion E01 included in the signal output line.

[0237] exist Figure 3A In the layout of the gate drive circuit shown, the active layer of T9 and the active layer of T10 can be formed by a continuous first semiconductor layer. The length of the first semiconductor layer in the first direction is increased, so that other devices included in the shift register unit can utilize the extra space in the vertical direction, narrowing the width of the shift register unit in the horizontal direction, which is beneficial to the close arrangement of the devices in the shift register unit in the horizontal direction and the development of a narrow frame of the display substrate.

[0238] like Figure 3A As shown, when the shift register unit of the above structure is arranged in the edge area of ​​the display substrate, the second voltage signal line VGL, the first voltage signal line VGH, the first clock signal line CK, and the second clock signal line CB are arranged in sequence along the direction away from the display area of ​​the display substrate; the second voltage signal line VGL, the first voltage signal line VGH, the first clock signal line CK, and the second clock signal line CB all extend along the first direction;

[0239] like Figure 3AAs shown, the first capacitor C1, the output capacitor C2, the output reset capacitor C3, the output transistor T10, the output reset transistor T9, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are all arranged between VGH and VGL; T5, T6, T4, T7 and T8 are all moved up to utilize the length of the first semiconductor layer stretched in the first direction;

[0240] T1 includes a first active pattern, and the first active pattern of T1 is arranged to extend along the second direction. T1 is arranged between T8 and C1. T8, T1, and C1 are arranged in sequence along the first direction, so that T1 is arranged in the space between T8 and C1, so that T2 and T3 can be arranged more compactly (the second electrode D2 of the second transistor T2 is coupled to the second electrode D2 of the third transistor T3, so for the convenience of wiring, T2 and T3 also need to be arranged close to each other), which can further narrow the width of the shift register unit in the second direction;

[0241] And, in Figure 3A In the layout shown, the shape of C1 is more consistent with the arrangement of T1, T2 and T3, and the space between T1, T2 and T3 is used to set the plate of C1;

[0242] exist Figure 3A In the illustrated layout, the width of the second electrode plate C3b of C3 in the second direction is set to be smaller, and the length of the second electrode plate C3b of C3 in the first direction is set to be larger, so as to narrow the width of the electrode plate of C3 in the second direction while ensuring the area of ​​the electrode plate of C3;

[0243] like Figure 3A As shown, the orthographic projection of the second electrode plate C3b of C3 on the substrate is within the orthographic projection of the first electrode plate C3a of C3 on the substrate.

[0244] And, as Figure 3A and Figure 6 ( Figure 6 for Figure 3A As shown in FIG. 1 , the gate G6 of T6 includes a first gate pattern G61 and a second gate pattern G62 coupled to each other, so that T6 forms a dual-gate structure.

[0245] The purpose of the dual-gate structure design is that during the second phase P2, when the shift register unit included in the scan driver circuit outputs a high voltage signal Vgh, T10 should be completely turned off, and the high voltage input to the gate of T10 is from the source of T8. Therefore, during the second phase P2, T8 must be turned on, that is, the potential of the second node N2 must be low. In the second phase P2, the potential of the gate of T6 is high. To ensure that T6 does not leak and cause the potential of the second node N2 to increase, T6 is configured with a dual-gate design, making it easier to turn off.

[0246] In at least one embodiment of the present invention, the first direction intersects with the second direction. For example, the first direction may be perpendicular to the second direction, but the present invention is not limited thereto.

[0247] Specifically, the angle between the second direction and the first direction can be set according to actual needs. For example, the second direction is perpendicular to the first direction.

[0248] In at least one embodiment of the present invention, the position of the first clock signal line CB and the position of the second clock signal line CK may be swapped, but this is not limited to the above.

[0249] exist Figure 3A In the layout shown, Figure 5 As shown ( Figure 5 yes Figure 3A Schematic diagram of the active layer in the first semiconductor layer 10), the length of the first semiconductor layer 10 in the first direction is the output active length L1, and the minimum width of the first semiconductor layer 10 in the second direction is the output active width W1;

[0250] The output active length L1 is a first predetermined length;

[0251] The ratio of the output active length L1 to the output active width W1 is within a predetermined ratio range;

[0252] The output active width W1 is within a predetermined width range;

[0253] At least one embodiment of the present invention increases the output active length L1 so that the devices other than the output circuit in the shift register unit can utilize the extra vertical space due to the increase in L1 for layout, thereby narrowing the lateral space occupied by the shift register unit; and at least one embodiment of the present invention reduces the output active width W1 so that the devices other than the output circuit in the shift register unit can utilize the saved horizontal space for layout, thereby narrowing the lateral space occupied by the shift register unit.

[0254] In at least one embodiment of the present invention, the predetermined ratio range may be greater than or equal to 3 and less than or equal to 11, but is not limited thereto.

[0255] In at least one embodiment of the present invention, the predetermined width may be greater than or equal to 12 um and less than or equal to 45 um, but is not limited thereto.

[0256] In at least one embodiment of the present invention, the first predetermined length may be greater than or equal to 50 um and less than or equal to 130 um, but is not limited thereto.

[0257] like Figure 3A and Figure 8 As shown, the first output line portion E01 is coupled to the second electrode D10 of the output transistor T10 through a plurality of first signal line vias H01 provided in the signal line overlapping region, and the first output line portion E01 is coupled to the second electrode D9 of the output reset transistor T9 through a plurality of second signal line vias H02 provided in the signal line overlapping region; the plurality of first signal line vias H01 are sequentially arranged along the first direction, and the plurality of second signal line vias H02 are sequentially arranged along the first direction;

[0258] like Figure 4 and Figure 10 ( Figure 10 yes Figure 3A Schematic diagram of the source and drain metal layers in Figure 10 As shown in the figure, the signal line overlapping area includes a first signal line overlapping area A01 and a second signal line overlapping area A02. The first signal line overlapping area A01 is an overlapping area of ​​the orthographic projection of the first output line portion E01 on the substrate and the orthographic projection of the first source-drain metal pattern Ds1 on the substrate, in which the second electrode D10 of the output transistor T10 is included. The second signal line overlapping area A02 is an overlapping area of ​​the orthographic projection of the first output line portion E01 on the substrate and the orthographic projection of the second source-drain metal pattern Ds2 on the substrate, in which the second electrode D9 of the output reset transistor T9 is included.

[0259] like Figure 4 and Figure 10 As shown, the ratio of the maximum distance K1 in the first direction between the first first signal line via and the last first signal line via arranged sequentially along the first direction to the third length L3 is a third predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance; the third length L3 is the length of the first signal line overlapping area A01 in the first direction;

[0260] The ratio of the maximum distance K2 in the first direction between the first second signal line via and the last second signal line via arranged sequentially along the first direction to the fourth length L4 is a fourth predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance; the fourth length L4 is the length of the second signal line overlapping area A02 in the first direction.

[0261] In at least one embodiment of the present invention, the number of the first signal line via holes and the number of the second signal line via holes can be selected according to actual conditions.

[0262] In at least one embodiment of the present invention, the maximum distance in the first direction between any two first signal line vias arranged sequentially along the first direction refers to: the maximum distance in the first direction between edges of orthographic projections of any two first signal line vias on the substrate;

[0263] The maximum distance K1 in the first direction between the first first signal line via and the last first signal line via arranged sequentially along the first direction refers to: the maximum distance in the first direction between the edge of the orthographic projection of the first first signal line via on the substrate and the edge of the orthographic projection of the last first signal line via on the substrate;

[0264] The minimum distance K01 between two adjacent first signal line vias in the first direction refers to: the minimum distance between the edges of the orthographic projections of the two adjacent first signal line vias on the substrate in the first direction;

[0265] The maximum distance K2 in the first direction between the first second signal line via and the last second signal line via arranged sequentially along the first direction refers to: the maximum distance in the first direction between the edge of the orthographic projection of the first second signal line via on the substrate and the edge of the orthographic projection of the last second signal line via on the substrate;

[0266] The maximum distance in the first direction between any two second signal line vias arranged sequentially along the first direction refers to: the maximum distance in the first direction between edges of orthographic projections of any two second signal line vias on the substrate;

[0267] The minimum distance K02 between two adjacent second signal line vias in the first direction refers to: the minimum distance between edges of orthographic projections of the two adjacent second signal line vias on the substrate in the first direction.

[0268] In at least one embodiment of the present invention, the first predetermined ratio may be greater than or equal to 0.05 and less than or equal to 0.9, but is not limited thereto;

[0269] The first predetermined distance may be greater than or equal to 1.5 μm and less than or equal to 45 μm, but is not limited thereto;

[0270] The second predetermined ratio may be greater than or equal to 0.05 and less than or equal to 0.9, but is not limited thereto;

[0271] The second predetermined distance may be greater than or equal to 1.5 um and less than or equal to 65 um, but is not limited thereto.

[0272] like Figure 3A 、 Figure 4 and Figure 10 As shown, since the active layers of T10 and T9 are longitudinally stretched, the third length L3 and the fourth length L4 are correspondingly lengthened, so that the plurality of first signal line vias H01 can be evenly arranged in the first signal line overlapping area A01, and the ratio of the maximum distance K1 between the first first signal line via from top to bottom and the last first signal line via from top to bottom in the first direction to the third length L3 is a third predetermined ratio. The plurality of first signal line vias H01 can cover the first signal line overlapping area A01 as much as possible, so that the second electrode D10 of the output transistor T10 can be better coupled to E01.

[0273] like Figure 3A 、 Figure 4 and Figure 10 As shown, since the active layer of T10 and the active layer of T9 are longitudinally stretched, the third length L3 and the fourth length L4 are correspondingly lengthened, so that the multiple second signal line vias H02 can be evenly arranged in the second signal line overlapping area A02, and the ratio of the maximum distance K2 in the first direction between the first second signal line via from top to bottom and the last second signal line via from top to bottom to the fourth length L4 is a fourth predetermined ratio. The multiple second signal line vias H02 can cover the second signal line overlapping area A02 as much as possible, so that the second electrode D9 of the output reset transistor T9 can be better coupled to E01.

[0274] In at least one embodiment of the present invention, the third predetermined ratio may be greater than or equal to 0.05 and less than or equal to 0.9; the fourth predetermined ratio may be greater than or equal to 0.05 and less than or equal to 0.9, but is not limited thereto.

[0275] A display substrate according to at least one embodiment of the present invention includes a scan drive circuit and a display area disposed on a substrate; the scan drive circuit includes a plurality of shift register units, at least one of the plurality of shift register units includes a signal output line and an output circuit, and the output circuit includes an output transistor and an output reset transistor;

[0276] The signal output line includes a first output line portion extending along a first direction;

[0277] The first output line portion is coupled to the second electrode of the output transistor through a plurality of first signal line vias provided in the signal line overlapping region, and the first output line portion is coupled to the second electrode of the output reset transistor through a plurality of second signal line vias provided in the signal line overlapping region; the plurality of first signal line vias are arranged sequentially along a first direction, and the plurality of second signal line vias are arranged sequentially along the first direction;

[0278] The signal line overlapping region includes a first signal line overlapping region and a second signal line overlapping region, the first signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a first source-drain metal pattern included in the second electrode of the output transistor on the substrate, and the second signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a second source-drain metal pattern included in the second electrode of the output reset transistor on the substrate;

[0279] The ratio of the maximum distance between any two first signal line vias arranged sequentially along the first direction in the first direction to the third length is a first predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance; the third length is the length of the overlapping area of ​​the first signal lines in the first direction;

[0280] The ratio of the maximum distance between any two second signal line vias arranged sequentially along the first direction in the first direction to the fourth length is a second predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance; and the fourth length is the length of the overlapping region of the second signal line in the first direction;

[0281] The first predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0282] The first predetermined distance is greater than or equal to 1.5 μm and less than or equal to 45 μm;

[0283] The second predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0284] The second predetermined distance is greater than or equal to 1.5 um and less than or equal to 65 um.

[0285] Optionally, the active layer of the output transistor and the active layer of the output reset transistor are arranged along a first direction, the length of the active layer of the output transistor in the first direction is a first length, the length of the active layer of the output reset transistor in the first direction is a second length, and the sum of the first length and the second length is the output active length;

[0286] The smaller of the minimum width of the active layer of the output transistor along the second direction and the minimum width of the active layer of the output reset transistor along the second direction is the output active width; the first direction intersects the second direction.

[0287] In at least one embodiment of the present invention, a ratio of the output active length to the output active width is within a predetermined ratio range; the predetermined ratio range is greater than or equal to 3 and less than or equal to 11, but is not limited thereto.

[0288] At least one embodiment of the present invention increases the output active length so that components other than the output circuit in the shift register unit can utilize the additional longitudinal space created by the increased output active length for layout, thereby narrowing the lateral space occupied by the shift register unit. Furthermore, in at least one embodiment of the present invention, because the active layer of the output transistor and the active layer of the output reset transistor are longitudinally elongated, the third length and the fourth length are correspondingly lengthened, thereby allowing multiple first signal line vias to be evenly arranged in the first signal line overlapping region, and the ratio of the maximum distance between any two first signal line vias in the first direction to the third length is a first predetermined ratio. The multiple first signal line vias can cover the first signal line overlapping region as much as possible, thereby enabling the second electrode of the output transistor to be better coupled to the first output line portion.

[0289] like Figure 3A 、 Figure 4 and Figure 10 As shown, since the active layer of the output transistor and the active layer of the output reset transistor are longitudinally stretched, the third length and the fourth length are correspondingly lengthened, so that the multiple second signal line vias can be evenly arranged in the second signal line overlapping area, and the ratio of the maximum distance between any two second signal line vias in the first direction from top to bottom to the fourth length is a second predetermined ratio. The multiple second signal line vias can cover the second signal line overlapping area as much as possible, so that the second electrode of the output reset transistor can be better coupled to the first output line portion.

[0290] In at least one embodiment of the present invention, the output active width may be within a predetermined width range.

[0291] At least one embodiment of the present invention can reduce the output active width, so that devices other than the output circuit in the shift register unit can be arranged using the saved horizontal space, and the lateral space occupied by the shift register unit can be narrowed.

[0292] Optional, such as Figure 3A and Figure 5 As shown, the active layer of the output transistor T10 and the active layer of the output reset transistor T9 may be formed by a continuous first semiconductor layer 10; the first semiconductor layer extends along the first direction 10;

[0293] like Figure 5 As shown, the length of the first semiconductor layer 10 in the first direction is the output active length L1;

[0294] The minimum length of the first semiconductor layer 10 in the second direction is the output active length W1.

[0295] like Figure 3A As shown, the output transistor T10 and the output reset transistor T9 are arranged in sequence along the first direction, but the present invention is not limited thereto. In actual operation, the output reset transistor T9 and the output transistor T10 may also be arranged in sequence along the first direction.

[0296] In at least one embodiment of the present invention, the output reset transistor T9 is used to provide an invalid light emitting control signal, and the output transistor T10 is used to provide a valid light emitting control signal.

[0297] In at least one embodiment of the present invention, the valid light-emitting control signal may be a voltage signal that can turn on the light-emitting control transistor in the pixel circuit (the gate of the light-emitting control transistor is coupled to the light-emitting control line), and the invalid light-emitting control signal may be a voltage signal that can turn off the light-emitting control transistor.

[0298] Specifically, the display area of ​​the display substrate includes multiple sub-pixels; at least one sub-pixel among the multiple sub-pixels includes a pixel driving circuit; the pixel driving circuit includes a transistor, a gate line, a light-emitting control line and a data line; the shift register unit included in the scanning driving circuit can correspond to at least one light-emitting control line, and the signal output line of each shift register unit is coupled to the corresponding at least one light-emitting control line for providing a light-emitting control signal to the corresponding light-emitting control line.

[0299] In at least one embodiment of the present invention, the active layer of the output transistor and the active layer of the reset transistor may be formed of a continuous first semiconductor layer;

[0300] The active layer of the output transistor may include at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each first channel portion is arranged between two adjacent first conductive portions;

[0301] The active layer of the output reset transistor may include at least two second conductive portions arranged opposite to each other along a first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions;

[0302] The first conductive portion in the active layer of the output transistor that is closest to the active layer of the output reset transistor can be reused as the second conductive portion in the output reset transistor. This can further reduce the layout space of the output transistor and the output reset transistor, which is conducive to achieving a narrow frame of the display substrate.

[0303] like Figure 5 As shown, the active layer of the output transistor T10 and the active layer of the output reset transistor T9 can be formed by a continuous first semiconductor layer 10;

[0304] The active layer of the output transistor T10 includes a first first conductive portion 111, a second first conductive portion 112, a third first conductive portion 113, a fourth first conductive portion 114, a fifth first conductive portion 115, and a sixth first conductive portion 116 that are arranged opposite to each other along a first direction; the active layer of the output transistor T10 also includes a first first channel portion 121, a second first channel portion 122, a third first channel portion 123, a fourth first channel portion 124, and a fifth first channel portion 125;

[0305] The first first channel portion 121 is disposed between the first first conductive portion 111 and the second first conductive portion 112 , and the second first channel portion 122 is disposed between the second first conductive portion 112 and the third first conductive portion 113 ;

[0306] The third first channel portion 123 is disposed between the third first conductive portion 113 and the second fourth conductive portion 114, the fourth first channel portion 124 is disposed between the fourth first conductive portion 114 and the fifth first conductive portion 115, and the fifth first channel portion 125 is disposed between the fifth first conductive portion 115 and the sixth first conductive portion 116.

[0307] The sixth first conductive portion 116 is multiplexed as the first second conductive portion included in the active layer of the output reset transistor T9;

[0308] The active layer of the output reset transistor T9 further includes a second second conductive portion 132, a third second conductive portion 133, a fourth second conductive portion 134, a fifth second conductive portion 135, and a sixth second conductive portion 136 arranged opposite to each other along the first direction; the active layer of the output reset transistor T9 further includes a first second channel portion 141, a second second channel portion 142, a third second channel portion 143, a fourth second channel portion 144, and a fifth second channel portion 145;

[0309] The first second channel portion 141 is arranged between the first second conductive portion and the second second conductive portion 132, the second second channel portion 142 is arranged between the second second conductive portion 132 and the third second conductive portion 133, the third second channel portion 143 is arranged between the third second conductive portion 133 and the fourth second conductive portion 134, the fourth second channel portion 144 is arranged between the fourth second conductive portion 134 and the fifth second conductive portion 135, and the fifth second channel portion 145 is arranged between the fifth second conductive portion 135 and the sixth second conductive portion 136.

[0310] In the output transistor T10 and the output reset transistor T9, the conductive parts on both sides of the channel part of each transistor can respectively correspond to the first electrode and the second electrode of the transistor, or can be coupled to the first electrode and the second electrode of the transistor, respectively, so that T10 and T9 can be electrically connected through the sixth first conductive part 116.

[0311] When manufacturing the first semiconductor layer 10, for example, a first semiconductor material layer can be formed first, and then after forming the gate G10 of the output transistor T10 and the gate G9 of the output reset transistor T9, the gate G10 of the output transistor T10 and the gate G9 of the output reset transistor T9 are used as masks to dope the portions of the first semiconductor material layer that are not covered by the gates of the transistors, so that the portions of the first semiconductor material layer that are not covered by the gates of the transistors are formed as the conductive portions, and the portions of the first semiconductor material layer that are covered by the transistors are formed as the channel portions.

[0312] According to the specific structure of the above-mentioned display substrate, it can be seen that in the display substrate described in at least one embodiment of the present invention, the output transistor T10 and the output reset transistor T9 in the shift register unit can be arranged along the first direction, thereby reducing the area occupied by the shift register unit in the second direction, thereby making the display substrate more in line with the development needs of narrow bezels.

[0313] Specifically, the gate of the output transistor may include at least one output gate pattern, the first electrode of the output transistor may include at least one first electrode pattern, and the second electrode of the output transistor may include at least one second electrode pattern;

[0314] The output gate pattern is located between the adjacent first electrode pattern and the second electrode pattern;

[0315] The first electrode pattern, the output gate pattern, and the second electrode pattern all extend along a second direction.

[0316] Specifically, the gate of the output reset transistor may include at least one output reset gate pattern, the first electrode of the output reset transistor may include at least one third electrode pattern, and the second electrode of the output reset transistor may include at least one fourth electrode pattern;

[0317] The output reset gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern;

[0318] The third electrode pattern, the output reset gate pattern and the fourth electrode pattern all extend along the second direction;

[0319] The fourth electrode pattern of the output reset transistor that is closest to the gate of the output transistor is multiplexed as the second electrode pattern of the output transistor.

[0320] In a specific implementation, the number of the output reset gate patterns, the number of the first electrode patterns, the number of the second electrode patterns, the number of the output gate patterns, the number of the third electrode patterns and the number of the fourth electrode patterns can be set according to actual needs. Figure 6 and Figure 9 As shown, the number of the output gate patterns and the number of the output reset gate patterns can be five, the number of the first electrode patterns can be three, the number of the second electrode patterns can be three, the number of the third electrode patterns can be three, and the number of the fourth electrode patterns can be three, but is not limited to this.

[0321] Furthermore, since the second electrode of the output transistor and the second electrode of the output reset transistor are both coupled to the signal output line, when laying out the output transistor and the output reset transistor, the fourth electrode pattern of the output reset transistor that is closest to the gate of the output transistor can be reused as the second electrode pattern of the output transistor. This can further reduce the layout space of the output transistor and the output reset transistor, which is conducive to achieving a narrow frame of the display substrate.

[0322] like Figure 3A and Figure 6As shown, in some embodiments, the gate of the output transistor T10 may include: a first output gate pattern G101, a second output gate pattern G102, a third output gate pattern G103, a fourth output gate pattern G104 and a fifth output gate pattern G105;

[0323] The gate of the output reset transistor T9 may include: a first output reset gate pattern G91, a second output reset gate pattern G92, a third output reset gate pattern G93, a fourth output reset gate pattern G94 and a fifth output reset gate pattern G95;

[0324] The first output gate pattern G101, the second output gate pattern G102, the third output gate pattern G103, the fourth output gate pattern G104 and the fifth output gate pattern G105 are arranged in sequence along the first direction;

[0325] The first output reset gate pattern G91, the second output reset gate pattern G92, the third output reset gate pattern G93, the fourth output reset gate pattern G94 and the fifth output reset gate pattern G95 are arranged in sequence along the first direction;

[0326] The first output gate pattern G101, the second output gate pattern G102, the third output gate pattern G103, the fourth output gate pattern G104 and the fifth output gate pattern G105 all extend along the second direction, and the first direction intersects the second direction;

[0327] The first output gate pattern G101, the second output gate pattern G102, the third output gate pattern G103, the fourth output gate pattern G104 and the fifth output gate pattern G105 are coupled to each other;

[0328] The first output reset gate pattern G91, the second output reset gate pattern G92, the third output reset gate pattern G93, the fourth output reset gate pattern G94 and the fifth output reset gate pattern G95 all extend along the second direction;

[0329] The first output reset gate pattern G91, the second output reset gate pattern G92, the third output reset gate pattern G93, the fourth output reset gate pattern G94 and the fifth output reset gate pattern G95 are coupled to each other;

[0330] like Figure 9 As shown, the first electrode S10 of the output transistor T10 includes a first first electrode pattern S101, a second first electrode pattern S102 and a third first electrode pattern S103;

[0331] The second electrode D10 of the output transistor T10 includes a first second electrode pattern D101 and a second second electrode pattern D102;

[0332] The first electrode S9 of the output reset transistor T9 includes a first third electrode pattern S91, a second third electrode pattern S92 and a third third electrode pattern S93;

[0333] The second electrode D9 of the output reset transistor T9 includes a first fourth electrode pattern D91, a second fourth electrode pattern D92 and a third fourth electrode pattern D93;

[0334] The first fourth electrode pattern D91 is multiplexed as the third second electrode pattern included in the output transistor T10;

[0335] like Figures 3A to 10 As shown, S101 is coupled to VGL, S101 is coupled to S102, S103 is coupled to VGL, S91, S92 and S93 are respectively coupled to the first conductive connection part F1, and the first conductive connection part F1 is coupled to the first voltage signal line VGH;

[0336] like Figures 3A to 10 As shown, the first output line portion E01 is coupled to D101 and D102 respectively through a plurality of first signal line vias H01 provided in the signal line overlapping area, and the first output line portion E01 is coupled to D91, D92 and D93 respectively through a plurality of second signal line vias H02 provided in the signal line overlapping area;

[0337] The plurality of first signal line vias H01 are sequentially arranged along the first direction, and the plurality of second signal line vias H02 are sequentially arranged along the first direction.

[0338] In a specific implementation, the active layer of the output transistor may include at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each first channel portion is arranged between two adjacent first conductive portions;

[0339] The first channel portions correspond to the output gate patterns one by one, and the orthographic projection of each first channel portion on the substrate is located inside the orthographic projection of the corresponding output gate pattern on the substrate;

[0340] A portion of the first conductive portions of the output transistor corresponds to the first electrode pattern one-to-one, an orthographic projection of the first electrode pattern on the substrate and an orthographic projection of the corresponding first conductive portion on the substrate having a first overlapping region, and the first electrode pattern is coupled to the corresponding first conductive portion via at least one first via provided in the first overlapping region;

[0341] Another part of the first conductive portion in the output transistor corresponds one-to-one to the second electrode pattern, and an orthographic projection of the second electrode pattern on the substrate has a second overlapping area with an orthographic projection of the corresponding first conductive portion on the substrate, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via provided in the second overlapping area.

[0342] In a specific implementation, the active layer of the output reset transistor includes at least two second conductive portions arranged opposite to each other along a first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions;

[0343] The second channel portions correspond to the output reset gate patterns one by one, and the orthographic projection of each second channel portion on the substrate is located inside the orthographic projection of the corresponding output reset gate pattern on the substrate;

[0344] A portion of the second conductive portions of the output reset transistor corresponds one-to-one to the third electrode pattern, an orthographic projection of the third electrode pattern on the substrate and an orthographic projection of the corresponding second conductive portion on the substrate form a third overlapping region, and the third electrode pattern is coupled to the corresponding second conductive portion via at least one third via provided in the third overlapping region;

[0345] Another part of the second conductive portion in the output reset transistor corresponds one-to-one to the fourth electrode pattern, and the orthographic projection of the fourth electrode pattern on the substrate has a fourth overlapping area with the orthographic projection of the corresponding second conductive portion on the substrate. The fourth electrode pattern is coupled to the corresponding second conductive portion through at least one fourth via provided in the fourth overlapping area.

[0346] like Figure 5 、 Figure 6 、 Figure 8 and Figure 9 As shown, the first first channel portion 121 corresponds to the first output gate pattern G101, the second first channel portion 122 corresponds to the second output gate pattern G102, the third first channel portion 123 corresponds to the third output gate pattern G103, the fourth first channel portion 124 corresponds to the fourth output gate pattern G104, and the fifth first channel portion 125 corresponds to the fifth output gate pattern G105;

[0347] The orthographic projection of the first first channel portion 121 on the substrate is located inside the orthographic projection of the first output gate pattern G101 on the substrate;

[0348] The orthographic projection of the second first channel portion 122 on the substrate is located inside the orthographic projection of the second output gate pattern G102 on the substrate;

[0349] The orthographic projection of the third first channel portion 123 on the substrate is located inside the orthographic projection of the third output gate pattern G103 on the substrate;

[0350] The orthographic projection of the fourth first channel portion 124 on the substrate is located inside the orthographic projection of the fourth output gate pattern G104 on the substrate;

[0351] The orthographic projection of the fifth first channel portion 125 on the substrate is located inside the orthographic projection of the fifth output gate pattern G105 on the substrate;

[0352] The first first conductive portion 111 corresponds to the first first electrode pattern S101, the second first conductive portion 112 corresponds to the first second electrode pattern D101, the third first conductive portion 113 corresponds to the second first electrode pattern S102, the fourth first conductive portion 114 corresponds to the second second electrode pattern D102, the fifth first conductive portion 115 corresponds to the third first electrode pattern S103, and the sixth first conductive portion 116 corresponds to the first fourth electrode pattern D91;

[0353] The sixth first conductive portion 116 is multiplexed as the first second conductive portion included in the active layer of the output reset transistor T9;

[0354] The first second channel portion 141 corresponds to the first output reset gate pattern G91, the second second channel portion 142 corresponds to the second output reset gate pattern G92, the third second channel portion 143 corresponds to the third output reset gate pattern G93, the fourth second channel portion 144 corresponds to the fourth output reset gate pattern G94, and the fifth second channel portion 145 corresponds to the fifth output reset gate pattern G95;

[0355] The orthographic projection of the first second channel portion 141 on the substrate is located inside the orthographic projection of the first output reset gate pattern G91 on the substrate;

[0356] The orthographic projection of the second second channel portion 142 on the substrate is located inside the orthographic projection of the second output reset gate pattern G92 on the substrate;

[0357] The orthographic projection of the third second channel portion 143 on the substrate is located inside the orthographic projection of the third output reset gate pattern G93 on the substrate;

[0358] The orthographic projection of the fourth second channel portion 144 on the substrate is located inside the orthographic projection of the fourth output reset gate pattern G94 on the substrate;

[0359] The orthographic projection of the fifth second channel portion 145 on the substrate is located inside the orthographic projection of the fifth output reset gate pattern G95 on the substrate;

[0360] The second second conductive portion 132 corresponds to the first third electrode pattern S91, the third second conductive portion 133 corresponds to the second fourth electrode pattern D92, the fourth second conductive portion 134 corresponds to the second third electrode pattern S92, the fifth second conductive portion 135 corresponds to the third fourth electrode pattern D93, and the sixth second conductive portion 136 corresponds to the third third electrode pattern S93;

[0361] There is a first first overlapping region between the orthographic projection of S101 on the substrate and the orthographic projection of the first first conductive portion 111 on the substrate, there is a second first overlapping region between the orthographic projection of S102 on the substrate and the orthographic projection of the third first conductive portion 113 on the substrate, there is a third first overlapping region between the orthographic projection of S103 on the substrate and the orthographic projection of the fifth first conductive portion 115 on the substrate, S101 is coupled to the first first conductive portion 111 via a first via H1 provided in the first first overlapping region, S102 is coupled to the third first conductive portion 113 via a first via H1 provided in the second first overlapping region, and S103 is coupled to the fifth first conductive portion 115 via a first via H1 provided in the third first overlapping region;

[0362] There is a first second overlapping region between the orthographic projection of D101 on the substrate and the orthographic projection of the second first conductive portion 112 on the substrate, and a second second overlapping region between the orthographic projection of D102 on the substrate and the fourth first conductive portion 114. D101 is coupled to the second first conductive portion 112 via a second via H2 provided in the first second overlapping region, and D102 is coupled to the fourth first conductive portion 114 via a second via H2 provided in the second second overlapping region.

[0363] There is a first fourth overlapping region between the orthographic projection of D91 on the substrate and the orthographic projection of the first second conductive portion 131 on the substrate, there is a second fourth overlapping region between the orthographic projection of D92 on the substrate and the orthographic projection of the third second conductive portion 133 on the substrate, and there is a third fourth overlapping region between the orthographic projection of D93 on the substrate and the fifth second conductive portion 135; D91 is coupled to the first second conductive portion 131 via a fourth via H4 provided in the first fourth overlapping region, D92 is coupled to the third second conductive portion 133 via a fourth via H4 provided in the second fourth overlapping region, and D93 is coupled to the fifth second conductive portion 133 via a fourth via H4 provided in the third fourth overlapping region;

[0364] There is a first third overlapping area between the orthographic projection of S91 on the substrate and the orthographic projection of the second second conductive part 132 on the substrate, there is a second third overlapping area between the orthographic projection of S92 on the substrate and the orthographic projection of the fourth second conductive part 134 on the substrate, and there is a third third overlapping area between the orthographic projection of S93 on the substrate and the orthographic projection of the sixth second conductive part 136 on the substrate; S91 is coupled to the second second conductive part 132 through the third via H3 set in the first third overlapping area, S92 is coupled to the fourth second conductive part 134 through the third via H3 set in the second third overlapping area, and S93 is coupled to the sixth second conductive part 136 through the third via H3 set in the third third overlapping area.

[0365] In at least one embodiment of the present invention, the number of the first via holes, the number of the second via holes, the number of the third via holes, and the number of the fourth via holes can be set according to actual needs.

[0366] exist Figure 3A In the layout shown, the number of the first vias, the number of the second vias, and the number of the third vias are all three. However, in actual operation, the number of the above vias can be selected according to actual conditions. For example, Figure 11 As shown, in another layout, the number of the first via holes, the number of the second via holes, and the number of the third via holes can all be two. Figure 11 In the layout shown, the length of the first semiconductor layer in the first direction is longer (compared to Figure 3A Compared with the layout shown in FIG, the width of the first semiconductor layer in the second direction is narrower (compared with FIG. Figure 3A Compared with the layout shown in FIG, it is more conducive to narrowing the width occupied by the shift register unit in the second direction, which is conducive to achieving a narrow frame.

[0367] In the display substrate provided by the above embodiment, the first semiconductor layer 10 is used to form the active layer of the output reset transistor T9 and the active layer of the output transistor T10. This not only reduces the space occupied by T9 and T10 in the second direction, but also ensures the channel width of T9 and the channel width of T10 by increasing the dimensions of the active layer of the output reset transistor T9 and the active layer of the output transistor T10 in the first direction. This allows the border width of the display substrate to be reduced while ensuring the operating performance of T9 and T10.

[0368] In at least one embodiment of the present invention, Figure 5 yes Figure 3A Schematic diagram of the active layer in Figure 6 yes Figure 3A Schematic diagram of the first gate metal layer in Figure 7 yes Figure 3A Schematic diagram of the second gate metal layer in FIG. Figure 8 This is a schematic diagram of a via hole made after the active layer, the first gate metal layer, and the second gate metal layer are sequentially arranged. Figure 9 yes Figure 3A Schematic diagram of the source and drain metal layers in .

[0369] In a specific implementation, an active layer, a first gate metal layer, a second gate metal layer, via holes and a source-drain metal layer are sequentially arranged on a substrate to form a display substrate.

[0370] In at least one embodiment of the present invention, the at least one shift register unit may include a plurality of transistors in addition to an output transistor and an output reset transistor; the conductive portions on both sides of the channel portion of each transistor may correspond to the first electrode and the second electrode of the transistor, respectively, or may be coupled to the first electrode of the transistor and the second electrode of the transistor, respectively.

[0371] like Figure 3A-Figure 9 As shown, S91, S92 and S93 are respectively coupled to the first conductive connection part F1, and the first conductive connection part F1 is coupled to the first voltage signal line VGH;

[0372] There is a fifth overlapping area between the orthographic projection of the first conductive connection portion F1 on the substrate and the orthographic projection of the second electrode plate C3b of the output reset capacitor C3 on the substrate. The first conductive connection portion F1 is coupled to the second electrode plate C3b of the output reset capacitor C3 through a fifth via H5 provided in the fifth overlapping area.

[0373] In a specific implementation, the at least one shift register unit may further include a first transistor;

[0374] The first transistor includes a first active pattern, and the first active pattern extends along a second direction;

[0375] The first transistor is located on a side of the output circuit away from the display area.

[0376] like Figure 1 、 Figures 3A to 9 As shown, the at least one shift register unit may further include a first transistor T1;

[0377] The first transistor T1 includes a first active pattern A1, and the first active pattern A1 extends along a second direction;

[0378] The first transistor T1 is located on a side of the output circuit O1 away from the display area.

[0379] In at least one embodiment of the present invention, the first active pattern A1 in T1 is arranged to extend along the second direction, so that T2 and T8 can be arranged more compactly, saving lateral space.

[0380] like Figures 3A to 9 As shown, the first transistor T1 includes a first active pattern A1, and the first active pattern A1 includes a first third conductive portion A11, a third channel portion A10 and a second third conductive portion A12 sequentially arranged along the second direction;

[0381] The first third conductive portion A11 is multiplexed as the first electrode S1 of the first transistor T1, and the second third conductive portion A12 is multiplexed as the second electrode D1 of the first transistor T1;

[0382] The first electrode S1 of the first transistor T1 is coupled to the second conductive connection portion F2 through a first connection via H11. A sixth overlapping region exists between an orthographic projection of the second conductive connection portion F2 on the substrate and an orthographic projection of the second electrode plate C2b of the output capacitor C2 on the substrate. The second conductive connection portion F2 is coupled to the second electrode plate C2b of the output capacitor C2 through a sixth via H6 provided in the sixth overlapping region.

[0383] The second electrode D1 of T1 is coupled to the third conductive connection portion F3 through the second connection via H21. There is a seventh overlapping region between the orthographic projection of the third conductive connection portion F3 on the substrate and the orthographic projection of the second electrode plate C1b of C1 on the substrate. F3 is coupled to the second electrode plate C1b of C1 through a seventh via H7 provided in the seventh overlapping region.

[0384] The gate G1 of T1 is coupled to the first plate C1 a of C1 , and the gate G1 of T1 is also coupled to the gate G8 of T8 .

[0385] like Figure 3AAs shown, the width of the portion of the output capacitor C2 between T4 and T10 in the second direction is narrowed, and the width of the portion of the output capacitor C2 between T7 and T10 in the second direction is also narrowed, so as to save space in the second direction for the layout of other devices. Figure 3A As shown, the length of the electrode plate of C2 in the first direction is also lengthened to ensure the area of ​​the electrode plate of C2.

[0386] In at least one embodiment of the present invention, Figure 1 、 Figure 3A-Figure 9 As shown, the at least one shift register unit may further include a second transistor T2 and a third transistor T3;

[0387] a maximum distance in the second direction between an orthographic projection of the gate G2 of the second transistor T2 on the substrate and an orthographic projection of the gate G3 of the third transistor T3 on the substrate is a third predetermined distance;

[0388] The second transistor T2 and the third transistor T3 are located on a side of the output circuit away from the display area;

[0389] The second electrode D2 of the second transistor T2 is coupled to the second electrode D3 of the third transistor T3.

[0390] In at least one embodiment of the present invention, the third predetermined distance may be greater than or equal to 14 um and less than or equal to 50 um, but is not limited thereto.

[0391] In a specific implementation, the second electrode D2 of the second transistor T2 is coupled to the second electrode D2 of the third transistor T3. Therefore, for the convenience of wiring, it is necessary to set T2 and T3 closer, and setting T2 and T3 closer can help narrow the width of the shift register unit in the second direction.

[0392] In at least one embodiment of the present invention, the maximum distance in the second direction between the orthographic projection of the gate G2 of the second transistor T2 and the orthographic projection of the gate G3 of the third transistor T3 on the substrate is less than the third predetermined distance, which means: the maximum distance in the second direction between the edge of the orthographic projection of G2 on the substrate and the edge of the orthographic projection of G3 on the substrate.

[0393] like Figure 3A-Figure 9 As shown, the second transistor T2 includes a second active pattern;

[0394] The second active pattern A2 includes a first fourth conductive portion A21, a fourth channel portion A20 and a second fourth conductive portion A22 sequentially arranged along the first direction;

[0395] The first fourth conductive portion A21 is multiplexed as the first electrode S2 of the second transistor T2, and the second fourth conductive portion A22 is multiplexed as the second electrode D2 of the second transistor T2;

[0396] The first electrode S2 of the second transistor T2 is coupled to the third conductive connection portion F3 via a third connection via H31. A seventh overlapping region exists between the orthographic projection of the third conductive connection portion F3 on the substrate and the orthographic projection of the second electrode plate C1b of C1 on the substrate. F3 is coupled to the second electrode plate C1b of C1 via a seventh via H7 provided in the seventh overlapping region, thereby coupling the first electrode S2 of the second transistor T2 to the second electrode plate C1b of C1.

[0397] The second electrode D2 of the second transistor T2 is coupled to the fourth conductive connection portion F4 through the fourth connection via H41;

[0398] The third transistor T3 includes a third active pattern A3;

[0399] The third active pattern A3 includes a first fifth conductive portion A31, a fifth channel portion A30 and a second fifth conductive portion A32 sequentially arranged along the second direction;

[0400] The first fifth conductive portion A31 is multiplexed as the first electrode S3 of the third transistor T3, and the second fifth conductive portion A32 is multiplexed as the second electrode D3 of the third transistor T3;

[0401] The first electrode S3 of the third transistor T3 is coupled to S91, S92 and S93 respectively through the fifth connection via H51;

[0402] The second electrode D3 of the third transistor T3 is coupled to the fourth conductive connection portion F4 through the sixth connection via H61.

[0403] Optionally, the at least one shift register unit may further include a first transistor, a second transistor and a first capacitor, wherein:

[0404] The second electrode of the first transistor and the first electrode of the second transistor are respectively coupled to the second plate of the first capacitor, and the gate of the first transistor is coupled to the first plate of the first capacitor;

[0405] The first transistor, the first capacitor and the second transistor are arranged in sequence along a first direction;

[0406] The first transistor, the first capacitor, and the second transistor are located on a side of the output circuit away from a display area.

[0407] like Figure 1 、 Figures 3A to 9As shown, the at least one shift register unit may further include a first transistor T1, a second transistor T2 and a first capacitor C1, wherein:

[0408] The second electrode D1 of the first transistor T1 and the first electrode D2 of the second transistor T2 are respectively coupled to the second plate C1b of the first capacitor C1, and the gate G1 of the first transistor T1 is coupled to the first plate C1a of the first capacitor C1;

[0409] The first transistor T1, the first capacitor C1 and the second transistor T2 are arranged in sequence along a first direction;

[0410] The first transistor T1 , the first capacitor C1 , and the second transistor T2 are located on a side of the output circuit O1 away from the display area.

[0411] In at least one embodiment of the present invention, C1 is located between T1 and T2, and the arrangement of T1, T2 and T3 matches the shape of the electrode plate of C1, so that T1, T2, T3 and C1 are arranged more compactly. Figure 3A-Figure 9 As shown, the scan driving circuit may further include a first voltage signal line VGH, and the at least one shift register unit may further include an output reset capacitor C3; a first plate C3a of the output reset capacitor C3 is coupled to the gate G9 of the output reset transistor T9, and a second plate C3b of the output reset capacitor C3 is coupled to the first voltage signal line VGH;

[0412] The maximum width of the second electrode plate C3b of the output reset capacitor C3 in the second direction is a first predetermined width, and the maximum length of the second electrode plate C3b of the output reset capacitor C3 in the first direction is a second predetermined length;

[0413] The output reset capacitor C3 is located on a side of the output circuit O1 away from the display area;

[0414] The orthographic projection of the second electrode plate C3b of the output reset capacitor C3 on the substrate is within the orthographic projection of the first electrode plate C3a of the output reset capacitor C3 on the substrate.

[0415] In at least one embodiment of the present invention, the first predetermined width may be greater than or equal to 3 um and less than or equal to 60 um, and the second predetermined length may be greater than or equal to 3 um and less than or equal to 20 um, but the present invention is not limited thereto.

[0416] Optional, such as Figure 3A As shown, the first voltage signal line VGH extends along a first direction, and the first voltage signal line VGH is located on a side of the output reset capacitor C3 away from the display area.

[0417] In at least one embodiment of the present invention, the width of the second plate C3b of C3 in the second direction is set to be smaller to narrow the width of the shift register unit in the second direction; and in order to ensure the area of ​​the plate of C3, the length of the second plate C3b of C3 in the first direction is set to be larger.

[0418] like Figures 3A to 9 As shown, the first plate C3a of C3 is coupled to the gate G9 of T9.

[0419] An eighth overlapping region exists between an orthographic projection of the first electrode C3a of the transistor C3 on the substrate and an orthographic projection of the fourth conductive connection portion F4 on the substrate. The transistor C3a is coupled to the fourth conductive connection portion F4 via an eighth via H8 provided in the eighth overlapping region, thereby coupling the transistor C3a to the second electrode D2 of the second transistor T2.

[0420] S91, S92 and S93 are respectively coupled to the first conductive connection portion F1, and the first conductive connection portion F1 is coupled to the first voltage signal line VGH;

[0421] There is a fifth overlapping area between the orthographic projection of the first conductive connection portion F1 on the substrate and the orthographic projection of the second plate C3b of the output reset capacitor C3 on the substrate. The first conductive connection portion F1 is coupled to the second plate C3b of the output reset capacitor C3 through a fifth via H5 provided in the fifth overlapping area, so that C3b is coupled to S91, S92 and S93 respectively.

[0422] In at least one embodiment of the present invention, Figures 3A to 9 As shown, the output transistor T10 and the output reset transistor T9 are arranged along the first direction; the scan driving circuit further includes a second voltage signal line VGL; and the at least one shift register unit further includes an output reset capacitor C3;

[0423] The second plate C3b of the output reset capacitor C3 is coupled to the first voltage signal line VGH;

[0424] The first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL, and the first electrode S9 of the output reset transistor T9 is coupled to the second electrode plate C3b of the output reset capacitor C3;

[0425] The output transistor T10 and the output reset transistor T9 are located on a side of the second voltage signal line VGL away from the display area.

[0426] Optionally, the scan driving circuit may further include a second voltage signal line; the at least one shift register unit may further include a fourth transistor;

[0427] The second voltage signal line is coupled to the electrode conductive connection portion, and the electrode conductive connection portion extends along the second direction; the at least one first electrode pattern is arranged in sequence along the first direction;

[0428] The electrode conductive connection portion is coupled to a first first electrode pattern included in the first electrode of the output transistor;

[0429] The first electrode of the fourth transistor is coupled to the electrode conductive connection portion;

[0430] A minimum distance in the first direction between an orthographic projection of the gate of the fourth transistor on the substrate and an orthographic projection of the electrode conductive connection portion on the substrate is a fourth predetermined distance.

[0431] In at least one embodiment of the present invention, the minimum distance in the first direction between the orthographic projection of the gate of the fourth transistor on the substrate and the orthographic projection of the electrode conductive connection portion on the substrate refers to: the minimum distance in the first direction between the edge of the orthographic projection of the gate of the fourth transistor on the substrate and the edge of the orthographic projection of the electrode conductive connection portion on the substrate.

[0432] In at least one embodiment of the present invention, the fourth predetermined distance may be greater than or equal to 1 um and less than or equal to 5 um, but is not limited thereto.

[0433] In at least one embodiment of the present invention, while the output active length is increased, the fourth transistor is moved upward, and the distance between the gate of the fourth transistor and the electrode conductive connection portion in the first direction is kept small, so that the space in the first direction that is extra due to the increase in the output active length can be used to layout other devices included in the shift register unit except the output circuit, thereby narrowing the width of the shift register unit in the second direction.

[0434] like Figures 3A to 9 As shown, the scan driving circuit may further include a second voltage signal line VGL; the at least one shift register unit may further include a fourth transistor T4;

[0435] The second voltage signal line VGL is coupled to the electrode conductive connection portion F01, and the electrode conductive connection portion F01 extends along the second direction; the first electrode S10 of the output transistor T10 includes a first first electrode pattern S101, a second first electrode pattern S102, and a third first electrode pattern S103 arranged in sequence along the first direction;

[0436] The electrode conductive connection portion F01 is coupled to the first first electrode pattern S101;

[0437] The first electrode S4 of the fourth transistor T4 is coupled to the electrode conductive connection portion F01 through the electrode connection via H0;

[0438] The minimum distance in the first direction between the orthographic projection of the gate G4 of the fourth transistor T4 on the substrate and the orthographic projection of the electrode conductive connection portion F01 on the substrate is a fourth predetermined distance, so that T4 moves up while S101 moves up.

[0439] like Figure 5 As shown, the fourth transistor T4 includes a fourth active pattern A4;

[0440] The fourth active pattern A4 includes a first sixth conductive portion A41, a sixth channel portion A40 and a second sixth conductive portion A42 sequentially arranged along the first direction;

[0441] The first sixth conductive portion A41 is multiplexed as the first electrode S4 of the fourth transistor T4 , and the second sixth conductive portion A42 is multiplexed as the second electrode D4 of the fourth transistor T4 .

[0442] In at least one embodiment of the present invention, the at least one shift register unit may further include a fourth transistor and a fifth transistor;

[0443] The gate of the fourth transistor is coupled to the gate of the fifth transistor;

[0444] The gate of the fourth transistor and the gate of the fifth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along a second direction.

[0445] In a specific implementation, the fourth transistor and the fifth transistor may be arranged side by side, and when the fourth transistor moves up, the fifth transistor also moves up.

[0446] Optionally, the scan driving circuit may further include a first clock signal line, and the gate of the fifth transistor is coupled to the first clock signal line;

[0447] The first clock signal line extends along a first direction, and the first clock signal line is located on a side of the five transistors away from the display area.

[0448] like Figure 1 、 Figure 3A-Figure 9 As shown, the at least one shift register unit may further include a fourth transistor T4 and a fifth transistor T5; the scan driving circuit may further include a first clock signal line CK,

[0449] The gate G4 of the fourth transistor T4 is coupled to the gate G5 of the fifth transistor T5;

[0450] The gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5 are included in a first gate metal pattern 45, and the first gate metal pattern 45 extends along the second direction;

[0451] The gate G5 of the fifth transistor T5 is coupled to the first clock signal line CK;

[0452] The first clock signal line CK extends along a first direction. The first clock signal line CK is located on a side of the five transistors T5 away from the display area.

[0453] like Figure 3A-Figure 9 As shown, there is a ninth overlapping region between the orthographic projection of the first gate metal pattern 45 on the substrate and the orthographic projection of the first clock signal line CK on the substrate, and the first gate metal pattern 45 is coupled to the first clock signal line CK through a ninth via H9 provided in the ninth overlapping region;

[0454] The first electrode S5 of T5 is coupled to the input signal terminal E1 through the seventh connection via H71.

[0455] like Figure 5 As shown, the fifth transistor T5 includes a fifth active pattern A5;

[0456] The fifth active pattern A5 includes a first seventh conductive portion A51, a seventh channel portion A50 and a second seventh conductive portion A52 sequentially arranged along the first direction;

[0457] The first seventh conductive portion A51 is multiplexed as the first electrode S5 of the fifth transistor T5 , and the second seventh conductive portion A52 is multiplexed as the second electrode D5 of the fifth transistor T5 .

[0458] In specific implementation, Figure 1 、 Figure 3A-Figure 9 As shown, the at least one shift register unit may further include a first transistor T1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and an output capacitor C2;

[0459] The second electrode D5 of the fifth transistor T5 is coupled to the gate G6 of the sixth transistor T6; the first electrode S1 of the fifth transistor T5 is coupled to the input signal terminal E1;

[0460] The gate G6 of the sixth transistor T6 includes a first gate pattern g61 and a second gate pattern g62 coupled to each other;

[0461] The first gate pattern g61 and the second gate pattern g62 are respectively coupled to the first plate C2a of the output capacitor C2, and the first plate C2a of the output capacitor C2 is coupled to the gate S10 of the output transistor T10;

[0462] A first electrode S6 of the sixth transistor T6 is coupled to the gate G4 of the fourth transistor T4, a second electrode D6 of the sixth transistor T6 is coupled to the second electrode D4 of the fourth transistor T4, and a second plate C2b of the output capacitor C2 is coupled to the first electrode S1 of the first transistor T1;

[0463] The fourth transistor T4, the sixth transistor T6 and the first transistor T1 are arranged in sequence along the first direction;

[0464] The fifth transistor T5, the sixth transistor T6 and the first transistor T1 are arranged in sequence along the first direction;

[0465] The output capacitor C2 is located between the sixth transistor T6 and the output circuit O1.

[0466] like Figure 5 As shown, the sixth transistor T6 includes a sixth active pattern A6;

[0467] The sixth active pattern A6 includes a first eighth conductive portion A61, a first eighth channel portion A601, a second eighth conductive portion A62, a second eighth channel portion A602 and a third eighth conductive portion A63 arranged in sequence along the first direction;

[0468] The first eighth conductive portion A61 is multiplexed as the first electrode S6 of the sixth transistor T6 , and the third eighth conductive portion A63 is multiplexed as the second electrode D6 of the sixth transistor T6 .

[0469] like Figure 3A-Figure 9 As shown, the gate of T6 is included in the second gate metal pattern 60, and the second gate metal pattern 60 is U-shaped, so that the gate of T6 includes a first gate pattern g61 and a second gate pattern g62 coupled to each other;

[0470] The second gate metal pattern 60 is coupled to the fifth conductive connection portion F5 through the eighth connection via H81;

[0471] The second electrode D5 of T5 is coupled to the fifth conductive connection portion F5 through the ninth connection via H91, so that the second electrode D5 of T5 is coupled to the gate of T6, including the first gate pattern g61 and the second gate pattern g62 coupled to each other;

[0472] The first electrode S6 of T6 is coupled to the sixth conductive connection portion F6 through the tenth connection via H101, and the first gate metal pattern 45 is coupled to the sixth conductive connection portion F6 through the eleventh connection via H111;

[0473] The second electrode D6 of T6 is coupled to the seventh conductive connection portion F7 through the twelfth connection via H121 , and the second electrode D4 of T4 is coupled to the seventh conductive connection portion F7 through the thirteenth connection via H131 , so that the second electrode D6 of T6 is coupled to the second electrode D4 of T4 .

[0474] In at least one embodiment of the present invention, Figure 1 、 Figures 3A to 9 As shown, the at least one shift register unit may further include a second transistor T2, a first transistor T1, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, wherein:

[0475] like Figure 5 As shown, the active layer of the seventh transistor T7 and the active layer of the eighth transistor T8 may be formed by a continuous second semiconductor layer 20, and the second semiconductor layer 20 extends along the first direction;

[0476] The active layer of the seventh transistor T7 includes a first ninth conductive portion 211, a ninth channel portion 201 and a second ninth conductive portion 212 sequentially arranged along the first direction;

[0477] The second ninth conductive portion 212 is multiplexed as the first tenth conductive portion;

[0478] The active layer of the eighth transistor T8 includes a first tenth conductive portion, a tenth channel portion 202 and a second tenth conductive portion 222 sequentially arranged along the first direction;

[0479] The first ninth conductive portion 211 is used as the second electrode D7 of the seventh transistor T7, the second ninth conductive portion 212 is used as the first electrode S7 of the seventh transistor T7, the second tenth conductive portion 222 is used as the first electrode S8 of the eighth transistor T8, and the first electrode S7 of the seventh transistor T7 is multiplexed as the second electrode D8 of the eighth transistor T8;

[0480] A gate G7 of the seventh transistor T7 is coupled to the second plate C2b of the output capacitor C2, and a second electrode D7 of the seventh transistor T7 is coupled to the gate G6 of the sixth transistor T6;

[0481] A gate G8 of the eighth transistor T8 is coupled to the gate G1 of the first transistor T1 , and a first electrode S8 of the eighth transistor T8 is coupled to a first voltage signal line VGH;

[0482] The first voltage signal line VGH extends along a first direction;

[0483] The sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , and the second transistor T2 are sequentially arranged along a first direction.

[0484] In at least one embodiment of the present invention, as the output active length increases, T5, T4, T6, T7 and T8 are all moved upward, utilizing the extra space in the first direction and narrowing the width of the shift register unit in the second direction.

[0485] Furthermore, the first electrode S7 of the seventh transistor T7 is reused as the second electrode D8 of the eighth transistor T8. That is, in the display substrate described in at least one embodiment of the present invention, the seventh transistor T7 and the eighth transistor T8 can be directly coupled through the second ninth conductive portion 212 included in the second semiconductor layer 20, thereby reducing the area occupied by T7 and T8 in the first direction.

[0486] Optional, such as Figure 1 、 Figure 3A-Figure 9 As shown, the scan driving circuit may further include a second clock signal line CB, and the gate G2 of the second transistor T2 and the gate G7 of the seventh transistor T7 are respectively coupled to the second clock signal line CB;

[0487] The second clock signal line CB extends along a first direction. The second clock signal line CB is located on a side of the second transistor T2 away from the display area.

[0488] like Figure 3A-Figure 9 As shown, the second electrode D7 of T7 is coupled to the fifth conductive connection portion F5 through the fourteenth connection via H141, so that the second electrode D7 of T7 is coupled to the gate G6 of T6;

[0489] The gate G7 of T7 is coupled to the eighth conductive connection portion F8 and the ninth conductive connection portion F9 respectively;

[0490] F8 is coupled to the second clock signal line CB through the fifteenth connecting via H151;

[0491] F9 is coupled to the second conductive connection portion F2 through the sixteenth connecting via H161, so that the gate G7 of T7 is coupled to the second electrode plate C2b of C2;

[0492] The first electrode S8 of T8 is coupled to the first voltage signal line VGH through the seventeenth connection via H171;

[0493] The gate G8 of T8 is coupled to the gate G1 of T1 and the first plate C1 a of C1 , respectively.

[0494] like Figure 3A-Figure 9As shown, the gate G2 of T2 is coupled to the tenth conductive connection portion F10 , and the tenth conductive connection portion F10 is coupled to the second clock signal line CB through the eighteenth connection via 181 .

[0495] like Figure 6 As shown, the gate G3 of T3 can be coupled to the first plate C2 a of the output capacitor C2 through the eleventh conductive connection portion F11 .

[0496] like Figure 9 As shown, G8 is coupled to the twelfth conductive connection portion F12 through the nineteenth connection via H191 , and the twelfth conductive connection portion F12 is coupled to the second electrode D6 of T6 through the twelfth connection via H121 .

[0497] Optionally, the scan driving circuit may further include a second voltage signal line and a signal output line;

[0498] The signal output line includes a first output line portion and at least one second output line portion;

[0499] The second voltage signal line and the first output line portion both extend along a first direction, and the first output line portion is located between the second voltage signal line and the output circuit;

[0500] The second output line portion extends along a second direction;

[0501] The second output line portion is used to provide a light emitting control signal to the pixel circuit in the display area;

[0502] The first output line portion and the output circuit are located on a side of the second voltage signal line away from the display area.

[0503] In such Figure 3A In the layout shown, the signal output line includes two second output line parts. In a specific implementation, the number of the second output line parts included in the signal output line can be selected according to actual conditions.

[0504] In a specific implementation, the scan driving circuit may further include a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line;

[0505] The first voltage signal line, the second voltage signal line, the first clock signal line and the second clock signal line all extend along a first direction;

[0506] The orthographic projection of the first voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate, and the orthographic projection of the second clock signal line on the substrate are all located on a side of the orthographic projection of the shift register unit on the substrate away from the display area;

[0507] The orthographic projection of the second voltage signal line on the substrate is located on a side of the shift register unit close to the display area.

[0508] In at least one embodiment of the present invention, the signal output line may further include at least one second output line portion, which is coupled to the first output line portion; the second output line portion extends to the display area and is used to provide a light-emitting control signal to the pixel circuit located in the display area.

[0509] Specifically, the specific positions of the first clock signal line, the second clock signal line and the first voltage signal line can be set according to actual needs. For example, the first clock signal line, the second clock signal line and the first voltage signal line can all be set at the edge of the display substrate, so that the orthographic projection of the first voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate and the orthographic projection of the second clock signal line on the substrate are all located on the side of the orthographic projection of the shift register unit on the substrate away from the display area of ​​the display substrate. In this way, when laying out the shift register unit, it is possible to avoid excessive overlap between the transistors in the shift register unit and the first clock signal line, the second clock signal line and the first voltage signal line, which is more conducive to improving the working performance of the shift register unit.

[0510] In addition, by arranging the first clock signal line, the second clock signal line, and the first voltage signal line to extend along the first direction, it is more conducive to achieving a narrow frame of the display substrate.

[0511] In at least one embodiment of the present invention, the phases of the first clock signal output by the first clock signal line and the second clock signal output by the second clock signal line may be opposite, but the present invention is not limited thereto.

[0512] In specific implementation, Figure 1 and Figure 3A As shown, the scan driving circuit may include a first voltage signal line VGH, a second voltage signal line VGL, a first clock signal line CK, a second clock signal line CB, and a signal output line; the at least one shift register unit may include a first capacitor C1, an output capacitor C2, an output reset capacitor C3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, an output reset transistor T9, and an output transistor T10;

[0513] The signal output line includes a first output line portion E01, a first second output line portion E021 and a second second output line portion E022;

[0514] The first output line portion E01, the first second output line portion E021 and the second second output line portion E022 are coupled to each other;

[0515] The first output line portion E01 extends along a first direction, and the first second output line portion E021 and the second second output line portion E022 are coupled to each other and extend along a second direction;

[0516] The output transistor T10 and the output reset transistor T9 are arranged along a first direction;

[0517] The gate G10 of the output transistor T10 is coupled to the first plate C2a of the output capacitor C2, the first electrode S10 of the output transistor T10 is coupled to the second voltage signal line VGL, and the second electrode D10 of the output transistor T10 is coupled to the first output line portion E01;

[0518] The gate G9 of the output reset transistor T9 is coupled to the first plate C3a of the output reset capacitor C3, the first electrode S9 of the output reset transistor T9 is coupled to the second plate C3b of the output reset capacitor C3, and the second electrode D9 of the output reset transistor T9 is coupled to the first output line portion E01;

[0519] The second plate C3b of the output reset capacitor C3 is coupled to the first voltage signal line VGH; the second plate C2b of the output capacitor C2 is coupled to the gate G7 of the seventh transistor T7;

[0520] The first electrode S1 of the first transistor T1 is coupled to the second plate C2b of the output capacitor C2, the second electrode D1 of the first transistor T1 and the first electrode D2 of the second transistor T2 are respectively coupled to the second plate C1b of the first capacitor C1, and the gate G1 of the first transistor T1 is coupled to the first plate C1a of the first capacitor C1;

[0521] The gate G2 of the second transistor T2 and the gate G7 of the seventh transistor T7 are respectively coupled to the second clock signal line CB, and the second electrode D2 of the second transistor T2 is coupled to the second electrode D3 of the third transistor T3;

[0522] The gate G3 of the third transistor T3 is coupled to the gate G10 of the output transistor T10, and the first electrode S3 of the third transistor T3 is coupled to the first plate C3a of the output reset capacitor C3;

[0523] A gate G4 of the fourth transistor T4 is coupled to a gate G5 of the fifth transistor T5, a first electrode S4 of the fourth transistor T4 is coupled to a first electrode S10 of the output transistor T10, and a second electrode D4 of the fourth transistor T4 is coupled to a second electrode D6 of the sixth transistor T6;

[0524] A gate electrode G5 of the fifth transistor T5 is coupled to the first clock signal line CK, a second electrode D5 of the fifth transistor T5 is coupled to a gate electrode G6 of the sixth transistor T6; a first electrode S5 of the fifth transistor T5 is coupled to an input signal terminal E1;

[0525] A first electrode S6 of the sixth transistor T6 is coupled to the gate G4 of the fourth transistor T4, and a second electrode D6 of the sixth transistor T6 is coupled to the second electrode D4 of the fourth transistor T4;

[0526] The gate G7 of the seventh transistor T7 is coupled to the second plate C2b of the output capacitor C2, the first electrode S7 of the seventh transistor T7 is multiplexed as the second electrode D8 of the eighth transistor G8, and the second electrode D7 of the seventh transistor T7 is coupled to the gate G6 of the sixth transistor G6;

[0527] A gate G8 of the eighth transistor T8 is coupled to the gate G1 of the first transistor T1 , and a first electrode S8 of the eighth transistor T8 is coupled to a first voltage signal line VGH;

[0528] The first second output line portion E021 is coupled to the first output line portion E01; the first second output line portion E021 extends to the display area, and is used to provide a light emitting control signal to a pixel circuit located in the display area;

[0529] The second second output line portion E022 is coupled to the first output line portion E01 ; the second second output line portion E022 extends to the display area and is used to provide a light emitting control signal to the pixel circuit located in the display area.

[0530] In a specific implementation, the second voltage signal line may be arranged on a side of the shift register unit close to the display area;

[0531] The first voltage signal line, the first clock signal line and the second clock signal line are arranged on a side of the shift register unit away from the display area;

[0532] Along the direction close to the display area, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence; or, along the direction close to the display area, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence.

[0533] In at least one embodiment of the present invention, the scan driving circuit may further include a first start signal line and a second start signal line;

[0534] Along a direction close to the display area, the second start signal line, the first start signal line, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence;

[0535] Along a direction close to the display area, the first start signal line, the second start signal line, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence;

[0536] Along a direction close to the display area, the second start signal line, the first start signal line, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence;

[0537] Along a direction close to the display area, the first start signal line, the second start signal line, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence.

[0538] like Figure 3B As shown, in Figure 3A Based on at least one embodiment of the shift register unit shown, at least one embodiment of the shift register unit may further include a first start signal line E11 and a second start signal line E12;

[0539] The first start signal line E11 and the second start signal line E12 may both extend along a first direction;

[0540] like Figure 3B As shown, along the direction close to the display area, E12, E11, CB, CK, and VGH are arranged in sequence.

[0541] In actual operation, the positions of E11 and E12 can be interchanged, that is, along the direction close to the display area, E11, E12, CB, CK, and VGH are arranged in sequence.

[0542] Optional, such as Figure 3AAs shown, the output transistor T10 and the output reset transistor T9 may be located between the output capacitor C2 and the first output line portion E01; along the first direction, the output transistor T10 and the output reset transistor T9 are arranged in sequence;

[0543] a first capacitor C1, an output capacitor C2, an output reset capacitor C3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8;

[0544] Along the first direction, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first transistor T1, the first capacitor C1, the second transistor T2 and the output reset transistor T9 are arranged in sequence;

[0545] The fifth transistor T5, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are located between the output capacitor C2 and the first voltage signal line VGH;

[0546] The gate G5 of the fifth transistor T5 and the gate G4 of the fourth transistor T4 are included in a first gate metal pattern, and the first gate metal pattern extends along the second direction.

[0547] In at least one embodiment of the present invention, the display substrate may further include a plurality of rows of pixel circuits disposed on the base; the pixel circuits may include light emitting control terminals;

[0548] The shift register unit corresponds to at least one row of pixel circuits;

[0549] The signal output line of the shift register unit is coupled to the light emitting control terminal of the at least one row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control terminal of the at least one row of pixel circuits.

[0550] exist Figure 3A In the layout shown, Figure 5 As shown ( Figure 5 yes Figure 3A Schematic diagram of the active layer in the first semiconductor layer 10), the length of the first semiconductor layer 10 in the first direction is the output active length L1, and the minimum width of the first semiconductor layer 10 in the second direction is the output active width W1;

[0551] The output active length L1 is a first predetermined length;

[0552] The ratio of the output active length L1 to the output active width W1 is within a predetermined ratio range;

[0553] The output active width W1 is within a predetermined width range;

[0554] In the present invention Figure 3A In the layout shown, the output active length L1 is increased so that the devices other than the output circuit in the shift register unit can utilize the extra vertical space due to the increase in L1 for layout, thereby narrowing the horizontal space occupied by the shift register unit; and at least one embodiment of the present invention can reduce the output active width W1, so that the devices other than the output circuit in the shift register unit can utilize the saved horizontal space for layout, and also narrow the horizontal space occupied by the shift register unit.

[0555] In the present invention Figure 3A In the layout shown, T5, T4, T6, T7, and T8 are moved up to utilize the extra space in the vertical direction for layout, thereby narrowing the space occupied by the shift register unit in the horizontal direction;

[0556] In the present invention Figure 3A In the layout shown, the active pattern of T1 is changed to a horizontal arrangement, so that T2 and T3 can be more compact, and the arrangement of T1, T2, and T3 is more consistent with the shape of the plate of C1;

[0557] In the present invention Figure 3A In the layout shown, the shapes of the first plate of C3 and the second plate of C3 are changed, and the width of the plate of C3 in the second direction is narrowed, so as to facilitate the compact arrangement of the shift register units in the horizontal direction.

[0558] In the present invention Figure 3A In the layout shown, Figure 3A and Figure 8 As shown, the first output line portion E01 is coupled to the second electrode D10 of the output transistor T10 through a plurality of first signal line vias H01 provided in the signal line overlapping region, and the first output line portion E01 is coupled to the second electrode D9 of the output reset transistor T9 through a plurality of second signal line vias H02 provided in the signal line overlapping region; the plurality of first signal line vias H01 are sequentially arranged along the first direction, and the plurality of second signal line vias H02 are sequentially arranged along the first direction;

[0559] like Figure 4 and Figure 10 ( Figure 10 yes Figure 3A Schematic diagram of the source and drain metal layers in Figure 10As shown in the figure, the signal line overlapping area includes a first signal line overlapping area A01 and a second signal line overlapping area A02. The first signal line overlapping area A01 is an overlapping area of ​​the orthographic projection of the first output line portion E01 on the substrate and the orthographic projection of the first source-drain metal pattern Ds1 on the substrate, in which the second electrode D10 of the output transistor T10 is included. The second signal line overlapping area A02 is an overlapping area of ​​the orthographic projection of the first output line portion E01 on the substrate and the orthographic projection of the second source-drain metal pattern Ds2 on the substrate, in which the second electrode D9 of the output reset transistor T9 is included.

[0560] like Figure 4 As shown, the ratio of the maximum distance K1 in the first direction between the first first signal line via and the last first signal line via arranged sequentially along the first direction to the third length L3 is a third predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance; the third length L3 is the length of the first signal line overlapping area A01 in the first direction;

[0561] The ratio of the maximum distance K2 in the first direction between the first second signal line via and the last second signal line via arranged sequentially along the first direction to the fourth length L4 is a fourth predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance; the fourth length L4 is the length of the second signal line overlapping area A02 in the first direction.

[0562] In at least one embodiment of the present invention, the number of the first signal line via holes and the number of the second signal line via holes can be selected according to actual conditions.

[0563] like Figure 3A 、 Figure 4 and Figure 10 As shown, since the active layers of T10 and T9 are longitudinally stretched, the third length L3 and the fourth length L4 are correspondingly lengthened, so that the plurality of first signal line vias H01 can be evenly arranged in the first signal line overlapping area A01, and the ratio of the maximum distance K1 between the first first signal line via from top to bottom and the last first signal line via from top to bottom in the first direction to the third length L3 is a third predetermined ratio. The plurality of first signal line vias H01 can cover the first signal line overlapping area A01 as much as possible, so that the second electrode D10 of the output transistor T10 can be better coupled to E01.

[0564] like Figure 3A 、 Figure 4 and Figure 10As shown, since the active layer of T10 and the active layer of T9 are longitudinally stretched, the third length L3 and the fourth length L4 are correspondingly lengthened, so that the multiple second signal line vias H02 can be evenly arranged in the second signal line overlapping area A02, and the ratio of the maximum distance K2 in the first direction between the first second signal line via from top to bottom and the last second signal line via from top to bottom to the fourth length L4 is a fourth predetermined ratio. The multiple second signal line vias H02 can cover the second signal line overlapping area A02 as much as possible, so that the second electrode D9 of the output reset transistor T9 can be better coupled to E01.

[0565] In at least one embodiment of the present invention, Figure 5 The semiconductor layer shown and Figure 6 A first gate insulating layer may also be provided between the first gate metal layers shown in FIG. Figure 6 The first gate metal layer shown and Figure 7 A second gate insulating layer may also be provided between the second gate metal layers shown in FIG. Figure 7 The second gate metal layer shown and Figure 9 An insulating layer may also be included between the source and drain metal layers shown.

[0566] When manufacturing the display substrate according to at least one embodiment of the present invention, a semiconductor material layer is first provided on a substrate, and the semiconductor material layer is patterned to form an active layer of each transistor; Figure 5 As shown, a first semiconductor layer 10, a second semiconductor layer 20, a first active pattern A1, a second active pattern A2, a third active pattern A3, a fourth active pattern A4, a fifth active pattern A5 and a sixth active pattern A6 are formed;

[0567] forming a first gate insulating layer on a side of the active layer facing away from the substrate;

[0568] A first gate metal layer is formed on the side of the first gate insulating layer facing away from the active layer, and a patterning process is performed on the first gate metal layer, such as Figure 6 As shown, the gates of the transistors, the first plate C3a of the output reset capacitor C3, the first plate C1a of the first capacitor C1 and the first plate C2a of the output capacitor C2, which form the shift register unit;

[0569] Using the gates of the transistors as masks, doping portions of the active layer not covered by the gates, so that the portions of the active layer not covered by the gates form conductive portions, and the portions of the active layer covered by the gates form channel portions; the conductive portions function as the first electrode or the second electrode; or the conductive portions are coupled to the first electrode or the second electrode;

[0570] A second gate metal layer is provided on a side of the second gate insulating layer facing away from the first gate metal layer, and a patterning process is performed on the second gate metal layer, such as Figure 7 As shown, a signal output line, an input signal terminal E1, a second plate C3b of the output reset capacitor C3, a second plate C1b of the first capacitor C1 and a first plate C2b of the output capacitor C2 are formed;

[0571] disposing an insulating layer on a side of the second gate metal layer facing away from the second gate insulating layer;

[0572] like Figure 8 As shown, a plurality of via holes are provided on a substrate provided with an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer and an insulating layer;

[0573] A source-drain metal layer is provided on a side of the insulating layer facing away from the second gate metal layer, and a patterning process is performed on the source-drain metal layer, such as Figure 9 As shown, a first voltage signal line VGH, a second voltage signal line VGL, a first clock signal line CK, a second clock signal line CB, the second electrode of the output reset transistor T9, the first electrode of the output reset transistor T9, the second electrode of the output transistor T10, and the first electrode of the output transistor T10 are formed.

[0574] A method for manufacturing a display substrate according to at least one embodiment of the present invention includes manufacturing a scan driving circuit on a substrate; the scan driving circuit includes a plurality of shift register units, at least one of the plurality of shift register units includes an output circuit; the output circuit includes an output transistor and an output reset transistor;

[0575] The method for manufacturing the display substrate further includes:

[0576] Fabricating a semiconductor layer on the substrate, and performing a patterning process on the semiconductor layer to form an active layer of an output transistor and an active layer of an output reset transistor;

[0577] forming a first gate metal layer on a side of the semiconductor layer facing away from the substrate, and patterning the first gate metal layer to form a gate of the output transistor and a gate of the output reset transistor;

[0578] Using the gates of the output transistor and the output reset transistor as masks, doping portions of the semiconductor layer not covered by the gates, so that the portions of the semiconductor layer not covered by the gates form conductive portions, and the portions of the semiconductor layer covered by the gates form channel portions;

[0579] Disposing a second gate metal layer on a side of the first gate metal layer facing away from the semiconductor layer, and patterning the second gate metal layer to form a signal output line; the signal output line includes a first output line portion extending along a first direction;

[0580] Disposing a first insulating layer on a side of the second gate metal layer facing away from the first gate metal layer;

[0581] A plurality of first signal line via holes and a plurality of second signal line via holes are formed in an area where the first insulating layer partially overlaps with the first output line; the first signal line via holes and the second signal line via holes pass through the first insulating layer;

[0582] forming a source-drain metal layer on a side of the first insulating layer facing away from the second gate metal layer, and patterning the source-drain metal layer to form a first source-drain metal pattern and a second source-drain metal pattern, wherein the first source-drain metal pattern includes the second electrode of the output transistor, and the second source-drain metal pattern includes the second electrode of the output reset transistor, so that the first output line portion is coupled to the second electrode of the output transistor through the plurality of first signal line vias, and the first output line portion is coupled to the second electrode of the output reset transistor through the plurality of second signal line vias;

[0583] The signal output line includes a first output line portion extending along a first direction;

[0584] The plurality of first signal line vias are sequentially arranged along the first direction, and the plurality of second signal line vias are sequentially arranged along the first direction;

[0585] The ratio of the maximum distance between any two first signal line vias arranged in sequence along the first direction and the third length is a first predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance;

[0586] The ratio of the maximum distance between any two second signal line vias arranged in sequence along the first direction in the first direction to the fourth length is a second predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance;

[0587] The third length is the length of the first signal line overlapping area in the first direction, and the fourth length is the length of the second signal line overlapping area in the first direction;

[0588] The first predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0589] The first predetermined distance is greater than or equal to 1.5 μm and less than or equal to 45 μm;

[0590] The second predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9;

[0591] The second predetermined distance is greater than or equal to 1.5 um and less than or equal to 65 um.

[0592] At least one embodiment of the present invention increases the output active length so that the devices other than the output circuit in the shift register unit can utilize the extra vertical space due to the increase in the output active length for layout, thereby narrowing the horizontal space occupied by the shift register unit; and at least one embodiment of the present invention reduces the output active width so that the devices other than the output circuit in the shift register unit can utilize the saved horizontal space for layout, thereby narrowing the horizontal space occupied by the shift register unit.

[0593] Optionally, the length of the active layer of the output transistor in the first direction is a first length, the length of the active layer of the output reset transistor in the first direction is a second length, and the sum of the first length and the second length is the output active length;

[0594] The smaller of the minimum width of the active layer of the output transistor along the second direction and the minimum width of the active layer of the output reset transistor along the second direction is the output active width; the first direction intersects the second direction.

[0595] Optionally, the first predetermined length is greater than or equal to 50 μm and less than or equal to 130 μm;

[0596] Optionally, a ratio of the output active length to the output active width is within a predetermined ratio range; the predetermined ratio range may be greater than or equal to 3 and less than or equal to 11.

[0597] In at least one embodiment of the present invention, the output active width may be within a predetermined width range.

[0598] Optionally, the predetermined width range is greater than or equal to 12 um and less than or equal to 45 um.

[0599] The first output line portion is coupled to the second electrode of the output transistor through a plurality of first signal line vias provided in the signal line overlapping region, and the first output line portion is coupled to the second electrode of the output reset transistor through a plurality of second signal line vias provided in the signal line overlapping region; the plurality of first signal line vias are arranged sequentially along a first direction, and the plurality of second signal line vias are arranged sequentially along the first direction;

[0600] The signal line overlapping region includes a first signal line overlapping region and a second signal line overlapping region, the first signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a first source-drain metal pattern included in the second electrode of the output transistor on the substrate, and the second signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a second source-drain metal pattern included in the second electrode of the output reset transistor on the substrate;

[0601] The ratio of the maximum distance between any two first signal line vias arranged sequentially along the first direction in the first direction to the third length is a first predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance; the third length is the length of the overlapping area of ​​the first signal lines in the first direction;

[0602] The ratio of the maximum distance between any two second signal line vias arranged sequentially along the first direction in the first direction to the fourth length is a second predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance; and the fourth length is the length of the overlapping area of ​​the second signal line in the first direction.

[0603] Because the active pattern of the output transistor and the active pattern of the output reset transistor are longitudinally elongated, the third length and the fourth length are correspondingly lengthened, thereby enabling the plurality of first signal line vias to be evenly arranged in the first signal line overlapping region, and the ratio of the maximum distance between any two first signal line vias in the first direction to the third length is a first predetermined ratio. The plurality of first signal line vias can cover the first signal line overlapping region as much as possible, thereby enabling the second electrode of the output transistor to be better coupled to the first output line portion.

[0604] Since the active layer of the output transistor and the active layer of the output reset transistor are longitudinally stretched, the third length and the fourth length are correspondingly lengthened, so that the multiple second signal line vias can be evenly arranged in the second signal line overlapping area, and the ratio of the maximum distance between any two second signal line vias in the first direction to the fourth length is a second predetermined ratio. The multiple second signal line vias can cover the second signal line overlapping area as much as possible, so that the second electrode of the output reset transistor can be better coupled to the first output line portion.

[0605] Optionally, the method for manufacturing a display substrate according to at least one embodiment of the present invention may further include: providing a first transistor on a side of the output transistor away from the display area; the step of manufacturing the first transistor includes:

[0606] A first active pattern of the first transistor is formed while the active layer of the output transistor and the active layer of the output reset transistor are formed. The first active pattern extends along the second direction.

[0607] At least one embodiment of the present invention sets the first active pattern to extend along the second direction, sets the first transistor between the eighth transistor and the first capacitor, and arranges the eighth transistor, the first transistor and the first capacitor in sequence along the first direction, so that the first transistor is set in the space between the eighth transistor and the first capacitor, so that the second transistor and the third transistor can be arranged more compactly (the second electrode of the second transistor is coupled to the second electrode of the third transistor, so for the convenience of wiring, the second transistor and the third transistor also need to be set closer), which can further narrow the width of the shift register unit in the second direction.

[0608] Optionally, the method for manufacturing a display substrate according to at least one embodiment of the present invention may further include: manufacturing a second transistor and a third transistor on a side of the output reset transistor away from the display area;

[0609] The steps of manufacturing the second transistor and the third transistor include:

[0610] forming the gate of the second transistor and the gate of the third transistor simultaneously with forming the gate of the output transistor and the gate of the output reset transistor;

[0611] A maximum distance in the second direction between an orthographic projection of the gate of the second transistor on the substrate and an orthographic projection of the gate of the third transistor on the substrate is a third predetermined distance.

[0612] Optionally, the third predetermined distance is greater than or equal to 14 um and less than or equal to 50 um.

[0613] In a specific implementation, the second electrode of the second transistor is coupled to the second electrode of the third transistor. Therefore, for the convenience of wiring, it is necessary to set the second transistor and the third transistor closer, and setting the second transistor and the third transistor closer can help narrow the width of the shift register unit in the second direction.

[0614] In a specific implementation, the method for manufacturing a display substrate according to at least one embodiment of the present invention may further include manufacturing an output reset capacitor on a side of the output transistor away from the display area; the steps of manufacturing the output reset capacitor include:

[0615] While forming the gate of the output transistor and the gate of the output reset transistor, forming a first plate of the output reset capacitor, wherein the first plate of the output reset capacitor is coupled to the gate of the output reset transistor;

[0616] while forming the signal output line, forming the second electrode plate of the output reset transistor;

[0617] The maximum width of the second plate of the output reset capacitor in the second direction is a first predetermined width, and the maximum length of the second plate of the output reset capacitor in the first direction is a second predetermined length;

[0618] The orthographic projection of the second plate of the output reset capacitor on the substrate is within the orthographic projection of the first plate of the output reset capacitor on the substrate.

[0619] Optionally, the first predetermined width is greater than or equal to 3 μm and less than or equal to 60 μm, and the second predetermined length is greater than or equal to 3 μm and less than or equal to 20 μm. In at least one embodiment of the present invention, the width of the first plate of the output reset capacitor in the second direction and the width of the second plate of the output reset capacitor in the second direction are set to be smaller, and the length of the first plate of the output reset capacitor in the first direction and the length of the second plate of the output reset capacitor in the first direction are set to be larger, so as to narrow the width of the output reset capacitor plate in the second direction while ensuring the area of ​​the output reset capacitor plate.

[0620] In at least one embodiment of the present invention, the signal output line may further include at least one second output line portion, which is coupled to the first output line portion; the second output line portion extends to the display area and is used to provide a light-emitting control signal to the pixel circuit located in the display area.

[0621] A display device according to at least one embodiment of the present invention includes the above-mentioned display substrate.

[0622] Since the display substrate provided in the above embodiment can achieve a narrow frame, the display device provided in the embodiment of the present invention can also achieve the beneficial effect of having a narrow frame when including the above display substrate, which will not be described in detail here.

[0623] The display device provided in at least one embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.

[0624] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar terms used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0625] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0626] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0627] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: The device comprises a scan drive circuit and a display area provided on a substrate; the scan drive circuit comprises a plurality of shift register units, at least one of the plurality of shift register units comprises a signal output line and an output circuit, the output circuit comprises an output transistor and an output reset transistor; The signal output line includes a first output line portion extending along a first direction; The first output line portion is coupled to the second electrode of the output transistor through a plurality of first signal line vias provided in the signal line overlapping region, and the first output line portion is coupled to the second electrode of the output reset transistor through a plurality of second signal line vias provided in the signal line overlapping region; the plurality of first signal line vias are arranged sequentially along a first direction, and the plurality of second signal line vias are arranged sequentially along the first direction; The signal line overlapping region includes a first signal line overlapping region and a second signal line overlapping region, the first signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a first source-drain metal pattern included in the second electrode of the output transistor on the substrate, and the second signal line overlapping region being an overlapping region of an orthographic projection of the first output line portion on the substrate and an orthographic projection of a second source-drain metal pattern included in the second electrode of the output reset transistor on the substrate; The ratio of the maximum distance between any two first signal line vias arranged sequentially along the first direction in the first direction to the third length is a first predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance; the third length is the length of the overlapping area of ​​the first signal lines in the first direction; The ratio of the maximum distance between any two second signal line vias arranged sequentially along the first direction in the first direction to the fourth length is a second predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance; and the fourth length is the length of the overlapping region of the second signal line in the first direction; The first predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9; The first predetermined distance is greater than or equal to 1.5 μm and less than or equal to 45 μm; The second predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9; The second predetermined distance is greater than or equal to 1.5 μm and less than or equal to 65 μm; The active layer of the output transistor and the active layer of the output reset transistor are arranged along a first direction, the length of the active layer of the output transistor in the first direction is a first length, the length of the active layer of the output reset transistor in the first direction is a second length, and the sum of the first length and the second length is the output active length; The smaller of the minimum width of the active layer of the output transistor along the second direction and the minimum width of the active layer of the output reset transistor along the second direction is the output active width; the first direction intersects the second direction; The ratio of the output active length to the output active width is within a predetermined ratio range; the predetermined ratio range is greater than or equal to 3 and less than or equal to 11; and / or, the output active width is within a predetermined width range; the predetermined width range is greater than or equal to 12um and less than or equal to 45um.

2. The display substrate according to claim 1, wherein The active layer of the output transistor and the active layer of the output reset transistor are formed by a continuous first semiconductor layer; the first semiconductor layer extends along a first direction; The length of the first semiconductor layer in the first direction is the output active length; A minimum length of the first semiconductor layer in the second direction is the output active length.

3. The display substrate according to claim 1, wherein The at least one shift register unit further comprises a first transistor; The first transistor includes a first active pattern, and the first active pattern extends along a second direction; The first transistor is located on a side of the output circuit away from the display area.

4. The display substrate according to claim 1, wherein The at least one shift register unit further includes a second transistor and a third transistor; the second electrode of the second transistor is coupled to the second electrode of the third transistor; a maximum distance in the second direction between an orthographic projection of the gate of the second transistor on the substrate and an orthographic projection of the gate of the third transistor on the substrate is a third predetermined distance; The second transistor and the third transistor are located on a side of the output circuit away from the display area.

5. The display substrate according to claim 4, wherein: The third predetermined distance is greater than or equal to 14 um and less than or equal to 50 um.

6. The display substrate according to claim 1, wherein The at least one shift register unit further includes a first transistor, a second transistor and a first capacitor, wherein: The second electrode of the first transistor and the first electrode of the second transistor are respectively coupled to the second plate of the first capacitor, and the gate of the first transistor is coupled to the first plate of the first capacitor; The first transistor, the first capacitor and the second transistor are arranged in sequence along a first direction; The first transistor, the first capacitor, and the second transistor are located on a side of the output circuit away from a display area.

7. The display substrate according to claim 1, wherein: The scan driving circuit further includes a first voltage signal line, and the at least one shift register unit further includes an output reset capacitor; a first plate of the output reset capacitor is coupled to the gate of the output reset transistor, and a second plate of the output reset capacitor is coupled to the first voltage signal line; The maximum width of the second plate of the output reset capacitor in the second direction is a first predetermined width, and the maximum length of the second plate of the output reset capacitor in the first direction is a second predetermined length; The output reset capacitor is located on a side of the output circuit away from the display area; The orthographic projection of the second plate of the output reset capacitor on the substrate is within the orthographic projection of the first plate of the output reset capacitor on the substrate.

8. The display substrate according to claim 7, wherein: The first predetermined width is greater than or equal to 3 um and less than or equal to 60 um, and the second predetermined length is greater than or equal to 3 um and less than or equal to 20 um.

9. The display substrate according to claim 7, wherein: The first voltage signal line extends along a first direction, and the first voltage signal line is located on a side of the output reset capacitor away from the display area.

10. The display substrate according to claim 7, wherein: The output transistor and the output reset transistor are arranged along a first direction; the scan drive circuit further includes a second voltage signal line; and the at least one shift register unit further includes an output reset capacitor; The second plate of the output reset capacitor is coupled to the first voltage signal line; The first electrode of the output transistor is coupled to the second voltage signal line, and the first electrode of the output reset transistor is coupled to the second plate of the output reset capacitor; The output transistor and the output reset transistor are located on a side of the second voltage signal line away from the display area.

11. The display substrate according to claim 10, wherein: The gate of the output transistor includes at least one output gate pattern, the first electrode of the output transistor includes at least one first electrode pattern, and the second electrode of the output transistor includes at least one second electrode pattern; The output gate pattern is located between the adjacent first electrode pattern and the second electrode pattern; The first electrode pattern, the output gate pattern, and the second electrode pattern all extend along a second direction.

12. The display substrate according to claim 10, wherein: The gate of the output reset transistor includes at least one output reset gate pattern, the first electrode of the output reset transistor includes at least one third electrode pattern, and the second electrode of the output reset transistor includes at least one fourth electrode pattern; The output reset gate pattern is located between the adjacent third electrode pattern and the fourth electrode pattern; The third electrode pattern, the output reset gate pattern and the fourth electrode pattern all extend along the second direction; The fourth electrode pattern of the output reset transistor that is closest to the gate of the output transistor is multiplexed as the second electrode pattern of the output transistor.

13. The display substrate according to claim 11, wherein: The active layer of the output transistor includes at least two first conductive portions arranged opposite to each other along a first direction, and at least one first channel portion; each first channel portion is arranged between two adjacent first conductive portions; The first channel portions correspond to the output gate patterns one by one, and the orthographic projection of each first channel portion on the substrate is located inside the orthographic projection of the corresponding output gate pattern on the substrate; A portion of the first conductive portions of the output transistor corresponds to the first electrode pattern one-to-one, an orthographic projection of the first electrode pattern on the substrate and an orthographic projection of the corresponding first conductive portion on the substrate having a first overlapping region, and the first electrode pattern is coupled to the corresponding first conductive portion via at least one first via provided in the first overlapping region; Another part of the first conductive portion in the output transistor corresponds one-to-one to the second electrode pattern, and an orthographic projection of the second electrode pattern on the substrate has a second overlapping area with an orthographic projection of the corresponding first conductive portion on the substrate, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via provided in the second overlapping area.

14. The display substrate according to claim 12, wherein: The active layer of the output reset transistor includes at least two second conductive portions arranged opposite to each other along a first direction, and at least one second channel portion; each second channel portion is arranged between two adjacent second conductive portions; The second channel portions correspond to the output reset gate patterns one by one, and the orthographic projection of each second channel portion on the substrate is located inside the orthographic projection of the corresponding output reset gate pattern on the substrate; A portion of the second conductive portions of the output reset transistor corresponds one-to-one to the third electrode pattern, an orthographic projection of the third electrode pattern on the substrate and an orthographic projection of the corresponding second conductive portion on the substrate form a third overlapping region, and the third electrode pattern is coupled to the corresponding second conductive portion via at least one third via provided in the third overlapping region; Another part of the second conductive portion in the output reset transistor corresponds one-to-one to the fourth electrode pattern, and the orthographic projection of the fourth electrode pattern on the substrate has a fourth overlapping area with the orthographic projection of the corresponding second conductive portion on the substrate. The fourth electrode pattern is coupled to the corresponding second conductive portion through at least one fourth via provided in the fourth overlapping area.

15. The display substrate according to claim 11, wherein The scan driving circuit further includes a second voltage signal line; the at least one shift register unit further includes a fourth transistor; The second voltage signal line is coupled to the electrode conductive connection portion, and the electrode conductive connection portion extends along the second direction; the at least one first electrode pattern is arranged in sequence along the first direction; The electrode conductive connection portion is coupled to a first first electrode pattern included in the first electrode of the output transistor; The first electrode of the fourth transistor is coupled to the electrode conductive connection portion; A minimum distance in the first direction between an orthographic projection of the gate of the fourth transistor on the substrate and an orthographic projection of the electrode conductive connection portion on the substrate is a fourth predetermined distance.

16. The display substrate according to claim 15, wherein The fourth predetermined distance is greater than or equal to 1 um and less than or equal to 5 um.

17. The display substrate according to claim 1, wherein The at least one shift register unit further comprises a fourth transistor and a fifth transistor; The gate of the fourth transistor is coupled to the gate of the fifth transistor; The gate of the fourth transistor and the gate of the fifth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along a second direction.

18. The display substrate according to claim 17, wherein: The scan driving circuit further includes a first clock signal line, and the gate of the fifth transistor is coupled to the first clock signal line; The first clock signal line extends along a first direction, and the first clock signal line is located on a side of the five transistors away from the display area.

19. The display substrate according to claim 1, wherein The at least one shift register unit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor and an output capacitor; A first electrode of the fifth transistor is coupled to the input signal terminal; a second electrode of the fifth transistor is coupled to the gate of the sixth transistor; The gate of the sixth transistor includes a first gate pattern and a second gate pattern coupled to each other; The first gate pattern and the second gate pattern are respectively coupled to a first plate of the output capacitor, and the first plate of the output capacitor is coupled to a gate of the output transistor; A first electrode of the sixth transistor is coupled to the gate of the fourth transistor, a second electrode of the sixth transistor is coupled to the second electrode of the fourth transistor, and a second plate of the output capacitor is coupled to the first electrode of the first transistor; The fourth transistor, the sixth transistor and the first transistor are arranged in sequence along the first direction; The fifth transistor, the sixth transistor and the first transistor are arranged in sequence along the first direction; The output capacitor is located between the sixth transistor and the output circuit.

20. The display substrate according to claim 1, wherein The at least one shift register unit further includes a second transistor, a first transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein, The active layer of the seventh transistor and the active layer of the eighth transistor are formed by a continuous second semiconductor layer, and the second semiconductor layer extends along the first direction; The active layer of the seventh transistor includes a first ninth conductive portion, a ninth channel portion, and a second ninth conductive portion sequentially arranged along the first direction; The second ninth conductive portion is multiplexed as the first tenth conductive portion; The active layer of the eighth transistor includes a first tenth conductive portion, a tenth channel portion, and a second tenth conductive portion sequentially arranged along the first direction; The first ninth conductive portion is used as the second electrode of the seventh transistor, the second ninth conductive portion is used as the first electrode of the seventh transistor, the second tenth conductive portion is used as the first electrode of the eighth transistor, and the first electrode of the seventh transistor is multiplexed as the second electrode of the eighth transistor; The gate of the seventh transistor is coupled to the second plate of the output capacitor, and the second electrode of the seventh transistor is coupled to the gate of the sixth transistor; A gate of the eighth transistor is coupled to the gate of the first transistor, and a first electrode of the eighth transistor is coupled to a first voltage signal line; The first voltage signal line extends along a first direction; The sixth transistor, the seventh transistor, the eighth transistor and the second transistor are arranged in sequence along a first direction.

21. The display substrate according to claim 20, wherein: The scan driving circuit further includes a second clock signal line, and the gate of the second transistor and the gate of the seventh transistor are respectively coupled to the second clock signal line; The second clock signal line extends along a first direction, and the second clock signal line is located on a side of the second transistor away from the display area.

22. The display substrate according to claim 1, wherein The scan driving circuit further includes a second voltage signal line and a signal output line; The signal output line includes a first output line portion and at least one second output line portion; The second voltage signal line and the first output line portion both extend along a first direction, and the first output line portion is located between the second voltage signal line and the output circuit; The second output line portion extends along a second direction; The second output line portion is used to provide a light emitting control signal to the pixel circuit in the display area; The first output line portion and the output circuit are located on a side of the second voltage signal line away from the display area.

23. The display substrate according to claim 1, wherein The scan driving circuit further includes a first voltage signal line, a second voltage signal line, a first clock signal line and a second clock signal line; The first voltage signal line, the second voltage signal line, the first clock signal line and the second clock signal line all extend along a first direction; The orthographic projection of the first voltage signal line on the substrate, the orthographic projection of the first clock signal line on the substrate, and the orthographic projection of the second clock signal line on the substrate are all located on a side of the orthographic projection of the shift register unit on the substrate away from the display area; The orthographic projection of the second voltage signal line on the substrate is located on a side of the shift register unit close to the display area.

24. The display substrate according to claim 1, wherein The signal output line further includes at least one second output line portion coupled to the first output line portion; the second output line portion extends to the display area and is used to provide a light emitting control signal to a pixel circuit located in the display area.

25. The display substrate according to claim 1, wherein The scan drive circuit further includes a first voltage signal line, a second voltage signal line, a first clock signal line, a second clock signal line, and a signal output line; the at least one shift register unit further includes a first capacitor, an output capacitor, an output reset capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the signal output line further includes at least one second output line portion; The gate of the output transistor is coupled to the first plate of the output capacitor, the first electrode of the output transistor is coupled to the second voltage signal line, and the second electrode of the output transistor is coupled to the signal output line; The gate of the output reset transistor is coupled to the first plate of the output reset capacitor, the first electrode of the output reset transistor is coupled to the second plate of the output reset capacitor, and the second electrode of the output reset transistor is coupled to the signal output line; The second plate of the output reset capacitor is coupled to the first voltage signal line; the second plate of the output capacitor is coupled to the gate of the seventh transistor; The first electrode of the first transistor is coupled to the second plate of the output capacitor, the second electrode of the first transistor and the first electrode of the second transistor are respectively coupled to the second plate of the first capacitor, and the gate of the first transistor is coupled to the first plate of the first capacitor; A gate of the second transistor and a gate of the seventh transistor are respectively coupled to the second clock signal line, and a second electrode of the second transistor is coupled to the second electrode of the third transistor; The gate of the third transistor is coupled to the gate of the output transistor, and the first electrode of the third transistor is coupled to the first plate of the output reset capacitor; A gate of the fourth transistor is coupled to a gate of the fifth transistor, a first electrode of the fourth transistor is coupled to a first electrode of the output transistor, and a second electrode of the fourth transistor is coupled to a second electrode of the sixth transistor; The gate of the fifth transistor is coupled to the first clock signal line, the first electrode of the fifth transistor is coupled to the input signal terminal, and the second electrode of the fifth transistor is coupled to the gate of the sixth transistor; A first electrode of the sixth transistor is coupled to the gate of the fourth transistor, and a second electrode of the sixth transistor is coupled to the second electrode of the fourth transistor; The gate of the seventh transistor is coupled to the second plate of the output capacitor, the first electrode of the seventh transistor is multiplexed as the second electrode of the eighth transistor, and the second electrode of the seventh transistor is coupled to the gate of the sixth transistor; A gate of the eighth transistor is coupled to the gate of the first transistor, and a first electrode of the eighth transistor is coupled to a first voltage signal line; the second output line portion being coupled to the first output line portion; The second output line portion extends to the display area and is used to provide a light emitting control signal to the pixel circuit located in the display area.

26. The display substrate according to claim 25, wherein The second voltage signal line is arranged on a side of the shift register unit close to the display area; The first voltage signal line, the first clock signal line and the second clock signal line are arranged on a side of the shift register unit away from the display area; Along the direction close to the display area, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence; or, along the direction close to the display area, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence.

27. The display substrate according to claim 26, wherein: The scan driving circuit further includes a first start signal line and a second start signal line; Along a direction close to the display area, the second start signal line, the first start signal line, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence; Along a direction close to the display area, the first start signal line, the second start signal line, the first clock signal line, the second clock signal line and the first voltage signal line are arranged in sequence; Along a direction close to the display area, the second start signal line, the first start signal line, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence; Along a direction close to the display area, the first start signal line, the second start signal line, the second clock signal line, the first clock signal line and the first voltage signal line are arranged in sequence.

28. The display substrate according to claim 25, wherein The output transistor and the output reset transistor are located between the output capacitor and the first output line portion; along the first direction, the output transistor and the output reset transistor are arranged in sequence; a first capacitor, an output capacitor, an output reset capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; Along a first direction, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the first transistor, the first capacitor, the second transistor and the output reset transistor are arranged in sequence; The fifth transistor, the fourth transistor, the sixth transistor, the seventh transistor and the eighth transistor are located between the output capacitor and the first voltage signal line; The gate of the fifth transistor and the gate of the fourth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along the second direction.

29. The display substrate according to claim 1, wherein The display substrate further comprises a plurality of rows of pixel circuits arranged on the base; the pixel circuits comprise light emitting control terminals; The shift register unit corresponds to at least one row of pixel circuits; The signal output line of the shift register unit is coupled to the light emitting control terminal of the at least one row of pixel circuits, and is used to provide a light emitting control signal to the light emitting control terminal of the at least one row of pixel circuits.

30. A method for manufacturing a display substrate, characterized in that: The manufacturing method of the display substrate includes manufacturing a scan driving circuit on a substrate; the scan driving circuit includes a plurality of shift register units, at least one shift register unit of the plurality of shift register units includes an output circuit; The output circuit includes an output transistor and an output reset transistor; The method for manufacturing the display substrate further includes: Fabricating a semiconductor layer on the substrate, and performing a patterning process on the semiconductor layer to form an active layer of an output transistor and an active layer of an output reset transistor; forming a first gate metal layer on a side of the semiconductor layer facing away from the substrate, and patterning the first gate metal layer to form a gate of the output transistor and a gate of the output reset transistor; Using the gates of the output transistor and the output reset transistor as masks, doping portions of the semiconductor layer not covered by the gates, so that the portions of the semiconductor layer not covered by the gates form conductive portions, and the portions of the semiconductor layer covered by the gates form channel portions; Disposing a second gate metal layer on a side of the first gate metal layer facing away from the semiconductor layer, and patterning the second gate metal layer to form a signal output line; the signal output line includes a first output line portion extending along a first direction; Disposing a first insulating layer on a side of the second gate metal layer facing away from the first gate metal layer; A plurality of first signal line via holes and a plurality of second signal line via holes are formed in an area where the first insulating layer partially overlaps with the first output line; the first signal line via holes and the second signal line via holes pass through the first insulating layer; forming a source-drain metal layer on a side of the first insulating layer facing away from the second gate metal layer, and patterning the source-drain metal layer to form a first source-drain metal pattern and a second source-drain metal pattern, wherein the first source-drain metal pattern includes the second electrode of the output transistor, and the second source-drain metal pattern includes the second electrode of the output reset transistor, so that the first output line portion is coupled to the second electrode of the output transistor through the plurality of first signal line vias, and the first output line portion is coupled to the second electrode of the output reset transistor through the plurality of second signal line vias; The signal output line includes a first output line portion extending along a first direction; The plurality of first signal line vias are sequentially arranged along the first direction, and the plurality of second signal line vias are sequentially arranged along the first direction; The ratio of the maximum distance between any two first signal line vias arranged in sequence along the first direction and the third length is a first predetermined ratio; the minimum distance between two adjacent first signal line vias in the first direction is the first predetermined distance; The ratio of the maximum distance between any two second signal line vias arranged in sequence along the first direction in the first direction to the fourth length is a second predetermined ratio; the minimum distance between two adjacent second signal line vias in the first direction is the second predetermined distance; The third length is the length of the first signal line overlapping area in the first direction, and the fourth length is the length of the second signal line overlapping area in the first direction; The first predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9; The first predetermined distance is greater than or equal to 1.5 μm and less than or equal to 45 μm; The second predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9; The second predetermined distance is greater than or equal to 1.5 μm and less than or equal to 65 μm; The length of the active layer of the output transistor in the first direction is a first length, the length of the active layer of the output reset transistor in the first direction is a second length, and the sum of the first length and the second length is the output active length; The smaller of the minimum width of the active layer of the output transistor along the second direction and the minimum width of the active layer of the output reset transistor along the second direction is the output active width; the first direction intersects the second direction; The ratio of the output active length to the output active width is within a predetermined ratio range; the predetermined ratio range is greater than or equal to 3 and less than or equal to 11; and / or, the output active width is within a predetermined width range; the predetermined width range is greater than or equal to 12um and less than or equal to 45um.

31. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 29.

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