Adaptive frequency control for high-speed memory devices

Abstract

The present application relates to an adaptive frequency control for a high-speed memory device. A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and a memory die at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). In response to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. In response to determining that the second error rate satisfies the second error threshold criterion (e.g., UECC persists), it is determined that the read operation has failed.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a memory subsystem, and more particularly to adaptively correcting a frequency mismatch between a memory controller and memory devices in the memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] Aspects of the present disclosure provide a method comprising: receiving a command to read specific data stored at a memory die; performing a read operation while operating both a memory controller and the memory die simultaneously at a first frequency; determining whether a first error rate associated with the memory die satisfies a first error threshold criterion; in response to determining that the first error rate satisfies the first error threshold criterion, repeating the read operation while operating the memory controller or at least one of the memory dies at a second frequency different from the first frequency; determining whether a second error rate associated with the memory die satisfies a second error threshold criterion; and in response to determining that the second error rate satisfies the second error threshold criterion, determining that the read operation has failed.

[0004] Another aspect of the present disclosure provides a method, which includes: receiving a command to read specific data stored at a memory die during data recovery; performing a read operation including multiple cycles while operating both a memory controller and the memory die simultaneously at an initial operating frequency; detecting the occurrence of an error event; setting an error threshold criterion; during each of the multiple cycles of the read operation, repeating the read operation while adjusting the operating frequency of at least one of the memory controller and the memory die relative to the initial operating frequency; during each of the multiple cycles of the read operation, determining whether the error threshold criterion is met at the adjusted value of the current operating frequency; and in response to the determination that the error threshold criterion is met, updating the operating frequency of at least one of the memory controller or the memory die to the adjusted value of the current operating frequency.

[0005] Another aspect of the present disclosure provides a system comprising: a plurality of memory dies; and a processing device in a memory controller operably coupled to the plurality of memory dies to perform a screening operation for each of the plurality of memory dies, the screening operation comprising: performing a first frequency-based screening test by causing the memory controller and the memory dies to operate at a first frequency simultaneously; determining whether a first error rate associated with the memory dies meets a predetermined first error threshold criterion; in response to determining that the first error rate does not meet the predetermined first error threshold criterion, performing a second frequency-based screening test by causing the memory controller or at least one of the memory dies to operate at a second frequency different from the first frequency; determining whether a second error rate associated with the memory die meets a predetermined second error threshold criterion; and in response to determining that the error rate does not meet the predetermined second error threshold criterion, determining that the memory die is suitable for assembly into a memory device in a memory subsystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a host system coupled to a memory subsystem is described according to some embodiments of the present disclosure.

[0008] Figure 2 A flow chart illustrating an example method of data recovery by dynamically reducing frequency mismatches between a memory controller and / or memory dies after an error event during the operational life of a memory device in accordance with some embodiments of the present disclosure.

[0009] Figure 3 A flow chart illustrating an example method of updating the operating frequency of a memory controller and / or memory die on a semi-permanent or permanent basis after a predetermined number of recovery attempts in accordance with some embodiments of the present disclosure.

[0010] Figure 4 A flow chart illustrating an example method of pre-screening dies having poor timing margin performance before assembling the dies into a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 Block diagram illustrating an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to adaptively correcting frequency mismatches between a memory controller and memory devices in a memory subsystem during the operational life of the memory subsystem. Additional aspects of the present disclosure relate to pre-screening memory dies before assembling the dies in a memory device based on reliability checks of the memory dies after subjecting the dies to frequency-based defect screening in a test setup. The memory subsystem may be a memory device, a memory module, or a mixture of memory devices and memory modules. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0013] The memory subsystem may include a high-density nonvolatile memory device where data retention is required when no power is supplied to the memory device. One example of a nonvolatile memory device is a NAND memory device. Another example is a three-dimensional cross-point ("3D cross-point") memory device that includes an array of nonvolatile memory cells. A 3D cross-point memory device may be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Figure 1 Other examples of nonvolatile memory devices are described. A nonvolatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of nonvolatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states associated with the number of bits stored. The logical state may be represented by a binary value (e.g., "0" and "1") or a combination of such values.

[0014] A memory device may consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines (BL)) and rows (hereinafter also referred to as word lines (WL)). A word line may refer to one or more rows of memory cells of a memory device, which are used together with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device for storing data, and may include a group of memory cells, a word line group, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of a memory device in order to allow concurrent operations on each plane. A 3D crosspoint-based memory device (and its controller) is referred to as a "driver" having multiple dies layered in multiple planes referred to as "layers" in a memory device.

[0015] Advanced memory devices, such as memory devices based on 3D crosspoints, run at extremely high speeds and have very tight timing margins. The timing margin in an integrated circuit (IC) is the difference between the time a signal arrives at a circuit and the latest time the signal can arrive at the circuit to function correctly. Due to process variations during manufacturing, different dies may have slightly different timing margins. In addition, the signals or power of the assembled memory devices have fluctuations in driving voltage levels, which can exacerbate timing margin variations between dies. If the timing margin of a fragment of a memory device becomes negative, and the controller in the memory subsystem drives the fragment of the memory device at a high frequency, the memory device is generally inoperable and causes write / read failures that exceed the ability of the error correction code (ECC) to correct the data. The memory subsystem then reports the occurrence of an uncorrectable error correction code (UECC) event.

[0016] Conventional systems do not have any ability to address UECC caused by timing margin loss. Aspects of the present disclosure address the above and other deficiencies by addressing the frequency mismatch between the memory controller and the memory die that can cause UECC during high-speed operation and adaptively correcting the frequency mismatch. The method is also modified to set frequency-based test criteria at the factory level to screen out bad dies (with unacceptably low, or even negative timing margins) before assembling the drive.

[0017] Advantages of the present disclosure include, but are not limited to, adaptively adjusting the frequency mismatch between a memory controller and a memory die during different stages of the useful life of a memory device, such as a tool for pre-screening dies at the factory, dynamic adjustment during read / write operations, and semi-permanent or permanent adjustment to account for changes in wear levels during the operating life of a memory device.

[0018] Figure 1An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like. It should be noted that in the present disclosure, the reliability test setup simulates the memory subsystem 110.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device including a memory and a processing device.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0022] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0023] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of a memory cell, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0027] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-OR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in the local memory 115. In the illustrated example, the local memory 115 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, local memory 115 may include memory registers that store memory pointers, fetched data, etc. Local memory 115 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0031] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name spaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0032] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0033] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 may further include an adaptive frequency control component 113 that can be used to facilitate operation for the memory device 130. The operation includes transferring data from the host to the memory device during a write cycle, and transferring data from the memory device to the host during a read cycle. Specifically, in some embodiments, Figure 1 The adaptive frequency control component 113 shown in can be part of an assembled memory subsystem 110 that is capable of dynamically controlling the operating frequency of a memory controller and / or a particular memory die during an operational lifetime. In some other embodiments, the adaptive frequency control component 113 can be part of a test setup that pre-screens a particular die in a factory before the die is assembled into a memory device. In some embodiments, a memory subsystem controller 115 includes at least a portion of the adaptive frequency control component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in a local memory 115 for performing the operations described herein. In some embodiments, the adaptive frequency control component 113 is part of a host system 110, an application, or an operating system. In other embodiments, a local media controller 135 includes at least a portion of the adaptive frequency control component 113 and is configured to perform the functionality described herein. Other details regarding the operation of the adaptive frequency control component 113 are described below.

[0035] Figure 2 2 is a flow chart of an example method 200 for data recovery by dynamically reducing the frequency mismatch between a memory controller and a memory die after an error event occurs during the useful life of a memory device in accordance with some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 may be performed by Figure 1The adaptive frequency control component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible. In addition, although the operations are shown with respect to the read command, similar operations can also be performed for the write command.

[0036] At operation 210, the processor receives a command to read specific data stored at a specific location in a memory die. The specific data may be a target codeword (CW) or any other unit of stored data. At operation 220, the processor performs a read operation while operating the memory controller and the memory die at an initial frequency. This initial frequency may be based on device specification data available in factory testing of similar memory dies.

[0037] At operation 230, the processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion. In some embodiments, satisfying the first error threshold criterion may determine that the error rate has exceeded a value at which the ECC cannot correct errors, i.e., the errors have become uncorrectable. This is referred to as a UECC event. UECC may be associated with a tight timing margin of the memory die.

[0038] If the first error threshold criteria is not met at operation 230, then at operation 270 the processor determines that the read operation was successful and that no additional data recovery operations are required.

[0039] On the other hand, in response to determining that the first error rate satisfies the first error threshold criterion, the processor proceeds to operation 240 and repeats the read operation while operating at least one of the memory controller or the memory die at a second frequency different from the initial frequency. For example, the processor may reduce the controller frequency while maintaining the die frequency at the initial level, or increase the die frequency while maintaining the controller frequency at the initial level. In certain other embodiments, both the controller frequency and the die frequency are changed relative to the initial frequency. This frequency adjustment is performed to re-execute the failure event to confirm that the UECC is indeed related to the poor timing margin of certain dies.

[0040] At operation 250, the processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Note that the first error threshold criterion and the second error threshold criterion may be similar, for example, satisfying the second error threshold criterion may be the occurrence of a UECC event.

[0041] If the second error threshold criteria is not met at operation 250, then at operation 270 the processor determines that the data has been successfully recovered by adjusting the operating frequency of the memory controller and / or the memory die, and that the read operation was successful.

[0042] On the other hand, in response to determining that the second error rate satisfies the second error threshold criteria (e.g., UECC persists), the processor determines that the read operation has failed at operation 260. It should be noted that the memory subsystem can be configured to repeat operations 240 and 250 a predetermined number of times before declaring the read operation successful or failed.

[0043] Figure 3 1 is a flow chart of an example method 300 for semi-permanently or permanently updating the operating frequency of a memory controller and / or memory die after a predetermined number of recovery attempts according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 may be performed by Figure 1 The adaptive frequency control component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0044] At operation 310, the processor receives a command to read specific data stored at a specific location in the memory die. This operation may be similar or identical to operation 210 in method 200, but once the processor formally enters the data recovery process, such as after operation 250 in method 200, operation 310 may occur.

[0045] At operation 320, the processor performs a read operation while operating the memory controller and the memory die at an initial frequency. This initial frequency may be based on device specification data available in factory testing of similar memory dies. This step may be similar or identical to operation 220 in method 200.

[0046] At operation 330, the processor determines whether an error event is detected. An error event may be detected when the error correction code cannot correct errors in the data, ie, when a UECC occurs. The UECC may be associated with tight timing margins of the memory die.

[0047] If no uncorrectable error event is detected at operation 330, then at operation 380 the processor determines that the initial frequency should be maintained for the controller and memory die.

[0048] On the other hand, in response to detecting an uncorrectable error event at operation 330, the processor proceeds to operation 340 and sets an error threshold criterion for repeating the read operation one or more times. The number of repetitions may be set by a counter.

[0049] At operation 350, the processor adjusts the operating frequency of at least one of the memory controller or the memory die to a frequency different from the initial frequency. For example, the processor may reduce the controller frequency while maintaining the die frequency at the initial level, or increase the die frequency while maintaining the controller frequency at the initial level. In certain other embodiments, both the controller frequency and the die frequency are changed relative to the initial frequency. This frequency adjustment is performed to re-execute the failure event so that the operating frequency of the die and / or controller conforms to the current wear level of the memory device. For example, through repeated use, after a certain time, a die that has sufficient timing margin at the beginning may degrade to the point where the timing margin is reduced and the probability of read failure increases.

[0050] At operation 350 , the processor determines whether a second error threshold criterion is met. It should be noted that meeting the error threshold criterion may be the occurrence of a UECC event, as in method 200 .

[0051] If the error threshold criteria is not met at operation 360, then at operation 380 the processor determines that the initial frequency should be maintained for the controller and memory die.

[0052] On the other hand, in response to determining that the error threshold criteria are met (e.g., UECC persists), at operation 370, the processor determines that the operating frequency of the memory controller and / or memory die needs to be semi-permanently or permanently updated to comply with the current wear level. Figure 1 The adaptive frequency control component 113 can periodically control the operating frequency during the service life of the driver, thereby extending the service life of the driver.

[0053] Figure 4 4 is a flow chart of an example method 400 of pre-screening dies with poor timing margin performance before assembling the dies into a memory device according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some other embodiments, the method 400 may be performed by Figure 1The adaptive frequency control component 113 of the embodiment is executed as part of the test setup in the factory before the die is assembled into the memory device. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0054] At operation 410, the test setup performs a first frequency-based screening test by operating both the memory controller and the memory die simultaneously at the same initial frequency. At operation 420, the processor determines whether a first error rate associated with the memory die meets a predetermined first error threshold criterion. The criterion may be similar to the criterion described in method 200, such as the occurrence of UECC. The error threshold criterion may be specific to a predetermined reliability level for the memory subsystem.

[0055] If the first error threshold criteria is met at operation 420, the processor determines that the memory die is not suitable for assembly into a memory device having a specific reliability level at operation 460. Therefore, memory dies with poor timing margins (UECC dependent) are discarded to ensure high quality assembled drivers.

[0056] On the other hand, in response to determining that the first error threshold criterion is not met, the test setup performs a second frequency-based screening test by operating at least one of the memory controller or the memory die at a frequency different from the initial frequency at operation 430. Performing the second frequency-based screening test may mean operating the memory controller at a frequency higher than the initial frequency, or operating the memory die at a frequency lower than the initial frequency.

[0057] At operation 440, the processor determines whether a second error rate associated with the memory die meets a predetermined second error threshold criterion after the second frequency-based screening test. The criterion may be similar to the criterion described in method 200, such as the occurrence of UECC. The error threshold criterion may be specific to a predetermined reliability level for the memory subsystem.

[0058] If the second error threshold criteria is met at operation 420, the processor determines that the memory die is not suitable for assembly into a memory device having a specific reliability level at operation 460. Therefore, memory dies with poor timing margins (UECC dependent) are discarded to ensure high quality assembled drivers.

[0059] On the other hand, in response to determining that the second error threshold criterion is not met, the processor determines that the memory die is suitable for assembly into the memory device at operation 450. As mentioned above, since the driver is likely to experience fluctuations in signal and power levels that cause loss of timing margin during its operational life, it is beneficial to initially select a good die with a higher timing margin so that even if the timing margin is slightly degraded during the operational life, it will not adversely affect the reliability level of the assembled driver.

[0060] Figure 5 An example machine of a computer system 500 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. For example, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the embodiment of the present invention may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0061] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0062] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 518, which communicate with each other via a bus 530.

[0063] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 to communicate over a network 520. The data storage device 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets or software 526 embodying any one or more methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage device 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0064] In one embodiment, instructions 526 include instructions for implementing a method corresponding to a particular component (e.g., Figure 1 The frequency control component 113 of the machine readable storage medium 524 performs the function of adaptive frequency control). Although the machine-readable storage medium 524 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0065] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is conceived herein and generally as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0066] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as will be apparent from the following discussion, it should be understood that throughout the description, discussions using terms such as "receiving" or "serving" or "publishing" etc. refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0067] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0068] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices for performing the methods. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0069] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0070] In the above description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method for memory operation, comprising: receiving a command to read data stored at the memory die; performing a read operation while operating both the memory controller and the memory die simultaneously at a first frequency; determining whether a first error rate associated with the memory die satisfies a first error threshold criterion; in response to determining that the first error rate satisfies the first error threshold criterion, repeating the read operation while operating at least one of the memory controller or the memory die at a second frequency different from the first frequency; determining whether a second error rate associated with the memory die satisfies a second error threshold criterion; and In response to determining that the second error rate satisfies the second error threshold criterion, repeating the read operation a predetermined number of times before determining that the read operation has failed, wherein at least one of satisfying the first error threshold criterion or satisfying the second error threshold criterion includes errors becoming uncorrectable by an error correction code.

2. The method of claim 1 , wherein repeating the read operation comprises: The memory controller is operated at a second frequency lower than the first frequency.

3. The method of claim 1 , wherein repeating the read operation comprises: The memory die is operated at a second frequency higher than the first frequency.

4. The method according to claim 1, further comprising: In response to determining that the first error rate does not satisfy the first error threshold criterion, the read operation is determined to be successful.

5. The method according to claim 1, further comprising: In response to determining that the second error rate does not satisfy the second error threshold criterion, the read operation is determined to be successful.

6. The method according to claim 1, further comprising: In response to determining that the read operation has failed, initiating a data recovery process including: issuing a new command to read data stored at the memory die; performing a data recovery read operation including a plurality of cycles while simultaneously operating both the memory controller and the memory die at an initial operating frequency; Detect the occurrence of error events; Setting error threshold criteria; repeating the data recovery read operation while adjusting the operating frequency of at least one of the memory controller and the memory die relative to the initial operating frequency during each of the plurality of cycles of the read operation; during each of the plurality of cycles of the data recovery read operation, determining whether the error threshold criterion is met at the adjusted value of the current operating frequency; and In response to determining that the error threshold criteria is met, the operating frequency of at least one of the memory controller or the memory die is updated to the adjusted value of the current operating frequency.

7. The method of claim 6, wherein adjusting the operating frequency during data recovery comprises: For each read cycle, the operating frequency of the memory die is incremented by a predetermined step size.

8. The method of claim 6, wherein adjusting the operating frequency comprises: For each read cycle, the operating frequency of the memory controller is decremented by a predetermined step size.

9. The method according to claim 6, further comprising: responsive to detecting said occurrence of said error event, setting a counter to repeat said data recovery read operation a predetermined maximum number of times; and In response to determining that the error threshold criterion is not satisfied after repeating the data recovery read operation the predetermined maximum number of times set in the counter, the initial operating frequency is maintained.

10. The method of claim 6, wherein the error event comprises an uncorrectable error correction code (UECC) event.

11. The method of claim 6, wherein an amount by which the operating frequency of at least one of the memory controller and the memory die is adjusted is based on a current wear state of the memory die over an operational lifetime of the memory die.

12. The method of claim 11, wherein the operating frequency of at least one of the memory controller and the memory die is periodically adjusted during a maintenance procedure of a memory device including the memory die.

13. A system for memory operation, comprising: multiple memory dies; and a processing device in a memory controller operably coupled to the plurality of memory dies to perform a screening operation for each of the plurality of memory dies, the screening operation comprising: receiving a command to read data stored at the memory die; performing a read operation while operating both the memory controller and the memory die simultaneously at a first frequency; determining whether a first error rate associated with the memory die satisfies a first error threshold criterion; in response to determining that the first error rate satisfies the first error threshold criterion, repeating the read operation while operating at least one of the memory controller or the memory die at a second frequency different from the first frequency; determining whether a second error rate associated with the memory die satisfies a second error threshold criterion; and In response to determining that the second error rate satisfies the second error threshold criterion, repeating the read operation a predetermined number of times before determining that the read operation has failed, wherein at least one of satisfying the first error threshold criterion or satisfying the second error threshold criterion includes errors becoming uncorrectable by an error correction code.

14. The system of claim 13, wherein repeating the read operation comprises: The memory controller is operated at a second frequency lower than the first frequency.

15. The system of claim 13, wherein repeating the read operation comprises: The memory die is operated at a second frequency higher than the first frequency.

16. The system of claim 13, wherein the screening operation performed by the processing device further comprises: In response to determining that the first error rate does not satisfy the first error threshold criterion, the read operation is determined to be successful.

17. The system of claim 13, wherein the screening operation performed by the processing device further comprises: In response to determining that the second error rate does not satisfy the second error threshold criterion, the read operation is determined to be successful.

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