semiconductor devices

Abstract

Provided herein may be a semiconductor device. The semiconductor device may include: a stack including a word line, a bit line penetrating the stack; a global bit line disposed above the stack; a global word line disposed above the stack; a common select line disposed above the stack; a first contact plug coupling the global bit line and the bit line to each other and penetrating the common select line; and a second contact plug coupling the global word line and the word line to each other and penetrating the common select line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0101348 filed on August 12, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to a semiconductor device including a memory. Background Art

[0004] To meet the trend of downsizing, power reduction, performance improvement, and diversification in modern electronic devices, various electronic devices such as computers and portable communication devices require semiconductor devices for storing information. Consequently, research is underway into semiconductor devices capable of storing data by switching between different resistance states in response to applied voltage or current. Examples of these semiconductor devices include resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and E-fuses. Summary of the Invention

[0005] Various embodiments of the present disclosure are directed to an electronic device capable of enhancing operating characteristics and reliability of a memory unit.

[0006] Embodiments of the present disclosure may provide a semiconductor device. The semiconductor device may include: a stack including a word line; a bit line penetrating the stack; a global bit line disposed above the stack; a global word line disposed above the stack; a common select line disposed above the stack; a first contact plug coupling the global bit line and the bit line to each other and penetrating the common select line; and a second contact plug coupling the global word line and the word line to each other and penetrating the common select line.

[0007] Embodiments of the present disclosure may provide a semiconductor device. The semiconductor device may include a bit line, a word line, a resistive memory cell coupled between the bit line and the word line, a first selection transistor configured to control coupling between a global bit line and the bit line, a second selection transistor configured to control coupling between the global word line and the word line, and a common selection line configured to jointly control the first selection transistor and the second selection transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2is a view for explaining the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3A and Figure 3B are views for explaining the structure and operation method of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 is a view for explaining the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5A and Figure 5B are views for explaining the structure and operation method of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 6 is a configuration diagram of a microprocessor for implementing a storage device according to an embodiment of the present disclosure.

[0014] Figure 7 is a configuration diagram of a processor for implementing a storage device according to an embodiment of the present disclosure.

[0015] Figure 8 is a configuration diagram of a system for implementing a storage device according to an embodiment of the present disclosure.

[0016] Figure 9 is a configuration diagram of a data storage system for implementing a storage device according to an embodiment of the present disclosure.

[0017] Figure 10 is a configuration diagram of a memory system for implementing a storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The specific structural or functional descriptions of the embodiments of the present disclosure introduced in this specification or application are only used to describe the embodiments of the present disclosure. The description should not be interpreted as being limited to the embodiments described in the specification or application.

[0019] Figure 1 is a view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0020] Reference Figure 1 The semiconductor device may include a stack ST, a bit line BL, a global bit line GBL, a global word line GWL, and a common selection line C_SL. The semiconductor device may further include a substrate 10, an insulating spacer 14, an interlayer insulating layer 16, a first contact plug CT1, a second contact plug CT2, or a combination thereof.

[0021] The stack ST may be provided on a substrate 10. The substrate 10 may be a semiconductor substrate. The substrate 10 may include a substructure such as a peripheral circuit.

[0022] Each stack ST may include a word line WL. In an embodiment of the present disclosure, the stack ST may include word lines WL and insulating layers 12, which are alternately stacked. The stack ST may extend in a first direction I. The stack ST may be arranged side by side in a second direction II intersecting the first direction I. The word lines WL and the insulating layers 12 may extend in the first direction I.

[0023] The stack ST may include a cell region CR and a contact region CTR. The cell region CR and the contact region CTR may be adjacent to each other in a first direction I. The cell region CR may be a region where memory cells are stacked. The contact region CTR may be a region where pads for applying a bias voltage to drive the stacked memory cells are arranged. The contact region CTR may be patterned to expose corresponding word lines WL. The contact region CTR may have a stepped form. For example, the word lines WL may extend from the cell region CR to the contact region CTR at different lengths in the first direction I to form a stepped form in the contact region CTR. In each word line WL, the exposed portion defined by the stepped form may serve as a pad.

[0024] although Figure 1 A word line WL is shown positioned at the top of each step, and an insulating layer 12 is positioned at the bottom of the step. In some embodiments, the word line WL and insulating layer 12 may be positioned oppositely within each step. Within each step, the insulating layer 12 may be positioned at the top, and the word line WL may be positioned at the bottom. Furthermore, each word line WL may have a uniform or non-uniform thickness in the third direction III. In an embodiment of the present disclosure, the pad of each word line WL may be thicker than the rest of the pad covered by the upper insulating layer 12.

[0025] The bit lines BL may penetrate the stack ST. The bit lines BL may penetrate the stack ST in a third direction III. In the embodiment of the present disclosure, the third direction III may be the direction in which the word lines WL are stacked. In other words, the third direction III may be a direction intersecting the first direction I and the second direction II, and may be a direction protruding from the plane defined by the first direction I and the second direction II. The bit lines BL may include a conductive material such as polysilicon or metal. Each bit line BL may have a planar cross-section in a shape such as a circle, an ellipse, or a polygon.

[0026] Bit lines BL may be disposed in the cell region CR. The bit lines BL may be arranged along a first direction I and a second direction II. The bit lines BL may penetrate word lines WL. In a plane defined by the first direction I and the second direction II, each word line WL may completely or partially surround the sidewalls of each bit line BL. Memory cells MC may be disposed in a region or area where the bit lines BL and word lines WL intersect. The memory cells MC may be arranged along the first direction I and the second direction II and may be stacked along a third direction III. Memory cells MC stacked along the third direction III may share a bit line BL. Memory cells MC arranged along the first direction I may share a word line WL.

[0027] A global bit line GBL may be provided to provide a bit line voltage to the bit line BL. The global bit line GBL may be disposed above the stack ST. The global bit line GBL may be disposed in the cell region CR and may be disposed above the bit line BL.

[0028] The global bit lines GBL may extend in the second direction II. Each of the global bit lines GBL may overlap with the bit lines BL arranged along the second direction II. The global bit lines GBL may be arranged side by side in the first direction I.

[0029] A global word line GWL may be provided to provide a word line voltage to the word line WL. The global word line GWL may be disposed above the stack ST. The global word line GWL may be disposed in the contact region CTR and may be disposed above a pad of the word line WL.

[0030] The global word lines GWL may extend in the second direction II. The global word lines GWL may be arranged side by side in the first direction I. The global word lines GWL may extend to be parallel to the global bit lines GBL. The global word lines GWL may be disposed at substantially the same level as the global bit lines GBL, or may be disposed at a different level than the global bit lines GBL.

[0031] Common selection lines C_SL may be provided to control coupling between global bit lines GBL and bit lines BL and between global word lines GWL and word lines WL. Common selection lines C_SL may be arranged above stack ST. Common selection lines C_SL may extend in a first direction I. Common selection lines C_SL may be arranged side by side in a second direction II.

[0032] Common selection lines C_SL may be provided between the stack ST and the global bit lines GBL, and between the stack ST and the global word lines GWL. Each common selection line C_SL may extend from the cell region CR to the contact region CTR. In the cell region CR, the common selection line C_SL may be provided between the bit lines BL and the global bit lines GBL. In the contact region CTR, the common selection line C_SL may be provided between the word lines WL and the global word lines GWL.

[0033] The first contact plug CT1 may couple the global bit line GBL and the bit line BL to each other. The first contact plug CT1 may penetrate the common selection line C_SL. The first selection transistor ST1 may be disposed in a region or area where the first contact plug CT1 and the common selection line C_SL intersect. The first selection transistor ST1 may be provided to control the electrical coupling between the global bit line GBL and the bit line BL.

[0034] The second contact plug CT2 may couple the global word line GWL and the word line WL to each other. The second contact plug CT2 may penetrate the common select line C_SL. In a plane defined by the first direction I and the second direction II, each common select line C_SL may completely or partially surround the sidewall of each second contact plug CT2. The second select transistor ST2 may be disposed in a region or area where the second contact plug CT2 and the common select line C_SL intersect. The second select transistor ST2 may be provided to control the electrical coupling between the global word line GWL and the word line WL.

[0035] Using the three-dimensional structure described above, the integration density of semiconductor devices can be increased by layering memory cells MC. Furthermore, the coupling between the global bit line GBL and the bit line BL, as well as the coupling between the global word line GWL and the word line WL, can be controlled by a common select line C_SL. Using a single common select line C_SL, both the word line WL and the bit line BL can be selected simultaneously. Therefore, each memory cell can be randomly accessed.

[0036] Figure 2 1 is a diagram for explaining the structure of a semiconductor device according to an embodiment of the present disclosure. Descriptions of structures or elements substantially the same as those described above will not be repeated.

[0037] Reference Figure 2 , the semiconductor device may include a memory cell MC, a first selection transistor ST1 and a second selection transistor ST2.

[0038] A memory cell MC may be disposed in a region or area where a bit line BL and a word line WL intersect. In a plane defined by a first direction I and a second direction II, the word line WL may completely surround the sidewalls of the bit line BL. The memory cell MC may include a memory layer ME interposed between the bit line BL and the word line WL. The memory layer ME functions as data storage and may include a variable resistance layer. The variable resistance layer may have a property of reversibly switching between different resistance states depending on an applied voltage or current. The memory cell MC may be a resistive memory cell including the variable resistance layer.

[0039] In an embodiment of the present disclosure, the variable resistance layer may include a resistive material. The variable resistance layer may include a transition metal oxide or a metal oxide such as a perovskite material. Therefore, depending on the applied voltage or current, an electrical path may be established or dissipated in the variable resistance layer, thereby enabling the memory cell MC to store data in a non-volatile manner.

[0040] In an embodiment of the present disclosure, the variable resistance layer may have a magnetic tunnel junction (MTJ) structure. The variable resistance layer may include a magnetization fixed layer and a magnetization free layer, and a tunnel barrier layer interposed between the magnetization fixed layer and the magnetization free layer. For example, the magnetization fixed layer and the magnetization free layer may include a magnetic material, and the tunnel barrier layer may include an oxide such as magnesium (Mg), aluminum (Al), zinc (An), titanium (Ti), etc. The magnetization direction of the magnetization free layer may be changed by the spin torque of electrons under an applied current. Therefore, the memory cell MC can store data based on the change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization fixed layer.

[0041] In an embodiment of the present disclosure, the variable resistance layer may include a phase change material and may include a chalcogenide material. The variable resistance layer may include chalcogenide glass, a chalcogenide alloy, or the like. The variable resistance layer may include silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), selenium (Se), or the like, or a combination thereof. The variable resistance layer may be Ge-Sb-Te (GST). For example, the variable resistance layer may include Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, Ge1Sb4Te7, or the like. The variable resistance layer may undergo a phase change according to a programming operation. For example, a set operation may cause the variable resistance layer to have a low-resistance crystalline state. A reset operation may cause the variable resistance layer to have a high-resistance amorphous state. Therefore, the memory cell MC may store data by using a resistance difference depending on the phase of the variable resistance layer.

[0042] In an embodiment of the present disclosure, the variable resistance layer may include a variable resistance material having a resistance change characteristic but no phase change characteristic, and may include a chalcogenide material. For example, the variable resistance layer may include Ge, Sb, Te, arsenic (As), Se, Si, In, Sb, sulfur (S), gallium (Ga), etc., or a combination thereof. The variable resistance layer may maintain its phase during a programming operation. For example, the variable resistance layer may have an amorphous state that does not change to a crystalline state during a programming operation. Therefore, using a programming pulse applied to the memory cell MC, the critical voltage of the memory cell MC may be changed, and the memory cell MC may be programmed to at least two states. A reset operation may cause the variable resistance layer to have a high resistance amorphous state, and the memory cell MC may be programmed to a reset state with a high critical voltage. A set operation may cause the variable resistance layer to have a low resistance amorphous state, and the memory cell MC may be programmed to a set state with a low critical voltage.

[0043] The first selection transistor ST1 may be disposed in a region or area where the first contact plug CT1 and the common selection line C_SL intersect. In a plane defined by the first direction I and the second direction II, the common selection line C_SL may completely surround the sidewalls of the first contact plug CT1. The first selection transistor ST1 may include a first channel layer, a first gate insulating layer GI1, and a first gate electrode. A portion of the first contact plug CT1 overlapping with the common selection line C_SL may serve as the first channel layer. A portion of the common selection line C_SL surrounding the sidewalls of the first contact plug CT1 may serve as the first gate electrode. The first selection transistors ST1 linearly arranged along the first direction I may share the common selection line C_SL.

[0044] The first contact plug CT1 may be coupled to the corresponding bit line BL. Therefore, when the first selection transistor ST1 is turned on, a bit line voltage of the global bit line GBL may be applied to the bit line BL through the first contact plug CT1.

[0045] The second selection transistor ST2 may be disposed in a region or area where the second contact plug CT2 and the common selection line C_SL intersect. The second selection transistor ST2 may include a second channel layer, a second gate insulating layer GI2, and a second gate electrode. The portion of the second contact plug CT2 overlapping the common selection line C_SL may serve as the second channel layer. The portion of the common selection line C_SL surrounding the sidewall of the second contact plug CT2 may serve as the second gate electrode. The second selection transistors ST2 linearly arranged along the first direction I may share the common selection line C_SL.

[0046] The second contact plug CT2 may be coupled to the corresponding word line WL. Therefore, when the second selection transistor ST2 is turned on, the word line voltage of the global word line GWL may be applied to the word line WL through the second contact plug CT2.

[0047] The second contact plugs CT2 may be coupled to the word lines WL directly or via the third contact plugs CT3. The third contact plugs CT3 may have the same height or may have different heights. In an embodiment of the present disclosure, the top planes of the third contact plugs CT3 may be positioned at substantially the same horizontal plane. As a result, the second contact plugs CT2 may have substantially the same height. The top planes of the third contact plugs CT3 may be positioned at substantially the same horizontal plane as the top plane of the bit lines BL.

[0048] Figure 3A and Figure 3B 1 is a diagram for explaining the structure and operation method of a semiconductor device according to an embodiment of the present disclosure. The description of structures or elements that are substantially the same as those described above will not be repeated.

[0049] Reference Figure 3A and Figure 3B The semiconductor device may include first to mth bit lines BL11 to BLmk, first to kth word lines WL11 to WLkn, memory cells MC11 to MCmn, first selection transistors ST11 to ST1m, and second selection transistors ST21 to ST2n. Furthermore, the semiconductor device may include first to kth common selection lines C_SL1 to C_SLk, first to mth global bit lines GBL1 to GBLm, and first to nth global word lines GWL1 to GWLn. Here, m and n may be integers equal to or greater than 2, and k may be an integer equal to or greater than 1.

[0050] First selection transistors ST11 to ST1m control coupling between first bit lines BL11 to BLm1 and first to mth global bit lines GBL1 to GBLm. In an embodiment of the present disclosure, when the first selection transistor ST11 is turned on, the first bit line BL11 and the first global bit line GBL1 are coupled.

[0051] Second selection transistors ST21 to ST2n control coupling between the first word lines WL11 to WL1n and the first to nth global word lines GWL1 to GWLn. In an embodiment of the present disclosure, when the second selection transistor ST21 is turned on, the first word line WL11 and the first global word line GWL1 are coupled.

[0052] Gate electrodes of the first and second selection transistors ST11 to ST1m and ST21 to ST2n may be coupled to a first common selection line C_SL1. In other words, the first common selection line C_SL1 may commonly control the first and second selection transistors ST11 to ST1m and ST21 to ST2n.

[0053] With this structure, a desired memory cell can be selected from the memory cells MC11 to MCmn using common select lines C_SL1 to C_SLk. For example, using a single common select line C_SL1, the first word lines WL11 to WL1n and the first bit line BL11 can be simultaneously selected. Therefore, each memory cell MC11 to MCmn can be randomly accessed.

[0054] An embodiment of selecting the first memory cell MC11 will now be described. A first global bit line GBL1 is selected from the global bit lines GBL1 to GBLm, and a first global word line GWL1 is selected from the global word lines GWL1 to GWLn. In addition, a first common selection line C_SL1 is selected from the common selection lines C_SL1 to C_SLk.

[0055] A selection voltage may be applied to the selected first common selection line C_SL1, while a non-selection voltage may be applied to the unselected second to kth common selection lines C_SL2 to C_SLk. The selection voltage may be a voltage sufficient to turn on the first selection transistors ST11 to ST1m and the second selection transistors ST21 to ST2n, such as a power supply voltage. The non-selection voltage may be a voltage that does not turn on or off the first selection transistors ST11 to ST1m and the second selection transistors ST21 to ST2n, such as a ground voltage.

[0056] When the first global bit line GBL1 is selected, a bit line voltage may be applied to the first bit lines BL11 to BL1k. Because the first common selection line C_SL1 is selected, only the first selection transistor ST11 coupled to the first common selection line C_SL1 is turned on. Therefore, only the first bit line BL11 of the first bit lines BL11 to BL1k is coupled to the first global bit line GBL1, and a bit line voltage may be applied only to the first bit line BL11.

[0057] When the first global word line GWL1 is selected, a word line voltage may be applied to the first word lines WL11 to WLk1. Because the first common selection line C_SL1 is selected, only the second selection transistor ST21 coupled to the first common selection line C_SL1 is turned on. Therefore, only the first word line WL11 of the first word lines WL11 to WLk1 is coupled to the first global word line GWL1, and a word line voltage may be applied only to the first word line WL11.

[0058] According to the above structure and operation method, a desired memory cell can be selected from the memory cells MC11 to MCmn by using the common selection lines C_SL1 to C_SLk. Each memory cell MC11 to MCmn can be randomly accessed. Therefore, a program operation, an erase operation, or a read operation can be performed on the selected memory cell. In the embodiment of the present disclosure, a set operation, a reset operation, or a read operation can be performed on the selected memory cell.

[0059] Figure 4 1 is a diagram for explaining the structure of a semiconductor device according to an embodiment of the present disclosure. Descriptions of structures or elements substantially the same as those described above will not be repeated.

[0060] Reference Figure 4 , the semiconductor device may include odd word lines WL_O and even word lines WL_E. The odd word lines WL_O may be stacked in the third direction III, and the even word lines WL_E may be stacked in the third direction III. The odd word lines WL_O and the even word lines WL_E may be arranged side by side in the second direction II.

[0061] The bit line BL may be disposed between a pair of odd and even word lines WL_O and WL_E located on the same horizontal plane. Each of the pair of odd and even word lines WL_O and WL_E may be formed as a portion of a sidewall surrounding the bit line BL. Odd memory cells MC_O may be disposed in a region or area where the bit line BL and the odd word line WL_O intersect. Even memory cells MC_O may be disposed in a region or area where the bit line BL and the even word line WL_E intersect. The pair of odd and even memory cells MC_O and MC_E may share the bit line BL.

[0062] The memory layer ME may be formed to surround the sidewall of the bit line BL. The pair of odd memory cells MC_O and even memory cells MC_E sharing the bit line BL may share the memory layer ME. The memory layer ME may include a variable resistance layer.

[0063] The first selection transistor ST1 may be disposed in an area where the first contact plug CT1 and the common selection line C_SL intersect. The common selection line C_SL may completely surround the sidewalls of the first contact plug CT1 in a plane defined by the first direction I and the second direction II. The first selection transistor ST1 may include a first channel layer, a first gate insulating layer GI1, and a first gate electrode. The first gate electrode may completely surround the sidewalls of the first channel layer in a plane defined by the first direction I and the second direction II.

[0064] The first contact plug CT1 may be coupled to the corresponding bit line BL. Therefore, when the first selection transistor ST1 is turned on, a bit line voltage of the global bit line GBL may be applied to the bit line BL through the first contact plug CT1.

[0065] The second odd selection transistor ST2_O may be disposed in a region or area where the second odd contact plug CT2_O and the common selection line C_SL intersect. The common selection line C_SL may surround a portion of a sidewall of the second odd contact plug CT2_O in a plane defined by the first direction I and the second direction II. The second odd selection transistor ST2_O may include a second channel layer, a second gate insulating layer GI2, and a second gate electrode. The second gate electrode may surround a portion of a sidewall of the second channel layer in a plane defined by the first direction I and the second direction II.

[0066] The second even selection transistor ST2_E may be disposed in a region or area where the second even contact plug CT2_E and the common selection line C_SL intersect. The common selection line C_SL may surround a portion of a sidewall of the second even contact plug CT2_E in a plane defined by the first direction I and the second direction II. The second even selection transistor ST2_E may include a second channel layer, a second gate insulating layer GI2, and a second gate electrode. The second gate electrode may surround a portion of a sidewall of the second channel layer in a plane defined by the first direction I and the second direction II.

[0067] A pair of second odd selection transistors ST2_O and second even selection transistors ST2_E may be coupled to the same common selection line C_SL. The second odd selection transistors ST2_O and second even selection transistors ST2_E linearly arranged along the first direction I may share the common selection line C_SL.

[0068] The second odd contact plugs CT2_O may be coupled to corresponding odd word lines WL_O. Therefore, when the second odd selection transistors ST2_O are turned on, a word line voltage of an odd global word line may be applied to the odd word line WL_O through the second odd contact plugs CT2_O.

[0069] The second even contact plug CT2_E may be coupled to the corresponding even word line WL_E. Thus, when the second even selection transistor ST2_E is turned on, the word line voltage of the even global word line may be applied to the even word line WL_E through the second even contact plug CT2_E.

[0070] The second odd contact plug CT2_O may be coupled to the odd word line WL_O directly or via the third contact plug CT3 . Similarly, the second even contact plug CT2_E may be coupled to the even word line WL_E directly or via the third contact plug CT3 .

[0071] Figure 5A and Figure 5Bare views for explaining the structure and operation method of a semiconductor device according to an embodiment of the present disclosure.

[0072] Reference Figure 5A and 5B The semiconductor device may include first to mth bit lines BL11 to BLmk, first to kth odd word lines WL11_O to WLkn_O, first to kth even word lines WL11_E to WLkn_E, odd memory cells MC11_O to MCmn_O, even memory cells MC11_E to MCmn_E, first select transistors ST11 to ST1m, second odd select transistors ST21_O to ST2n_O, and second even select transistors ST21_E to ST2n_E. Furthermore, the semiconductor device may include first to kth common select lines C_SL1 to C_SLk, first to mth global bit lines GBL1 to GBLm, first to nth odd global word lines GWL1_O to GWLn_O, and first to nth even global word lines GWL1_E to GWLn_E. Here, m and n may be integers equal to or greater than 2, and k may be an integer equal to or greater than 1.

[0073] First selection transistors ST11 to ST1m control coupling between first bit lines BL11 to BLm1 and first to mth global bit lines GBL1 to GBLm. In an embodiment of the present disclosure, when the first selection transistor ST11 is turned on, the first bit line BL11 and the first global bit line GBL1 are coupled.

[0074] The second odd selection transistors ST21_O to ST2n_O control the coupling between the first odd word lines WL11_O to WL1n_O and the first to nth odd global word lines GWL1_O to GWLn_O. In an embodiment of the present disclosure, when the second odd selection transistors ST21_O are turned on, the first odd word line WL11_O and the first odd global word line GWL1_O are coupled.

[0075] The second even selection transistors ST21_E to ST2n_E control the coupling between the first even word lines WL11_E to WL1n_E and the first to nth even global word lines GWL1_E to GWLn_E. In an embodiment of the present disclosure, when the second even selection transistors ST21_E are turned on, the first even word line WL11_E and the first even global word line GWL1_E are coupled.

[0076] The gate electrodes of the first selection transistors ST11 to ST1m, the gate electrodes of the second odd selection transistors ST21_O to ST2n_O, and the gate electrodes of the second even selection transistors ST21_E to ST2n_E may be coupled to a first common selection line C_SL1. In other words, the first common selection line C_SL1 may collectively control the first selection transistors ST11 to ST1m, the second odd selection transistors ST21_O to ST2n_O, and the second even selection transistors ST21_E to ST2n_E.

[0077] With this structure, a desired memory cell can be selected from the odd memory cells MC11_O to MCmn_O and the even memory cells MC11_E to MCmn_E using common select lines C_SL1 to C_SLk. Using a single common select line C_SL1, both the first even word lines WL11_E to WL1n_E and the first bit line BL11 can be selected simultaneously, or both the first odd word lines WL11_O to WL1n_O and the first bit line BL11 can be selected simultaneously. Therefore, each of the even memory cells MC11_E to MCmn_E and the odd memory cells MC11_O to MCmn_O can be randomly accessed.

[0078] An embodiment of selecting a first odd-numbered memory cell MC11_O will now be described. A first global bit line GBL1 is selected from among the global bit lines GBL1 to GBLm, and a first odd-numbered global word line GWL1_O is selected from among the global word lines GWL1_O to GWLn_O and GWL1_E to GWLn_E. Furthermore, a first common select line C_SL1 is selected from among the common select lines C_SL1 to C_SLk. A select voltage may be applied to the selected first common select line C_SL1, while a non-select voltage may be applied to the unselected second to kth common select lines C_SL2 to C_SLk.

[0079] When the first global bit line GBL1 is selected, a bit line voltage may be applied to the first bit lines BL11 to BL1k. Because the first common selection line C_SL1 is selected, only the first selection transistor ST11 coupled to the first common selection line C_SL1 is turned on. Therefore, only the first bit line BL11 of the first bit lines BL11 to BL1k is coupled to the first global bit line GBL1, and a bit line voltage may be applied only to the first bit line BL11.

[0080] When the first odd global word line GWL1_O is selected, a word line voltage may be applied to the first odd word lines WL11_O through WLk1_O. Because the first common select line C_SL1 is selected, only the second odd select transistor ST21_O coupled to the first common select line C_SL1 is turned on. Therefore, only the first odd word line WL11_O of the first odd word lines WL11_O through WLk1_O is coupled to the first odd global word line GWL1_O, and a word line voltage may be applied only to the first odd word line WL11_O.

[0081] With the above-described structure and operating method, a desired memory cell can be selected from the odd-numbered memory cells MC11_O to MCmn_O and the even-numbered memory cells MC11_E to MCmn_E using common select lines C_SL1 to C_SLk. Consequently, each of the odd-numbered memory cells MC11_O to MCmn_O and the even-numbered memory cells MC11_E to MCmn_E can be randomly accessed. Consequently, a program operation, an erase operation, or a read operation can be performed on the selected memory cell. In embodiments of the present disclosure, a set operation, a reset operation, or a read operation can be performed on the selected memory cell.

[0082] Figure 6 is a configuration diagram of a microprocessor for implementing a storage device according to an embodiment of the present disclosure.

[0083] Reference Figure 6 The microprocessor 1000 may control and coordinate a series of processes of receiving data from various external devices, processing the data, and then sending the results to the external devices, and may include a memory 1010, an operation component 1020, a controller 1030, etc. The microprocessor 1000 may be any of various data processing devices, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), an application processor (AP), etc.

[0084] The memory 1010 may include registers, processor registers, and the like, which may be components for storing data in the microprocessor 1000, including data registers, address registers, floating-point registers, and other various registers. The memory 1010 may be used to temporarily store data to be subjected to an operation performed by the operation unit 1020 or data generated by the operation, as well as addresses for storing the data.

[0085] The memory 1010 may include one or more embodiments of the electronic device described above. For example, the memory 1010 may include bit lines, word lines, a resistive memory cell coupled between the bit lines and the word lines, a first select transistor for controlling coupling between a global bit line and the bit line, a second select transistor for controlling coupling between a global word line and the word line, and a common select line for jointly controlling the first select transistor and the second select transistor. This can improve the integration and operational characteristics of the memory 1010. As a result, the operational characteristics of the microprocessor 1000 can be enhanced.

[0086] The operation component 1020 may perform four basic mathematical operations or logic operations based on the result of decrypting the command by the controller 1030. The operation component 1020 may include one or more arithmetic and logic units (ALUs).

[0087] The controller 1030 may receive signals from the memory 1010 , the operating component 1020 , or external devices of the microprocessor 1000 , extract or decrypt commands, control the signal input or output of the microprocessor 1000 , and execute processes indicated in a program.

[0088] In an embodiment of the present disclosure, the microprocessor 1000 may further include a cache memory 1040 that temporarily stores data to be input from or output to external devices other than the memory 1010. In this case, the cache memory 1040 may exchange data with the memory 1010, the operation component 1020, and the controller 1030 through the bus interface 1050.

[0089] Figure 7 is a configuration diagram of a microprocessor for implementing a storage device according to an embodiment of the present disclosure.

[0090] Reference Figure 7 , the processor 1100 can enable performance enhancement and can utilize various capabilities in addition to those of a microprocessor to implement various functions. The processor 1100 controls and coordinates a series of processes of receiving data from multiple external devices, processing the data, and then sending the results to the external devices. The processor 1100 may include: a core 1110 serving as a microprocessor; a cache memory 1120 for temporarily storing data; and a bus interface 1130 for transmitting data between internal devices and external devices. The processor 1100 may include various systems on a chip (SoCs) such as a multi-core processor, a GPU, an AP, etc.

[0091] In an embodiment of the present disclosure, the core 1110 may be a component for performing arithmetic and logical operations on data input from an external device, and may include a memory 1111 , an operation component 1112 , and a controller 1113 .

[0092] The memory 1111 may be a register, a processor register, or the like that is a component for storing data in the processor 1100, and may include data registers, address registers, floating-point registers, and various other registers. The memory 1111 may be used to temporarily store data to be subjected to an operation performed by the operation component 1112 or data generated by the operation, as well as the address where the data is stored. The operation component 1112 may be a component for performing an operation in the processor 1100, and may perform four basic mathematical operations or logical operations based on the result of decrypting the command by the controller 1113. The operation component 1112 may include one or more arithmetic and logic units (ALUs). The controller 1113 may receive signals from the memory 1111, the operation component 1112, an external device of the processor 1100, etc., extract or decrypt commands, control the signal input or output of the processor 1100, and execute the process represented in the program.

[0093] The cache memory 1120 may be a component for temporarily storing data to compensate for the difference in data processing speed between the high-speed core 1110 and the slower-speed external devices, and may include a primary storage unit 1121, a secondary storage unit 1122, and a tertiary storage unit 1123. The cache memory 1120 may typically include primary and secondary storage units 1121 and 1122, and may further include a tertiary storage unit 1123 when higher capacity is required, or when even more storage units are needed as needed. That is, the number of storage units included in the memory 1120 may vary depending on the design. Furthermore, the processing rates for storing and identifying data in the primary, secondary, and tertiary storage units 1121, 1122, and 1123 may be the same or different. When each storage unit has a different processing rate, the primary storage unit may have the highest rate. One or more of the primary storage unit 1121, secondary storage unit 1122, and tertiary storage unit 1123 of the cache memory 1120 may include one or more of the aforementioned embodiments of the electronic device. For example, the cache memory 1120 may include a bit line, a word line, a resistive memory cell coupled between the bit line and the word line, a first selection transistor for controlling coupling between a global bit line and the bit line, a second selection transistor for controlling coupling between a global word line and the word line, and a common selection line for jointly controlling the first selection transistor and the second selection transistor. As a result, the operating characteristics of the processor 1100 can be enhanced.

[0094] Despite Figure 7While the primary, secondary, and tertiary storage units 1121, 1122, and 1123 are shown as being located within the cache memory 1120, all of the primary, secondary, and tertiary storage units 1121, 1122, and 1123 may be located outside the core 1110 to compensate for differences in processing speed between the core 1110 and external devices. In some embodiments, the primary storage unit 1121 of the cache memory 1120 may be located within the core 1110, while the secondary and tertiary storage units 1122 and 1123 may be located outside the core 1110 to further enhance the performance of compensating for storage units with different processing speeds. In other embodiments, for similar reasons, the primary storage unit 1121 and the secondary storage unit 1122 may be located within the core 1110, while the tertiary storage unit 1123 may be located outside the core 1110.

[0095] The bus interface 1130 is a component that couples the core 1110 , the cache memory 1120 , and external devices to each other in order to efficiently transfer data.

[0096] In an embodiment of the present disclosure, the processor 1100 may include multiple cores 1110, which may share a cache memory 1120. The multiple cores 1110 and the cache memory 1120 may be directly coupled (not shown) or coupled via a bus interface 1130. All cores in the multiple cores 1110 may be configured in the same or substantially the same manner as the above-mentioned cores. When the processor 1100 includes multiple cores 1110, the primary storage unit 1121 of the cache memory 1120 may be configured in each core of the multiple cores 1110, and the secondary storage unit 1122 and the tertiary storage unit 1123 may be configured outside the multiple cores 1110 and may be shared through the bus interface 1130. The processing rate of the primary storage unit 1121 may be higher than the processing rates of the secondary and tertiary storage units 1122 and 1123. In an embodiment of the present disclosure, the primary and secondary storage units 1121 and 1122 may be configured in each of the plurality of cores 1110 , and the tertiary storage unit 1123 may be configured outside the plurality of cores 1110 and may be shared through the bus interface 1130 .

[0097] In an embodiment of the present disclosure, the processor 1100 may further include: an embedded memory 1140 for storing data; a communication module 1150 for transmitting or receiving data to or from an external device via a wired or wireless interface; a memory controller 1160 for driving an external storage device; a media processor 1170 for manipulating and outputting data processed by the processor 1100 or input from an external device; and various other modules and devices. In this case, the multiple added modules can exchange data with each other, the core 1110, and the cache memory 1120 via the bus interface 1130.

[0098] The embedded memory 1140 may include not only volatile memory but also non-volatile memory. The volatile memory may include dynamic random access memory (DRAM), mobile DRAM, static RAM (SRAM), and memories having similar functions, and the non-volatile memory may include read-only memory (ROM), NOR flash memory, NAND flash memory, phase change RAM (PRAM), resistive RAM (RRAM), spin transfer torque RAM (STTRAM), magnetic RAM (MAM), and memories having similar functions.

[0099] The communication module 1150 may include a module to be coupled to a wired network, a module to be coupled to a wireless network, or both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), etc., or may be similar to various devices for sending or receiving data through a transmission line. The wireless network module may include, for example, infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN (WLAN), Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), etc.

[0100] The memory controller 1160 can be used to process and manage data transmitted between the processor 1100 and external storage devices operating according to different communication standards, and can include any one of a variety of memory controllers, such as a controller for controlling the following devices: integrated device electronics (IDE), serial advanced technology attachment (SATA), small computer system interface (SCSI), redundant array of independent disks (RAID), solid-state disk (SSD), external SATA (eSATA), Personal Computer Memory Card Association (PCMCIA), USB, secure digital card (SD), mini SD (mSD), micro SD, secure digital high-capacity card (SDHC), memory stick card, smart media card (SM), multimedia card (MMC), embedded MMC (eMMC), compact flash card (CF), etc.

[0101] The media processor 1170 may manipulate data processed by the processor 1100 or data input from an external device in a video, sound, or any other format, and output the data to an external interface device. The media processor 1170 may include, for example, a GPU, a DSP, a high-definition audio (HD audio), a high-definition multimedia interface (HDMI) controller, and the like.

[0102] Figure 8 is a configuration diagram of a system for implementing a storage device according to an embodiment of the present disclosure.

[0103] Reference Figure 8 The system 1200 is a device for processing data, which can perform input, processing, output, transmission, etc. on the data to manipulate the data. The system 1200 may include a processor 1210, a primary storage device 1220, an auxiliary storage device 1230, an interface device 1240, etc. In this embodiment, the system 1200 may be any of various electronic systems that operate using a process, such as a computer, a server, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics system, an audio-visual (AV) system, a smart TV, etc.

[0104] The processor 1210 may control input instructions to be interpreted and materials stored in the system 1200 to be operated and compared, and may include a microprocessor unit (MPU), a CPU, a single / multi-core processor, a GPU, an AP, a DSP, etc.

[0105] The main storage device 1220 is a memory for storing program code or materials that are removed from the auxiliary storage device 1230 for execution when the program is running, and its contents can be retained even if the power is off. The main storage device 1220 may include one or more embodiments of the electronic device described above. For example, the main storage device 1220 may include a bit line, a word line, a resistance storage unit coupled between the bit line and the word line, a first selection transistor for controlling the coupling between the global bit line and the bit line, a second selection transistor for controlling the coupling between the global word line and the word line, and a common selection line for jointly controlling the first selection transistor and the second selection transistor. This can improve the integration and operating characteristics of the main storage device 1220. As a result, the operating characteristics of the system 1200 can be enhanced.

[0106] In addition, the main storage device 1220 may also include a volatile memory, such as SRAM, DRAM, etc., the contents of which are all deleted when the power of the main storage device 1220 is turned off. In some other embodiments, the main storage device 1220 may further include a volatile memory, such as SRAM, DRAM, etc., the contents of which are all deleted when the power of the main storage device 1220 is turned off, without including the electronic device according to the above-described embodiments of the present disclosure.

[0107] The auxiliary storage device 1230 is referred to as a storage device for storing program code or data. It can operate at a slower speed than the main storage device 1220, but can store a large amount of material. The auxiliary storage device 1230 may include one or more embodiments of the electronic device described above. For example, the auxiliary storage device 1230 may include a bit line, a word line, a resistive storage cell coupled between the bit line and the word line, a first select transistor for controlling the coupling between the global bit line and the bit line, a second select transistor for controlling the coupling between the global word line and the word line, and a common select line for jointly controlling the first select transistor and the second select transistor. This can improve the integration and operating characteristics of the auxiliary storage device 1230. As a result, the operating characteristics of the system 1200 can be enhanced.

[0108] In addition, the auxiliary storage device 1230 may also include a data storage system 1300 (see Figure 9 ), such as magnetic tape or disk, laser optical disk, magneto-optical disk, solid-state disk (SSD), USB memory, SD, mSD, micro SD, SDHC, memory stick, SM, MMC, eMMC, CF, etc. In some other embodiments, the auxiliary storage device 1230 may include the data storage system 1300 (see Figure 9), such as a magnetic tape or disk using magnetism, a laser optical disk using light, a magneto-optical disk using both a magnetic disk and an optical disk, a solid-state disk (SSD), a USB memory, SD, mSD, micro SD, SDHC, a memory stick, SM, MMC, eMMC, CF, etc., but does not include the electronic devices according to the embodiments of the present disclosure as described above.

[0109] The interface device 1240 can be used to exchange commands, data, etc. between the system 1200 according to an embodiment of the present disclosure and an external device, and can be a keypad, keyboard, mouse, speaker, microphone, display, any of various human interface devices (HIDs), communication devices, etc. The communication device may include a module to be coupled to a wired network, a module to be coupled to a wireless network, or both. The wired network module may include LAN, USB, Ethernet, PLC, etc., and various devices similar to those for sending or receiving data through a transmission line, and the wireless network module may include IrDA, CDMA, TDMA, FDMA, wireless LAN, Zigbee, USN, Bluetooth, RFID, LTE, NFC, Wibro, HSDPA, WCDMA, UWB, etc., and various similar devices that can send or receive data without any transmission line.

[0110] Figure 9 is a configuration diagram of a data storage system for implementing a storage device according to an embodiment of the present disclosure.

[0111] Reference Figure 9 The data storage system 1300 is configured to store data and may include a storage device 1310 having a non-volatile characteristic, a controller 1320 for controlling the data storage system 1300, an interface 1330 for coupling to an external device, and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 may have a disk type such as a hard disk drive (HDD), a compact disc ROM (CD-ROM), a digital versatile disc (DVD), an SSD, etc., and a card type such as a USB memory, SD, mSD, micro SD, SDHC, a memory stick card, SM, MMC, eMMC, CF, etc.

[0112] The storage device 1310 may include a nonvolatile memory for semi-permanently storing data. The nonvolatile memory may include ROM, NOR flash memory, NAND flash memory, PRAM, RRAM, MRAM, etc.

[0113] The controller 1320 may control data to be exchanged between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing an operation to process a command input from outside the data storage system 1300 through the interface 1330.

[0114] Interface 1330 is used to exchange commands and data between data storage system 1300 and external devices. If data storage system 1300 is a card, interface 1330 may be compatible with interfaces used by devices such as USB memory, SD, mSD, micro SD, SDHC, Memory Stick, SM, MMC, eMMC, CF, or similar devices. If data storage system 1300 is a disk, interface 1330 may be compatible with interfaces such as IDE, SATA, SCSI, eSATA, PCMCIA, USB, or similar interfaces. Interface 1330 may be compatible with one or more interfaces of different types.

[0115] To allow for diversification and higher performance of interfaces, controllers, and systems, a temporary storage device 1340 can temporarily store data for efficient data transmission between the interface 1330 and the storage device 1310. The temporary storage device 1340 may include one or more embodiments of the electronic device as described above. For example, the temporary storage device 1340 may include a bit line, a word line, a resistive memory cell coupled between the bit line and the word line, a first selection transistor configured to control the coupling between the global bit line and the bit line, a second selection transistor configured to control the coupling between the global word line and the word line, and a common selection line configured to jointly control the first selection transistor and the second selection transistor. This can improve the integration and operating characteristics of the temporary storage device 1340. As a result, the operating characteristics of the data storage system 1300 can be enhanced.

[0116] Figure 10 is a configuration diagram of a memory system for implementing a storage device according to an embodiment of the present disclosure.

[0117] Reference Figure 10 The memory system 1400 is configured to store data and may include a memory 1410 having a non-volatile characteristic, a memory controller 1420 for controlling the memory system 1400, an interface 1430 for coupling to an external device, etc. The memory system 1400 may have a card type such as SSD, USB memory, SD, mSD, micro SD, SDHC, memory stick card, SM, MMC, eMMC, CF, etc.

[0118] The memory 1410 for storing data may include one or more embodiments of the electronic device described above. For example, the memory 1410 may include bit lines, word lines, a resistive memory cell coupled between the bit lines and the word lines, a first select transistor for controlling the coupling between a global bit line and the bit line, a second select transistor for controlling the coupling between a global word line and the word line, and a common select line for jointly controlling the first select transistor and the second select transistor. This can improve the integration and operational characteristics of the memory 1410. As a result, the operational characteristics of the memory system 1400 can be enhanced.

[0119] In addition, the memory in the embodiment of the present disclosure may include ROM, NOR flash memory, NAND flash memory, PRAM, RRAM, MRAM, etc. having non-volatile characteristics.

[0120] The memory controller 1420 may control data to be exchanged between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing an operation to process a command input from outside the memory system 1400 through the interface 1430.

[0121] The interface 1430 can be used to exchange commands and data between the memory system 1400 and an external device, and can be compatible with interfaces used by devices such as USB memory, SD, mSD, micro SD, SDHC, Memory Stick card, SM, MMC, eMMC, CF, or similar devices. The interface 1430 can be compatible with one or more different types of interfaces.

[0122] In order to follow the trend of diversification and higher performance of interfaces with external devices, memory controllers, and memory systems, the memory system 1400 in the embodiment of the present disclosure may further include a buffer memory 1440 for efficient transmission of input / output data between the interface 1430 and the memory 1410. The buffer memory 1440 for temporarily storing data may include one or more of the above-described embodiments of the electronic device. For example, the buffer memory 1440 may include a bit line, a word line, a resistive memory cell coupled between the bit line and the word line, a first selection transistor for controlling the coupling between the global bit line and the bit line, a second selection transistor for controlling the coupling between the global word line and the word line, and a common selection line for jointly controlling the first selection transistor and the second selection transistor. As a result, the operating characteristics of the memory system 1400 can be enhanced.

[0123] In addition, the buffer memory 1440 in some embodiments of the present disclosure may further include volatile memories such as SRAM and DRAM, and non-volatile memories such as ROM, NOR flash memory, NAND flash memory, PRAM, RRAM, STTRAM, MRAM, etc. However, in other embodiments, the buffer memory 1440 may include volatile memories such as SRAM and DRAM, and non-volatile memories such as ROM, NOR flash memory, NAND flash memory, PRAM, RRAM, STTRAM, MRAM, etc., excluding the electronic device according to the above embodiments.

[0124] According to the embodiments of the present disclosure, the operational characteristics and reliability of a semiconductor device may be enhanced.

[0125] Examples of embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as of the date of filing this application, it will be apparent to one of ordinary skill in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically noted. Therefore, those skilled in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A semiconductor device comprising: a stack including word lines; a bit line penetrating the stack; a global bit line disposed above the stack; a global word line disposed above the stack; a common select line disposed above the stack; a first contact plug coupling the global bit line and the bit line to each other and penetrating the common selection line; and A second contact plug couples the global word line and the word line to each other and penetrates the common selection line, wherein the common selection line surrounds at least a portion of a sidewall of the first contact plug.

2. The semiconductor device according to claim 1, wherein The common selection line commonly controls coupling between the global bit line and the bit line and coupling between the global word line and the word line.

3. The semiconductor device according to claim 1 , further comprising: a first gate insulating layer interposed between the first contact plug and the common selection line; and A second gate insulating layer is interposed between the second contact plug and the common selection line.

4. The semiconductor device according to claim 1 , further comprising: a first selection transistor disposed in a region where the first contact plug and the common selection line intersect; and A second selection transistor is provided in a region where the second contact plug and the common selection line intersect. The semiconductor device according to claim 1 , wherein The common selection line completely surrounds a sidewall of the first contact plug in a cross section defined by a first direction and a second direction. The semiconductor device according to claim 1 , wherein: The common selection line partially surrounds a sidewall of the first contact plug in a cross section defined by a first direction and a second direction.

7. The semiconductor device according to claim 1, wherein The common selection line is provided between the global bit line and the bit line, and between the global word line and the word line.

8. The semiconductor device according to claim 1, wherein The word lines include odd word lines and even word lines, and the bit lines are disposed between pairs of odd and even word lines.

9. The semiconductor device according to claim 1, further comprising: A first selection transistor is provided in a region where the first contact plug and the common selection line intersect, and is turned on when a selection voltage is applied to the common selection line.

10. The semiconductor device according to claim 9, further comprising: A second selection transistor is provided in a region where the second contact plug and the common selection line intersect, and is turned on when the selection voltage is applied to the common selection line. The semiconductor device according to claim 10 , wherein: When a non-select voltage is applied to the common selection line, the first selection transistor and the second selection transistor are turned off.

12. The semiconductor device according to claim 9, wherein: The word lines include even word lines and odd word lines, and the global word lines include even global word lines and odd global word lines, and The semiconductor device also includes: a second even selection transistor, which is arranged in a region where a second contact plug coupled to the even global word line intersects the common selection line; and a second odd selection transistor, which is arranged in a region where a second contact plug coupled to the odd global word line intersects the common selection line.

13. The semiconductor device according to claim 12, wherein When a selection voltage is applied to the common selection line, the first selection transistor, the second even selection transistor, and the second odd selection transistor are turned on.

14. The semiconductor device according to claim 1, wherein The word lines extend in a first direction, and the global bit lines and the global word lines extend in a second direction intersecting the first direction.

15. The semiconductor device according to claim 14, wherein The common selection line extends in the first direction.

16. The semiconductor device according to claim 1, wherein The word lines are stacked in a staircase shape.

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