Memory system and method of operating a memory device included therein

Abstract

The present application discloses a memory system and an operating method of a memory device included therein. A memory system includes: a plurality of memory devices including a memory cell array having a plurality of planes, the plurality of memory devices being commonly connected to a memory controller through a channel; a super block including pages included in the planes of at least two memory devices among the plurality of memory devices; and a memory controller sending at least one command indicating an operation on the super block and an address corresponding to the command to the memory device. Each memory device includes: a peripheral circuit for performing an operation on the memory cell array; a group selection signal generator for outputting a group selection signal indicating the at least two memory devices constituting the super block; and a control logic for controlling the peripheral circuit to perform an operation corresponding to the command based on the group selection signal.

Description

Technical Field

[0001] The present disclosure relates generally to a memory system, and more particularly, to a memory system and an operating method of a memory device included in the memory system. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device that stores data and a storage controller that controls the memory device. The memory device is classified into a volatile memory device and a non-volatile memory device.

[0003] A volatile memory device is a memory device that stores data only when power is supplied, and the stored data disappears when power is interrupted. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0004] A nonvolatile memory device is a memory device in which data does not disappear even when power is interrupted. Nonvolatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the invention

[0005] According to one aspect of the present disclosure, a memory system is provided. The memory system may include: a plurality of memory devices including a memory cell array having a plurality of planes, the plurality of memory devices being commonly connected to a memory controller through a channel; a super block including pages included in the planes of at least two memory devices among the plurality of memory devices; and a memory controller configured to send at least one command indicating an operation on the super block and an address corresponding to the command to the memory device.

[0006] Each memory device may include: a peripheral circuit configured to perform an operation on a memory cell array; a group selection signal generator configured to output a group selection signal indicating the at least two memory devices constituting the super block; and control logic configured to control the peripheral circuit to perform an operation corresponding to a command based on the group selection signal.

[0007] According to another aspect of the present disclosure, a method for operating a memory device may be provided, the method may include the following steps: receiving a group address assignment command and a first group address from a storage controller; storing the first group address in a group address register in response to the group address assignment command; receiving a group selection command and a second group address from the storage controller; generating a group selection signal based on a result obtained by comparing the first group address and the second group address in response to the group selection command; receiving at least one command indicating an operation on a super block and an address corresponding to the command from the storage controller; and performing an operation corresponding to the command based on the group selection signal.

[0008] The memory device may include multiple planes and be connected to a memory controller through channels.

[0009] The super block may include pages included in planes of at least two memory devices among a plurality of memory devices commonly connected to the memory controller through a channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Examples of implementations will now be described below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the implementations set forth herein. Rather, these implementations are provided so that this disclosure will be thorough and complete, and will convey the scope of the examples of implementations to those skilled in the art.

[0011] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0012] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 A diagram showing signals exchanged between a memory controller and a memory device.

[0014] Figure 3 It is shown Figure 1 A diagram of a memory device is shown.

[0015] Figure 4 It is shown Figure 3 A diagram of an embodiment of a memory cell array is shown.

[0016] Figure 5 It is shown Figure 4 A diagram of a memory block is shown.

[0017] Figure 6 It is shown Figure 4A diagram of an embodiment of a three-dimensional configuration of memory blocks is shown.

[0018] Figure 7 It is shown Figure 4 FIG. 2 is a diagram of another embodiment of a three-dimensional configuration of memory blocks.

[0019] Figure 8 It is shown Figure 1 A diagram of a multi-plane structure in a memory device is shown.

[0020] Fig. 9 is a conceptual diagram illustrating a super block according to an embodiment of the present disclosure.

[0021] Fig.10 It is shown that read Fig. 9 A timing diagram of a read operation of pages included in a superblock is shown.

[0022] Fig.11 is to show that data is programmed in Fig. 9 A timing diagram of a programming operation in pages included in a super block is shown.

[0023] Fig.12 is shown by using the group address selection configuration Fig. 9 A timing diagram illustrating the concept of minimizing command transmissions by using at least two memory devices of a super-block is shown.

[0024] Fig.13 It is shown in Fig.12 A timing diagram showing a case where a read command is received after at least two memory devices constituting a super block are selected.

[0025] Fig.14 It is shown in Fig.12 A timing diagram showing a case where a program command is received after at least two memory devices constituting a super block are selected.

[0026] Fig.15 It is shown Figure 3 An example of a diagram of a group selection signal generator is shown.

[0027] Fig.16 It shows reference Figures 9 to 15 An example of a flowchart of a method of operating a memory device is described.

[0028] Fig.17 It shows that the application Figure 1 A diagram of a memory card of a memory system is shown.

[0029] Fig.18 It shows that the application Figure 1 A block diagram of an SSD system of a memory system is shown. DETAILED DESCRIPTION

[0030] In order to describe the embodiments of the concepts according to the present disclosure, the specific structural or functional descriptions disclosed herein are only illustrative. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein.

[0031] Embodiments provide a memory system capable of quickly performing a program operation or a read operation on a super block configured using at least two memory devices and an operating method of a memory device included in the memory system.

[0032] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0033] Reference Figure 1 , the memory system 1000 may include a memory device 1100 storing data and / or a memory controller 1200 controlling the memory device 1100 according to a request of a host 2000 .

[0034] The host 2000 may communicate with the memory system 1000 using at least one of various communication schemes such as a universal serial bus (USB), a serial AT attachment (SATA), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a firewire, a peripheral component interconnect (PCI), a high-speed PCI (PCIe), a high-speed non-volatile memory (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduction DIMM (LRDIMM).

[0035] The memory device 1100 may be implemented as a volatile memory device in which data disappears when power is interrupted or a non-volatile memory device in which data is retained even when power is interrupted. The memory device 1100 may perform a programming operation, a read operation, or an erase operation under the control of the storage controller 1200. For example, in a programming operation, the memory device 1100 may receive a command, an address, and data input from the storage controller 1200, and perform a programming operation. In a read operation, the memory device 1100 may receive a command and an address input from the storage controller 1200, and output data stored at a location (e.g., a physical address) corresponding to the input address to the storage controller 1200. The memory device 1100 is a separate integrated chip (IC) that fully performs device processing, and may be designated as a chip or a die.

[0036] The memory system 1000 may include a plurality of memory devices 1100, and the plurality of memory devices may be grouped into a plurality of memory device groups 1300 according to channels connected to the memory controller 1200. For example, memory devices connected to the memory controller 1200 through a first channel CH1 among the memory devices may be designated as a first group GR1, and memory devices connected to the memory controller 1200 through a second channel CH2 among the memory devices may be designated as a second group GR2. Figure 1 1100 , but one group may include a single memory device 1100 .

[0037] The memory controller 1200 may control the overall operation of the memory system 1000 and control data exchange between the host 2000 and the memory device 1100. For example, when receiving a command from the host 2000, the memory controller 1200 may control the memory device group 1300 connected to each of the channels CH1 to CHk according to the received command. The memory controller 1200 may program, read, or erase data by controlling the memory device group 1300 connected to each channel according to a request of the host 2000.

[0038] Figure 2 It is shown Figure 1 A diagram showing signals exchanged between a memory controller and memory devices.

[0039] Reference Figure 2 , the memory controller 1200 and the memory device 1100 may exchange commands, data and / or addresses through the input / output pad DQ. For example, the input / output pad DQ may be configured with 8 lines to send / receive 8-bit data, and each line may send / receive 1-bit data.

[0040] The memory device 1100 may receive a chip enable signal through the CE# pad, a write enable signal through the WE# pad, a read enable signal through the RE# pad, an address latch enable signal through the ALE pad, a command latch enable signal through the CLE pad, and a write protection signal through the WP# pad.

[0041] The address latch enable signal may be a signal used by the memory controller 1200 to instruct the memory device 1100 to load the address provided to the memory device 1100 through the input / output pad DQ into the address register. The chip enable signal may be a signal used by the memory controller 1200 to instruct the memory device 1100 to enable or disable one or more memory devices. The command latch enable signal may be a signal used by the memory controller 1200 to instruct the memory device 1100 to load the command provided to the memory device 1100 through the input / output pad DQ into the command register. The read enable signal may be a signal used by the memory controller 1200 to instruct the memory device 1100 to send data to the memory controller 1200. The write enable signal may be a signal that informs that the command, address, and data are transmitted.

[0042] The memory device 1100 may output a ready-busy signal to the memory controller 1200 through the RB pad. The ready-busy signal may indicate whether the memory array of the memory device 1100 is in a busy state or an idle state.

[0043] although Figure 2 , the connection relationship between one memory device 110 and the memory controller 1200 is shown, but the input / output pads DQ, CE# pads, WE# pads, RE# pads, ALE pads, CLE pads and WP# pads can form one of the channels CH1 to CHk, and one of the memory device groups 1300 can be connected to the memory controller 120 through the formed channels.

[0044] Therefore, when the memory controller 1200 transmits a command, data, and / or address through the input / output pad DP included in one channel, all memory devices 1100 belonging to the group connected to the corresponding channel or the memory device 1100 selected by the memory controller 1200 in the group connected to the corresponding channel may receive the command, data, and / or address. For example, the memory controller 1200 may transmit a status read command to the memory device 1100 through the input / output pad DQ corresponding to the first channel CH1, and at least one memory device in the first group GR1 connected to the first channel CH1 may transmit status information to the input / output pad DQ as a response to the status read command.

[0045] Figure 3 It is shown Figure 1 A diagram of a memory device is shown.

[0046] The memory device 1100 may be implemented as a volatile memory device or a nonvolatile memory device. For example, the memory device 1100 may be a volatile memory device such as a dynamic random access memory (DRAM) or a static RAM (SRAM) and a nonvolatile memory device such as a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EROM), an electrically erasable ROM (EEROM), a ferromagnetic ROM (FROM), a phase change RAM (PRAM), a resistive RAM (RRAM), or a flash memory. Figure 3 , a nonvolatile memory device will be shown as an example.

[0047] The memory device 1100 may include a memory cell array 100 storing data. The memory device 1100 may include a peripheral circuit 200 configured to perform a program operation of storing data in the memory cell array 100, a read operation of outputting the stored data, and an erase operation of erasing the stored data. The memory device 1100 may include a control logic 300 that controls the peripheral circuit 200 under the control of the memory controller 1200. The control logic 300 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 300 may be a control logic circuit operating according to an algorithm and / or a processor that executes a control logic code.

[0048] The memory cell array 100 includes a plurality of memory cells storing data. For example, the memory cell array 100 may include at least one plane, and the plane may include one or more memory blocks. In an embodiment, a plane may be a unit for accessing a memory area when performing a programming operation, a read operation, or an erase operation. Each memory block may include a plurality of memory cells. A structure including a plurality of planes may be designated as a multi-plane structure. User data and information required for the operation of the memory device 1100 may be stored in a memory block. The memory block may be implemented in a two-dimensional or three-dimensional structure. A memory block having a two-dimensional structure may include memory cells arranged parallel to a substrate, and a memory block having a three-dimensional structure may include memory cells stacked perpendicular to a substrate.

[0049] The peripheral circuit 200 may be configured to perform a program operation, a read operation, and an erase operation under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, and a current sensing circuit 260.

[0050] The voltage generation circuit 210 may generate various operation voltages Vop for program operation, read operation, and erase operation in response to the operation signal OP_CMD output from the control logic 300. For example, the voltage generation circuit 210 may generate various voltages such as a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage under the control of the control logic 300.

[0051] The row decoder 220 may supply the operating voltage Vop to the local line LL of the selected memory block among the memory blocks of the memory cell array 100 in response to the row address RADD output from the control logic 300. The local line LL may include a local word line, a local drain selection line, and / or a local source selection line. In addition, the local line LL may include various lines connected to the memory block, such as a source line.

[0052] The page buffer group 230 may be connected to the bit lines BL1 to BLI connected to the memory blocks of the memory cell array 100. The page buffer group 230 may include a plurality of page buffers PB1 to PBI connected to the bit lines BL1 to BLI. The page buffers PB1 to PBI may operate in response to the page buffer control signal PBSIGNALS output from the control logic 300. For example, the page buffers PB1 to PBI may temporarily store data received through the bit lines BL1 to BLI, or sense a voltage or current of the bit lines BL1 to BLI in a read operation or a verification operation.

[0053] The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD output from the control logic 300. For example, the column decoder 240 may exchange data with the page buffers PB1 to PBI through the data lines DL or with the input / output circuit 250 through the column lines CL.

[0054] The input / output circuit 250 may receive a command CMD, an address ADD, and data from the controller 1200 through the input / output pad DQ, and output data read from the memory cell array 100 to the memory controller 1200 through the input / output pad DQ. For example, the input / output circuit 250 may transfer the command CMD and the address ADD received from the memory controller 1200 to the control logic 300, or exchange data DATA with the column decoder 240.

[0055] In a read operation or a verification operation, the current sensing circuit 260 may generate a reference current in response to the enable bit VRY_BIT<#> and output a pass signal PASS or a fail signal FAIL by comparing a reference voltage generated by the reference current with a sensing voltage VPB received from the page buffer group 230 .

[0056] In response to the signals received through the CE# pad, the WE# pad, the RE# pad, the ALE pad, the CLE pad, and the WP# pad, the control logic 300 may receive a command CMD and an address ADD. In response to the control logic 300 receiving the command CMD and the address ADD, the control logic 300 may generate a control signal for the peripheral circuit 200 and output the generated control signal to the peripheral circuit 200. For example, the control signal may include at least one of an operation signal OP_CMD, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRY_BIT<#>. The control logic 300 may output the operation signal OP_CMD to the voltage generation circuit 210, the row address RADD to the row decoder 220, the page buffer control signal PBSIGNALS to the page buffer group 230, and the enable bit VRY_BIT<#> to the current sensing circuit 260. In addition, the control logic 300 may determine whether the verification operation passes or fails in response to the pass signal PASS or the fail signal FAIL.

[0057] The memory device 1100 may include a group selection signal generator 400 that generates a group selection signal SGRP and outputs the group selection signal SGRP to the control logic 300 , and a group address register 500 that stores a group address GADD.

[0058] The group address GADD may be an address commonly allocated to at least two memory devices constituting a super block SBLK configured with pages included in planes P1 to P4 included in the at least two memory devices to perform an operation (eg, a program operation or a read operation) on the super block SBLK.

[0059] In addition, the control logic 300 may receive the group address assignment commands D5h to AAh and the group selection command AAh through the input / output circuit 250 as commands that the memory controller 1200 transmits to at least two memory devices constituting the super block SBLK.

[0060] The control logic 300 may store the group address GADD received from the memory controller 1200 through the input / output circuit 250 in the group address register 500 corresponding to the group address allocation command, generate a signal corresponding to the stored operation, and provide the generated signal to the group selection signal generator 400 .

[0061] The control logic 300 may compare the group address received together with the group selection command with the group address GADD stored in the group address register 500 , generate a signal indicating a comparison result, and provide the generated signal to the group selection signal generator 400 .

[0062] The group selection signal generator 400 may generate the group selection signal SGRP as a signal indicating at least two memory devices constituting the super block SBLK. For example, the group selection signal generator 400 may generate the group selection signal SGRP based on a group address allocation command received from the memory controller 1200 and a signal generated by the control logic 300 according to the group selection command (however, the signal may be generated by another independent signal generation circuit other than the control logic 300).

[0063] When the group selection signal SGRP is output from the group selection signal generator 400 , the control logic 300 may respond to a command received from the memory controller 1200 based on the group selection signal SGRP or control a reset operation of the page buffer group 230 by controlling the peripheral circuit 200 .

[0064] Figure 4 It is shown Figure 3 A diagram of an embodiment of a memory cell array is shown.

[0065] Reference Figure 4 , the memory cell array 100 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate (not shown). The plurality of memory cells may be arranged along +X, +Y, and +Z directions.

[0066] Figure 5 It is shown Figure 4 A diagram of a memory block is shown.

[0067] Reference Figure 5 , showing by way of example Figure 4 A first memory block BLK1 among a plurality of memory blocks BLK1 to BLKz is shown. The other memory blocks BLK2 to BLKz may have the same form as the first memory block BLK1.

[0068] The first memory block BLK1 may include a plurality of cell strings ST connected between the bit lines BL1 to BLI and the source line SL. For example, the cell strings ST may be connected to the bit lines BL1 to BLI, respectively, and commonly connected to the source line SL. Since the cell strings ST are configured similarly to each other, the cell string ST connected to the first bit line BL1 among the cell strings ST will be described as an example.

[0069] The cell string ST may include a source selection transistor SST, first to nth memory cells F1 to Fn (n is a positive integer), and a drain selection transistor DST connected in series with each other between a source line SL and a first bit line BL1. The number of the source selection transistors SST and the drain selection transistors DST is not limited to Figure 5As shown. The source selection transistor SST may be connected between the source line SL and the first memory cell F1. The first memory cell F1 to the nth memory cell Fn may be connected in series with each other between the source selection transistor SST and the drain selection transistor DST. The drain selection transistor DST may be connected between the nth memory cell Fn and the first bit line BL1. Although not shown in the figure, a dummy cell may be further connected between the memory cells F1 to Fn or between the source selection transistor SST and the drain selection transistor DST.

[0070] The gates of the source selection transistors SST included in the different cell strings ST may be connected to the source selection line SSL, the gates of the first memory cells F1 to the nth memory cells Fn included in the different cell strings ST may be connected to the first word lines WL1 to the nth word lines WLn, and the gates of the drain selection transistors DST included in the different cell strings ST may be connected to the drain selection line DSL. A group of memory cells connected to each of the word lines WL1 to WLn may be referred to as a page PG. For example, a group of first memory cells F1 connected to the first word line WL1 among the memory cells F1 to Fn included in the different strings may become a physical page PPG. Programming operations and read operations may be performed in units of physical pages PPG.

[0071] Figure 6 It is shown Figure 4 A diagram of an embodiment of a three-dimensional configuration of memory blocks is shown.

[0072] Reference Figure 6 , showing by way of example Figure 4 A first memory block BLK1 among a plurality of memory blocks BLK1 to BLKz is shown. The other memory blocks BLK2 to BLKz may have the same form as the first memory block BLK1.

[0073] The first memory block BLK implemented in a three-dimensional structure may be formed in an I-shape on a substrate in a vertical direction (Z direction), and include a plurality of cell strings ST arranged between a bit line BL and a source line SL. Alternatively, a well may be formed instead of the source line SL. This structure may also be referred to as a bit cost scalable (BiCS) structure. For example, when the source line SL is horizontally formed above the substrate, a cell string ST having a BiCS structure may be formed above the source line SL in a vertical direction (Z direction).

[0074] For example, the cell string ST may be arranged in a first direction (X direction) and a second direction (Y direction). The cell string ST may include a source selection line SSL, a word line WL, and a drain selection line DSL stacked to be spaced apart from each other. The number of the source selection line SSL, the word line WL, and the drain selection line DSL is not limited to that shown in the figure, and may be changed according to the memory device 1100. The cell string ST may include a vertical channel layer CH vertically penetrating the source selection line SSL, the word line WL, and the drain selection line DSL, and a bit line BL contacting the top of the vertical channel layer CH protruding upward from the drain selection line DSL and extending in the second direction (Y direction). The memory cell may be formed between the word line WL and the vertical channel layer CH. The contact plug CT may be further formed between the bit line BL and the vertical channel layer CH.

[0075] Figure 7 It is shown Figure 4 FIG. 2 is a diagram of another embodiment of a three-dimensional configuration of memory blocks.

[0076] Reference Figure 7 , showing by way of example Figure 4 A first memory block BLK1 among a plurality of memory blocks BLK1 to BLKz is shown. The other memory blocks BLK2 to BLKz may have the same form as the first memory block BLK1.

[0077] The first storage block BLK1 implemented in a three-dimensional structure may be formed in a U-shape on a substrate in a vertical direction (Z direction), and includes a source string ST_S and a drain string ST_D connected between a bit line BL and a source line SL and forming a pair. The source string ST_S and the drain string ST_D may be connected to each other through a pipe gate PG to form a U structure. The pipe gate PG may be formed in a pipeline PL. More specifically, the source string ST_S may be formed vertically between the source line SL and the pipeline PL, and the drain string ST_D may be formed vertically between the bit line BL and the pipeline PL. This structure may also be referred to as a pipe-shaped bit cost scalable (P-BiCS) structure.

[0078] For example, the drain string ST_D and the source string ST_S may be arranged in a first direction (X direction) and a second direction (Y direction), and may be arranged alternately along the second direction (Y direction). The drain string ST_D may include a word line WL and a drain selection line DSL stacked to be spaced apart from each other, and a drain vertical channel layer D_CH vertically penetrating the word line WL and the drain selection line DSL. The source string ST_S may include a word line and a source selection line SSL stacked to be spaced apart from each other, and a source vertical channel layer S_CH vertically penetrating the word line WL and the source selection line SSL. The drain vertical channel layer D_CH and the source vertical channel layer S_CH may be connected to each other through a pipe gate PG in a pipeline PL. The bit line BL may contact the top of the drain vertical channel layer D_CH protruding upward from the drain selection line DSL, and extend in the second direction (Y direction).

[0079] Figure 8 It is shown Figure 1 A diagram of a multi-plane structure in a memory device is shown.

[0080] Reference Figure 8 , the memory cell array 100 of the memory device 1100 may include a plurality of planes P1 to P4. For example, the first plane P1 to the fourth plane P4 may be included in the memory cell array 100 in one memory device 1100.

[0081] The first plane P1 to the fourth plane P4 may be connected to the row decoders RD1 to RD4 and the page buffer groups PBG1 to PBG4, respectively, and operate independently of each other. For example, the first plane P1 may be connected to the first row decoder RD1 and the first page buffer group PBG1 for operation, the second plane P2 may be connected to the second row decoder RD2 and the second page buffer group PBG2 for operation, the third plane P3 may be connected to the third row decoder RD3 and the third page buffer group PBG3 for operation, and the fourth plane P4 may be connected to the fourth row decoder RD4 and the fourth page buffer group PBG4 for operation.

[0082] The read operation will be described as an example. Each of the first row decoder RD1 to the fourth row decoder RD4 may apply a read voltage to a selected memory block in each of the first plane P1 to the fourth plane P4 in response to the received row address. The first page buffer group PBG1 to the fourth page buffer group PBG4 may temporarily store the read data by sensing the voltage or current of the bit line connected to the first plane P1 to the fourth plane P4. When the sensing operations of the first plane P1 to the fourth plane P4 are all completed, the read data temporarily stored in the first page buffer group PBG1 to the fourth page buffer group PBG4 may be output sequentially through the input / output circuit 250. For example, after the read data of the first page buffer group PBG1 is first output, the read data of the second page buffer group PBG2 to the fourth page buffer group PBG4 may be output sequentially.

[0083] like Figure 8 As shown, a memory device 1100 including a plurality of planes P1 to P4 may simultaneously (or in parallel) perform a read operation, a program operation, or an erase operation on blocks or pages located in different planes. For example, the control logic 300 may perform a plane interleaving operation of simultaneously (or temporally overlapping) reading pages located in different planes. The words "simultaneously" and "simultaneously" used herein for occurrences mean that the occurrences are performed at overlapping time intervals. For example, if a first occurrence is performed within a first time interval and a second occurrence is performed simultaneously within a second time interval, the first interval and the second interval overlap each other at least partially, so that there is a time when both the first occurrence and the second occurrence are performed.

[0084] In addition, the control logic 300 may include independent control logics CL1 to CL4 corresponding to the planes P1 to P4, respectively, to perform a plane interleaving operation. For example, the first control logic CL1 may control an operation on the first plane P1, the second control logic CL2 may control an operation on the second plane P2, the third control logic CL3 may control an operation on the third plane P3, and the fourth control logic CL4 may control an operation on the fourth plane P4. Therefore, the first row decoder RD1 to the fourth row decoder RD4 and the first page buffer group PBG1 to the fourth page buffer group PBG4 may be independently controlled by the first control logic CL1 to the fourth control logic CL4, respectively. In addition, at least some or all of the first control logic CL1 to the fourth control logic CL4 may be integrated so that one control logic controls two or more planes.

[0085] Fig. 9 is a conceptual diagram illustrating a super block according to an embodiment of the present disclosure.

[0086] Reference Fig. 9, the memory device 1100 may be connected to the storage controller 1200 through one first channel CH1. For example, the first memory device LUN1, the second memory device LUN2, the third memory device LUN3, and the fourth memory device LUN4 may be connected to the storage controller 1200 through the first channel CH1.

[0087] In addition, pages included in a plurality of planes P1 to P4 of two or more memory devices may constitute a super block SBLK. For example, the first page page 1 included in the i-th (i is a natural number of 1 or greater) block of the first plane P1 to the fourth plane P4 belonging to the first memory device LUN1 and the second memory device LUN2 may be configured as a super block SBLK[i1], and the k-th (k is a natural number of 2 or greater) page page k included in the i-th block of the first plane P1 to the fourth plane P4 belonging to the first memory device LUN1 and the second memory device LUN2 may be configured as a super block SBLK[ik].

[0088] Similar to the first memory device LUN1 and the second memory device LUN2, the first page page 1 included in the jth (j is a natural number of 1 or greater) of the first plane P1 to the fourth plane P4 belonging to the third memory device LUN3 and the fourth memory device LUN4 can be configured as a super block SBLK[j1], and the kth (k is a natural number of 2 or greater) page page k included in the jth block of the first plane P1 to the fourth plane P4 belonging to the third memory device LUN3 and the fourth memory device LUN4 can be configured as a super block SBLK[jk].

[0089] Each page included in a super block SBLK may have the same column address and the same row address. For example, the first page page 1 constituting the super block SBLK[i1] may have the same column address and the same row address in each plane. Similarly, the kth page page k constituting the super block SBLK[ik] may have the same column address and the same row address in each plane.

[0090] Furthermore, when a program operation or a read operation is performed on a super block SBLK configured with pages of planes P1 to P4 belonging to two or more memory devices, the memory controller 1200 may be requested to transmit a program command or a read command to each memory device.

[0091] For example, when each of the first storage device LUN1 and the second storage device LUN2 is Fig. 9When four planes P1 to P4 are included as shown, the storage controller 1200 may send four programming commands (or read commands) corresponding to the planes P1 to P4, respectively, to the first memory device LUN1, and send four programming commands (or read commands) corresponding to the planes P1 to P4, respectively, to the second memory device LUN2 to indicate programming operations (or read operations) on super blocks SBLK[i1] to SBLK[ik] configured using the first memory device LUN1 and the second memory device LUN2.

[0092] As described above, when the storage controller 1200 sends a plurality of commands to the first storage device LUN1 and the second storage device LUN2 to instruct a programming operation (or a read operation) on one super block SBLK, the storage controller 1200 may send the commands through the input / output pad DQ of the first channel CH1 used to connect the first storage device LUN1 and the second storage device LUN2 in common. Therefore, the storage controller 1200 may sequentially send a programming command corresponding to the first storage device LUN1 and a programming command corresponding to the second storage device LUN2 through the input / output pad DQ of the first channel CH1.

[0093] although Fig. 9 2 shows a case where one super block SBLK is configured using two memory devices LUN1 and LUN2 or LUN3 and LUN4, but the present disclosure is not limited thereto. For example, one super block SBLK may be configured using at least two memory devices connected through a common channel.

[0094] Fig.10 It is shown that read Fig. 9 A timing diagram of a read operation of pages included in a superblock is shown.

[0095] Reference Fig.10 , the memory controller 1200 may sequentially transmit read commands instructing to read pages included in the super block SBLK[i1] to the input / output pads DQ of the first channel CH1.

[0096] For example, in order to instruct the first memory device LUN1 to perform a read operation on the super block SBLK[i1], the storage controller 1200 may send read commands corresponding to the planes P1 to P4 of the first memory device LUN1 constituting the super block SBLK[i1] together with the address Addr to the input / output pad DQ of the first channel CH1 in sequence.

[0097] The address Addr may include a die address LUNADD indicating one of the memory devices LUN1 to LUN4 connected to the first channel CH1 , a plane address PADD indicating one of the planes P1 to P4 of the respective memory devices, and a column address CADD and a row address RADD indicating a page included in one of the planes.

[0098] Specifically, for example, the memory controller 1200 may send an address Addr including a die address LUNADD indicating the first memory device LUN1, a plane address PADD indicating the first plane P1, and a column address CADD and a row address RADD indicating the first page page 1, and a read command 00h-32h to the input / output pad DQ of the first channel CH1. In addition, the memory controller 1200 may send an address Addr including a die address LUNADD indicating the first memory device LUN1, a plane address PADD indicating the second plane P2, and a column address CADD and a row address RADD indicating the first page page 1, and a read command 00h-32h to the input / output pad DQ of the first channel CH1. In addition, the memory controller 1200 may send an address Addr including a die address LUNADD indicating the first memory device LUN1, a plane address PADD indicating the third plane P3, and a column address CADD and a row address RADD indicating the first page page 1, and a read command 00h-32h to the input / output pad DQ of the first channel CH1. In addition, the memory controller 1200 may transmit an address Addr including a die address LUNADD indicating the first memory device LUN1, a plane address PADD indicating the fourth plane P4, and a column address CADD and a row address RADD indicating the first page page 1, and a last command 00h-30h to the input / output pad DQ of the first channel CH1.

[0099] Since the die address LUNADD included in the four addresses Addr transmitted by the memory controller 1200 indicates the first memory device LUN1 , the first memory device LUN1 may perform an operation according to four read commands 00h-32h and 00h-30h transmitted to the input / output pad DQ of the first channel CH1 .

[0100] Whenever the first memory device LUN1 receives three read commands 00h-32h transmitted by the memory controller 1200 through the input / output pad DQ of the first channel CH1, the first memory device LUN1 may queue up a read operation on the first page page 1 of the first plane P1, a read operation on the first page page 1 of the second plane P2, and a read operation on the first page page 1 of the third plane P3 in sequence. When the first memory device LUN1 receives the last read command 00h-30h, the first memory device LUN1 may perform the queued read operations on the first pages page 1 of the first to third planes P1 to P3 and perform the read operation indicated by the last read command 00h-30h on the first page page 1 of the fourth plane P4.

[0101] For example, the first memory device LUN1 may read the first page page 1 of the first to fourth planes P1 to P4 using the plane interleaving method and store the read data in the page buffer group 230 connected to the respective planes. For example, the first memory device LUN1 may store the read data in a cache register (not shown) included in the page buffer group 230.

[0102] Data stored in the page buffer groups 230 of the respective planes may be sequentially transmitted to the memory controller 1200 in response to a read enable signal transmitted to the first memory device LUN through the RE# pad.

[0103] Furthermore, since the super block SBLK[i1] includes the first page page 1 included in the planes P1 to P4 of the second memory device LUN2 , the memory controller 1200 may also send four read commands to the second memory device LUN2 through the input / output pad DQ of the first channel CH1 .

[0104] For example, the memory controller 1200 may send an address Addr including a die address LUNADD indicating the second memory device LUN2, a plane address PADD indicating the first plane P1, and a column address CADD and a row address RADD indicating the first page page 1, and a read command 00h-32h to the input / output pad DQ of the first channel CH1. In addition, the memory controller 1200 may send an address Addr including a die address LUNADD indicating the second memory device LUN2, a plane address PADD indicating the second plane P2, and a column address CADD and a row address RADD indicating the first page page 1, and a read command 00h-32h to the input / output pad DQ of the first channel CH1. In addition, the memory controller 1200 may send an address Addr including a die address LUNADD indicating the second memory device LUN2, a plane address PADD indicating the third plane P3, and a column address CADD and a row address RADD indicating the first page page 1, and a read command 00h-32h to the input / output pad DQ of the first channel CH1. In addition, the memory controller 1200 may transmit an address Addr including a die address LUNADD indicating the second memory device LUN2, a plane address PADD indicating the fourth plane P4, and a column address CADD and a row address RADD indicating the first page page 1, and a last read command 00h-30h to the input / output pad DQ of the first channel CH1.

[0105] That is, the memory controller 1200 may send read commands corresponding to the planes of at least two memory devices constituting one super block SBLK, respectively, to read pages included in one super block SBLK. Fig. 9As shown, when one super block is configured with four planes and two memory devices, the memory controller 1200 may send eight read commands to read pages included in one super block.

[0106] Fig.11 is to show that data is programmed in Fig. 9 A timing diagram of a programming operation in pages included in a super block is shown.

[0107] Reference Fig.11 , the memory controller 1200 may sequentially transmit a program command instructing to program data in pages included in the super block SBLK[i1] to the input / output pads DQ of the first channel CH1.

[0108] For example, in order to perform a programming operation of programming data in the super block SBLK[i1], the storage controller 1200 may sequentially send programming commands corresponding to the planes P1 to P4 of the first memory device LUN1 constituting the super block SBLK[i1] as well as the address Addr and the data D1 to Dn.

[0109] The address Addr may include a die address LUNADD indicating one of the memory devices LUN1 to LUN4 connected to the first channel CH1 , a plane address PADD indicating one of the planes P1 to P4 of the respective memory devices, and a column address CADD and a row address RADD indicating a page included in one of the planes.

[0110] The data D1 to Dn may be data to be stored in a memory cell indicated by the address Addr.

[0111] For example, refer to Fig.11 , the memory controller 1200 may send an address Addr and data D1 to Dn including a die address LUNADD indicating a first memory device LUN1, a plane address PADD indicating a first plane P1, and a column address CADD and a row address RADD indicating a first page page 1, and a program command 80h-11h to the input / output pad DQ of the first channel CH1.

[0112] In addition, although Fig.11In the embodiment, the memory controller 1200 may send an address Addr and data D1 to Dn including a die address LUNADD indicating the first memory device LUN1, a plane address PADD indicating the second plane P2, and an address CADD and a row address RADD indicating the first page page 1, and a program command 80h-11h to the input / output pad DQ of the first channel CH1. In addition, the memory controller 1200 may send an address Addr and data D1 to Dn including a die address LUNADD indicating the first memory device LUN1, a plane address PADD indicating the third plane P3, and an address Addr and data D1 to Dn including a column address CADD and a row address RADD indicating the first page page 1, and a program command 80h-11h to the input / output pad DQ of the first channel CH1.

[0113] In addition, refer to Fig.11 , the memory controller 1200 may send an address Addr and data D1 to Dn including a die address LUNADD indicating a first memory device LUN1, a plane address PADD indicating a fourth plane P4, and a column address CADD and a row address RADD indicating a first page page 1, and a final program command 80h-10h to the input / output pad DQ of the first channel CH1.

[0114] Since the die address LUNADD included in the four addresses Addr transmitted by the memory controller 1200 indicates the first memory device LUN1, the first memory device LUN1 may perform operations according to the four program commands 80h-11h and 80h-10h transmitted to the input / output pad DQ of the first channel CH1.

[0115] Whenever the first memory device LUN1 receives three program commands 80h-11h and data D1 to Dn transmitted through the input / output pad DQ of the first channel CH1 by the memory controller 1200, the first memory device LUN1 may store the received data in the page buffer group 230 of the plane corresponding to the plane address PADD. When the first memory device LUN1 receives the last program command 80h-10h and the data D1 to Dn, the first memory device LUN1 may store the data D1 to Dn received together with the last program command 80h-10h in the page buffer group 230 of the fourth plane P4, and then the data respectively stored in the page buffer groups 230 of the first to fourth planes P1 to P4 are simultaneously (or temporally overlapped) stored (or programmed) in the memory cells included in the first to fourth planes P1 to P4.

[0116] In addition, the first memory device LUN1 may perform a reset operation (or an initialization operation) on the page buffer group 230 connected to the plane corresponding to the plane address PADD in the data loading period tADL corresponding to the period from when the address Addr is received to when the data D1 to Dn are received. That is, the first memory device LUN1 may perform a reset operation on the page buffer group 230 connected to the plane corresponding to the plane address PADD before the new data D1 to Dn are stored in the page buffer group 230 so that the cache register included in the page buffer group 230 is reset.

[0117] Furthermore, since the super block SBLK[i1] includes the first page page 1 included in the planes P1 to P4 of the second memory device LUN2 , the memory controller 1200 may also transmit four read commands and data to the second memory device LUN2 through the input / output pad DQ of the first channel CH1 .

[0118] For example, the memory controller 1200 may transmit an address Addr and data D1 to Dn including a die address LUNADD indicating the second memory device LUN2, a plane address PADD indicating the first plane P1, and a column address CADD and a row address RADD indicating the first page page 1, and a program command 80h-11h to the input / output pad DQ of the first channel CH1.

[0119] In addition, although Fig.11 The memory controller 1200 may transmit the address Addr and data D1 to Dn and the programming commands 80h-11h to the input / output pad DQ of the first channel CH1, including the die address LUNADD indicating the second memory device LUN2, the plane address PADD indicating the second plane P2, and the column address CADD and the row address RADD indicating the first page page 1. In addition, the memory controller 1200 may transmit the address Addr and data D1 to Dn and the programming commands 80h-11h to the input / output pad DQ of the first channel CH1, including the die address LUNADD indicating the second memory device LUN2, the plane address PADD indicating the third plane P3, and the column address CADD and the row address RADD indicating the first page page 1.

[0120] In addition, refer to Fig.11 , the memory controller 1200 may send an address Addr and data D1 to Dn including a die address LUNADD indicating a second memory device LUN2, a plane address PADD indicating a fourth plane P4, and a column address CADD and a row address RADD indicating a first page page 1, and a final program command 80h-10h to the input / output pad DQ of the first channel CH1.

[0121] That is, the memory controller 1200 may send program commands corresponding to the planes of at least two memory devices constituting one super block SBLK, respectively, to store data in pages included in one super block SBLK. Fig. 9 As shown, when one super block is configured with four planes and two memory devices, the memory controller 1200 may send eight read commands to store data in pages included in one super block.

[0122] Fig.12 is shown by using the group address selection configuration Fig. 9 A timing diagram illustrating the concept of minimizing command transmissions by using at least two memory devices of a super-block is shown.

[0123] exist Fig.10 In the case of the read command shown, the read commands corresponding to the planes of the memory devices constituting the super block SBLK, respectively, may be sent to the input / output pad DQ of one channel. Therefore, multiple commands will be sent to one channel in sequence to read one super block SBLK, which may cause a channel bottleneck. Therefore, it may be necessary to perform a read operation on the super block SBLK by sending only the minimum number of read commands to solve the channel bottleneck.

[0124] In addition, Fig.11 In the case of each programming command shown, a reset operation (or initialization operation) can be performed on the page buffer group 230 connected to the plane corresponding to the plane address PADD in the data loading period tADL corresponding to the period from receiving the address Addr to receiving the data D1 to Dn. That is, when eight programming commands are issued, it is necessary to ensure eight data loading periods tADL. In order to reduce the data loading period tADL, when the first programming command is issued, a reset operation is performed simultaneously on all page buffer groups 230 of the planes connected to the various memory devices constituting the super block, so that the data loading period tADL according to other programming commands can be omitted. The words "simultaneously" and "simultaneously" used herein for occurrence mean that the occurrence is performed at overlapping time intervals. For example, if the first occurrence is performed in a first time interval and the second occurrence is performed simultaneously in a second time interval, the first interval and the second interval overlap each other at least partially, so that there is a time when both the first occurrence and the second occurrence are performed.

[0125] According to an embodiment for solving a channel bottleneck and reducing a data loading period, the memory controller 1200 may allocate the same group address GADD to at least two memory devices constituting a super block SBLK and select the at least two memory devices constituting the super block SBLK using the group address GADD.

[0126] The selected at least two memory devices may perform a read operation corresponding to the read command in response to the read command, regardless of any die address LUNADD. In addition, the selected at least two memory devices may perform a read operation corresponding to the read command on all planes constituting the super block SBLK in response to the read command, regardless of any plane address PADD.

[0127] In addition, the selected at least two memory devices may simultaneously perform a reset operation on all page buffer groups 230 connected to all planes P1 to P4 constituting the super block SBLK in response to the first program command. In addition, as a response to a program command after the first program command, the selected at least two memory devices may omit the data loading period tADL (i.e., omit the reset operation on the page buffer group 230).

[0128] exist Fig.12 In the timing diagram shown, although the output high level signal is represented as an output (or enable) signal, the output low level signal is represented as not outputting any signal, it should be understood that this is only for convenience of description. For example, on the contrary, the output low level signal can be represented as an output signal. In addition, it can be interpreted that the high level signal and the low level signal represent relative magnitudes (e.g., relative magnitudes of voltages).

[0129] For example, refer to Fig.12 , the memory controller 1200 may transmit a group address assignment command D5h-AAh for assigning a group address GADD to the first and second memory devices LUN1 and LUN2 constituting the super block SBLK[i1] to the input / output pad DQ of the first channel CH1.

[0130] First, the memory controller 1200 may transmit a group address assignment command D5h-AAh and a die address LUNADD1 indicating the first memory device LUN1 to the input / output pad DQ of the first channel CH1, and transmit a group address GADD to be assigned to the first memory device LUN1 to the input / output pad DQ of the first channel CH1.

[0131] The first memory device LUN1 corresponding to the die address LUNADD1 or the control logic 300 of the first memory device LUN1 may store the group address GADD in its group address register 500 and output a high level group allocation enable signal GRPEN1 in response to the group address allocation command D5h-AAh transmitted to the input / output pad DQ.

[0132] The memory controller 1200 may transmit a group address assignment command D5h-AAh and a die address LUNADD2 indicating the second memory device LUN2 to the input / output pad DQ of the first channel CH1, and transmit a group address GADD to be assigned to the second memory device LUN2 to the input / output pad DQ of the first channel CH1.

[0133] The second memory device LUN2 corresponding to the die address LUNADD2 or the control logic 300 of the second memory device LUN2 may store the group address GADD in its group address register 500 and output a high level group allocation enable signal GRPEN2 in response to the group address allocation command D5h-AAh transmitted to the input / output pad DQ.

[0134] The third and fourth memory devices LUN3 and LUN4 are connected to the first channel CH1 but do not have any allocated group addresses GADD to be stored therein. Therefore, the third and fourth memory devices LUN3 and LUN4 may not output high-level group allocation enable signals GRPEN3 and GRPEN4.

[0135] After the group address GADD is assigned to the first memory device LUN1 and the second memory device LUN2 constituting the super block SBLK[i1], the storage controller 1200 may send a group selection command AAh and the group address GADD to the input / output pad DQ of the first channel CH1 for selecting the first memory device LUN1 and the second memory device LUN2 constituting the super block SBLK[i1].

[0136] In response to the control logic 300 receiving the group selection command AAh, the control logic 300 of the first to fourth memory devices LUN1 to LUN4 connected to the first channel CH1 may output high-level first group enable signals GRPACT1 to GRPACT4 .

[0137] In addition, the control logic 300 of the first to fourth memory devices LUN1 to LUN4 connected to the first channel CH1 may compare the group address GADD transmitted together with the group selection command AAh with the group address GADD stored in the group address register 500 of the first to fourth memory devices LUN1 to LUN4. The control logic 300 of the first to second memory devices LUN1 to LUN2 may determine that the two group addresses GADD are the same based on the comparison result, and generate a second group enable signal GADDSIG (see Fig.15In addition, since no group address GADD is stored in the group address register 500 of the third memory device LUN3 and the fourth memory device LUN4, the control logic 300 of the third memory device LUN3 and the fourth memory device LUN4 may determine that the two group addresses GADD are different from each other and may not output the second group enable signal GADDSIG (see Fig.15 ).

[0138] Next, the group selection signal generator 400 of the first to fourth memory devices LUN1 to LUN4 may output the group selection signal GRPSEL based on the first group enable signal GRPACT, the second group enable signal GADDSIC, and the group allocation enable signal GRPEN.

[0139] For example, the group selection signal generator 400 of the first memory device LUN1 and the second memory device LUN2 may output high-level group selection signals GRPSEL1 and GRPSEL2 based on high-level first group enable signals GRPACT1 and GRPACT2, high-level second group enable signals, and high-level group allocation enable signals GRPEN1 and GRPEN2. The high-level group selection signals GRPSEL1 and GRPSEL2 outputted here may be received by the control logic 300 of the first memory device LUN1 and the control logic 300 of the second memory device LUN2, respectively.

[0140] However, the group selection signal generator 400 of the third and fourth memory devices LUN3 and LUN4 may not output the high level group selection signals GRPSEL3 and GRPSEL4 based on the low level group allocation enable signals GRPEN3 and GRPEN4 and / or the low level second group enable signal.

[0141] Finally, based on the high level group selection signal GRPSEL, the control logic 300 of the first memory device LUN1 and the control logic 300 of the second memory device LUN2 can perform a program operation (or read operation) corresponding to the program command (or read command) sent through the first channel CH1 in response to the program command (or read command).

[0142] Fig.13 It is shown in Fig.12 A timing diagram showing a case where a read command is received after at least two memory devices constituting a super block are selected.

[0143] In from Fig.12 After the group selection signal generator 400 of the first memory device LUN1 and the second memory device LUN2 in the embodiment outputs the high level group selection signals GRPSEL1 and GRPSEL2, a read command may be received. Fig.13, the memory controller 1200 may send a read command 00h-30h and an address Addr to the input / output pad DQ of the first channel CH1.

[0144] like Fig.10 and Fig.11 As described in, the address Addr may include a die address LUNADD indicating one of the memory devices LUN1 to LUN4 connected to the first channel CH1, a plane address PADD indicating one of the planes P1 to P4 of each memory device, and a column address CADD and a row address RADD indicating a page included in one of the planes.

[0145] In response to the control logic 300 of the first memory device LUN1 and the second memory device LUN2 receiving the high-level group selection signals GRPSEL1 and GRPSEL2, the control logic 300 of the first memory device LUN1 and the second memory device LUN2 responds to the read command 00h-30h regardless of the die address LUNADD included in the address Addr, so that the control logic 300 of the first memory device LUN1 and the second memory device LUN2 can perform the read operation corresponding to the read command 00h-30h transmitted to the input / output pad DQ by controlling the peripheral circuit 200. That is, although the die address LUNADD included in the address Addr indicates the first memory device LUN1, the control logic 300 of the second memory device LUN2 receiving the high-level group selection signal GRPSEL2 can perform the read operation corresponding to the read command 00h-30h.

[0146] In response to the control logic 300 of the first memory device LUN1 and the second memory device LUN2 receiving the high level group selection signal, the control logic 300 of the first memory device LUN1 and the second memory device LUN2 may perform a read operation corresponding to the read command 00h-30h on all the first planes P1 to the fourth planes P4 constituting the super block SBLK, regardless of the plane address PADD included in the address Addr. For example, the respective control logics 300 of the first memory device LUN1 and the second memory device LUN2 may read the first page page 1 indicated by the column address CADD and the row address LADD included in the address Addr in each of the first planes P1 to the fourth planes P4 of the first memory device LUN1 and the second memory device LUN2 by controlling the peripheral circuit 200, and store the read data in the page buffer group 230 connected to the respective planes. The operation of reading the first page page 1 in the planes P1 to P4 of the first memory device LUN1 and the second memory device LUN2 may be performed during the 4-plane read period tRMP.

[0147] In addition, since the control logic 300 of the third memory device LUN3 and the fourth memory device LUN4 receives the low level group selection signal, the control logic 300 of the third memory device LUN3 and the fourth memory device LUN4 may be as follows: Fig.10 That is, only when the die address LUNADD sent with the read command 00h-30h indicates each of the third memory device LUN3 and the fourth memory device LUN4, the respective control logics 300 of the third memory device LUN3 and the fourth memory device LUN4 can read the page of the plane corresponding to the plane address PADD.

[0148] As mentioned above, when Fig.12 When at least two memory devices constituting a super block are selected as shown, a read operation can be performed on all planes P1 to P4 of the memory devices LUN1 and LUN2 constituting the super block SBLK[i1] using one read command 00h-30h. That is, since a read command 00h-30h is issued once when reading one super block SBLK, a channel bottleneck can be solved and command processing time can be reduced.

[0149] Fig.14 It is shown in Fig.12 A timing diagram showing a case where a program command is received after at least two memory devices constituting a super block are selected.

[0150] In from Fig.12 After the group selection signal generator 400 of the first memory device LUN1 and the second memory device LUN2 in the embodiment outputs the high level group selection signals GRPSEL1 and GRPSEL2, the first programming command may be received. Fig.14 , the memory controller 1200 may transmit the first program commands 80h-11h, the address Addr, and the data D1 to Dn to the input / output pads DQ of the first channel CH1.

[0151] In response to the control logic 300 of the first memory device LUN1 and the second memory device LUN2 receiving the high-level group selection signals GRPSEL1 and GRPSEL2, the control logic 300 of the first memory device LUN1 and the second memory device LUN2 may perform a reset operation on all page buffer groups 230 connected to all planes P1 to P4 constituting the super block SBLK in response to the first program command 80h-11h. For example, when it is checked that the front-end command 80h of the first program command 80h-11h has been received, the control logic 300 of the first memory device LUN1 and the second memory device LUN2 may immediately perform a reset operation on all page buffer groups 230 connected to all planes P1 to P4 constituting the super block SBLK during the reset period tPBRST. That is, since the reset operation of all page buffer groups 230 connected to all planes P1 to P4 constituting the super block SBLK can be started without referring to the address Addr, the reset operation can be quickly ended. Therefore, the ratio can be set Fig.11 The data loading period tADL shown is shorter than the data loading period tADL2.

[0152] The data D1 to Dn may be stored in the page buffer group 230 of the plane connected to the memory device indicated by the address Addr among the first to fourth memory devices LUN1 to LUN4. For example, the data D1 to Dn may be stored in the page buffer group 230 of the first plane P1 connected to the first memory device LUN1.

[0153] When the memory controller 1200 sends the program commands 80h-11h (program commands from the second program command) (not shown) to the input / output pads DQ of the first channel CH1 after the first program commands 80h-11h, the address Addr, and the data D1 to Dn, all reset operations of the page buffer groups 230 of the planes of the memory device connected to the address Addr may be omitted (due to the reset operation of all the page buffer groups 230 corresponding to the super block SBLK as a response to the first program command). That is, the memory controller 1200 may send the address Addr to the input / output pads DQ and immediately send the data D1 to Dn to the input / output pads DQ without delay during the data loading period tADL2. Even in response to a program command 80h-11h (program command from the second program command) (not shown) subsequent to the first program command 80h-11h, data D1 to Dn may be stored in a page buffer group 230 of a plane connected to a memory device indicated by an address Addr among the first to fourth memory devices LUN1 to LUN4.

[0154] In addition, when the memory controller 1200 transmits the last program command 80h-10h, the address Addr, and the data D1 to Dn to the input / output pad DQ of the first channel CH1, the data D1 to Dn may be stored in the page buffer group 230 of the plane connected to the memory device indicated by the address Addr among the first to fourth memory devices LUN1 to LUN4. Subsequently, the data stored in the page buffer group 230 corresponding to the address Addr from the first program command 80h-11h to the last program command 80h-10h may be respectively stored in the pages indicated by the column address CADD and the row address RADD included in the address Addr.

[0155] Fig.15 It is shown Figure 3 An example of a diagram of a group selection signal generator is shown.

[0156] Reference Fig.15 , the group selection signal generator 400 may include: a first signal generator 410, which outputs a first group enable signal GRPACT in response to a command reception signal ACCMDSIG indicating that a group selection command AAh is received; and a second signal generator 420, which outputs a group selection signal GRPSEL in response to the first group enable signal GRPACT, a second group enable signal GADDSIG and a group allocation enable signal GRPEN.

[0157] The second group enable signal GADDSIG may indicate that the group address stored in the group address register 500 is the same as the group address received together with the group select command AAh.

[0158] The group allocation enable signal GRPEN may indicate that the group address GADD has been received.

[0159] The first signal generator 410 may include a first multiplexer 411 that selects and outputs one of a command reception signal ACCMDSIG and a first group enable signal GRPACT based on a command latch enable signal supplied to a CLE pad, a second multiplexer 412 that selects and outputs one of an output of the first multiplexer 411 and a low level signal 0 based on an address latch enable signal supplied to an ALE pad, and a first flip-flop 413 that outputs the output of the second multiplexer 412 according to a clock CLK of a write enable signal supplied through a WE# pad. The output of the first flip-flop 413 may be the first group enable signal GRPACT.

[0160] The first trigger 413 may be a D trigger. In addition, the first trigger 413 may be reset according to the start pulse signal SPLS. For example, the start pulse signal SPLS may be Figure 3 After all read commands 00h-30h and address Addr are received or Fig.14 The high level signal appears for a short period of time after the last read command 80h-10h, address Addr and data D1 to Dn are all received as shown.

[0161] The second signal generator 420 may include: a first AND gate 421, which performs a logic AND operation on the second group enable signal GADDSIG and the group allocation enable signal GRPEN, and then outputs the result of the logic AND operation; a second AND gate 422, which performs a logic AND operation on the first group enable signal GRPACT and the address latch enable signal supplied through the ALE pad, and then outputs the result of the logic AND operation; a third multiplexer 423, which outputs a signal selected from the output of the first AND gate 421 and the group selection signal GRPSEL based on the output of the second AND gate 422; and a second flip-flop 424, which outputs the output of the third multiplexer 423 according to the clock CLK of the write enable signal supplied through the WE# pad. The output of the second flip-flop 424 may be the group selection signal GRPSEL. The second flip-flop 424 may be a D flip-flop. In addition, the second flip-flop 424 may be reset according to the start pulse signal SPLS.

[0162] The start pulse signal SPLS, the command reception signal ACCMDSIG, the second group enable signal GADDSIG, and the group allocation enable signal GRPEN may be generated by the control logic 300 or a separate signal generation circuit.

[0163] Fig.16 It shows reference Figures 9 to 15 An example of a flowchart of a method of operating a memory device is described.

[0164] Reference Fig.16 , a method for operating a memory device may include: step S100, receiving a group address allocation command and a first group address from a memory controller; step S110, storing the first group address in a group address register as a response to the group address allocation command; step S120, receiving a group selection command and a second group address from the memory controller; step S130, generating a group selection signal based on a result obtained by comparing the first group address and the second group address as a response to the group selection command; step S140, receiving at least one command indicating an operation on a super block and an address corresponding to the command from the memory controller; and step S150, performing an operation corresponding to the command based on the group selection signal.

[0165] The super block may include pages included in planes of at least two memory devices among a plurality of memory devices commonly connected to the memory controller through one channel.

[0166] The command may include a read command.

[0167] The step S150 of performing the operation may include the step of performing a read operation corresponding to the read command by responding to the read command based on the group selection signal.

[0168] The step of performing the read operation may include the step of performing the read operation corresponding to the read command on the planes included in the super block based on the group selection signal.

[0169] The first group of addresses may be addresses commonly allocated for at least two memory devices each including a page included in the super block.

[0170] The step S120 of receiving the group selection command and the second group address from the memory controller may include the step of generating a first group enable signal indicating that the group selection command has been received.

[0171] The step S130 of generating the group selection signal may include the step of generating a second group enable signal indicating that the first group address and the second group address are the same.

[0172] The step S110 of storing the first group address in the group address register may further include the step of generating a group allocation enable signal indicating that the group address has been allocated.

[0173] In the step S130 of generating the group selection signal, the group selection signal may be generated based on the first group enable signal, the second group enable signal, and the group allocation enable signal.

[0174] The commands may include programming commands.

[0175] The step S140 of receiving at least one command and an address corresponding to the command may include the steps of receiving the program command and performing a reset operation on a memory buffer group connected to a plane constituting the super block before receiving the address.

[0176] In addition, it should be interpreted that the method of operating the memory device includes referring to Figures 12 to 15 The operation of memory device 1100 is described.

[0177] Fig.17 It shows that the application Figure 1 A diagram of a memory card of a memory system is shown.

[0178] Reference Fig.17 , the memory system may include a host 2000 and a memory card 70000 .

[0179] The memory card 70000 may be implemented as a smart card. The memory card 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0180] The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In an implementation, the card interface 7100 may be a secure digital (SD) interface or a multimedia card (MMC) interface, but the present disclosure is not limited thereto.

[0181] The card interface 7100 may interface data exchange between the host 2000 and the storage controller 1200 according to the protocol of the host 2000. In some embodiments, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. The card interface 7100 may refer to hardware capable of supporting a protocol used by the host 2000, software embedded in the hardware, or a signal transmission method.

[0182] Fig.18 It shows that the application Figure 1 A block diagram of an SSD system of a memory system is shown.

[0183] Reference Fig.18 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 through a signal connector 3001, and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0184] In an embodiment, the SSD controller 3210 may be Figure 1 The components corresponding to the storage controller 1200 shown in FIG. 1 and FIG. 2 may be flash memories 3221 to 322n. Figure 1 Components corresponding to the memory device 1100 are shown.

[0185] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. Exemplarily, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of an interface such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0186] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. When the power supply from the host 3100 is not smooth, the auxiliary power supply 3230 can provide power to the SSD 3200. Exemplarily, the auxiliary power supply 3230 can be located in the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the mainboard and provide auxiliary power to the SSD 3200.

[0187] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDRSDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0188] According to the present disclosure, a memory system capable of quickly performing a program operation or a read operation on a super block configured using at least two memory devices and an operating method of a memory device included in the memory system may be provided.

[0189] Although the present disclosure is shown and described with reference to specific examples of its embodiments, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0190] In the above-mentioned embodiments, all steps may be selectively performed, or some steps may be omitted. In various embodiments, the steps may not be performed in the order described, but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0191] In addition, examples of embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, those terms are only used to illustrate the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and many changes can be made within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can also be made based on the technical scope of the present disclosure.

[0192] CROSS-REFERENCE TO RELATED APPLICATIONS

[0193] This application claims the priority of Korean Patent Application No. 10-2020-0102748 filed on August 14, 2020 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory system, the memory system comprising: a plurality of memory devices, the plurality of memory devices including a memory cell array having a plurality of planes, the plurality of memory devices being commonly connected to a memory controller via a channel; a superblock comprising pages included in planes of at least two memory devices among the plurality of memory devices; as well as the storage controller being configured to send at least one command indicating an operation on the super block and an address corresponding to the command to the memory device, Wherein, each of the memory devices comprises: a peripheral circuit configured to perform operations on the memory cell array; a group selection signal generator configured to output a group selection signal indicating the at least two memory devices constituting the super block; and a control logic configured to control the peripheral circuit to perform an operation corresponding to the command based on the group selection signal, Wherein, the command includes a read command, wherein the control logic controls the peripheral circuit to perform a read operation corresponding to the read command on all planes included in the super block by responding to the read command based on the group selection signal, regardless of a plane address included in the address, and Among them, even if the tube core address included in the address indicates the first memory device among the at least two memory devices, the second memory device among the at least two memory devices that receives the high level group selection signal also performs the read operation corresponding to the read command.

2. The memory system according to claim 1, wherein: Each of the memory devices further includes a group address register configured to store a group address commonly allocated to the at least two memory devices, each of which includes a page included in the super block.

3. The memory system according to claim 2, wherein: The control logic receives a group address assignment command and a first group address corresponding to the group address assignment command from the storage controller, and stores the first group address in the group address register in response to the group address assignment command.

4. The memory system according to claim 3, wherein: The control logic receives a group selection command and a second group address corresponding to the group selection command from the memory controller, and compares the first group address and the second group address in response to the group selection command.

5. The memory system according to claim 4, wherein: The control logic outputs a first group enable signal to the group select signal generator indicating that the group select command has been received.

6. The memory system according to claim 5, wherein: The control logic outputs a second group enable signal to the group selection signal generator indicating that the first group address and the second group address are the same.

7. The memory system according to claim 6, wherein: After the first group address is stored in the group address register, the control logic outputs a group allocation enable signal indicating that the group address has been allocated to the group selection signal generator.

8. The memory system according to claim 7, wherein: The group selection signal generator outputs the group selection signal to the control logic based on the first group enable signal, the second group enable signal, and the group allocation enable signal.

9. The memory system according to claim 1, wherein: Each of the memory devices includes a memory buffer group connected to each of the planes through a bit line, wherein the command comprises a programming command, and Wherein, before the control logic receives the program command from the storage controller and receives the address from the storage controller, the control logic performs a reset operation on the memory buffer group by controlling the memory buffer group connected to the plane constituting the super block.

10. A method of operating a memory device, the memory device comprising a plurality of planes and connected to a memory controller via a channel, the method comprising the steps of: receiving a group address assignment command and a first group address from the storage controller; storing the first group address in a group address register in response to the group address assignment command; receiving a group select command and a second group address from the memory controller; generating a group selection signal based on a result obtained by comparing the first group address and the second group address in response to the group selection command; receiving from the storage controller at least one command indicating an operation on a super block and an address corresponding to the command; as well as executing an operation corresponding to the command based on the group selection signal, wherein the super block includes pages included in planes of at least two memory devices among a plurality of memory devices commonly connected to the memory controller through the channel, Wherein, the command includes a read command, wherein the step of performing the operation includes the steps of: performing a read operation corresponding to the read command on all planes included in the super block by responding to the read command based on the group selection signal regardless of the plane address included in the address, and Wherein, even if the die address included in the address indicates a first memory device among the at least two memory devices, a second memory device among the at least two memory devices that receives a high level group selection signal also performs a read operation corresponding to the read command.

11. The method according to claim 10, wherein: The first set of addresses are addresses commonly allocated for the at least two memory devices, each of which includes a page included in the super block.

12. The method according to claim 10, wherein: Receiving the group select command and the second group address from the memory controller includes generating a first group enable signal indicating that the group select command has been received.

13. The method according to claim 12, wherein: Generating the group select signal includes generating a second group enable signal indicating that the first group address and the second group address are the same.

14. The method according to claim 13, wherein: Storing the first group address in the group address register further includes generating a group allocation enable signal indicating that a group address has been allocated.

15. The method according to claim 14, wherein: In the step of generating the group selection signal, the group selection signal is generated based on the first group enable signal, the second group enable signal, and the group allocation enable signal.

16. The method according to claim 10, wherein: The commands include programming commands, and Wherein, in the step of receiving the at least one command and an address corresponding to the command, before receiving the programming command and receiving the address, a reset operation is performed on a memory buffer group connected to the plane constituting the super block.

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