Page buffer circuits and non-volatile memory devices including page buffer circuits

Abstract

A page buffer circuit and a non-volatile memory device including the page buffer circuit are provided. The non-volatile memory device includes a memory cell array containing memory cells and the page buffer circuit. The page buffer circuit includes a plurality of page buffer cells and a plurality of cache latches. The plurality of cache latches are spaced apart from the plurality of page buffer cells along a first horizontal direction and correspond to a respective page buffer cell among the plurality of page buffer cells. Each page buffer cell includes a transmission transistor connected to each sensing node and driven in response to a transmission control signal. The page buffer circuit is configured to perform a data transfer operation configured to dump sensing data from a second portion of the page buffer cells to a second portion of the cache latch based on performing a first data output operation for outputting data provided from a first portion of the page buffer cells from a first portion of the cache latch to a data input / output (I / O) line.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0101529, filed on August 13, 2020, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2020-0175022, filed on December 15, 2020, with the disclosure of each of the Korean Patent Applications, which is incorporated herein by reference in its entirety. Technical Field

[0002] The example embodiments generally relate to semiconductor memory devices, and more specifically, to page buffer circuitry and non-volatile memory devices including the page buffer circuitry. Background Technology

[0003] Semiconductor memory devices used for storing data can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices (such as dynamic random access memory (DRAM) devices) are typically configured to store data by charging or discharging capacitors in memory cells, and the stored data is lost when power is off. Non-volatile memory devices (such as flash memory devices) retain stored data even when power is off. Volatile memory devices are widely used as main memory in various devices, while non-volatile memory devices are widely used to store program code and / or data in various electronic devices (such as computers, mobile devices, etc.).

[0004] Recently, three-dimensional non-volatile memory devices (such as vertical NAND memory devices) have been developed to increase the integration density and memory capacity of non-volatile memory devices. Non-volatile memory devices may include page buffer circuitry for storing data in or outputting data from memory cells, and the page buffer circuitry may include semiconductor devices (such as transistors). Due to the increased integration density of non-volatile memory devices leading to the need for smaller page buffer circuitry and advancements in process technology, the size of the semiconductor devices included in the page buffer circuitry can be reduced; therefore, the layout of wiring connected to the semiconductor devices may become more complex. Summary of the Invention

[0005] Some example embodiments may provide non-volatile memory devices that can improve the efficiency of programming operations.

[0006] Some example embodiments may provide a method for programming in a non-volatile memory device that can improve the efficiency of programming operations.

[0007] According to some example embodiments, a non-volatile memory device includes a memory cell array comprising a plurality of memory cells and a page buffer circuit. The page buffer circuit includes a plurality of page buffer cells and a plurality of cache latches. The plurality of page buffer cells are disposed along a first horizontal direction and connected to each of the plurality of memory cells via a plurality of bit lines. The plurality of cache latches are spaced apart from the plurality of page buffer cells along the first horizontal direction, and the plurality of cache latches correspond to a respective page buffer cell among the plurality of page buffer cells. Each of the plurality of page buffer cells includes a transmission transistor connected to each sensing node and driven in response to a transmission control signal. The page buffer circuit is configured to perform a data transfer operation based on performing a first data output operation, the first data output operation being used to output data provided from a first portion of the page buffer cells from a first portion of the cache latches to a data input / output line, and the data transfer operation being configured to dump sensing data from a second portion of the page buffer cells to a second portion of the cache latches.

[0008] According to some example embodiments, a non-volatile memory device includes a memory cell array comprising a plurality of memory cells and a page buffer circuit. The page buffer circuit includes a plurality of page buffer cells and a plurality of cache latches. The plurality of page buffer cells are connected to each of the plurality of memory cells along a first horizontal direction and via a plurality of bit lines. The plurality of cache latches are spaced apart from the plurality of page buffer cells along the first horizontal direction, and the plurality of cache latches correspond to a respective page buffer cell among the plurality of page buffer cells. The plurality of cache latches are commonly connected to a data transmission line. Each of the plurality of page buffer cells includes a transmission transistor connected to each sensing node, connected to the data transmission line, and driven in response to a transmission control signal. While performing the first data output operation, the page buffer circuit performs a data transfer operation. The first data output operation is used to output data provided from a first portion of the page buffer units among the plurality of page buffer units from a first portion of the cache latches among the plurality of cache latches to the data input / output (I / O) line. The data transfer operation is used to dump the sensed data from a second portion of the page buffer units among the plurality of page buffer units to a second portion of the cache latches among the plurality of cache latches.

[0009] According to some example embodiments, a non-volatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a plurality of memory cells connected to each of a plurality of bit lines extending along a first horizontal direction. The second semiconductor layer, in a direction perpendicular to the first semiconductor layer, includes page buffer circuitry. The page buffer circuitry includes a main region and a cache region. The main region includes a plurality of page buffer cells along the first horizontal direction. The cache region is adjacent to the main region along the first horizontal direction and includes a plurality of cache latches connected along the first horizontal direction and commonly connected to a combined sensing node. The plurality of cache latches respectively correspond to a corresponding page buffer cell among the plurality of page buffer cells. Each of the plurality of page buffer cells includes a transmission transistor connected to each sensing node and driven in response to a transmission control signal. While performing the first data output operation, the page buffer circuit performs a data transfer operation. The first data output operation is used to output data provided from a first portion of the page buffer units among the plurality of page buffer units from a first portion of the cache latches among the plurality of cache latches to the data input / output (I / O) line. The data transfer operation is used to dump the sensed data from a second portion of the page buffer units among the plurality of page buffer units to a second portion of the cache latches among the plurality of cache latches.

[0010] According to some example embodiments, a page buffer circuit includes a plurality of page buffer units and a plurality of cache latches. The plurality of cache latches are commonly connected to the plurality of page buffer units via a combined sensing node, and the plurality of cache latches correspond to a specific page buffer unit among the plurality of page buffer units. Each of the plurality of page buffer units includes a pair of transfer transistors and a sensing node for connecting the pair of transfer transistors to each other. During data transmission, a sensing node line, including in each of the plurality of page buffer units, is connected to the combined sensing node between the plurality of page buffer units and the plurality of cache latches, and the plurality of page buffer units are electrically connected to the plurality of cache latches. While the page buffer circuit performs the first data output operation, the page buffer circuit is configured to perform a data transfer operation. The first data output operation is used to output data provided from a first portion of the page buffer units among the plurality of page buffer units from a first portion of the cache latches among the plurality of cache latches to a data input / output (I / O) line. The data transfer operation is used to dump sensed data from a second portion of the page buffer units among the plurality of page buffer units to a second portion of the cache latches among the plurality of cache latches.

[0011] According to some example embodiments, a non-volatile memory device includes a memory cell region and a peripheral circuitry region. The memory cell region includes a plurality of memory cells and a first metal pad. The peripheral circuitry region includes a second metal pad and is vertically connected to the first and second metal pads of the memory cell region. The peripheral circuitry region includes a page buffer circuit comprising a plurality of page buffer units and a plurality of cache latches. The plurality of page buffer units are connected to each of the plurality of memory cells along a first horizontal direction and via a plurality of bit lines. The plurality of cache latches are spaced apart from the plurality of page buffer units along the first horizontal direction and are collectively connected to a combined sensing node. The plurality of cache latches correspond to a specific page buffer unit among the plurality of page buffer units. Each of the plurality of page buffer units includes a transmission transistor connected to each sensing node and driven based on a transmission control signal. While performing the first data output operation, the page buffer circuit performs a data transfer operation. The first data output operation is used to output data provided from a first portion of the page buffer units among the plurality of page buffer units from a first portion of the cache latches among the plurality of cache latches to the data input / output (I / O) line. The data transfer operation is used to dump the sensed data from a second portion of the page buffer units among the plurality of page buffer units to a second portion of the cache latches among the plurality of cache latches.

[0012] Therefore, the page buffer circuit in a non-volatile memory device includes multiple page buffer units and multiple cache latches. The multiple cache latches are collectively connected to the multiple page buffer units via a combined sensing node. While the page buffer circuit performs a first data output operation, it is also configured to perform a data transfer operation. The first data output operation outputs data from a first portion of the page buffer units from one of the multiple page buffer units to a data input / output (I / O) line. The data transfer operation dumps sensed data from a second portion of the page buffer units to a second portion of the multiple cache latches. Thus, the non-volatile memory device can reduce the intervals associated with read operations. Attached Figure Description

[0013] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 This is a block diagram of a non-volatile memory device according to an example embodiment.

[0015] Figure 2This is a block diagram illustrating a memory system including a non-volatile memory device according to an example embodiment.

[0016] Figure 3 Schematic illustration according to an example embodiment Figure 1 The structure of a non-volatile memory device.

[0017] Figure 4A This illustrates an example embodiment. Figure 1 A block diagram of an example memory cell array.

[0018] Figure 4B It shows Figure 4A A circuit diagram of one of the memory blocks.

[0019] Figure 4C It shows Figure 4B An example of the structure of the cell string CS in a memory block.

[0020] Figure 5 According to the example embodiment Figure 1 A schematic diagram showing the connection between the memory cell array and the page buffer circuit.

[0021] Figure 6 The page buffer according to the example embodiment is shown in detail.

[0022] Figure 7 This is a timing diagram illustrating an example of the voltage level of the transmission control signal according to the core operation sequence in an example embodiment.

[0023] Figure 8 This is a timing diagram of another example of the voltage level of the transmission control signal according to the core operation sequence in the example embodiment.

[0024] Figure 9 This is a plan view of the page buffer circuit according to an example embodiment.

[0025] Figure 10A This illustrates an example embodiment. Figure 9 A circuit diagram of an example page buffer circuit.

[0026] Figure 10B This is a circuit diagram illustrating an example of a page buffer circuit according to an exemplary embodiment.

[0027] Figure 11 It is a timing diagram of the voltage levels of multiple transmission control signals according to the core operation sequence in an example embodiment.

[0028] Figure 12 This is a timing diagram illustrating an example of a data dumping operation of a page buffer circuit according to an example embodiment.

[0029] Figure 13 This is a circuit diagram illustrating an example of a cache unit according to an exemplary embodiment.

[0030] Figure 14 This is a timing diagram illustrating an example of data dumping and data output operations of a page buffer circuit according to an example embodiment.

[0031] Figure 15A An example operation of a page buffer circuit according to an example embodiment is shown.

[0032] Figure 15B An example operation of a page buffer circuit according to an example embodiment is shown.

[0033] Figure 16 The configuration of the data I / O lines corresponding to a group (mat) according to an example embodiment is shown.

[0034] Figure 17 The mapping between burst length and column address in a page buffer circuit according to an example embodiment is shown.

[0035] Figure 18 This is a timing diagram illustrating the operation of a non-volatile memory device according to an example embodiment.

[0036] Figure 19 This is a timing diagram illustrating the operation of a non-volatile memory device according to an example embodiment.

[0037] Figure 20 This is a timing diagram illustrating the operation of a non-volatile memory device according to an example embodiment.

[0038] Figure 21 The arrangement of the first page buffer unit to the eighth page buffer unit and the first cache unit to the eighth cache unit in a page buffer circuit according to an example embodiment is shown.

[0039] Figure 22 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0040] Figure 23 This is a plan view illustrating the page buffer circuitry and page buffer decoder (PBDEC) according to an example embodiment.

[0041] Figure 24 A page buffer circuit and PBDEC according to an example embodiment are shown.

[0042] Figure 25 This is a cross-sectional view of a non-volatile memory device according to an example embodiment.

[0043] Figure 26 This is a block diagram illustrating a storage device including a non-volatile memory device according to an example embodiment. Detailed Implementation

[0044] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, some of which illustrate exemplary embodiments.

[0045] It will be understood that, according to the example embodiments described herein (including...), Figure 1 The peripheral circuit 200 shown in the figure Figure 1 The memory cell array (MCA) 100 shown in the figure Figure 2 Some or all of the elements of any example embodiment of the memory controller 40, any combination thereof, etc. shown may be included in one or more examples of processing circuitry (such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof), and / or may be implemented by one or more instances of processing circuitry (such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof). In some example embodiments, the one or more instances of processing circuitry may include, but are not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC), etc. In some example embodiments, any of the memory, memory cell, etc., as described herein may include a non-transitory computer-readable storage device (e.g., a solid-state drive (SSD)) storing a program of instructions, and one or more instances of processing circuitry may be configured to execute the program of instructions to perform some or all of the functions of any of the devices, controllers, decoders, units, modules, etc., according to any of the example embodiments described herein, including any of the methods of operating any of any of the devices, controllers, decoders, units, modules, etc., as described herein.

[0046] Figure 1 This is a block diagram of a non-volatile memory device according to an example embodiment.

[0047] Reference Figure 1The non-volatile memory device 10 may include a memory cell array 100 and peripheral circuitry 200. Peripheral circuitry 200 may include page buffer circuitry 210, control circuitry 220, voltage generator 230, address decoder 240 (e.g., address decoder circuitry), and data input / output (I / O) circuitry 250. Although... Figure 1 Although not shown in the diagram, the peripheral circuit 200 may also include I / O interfaces, column logic, pre-decoder, temperature sensor, command decoder, etc.

[0048] The memory cell array 100 can be integrated into the address decoder 240 via a serial select line SSL, multiple word lines WL, and a ground select line GSL. Optionally or additionally, the memory cell array 100 can be connected to the page buffer circuit 210 via multiple bit lines BL. The memory cell array 100 may include multiple non-volatile memory cells connected to the multiple word lines WL and the multiple bit lines BL.

[0049] The memory cell array 100 may include a plurality of memory blocks BLK1 to BLKz, and each of the memory blocks BLK1 to BLKz (z is any positive integer) may have a three-dimensional (3D) structure. The memory cell array 100 may include a plurality of vertical cell strings, and each vertical cell string includes a plurality of memory cells stacked relative to each other.

[0050] The control circuit 220 can receive commands CMD, address ADDR, and control signals CTRL from the memory controller, and can control the erase cycle, programming cycle, and read operation of the non-volatile memory device 10. The programming cycle can include programming operations and programming verification operations, and the erase cycle can include erase operations and erase verification operations.

[0051] In some example embodiments, control circuitry 220 may generate control signals CTL for controlling voltage generator 230 based on command CMD, page buffer control signals PBCTL for controlling page buffer circuitry 210, and row address R_ADDR and column address C_ADDR based on address ADDR. Control circuitry 220 may provide control signals CTL to voltage generator 230 and page buffer control signals PBCTL to page buffer circuitry 210. Optionally or additionally, control circuitry 220 may provide row address R_ADDR to address decoder 240 and column address C_ADDR to data I / O circuitry 250. Control circuitry 220 may include state generator 225, and state generator 225 may generate a state signal RnB indicating the operating state of non-volatile memory device 10. Because state signal RnB indicates a busy or ready state of non-volatile memory device 10, state signal RnB may be referred to as a ready / busy signal.

[0052] Address decoder 240 can be connected to memory cell array 100 via serial select line SSL, multiple word lines WL, and ground select line GSL. During programming or reading operations, address decoder 240 can determine one of the multiple word lines WL as the selected word line based on the row address R_ADDR, and can determine the remaining word lines in the multiple word lines WL as unselected word lines.

[0053] Voltage generator 230 can generate word line voltages VWL associated with the operation of the non-volatile memory device 10 using power PWR supplied from the memory controller, based on control signal CTL from control circuitry 220. Word line voltages VWL can include programming voltages, read voltages, transfer voltages, erase verification voltages, or program verification voltages. Word line voltages VWL can be applied to multiple word lines WL via address decoder 240.

[0054] In some example embodiments, during an erase operation, voltage generator 230 may apply an erase voltage to the well of the selected memory block and may apply a ground voltage to all word lines of the selected memory block. During an erase verification operation, voltage generator 230 may apply an erase verification voltage to all word lines of the selected memory block, or may apply an erase verification voltage to the word lines of the selected memory block on a word line basis.

[0055] In some example embodiments, during a programming operation, voltage generator 230 may apply a programming voltage to a selected word line and a programming pass voltage to an unselected word line. Alternatively or additionally, during a programming verification operation, voltage generator 230 may apply a programming verification voltage to a selected word line and a verification pass voltage to an unselected word line. Alternatively or additionally, during a read operation, voltage generator 230 may apply a read voltage to a selected word line and a read pass voltage to an unselected word line.

[0056] Page buffer circuit 210 can be connected to memory cell array 100 via multiple bit lines BL. Page buffer circuit 210 may include multiple page buffers PB. Page buffer circuit 210 can store (e.g., temporarily store) data that will be programmed into selected pages of memory cell array 100 or data read from selected pages of memory cell array 100.

[0057] In some example embodiments, a page buffer cell (e.g., included in each of a plurality of page buffers PB) is included. Figure 5The first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn) and the cache latches included in each of the multiple page buffers PB (e.g., Figure 5 The first cache latch CL0 to the (n+1)th cache latch CLn can be separated from each other and have independent structures. Therefore, the routing freedom on the page buffer unit can be increased, and the layout complexity can be reduced. Alternatively or additionally, because the cache latches are adjacent to the data I / O lines, the distance between the cache latches and the data I / O lines can be reduced, thus increasing the data I / O speed.

[0058] Optionally or additionally, when the page buffer circuit 210 performs a first data output operation, it can also perform a data transfer operation. The first data output operation is used to output data provided from a first portion of the page buffer units among the plurality of page buffer units from a first portion of the cache latches among the plurality of cache latches to the data I / O line. The data transfer operation is used to dump sensed data from a second portion of the page buffer units among the plurality of page buffer units to a second portion of the cache latches among the plurality of cache latches. That is, the page buffer circuit 210 essentially performs the first data output operation and the data transfer operation simultaneously. Therefore, the read time of the non-volatile memory device 10 can be reduced.

[0059] Page buffer circuit 210 may also include register 270 disposed between page buffer circuit 210 and data I / O circuit 250. Register 270 may temporarily store data output from cache latch. Register 270 may include a first register segment (PRL_SG1) 271 and a second register segment (PRL_SG2) 273 distributed between page buffer circuit 210 and data I / O circuit 250. The number of register segments distributed between page buffer circuit 210 and data I / O circuit 250 may vary based on the distance between page buffer circuit 210 and data I / O circuit 250.

[0060] In some example embodiments, a first data output operation can be performed by sequentially moving data to register 270 based on the column address C_ADDR selected for the data output operation and outputting the data through data I / O circuit 250. When performing a data output operation after the status signal RnB transitions to the ready state, the data to be output from the cache latch is moved to register 270 before the status signal RnB transitions to the ready state to reduce the waiting time of the data output operation.

[0061] Data I / O circuit 250 can be connected to register 270 via data line DL. During programming operations, data I / O circuit 250 can access the memory controller (…). Figure 2 The data I / O circuit 250 receives programming data DATA and provides the programming data DATA to the page buffer circuit 210 based on the column address C_ADDR received from the control circuit 220. During a read operation, the data I / O circuit 250 may provide read data DATA to the memory controller 40 based on the column address C_ADDR received from the control circuit 220.

[0062] The data line DL may be referred to as a data I / O line, and the data I / O circuit 250 may include I / O pads connected to the data I / O line.

[0063] In some example embodiments, each page buffer unit may include a pair of transfer transistors (e.g., Figure 9 TR0 and TR0' in the figure), and sensing node lines for connecting the pair of transmission transistors to each other (e.g., Figure 9 MT0a in the example. In some example embodiments, the sensing node line can be implemented as the underlying metal layer (e.g., Figure 9 A trace of LM0 in the page buffer circuit can correspond to a sensing node. During the data sensing period, the transfer transistors included in each of the multiple page buffer units may not be electrically connected to each other, and therefore, the sensing node lines included in each of the multiple page buffer units may not be electrically connected to each other. On the other hand, during the data transmission period, the transfer transistors included in each of the multiple page buffer units may be connected in series with each other, and therefore, the sensing node lines included in each of the multiple page buffer units may be electrically connected to each other and used as data transmission lines. Therefore, since the page buffer circuit 210 does not need to include multiple data transmission lines separately for connecting the multiple page buffer units to the corresponding cache latches in the multiple cache latches, the area occupied by the page buffer circuit 210 can be reduced.

[0064] Although each of the page buffer circuit 210, control circuit 220, voltage generator 230, address decoder 240 (e.g., address decoder circuit), and data input / output (I / O) circuit 250 is shown as different, the example embodiment is not limited thereto, and some of the functions of one of the page buffer circuit 210, control circuit 220, voltage generator 230, address decoder 240 (e.g., address decoder circuit), and data input / output (I / O) circuit 250 may be performed by others of the page buffer circuit 210, control circuit 220, voltage generator 230, address decoder 240 (e.g., address decoder circuit), and data input / output (I / O) circuit 250. This may also be the case for additional elements within the peripheral circuitry 200, as described in the example embodiment herein.

[0065] Figure 2 This is a block diagram illustrating a memory system including a non-volatile memory device according to an example embodiment.

[0066] Reference Figure 2 The memory system 30 may include a memory controller 40 and a non-volatile memory device 10.

[0067] The memory controller 40 can control the operation of the non-volatile memory device 10 by applying control signals CTRL, commands CMD, and addresses ADDR to the non-volatile memory device 10, and can exchange data DATA with the non-volatile memory device 10. The non-volatile memory device 10 can provide a status signal RnB indicating the operating state of the non-volatile memory device 10. In some example embodiments, when the status signal RnB is at a logic high level (ready state), the status signal RnB indicates that the non-volatile memory device 10 is ready to receive commands from the memory controller 40.

[0068] Figure 3 The illustration schematically shows an example embodiment. Figure 1 The structure of a non-volatile memory device.

[0069] Reference Figure 3 The memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked relative to the second semiconductor layer L2 in a vertical direction (or third direction) VD. The second semiconductor layer L2 may be located below the first semiconductor layer L1 in the vertical direction VD, and therefore, the second semiconductor layer L2 may be close to the substrate.

[0070] In some example embodiments, Figure 1 The memory cell array 100 can be formed (or disposed) on the first semiconductor layer L1, and Figure 1The peripheral circuitry 200 can be formed (or disposed) on the second semiconductor layer L2. Therefore, the memory device 10 can have a structure in which the memory cell array 100 is located on the peripheral circuitry 200 (i.e., a cell-over-periphery (COP) structure). The COP structure can effectively reduce the area in the horizontal direction and improve the integration density of the memory device 10.

[0071] In some example embodiments, the second semiconductor layer L2 may include a substrate, and transistors and metal patterns for wiring the transistors may be formed on the substrate (e.g., Figure 9 The peripheral circuitry 200 can be formed in the second semiconductor layer L2, which contains a first lower metal layer LM0 and a third lower metal layer LM2. After the peripheral circuitry 200 is formed on the second semiconductor layer L2, a first semiconductor layer L1 including the memory cell array 100 can be formed, and a metal pattern for connecting the word lines WL and bit lines BL of the memory cell array 100 to the peripheral circuitry 200 formed in the second semiconductor layer L2 can be formed. In some example embodiments, the bit line BL can extend in a first horizontal direction (or first direction) HD1, and the word line WL can extend in a second horizontal direction (or second direction) HD2.

[0072] As semiconductor technology advances, the number of memory cell levels in the memory cell array 100 increases (i.e., due to the increased number of stacked word lines WL), allowing for a reduction in the area of ​​the memory cell array 100, and consequently, a reduction in the area of ​​the peripheral circuitry 200. According to some example embodiments, to reduce the area occupied by the page buffer circuitry 210, the page buffer circuitry 210 may have a structure where the page buffer cells and cache latches are separated from each other, and the page buffer circuitry 210 may connect the sensing nodes included in each page buffer cell to a combined sensing node. This will be referred to... Figure 9 Detailed explanation.

[0073] Figure 4A This illustrates an example embodiment. Figure 1 A block diagram of an example memory cell array.

[0074] Reference Figure 4A The memory cell array 100 may include multiple memory blocks BLK1 to BLKz extending along multiple directions HD1, HD2, and VD. In some example embodiments, memory blocks BLK1 to BLKz are... Figure 1 The address decoder 240 selects the memory block BLK corresponding to the block address from among memory blocks BLK1 to BLKz. In some example embodiments, the address decoder 240 can select the memory block BLK corresponding to the block address from among memory blocks BLK1 to BLKz.

[0075] Figure 4B It is shown Figure 4A A circuit diagram of one of the memory blocks.

[0076] Figure 4B The memory block BLKi can be formed on the substrate SUB in a three-dimensional (or vertical) structure. In some example embodiments, multiple strings of memory cells included in the memory block BLKi can be formed on a direction PD perpendicular to the substrate SUB.

[0077] Reference Figure 4B The memory block BLKi may include memory cell strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common-source line CSL. Each of the memory cell strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST. Figure 4B In the diagram, each of the memory cell strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, the inventive concept is not limited thereto. In some example embodiments, each of the memory cell strings NS11 to NS33 may include any number of memory cells.

[0078] The serial select transistor SST can be connected to the corresponding serial select lines SSL1 to SSL3. Multiple memory cells MC1 to MC8 can be connected to their respective word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select lines GSL1 to GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0079] Word lines (e.g., WL1) at the same height (e.g., at the same position relative to the surface of the substrate) can be commonly connected, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated / electrically separated.

[0080] Figure 4C It shows Figure 4B An example of the structure of the cell string CS in a memory block.

[0081] Reference Figure 4B and Figure 4C The post PL is disposed on the base SUB such that the post PL extends in a direction perpendicular to the base SUB to contact the base SUB. Figure 4CEach of the ground select line GSL1, word lines WL1 to WL8, and string select line SSL1 shown can be formed of a conductive material (in some example embodiments, a metallic material) parallel to the substrate SUB. The post PL can be in contact with the substrate SUB through the conductive material forming the string select lines SSL1, word lines WL1 to WL8, and ground select line GSL1.

[0082] Figure 4C The diagram also shows a cross-sectional view taken along line A-A'. In some example embodiments, a cross-sectional view of the first memory cell MC1 corresponding to the first word line WL1 is shown. The pillar PL may include a cylindrical body BD and may be tapered. The air gap AG may be defined inside the body BD.

[0083] The main body BD may include P-type silicon and may be the region where the channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the main body BD and a cylindrical charge trapping layer Ct surrounding the tunnel insulating layer TI. A barrier insulating layer BI may be disposed between the first word line WL1 and the pillar PL. The main body BD, tunnel insulating layer TI, charge trapping layer Ct, barrier insulating layer BI, and first word line WL1 may constitute a charge trapping transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB, or may be included in a charge trapping transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string select transistor SST, ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0084] Figure 5 According to the example embodiment Figure 1 A schematic diagram showing the connection between the memory cell array and the page buffer circuit.

[0085] Reference Figure 5 The memory cell array 100 may include a first NAND string NS0 to a (n+1)th NAND string NSn. Each of the first NAND strings NS0 to the (n+1)th NAND string NSn may include a ground select transistor GST connected to a ground select line GSL, a plurality of memory cells MC connected to a corresponding word line among the first word lines WL0 to the (m+1)th word lines WLm, and a string select transistor SST connected to a string select line SSL. The ground select transistor GST, the plurality of memory cells MC, and the string select transistor SST may be connected in series with each other. In other words, the plurality of memory cells MC may be connected to the corresponding first word lines WL0 to the (m+1)th word lines WLm. In some example embodiments, m may be a positive integer.

[0086] Page buffer circuit 210 may include a first page buffer unit PBU0 to a (n+1)th page buffer unit PBUn. The first page buffer unit PBU0 may be connected to a first NAND string NS0 via a first bit line BL0, and the (n+1)th page buffer unit PBUn may be connected to the (n+1)th NAND string NSn via a (n+1)th bit line BLn. In some example embodiments, n may be a positive integer. In some example embodiments, n may be 7, and page buffer circuit 210 may have eight levels of page buffer units or a structure in which the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn are arranged in a row. In some example embodiments, the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn may be arranged in a row along the extension direction of the first bit line BL0 to the (n+1)th bit line BLn.

[0087] Page buffer circuit 210 may further include first cache latches CL0 to (n+1) cache latches CLn, corresponding to the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn, respectively. That is, the first cache latches CL0 to (n+1)th cache latches CLn may correspond to the corresponding page buffer units in the first page buffer units PBU0 to (n+1)th page buffer units PBUn. In some example embodiments, page buffer circuit 210 may have an eight-level cache latch structure or a structure where the first cache latches CL0 to (n+1)th cache latches CLn are arranged in a row. In some example embodiments, the first cache latches CL0 to (n+1)th cache latches CLn may be arranged in a row along the extension direction of the first bit line BL0 to the (n+1)th bit line BLn.

[0088] The sensing nodes of each of the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn can be collectively connected to the combined sensing node (or combined sensing node) SOC. Optionally or additionally, the first cache latch CL0 to the (n+1)th cache latch CLn can be collectively connected to the combined sensing node SOC. Therefore, the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn can be connected to the first cache latch CL0 to the (n+1)th cache latch CLn via the combined sensing node SOC.

[0089] Figure 6 The page buffer according to the example embodiment is shown in detail.

[0090] Reference Figure 6 The page buffer PB can correspond to Figure 1An example of a page buffer PB is provided. The page buffer PB may include a page buffer unit PBU and a cache unit CU. Because the cache unit CU includes a cache latch (C-LATCH) CL, and the C-LATCH CL is connected to a data input / output line (not shown), the cache unit CU may be adjacent to the data input / output line. Therefore, the page buffer unit PBU and the cache unit CU may be separate from each other, and the page buffer PB may have a structure in which the page buffer unit PBU and the cache unit CU are separate from each other.

[0091] Page buffer unit PBU may include master unit MU. Master unit MU may include master transistors in page buffer PB. Page buffer unit PBU may also include bit line select transistor TR_hv connected to bit line BL and driven by bit line select signal BLSLT. Bit line select transistor TR_hv may include high-voltage transistor, and therefore, bit line select transistor TR_hv may be in a different well region from master unit MU (i.e., in high-voltage unit HVU).

[0092] The master unit MU may include a sense latch (S-LATCH) SL, a force latch (F-LATCH) FL, a higher latch (M-LATCH) ML, and a lower latch (L-LATCH) LL. According to some example embodiments, S-LATCH SL, F-LATCH FL, M-LATCH ML, or L-LATCH LL may be referred to as the master latch. The master unit MU may also include a precharge circuit PC capable of controlling the precharge operation of the bit line BL or the sense node SO based on the bit-line clamping control signal BLCLAMP, and the master unit MU may also include a transistor PM' driven by the bit-line setup signal BLSETUP.

[0093] S-LATCH SL can store data stored in memory cell MC or a sensed result of the threshold voltage of memory cell MC during read or program verification operations. Optionally or additionally, S-LATCH SL can be used to apply a programming bit line voltage or a programming inhibit voltage to bit line BL during programming operations. F-LATCH FL can be used to improve the threshold voltage distribution during programming operations. F-LATCH FL can store forced data. After the forced data is initially set to "1", it can be converted to "0" when the threshold voltage of memory cell MC enters a forced region with a voltage lower than the target region. By utilizing forced data during programming execution operations, the bit line voltage can be controlled, and the programming threshold voltage distribution can be narrower.

[0094] M-LATCH ML, L-LATCH LL, and C-LATCH CL can be used to store externally input data during programming operations and can be referred to as data latches. When 3 bits of data are programmed into a memory cell MC, the 3 bits of data can be stored in M-LATCH ML, L-LATCH LL, and C-LATCH CL respectively. M-LATCH ML, L-LATCH LL, and C-LATCH CL can retain the stored data until the programming of the memory cell MC is complete. Optionally or additionally, C-LATCH CL can receive data read from the memory cell MC during a read operation from S-LATCH SL and output the received data externally via data input / output lines.

[0095] Optionally or additionally, the main unit MU may also include a first transistor NM1 to a fourth transistor NM4. The first transistor NM1 may be connected (e.g., directly connected) between sensing node SO and S-LATCH SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected (e.g., directly connected) between sensing node SO and F-LATCH FL, and may be driven by the forced monitoring signal MON_F. The third transistor NM3 may be connected (e.g., directly connected) between sensing node SO and M-LATCH ML, and may be driven by the high-order monitoring signal MON_M. The fourth transistor NM4 may be connected (e.g., directly connected) between sensing node SO and L-LATCH LL, and may be driven by the low-order monitoring signal MON_L.

[0096] Optionally or additionally, the main unit MU may further include a fifth transistor NM5 and a sixth transistor NM6 connected in series between the bit line selection transistor TV_hv and the sensing node SO. The fifth transistor NM5 may be driven by a bit line off signal BLSHF, and the sixth transistor NM6 may be driven by a bit line connection control signal CLBLK. Optionally or additionally, the main unit MU may further include a precharge transistor PM. The precharge transistor PM may be connected to the sensing node SO, driven by a load signal LOAD, and precharges the sensing node SO to a precharge level during the precharge period.

[0097] In some example embodiments, the main unit MU may further include a pair of transmission transistors connected to the sensing node SO, or a first transmission transistor TR and a second transmission transistor TR'. According to some example embodiments, the first transmission transistor TR and the second transmission transistor TR' may also be referred to as a first sensing node connection transistor and a second sensing node connection transistor, respectively. The first transmission transistor TR and the second transmission transistor TR' may be driven in response to a transmission control signal SO_PASS. According to some example embodiments, the transmission control signal SO_PASS may be referred to as a sensing node connection control signal. The first transmission transistor TR may be connected between the first terminal SOC_U and the sensing node SO, and the second transmission transistor TR' may be connected between the sensing node SO and the second terminal SOC_D.

[0098] In some example embodiments, when the page buffer unit (PBU) corresponds to Figure 5 When the second page buffer unit PBU1 is in the middle, the first terminal SOC_U can be connected to one end of the transmission transistor included in the first page buffer unit PBU0, and the second terminal SOC_D can be connected to one end of the transmission transistor included in the third page buffer unit PBU2. In this way, the sensing node SO can be electrically connected to the combined sensing node SOC via the transmission transistor included in each of the third page buffer unit PBU2 to the (n+1)th page buffer unit PBUn.

[0099] During programming operations, the page buffer PB can verify whether programming is complete in a selected memory cell MC among the memory cells MC included in the NAND string connected to the bit line BL. The page buffer PB can store data sensed via the bit line BL during the programming verification operation in the S-LATCH SL. The M-LATCH ML and L-LATCH LL, which store the target data, can be set based on the sensed data stored in the S-LATCH SL. In some example embodiments, when the sensed data indicates that programming is complete, the M-LATCH ML and L-LATCH LL can be switched to a programming-disabled setting for the selected memory cell MC in subsequent programming cycles. The C-LATCH CL can temporarily store input data provided from an external source. During programming operations, the target data to be stored in the C-LATCH CL can be stored in the M-LATCH ML and L-LATCH LL.

[0100] In the following text, it is assumed that the signals used to control the elements in the page buffer circuit 210 include Figure 1 The page buffer control signal PBCTL is used in the process.

[0101] Figure 7This is a timing diagram illustrating an example of the voltage level of the transmission control signal according to the core operation sequence in an example embodiment.

[0102] Refer to together Figure 6 and Figure 7 The core operation sequence can represent the operation of the page buffer PB, and in some example embodiments, the core operation sequence may include a data sensing period 71 that performs a data sensing operation, a data dumping period or data transfer period 72 that performs a data dumping operation, and a data output period (Dout) 73 that outputs the dumped data to the data I / O line (performing a data output operation Dout).

[0103] During the data sensing period 71, the transmission control signal SO_PASS can be deactivated, and the first transmission transistor TR and the second transmission transistor TR' can be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the combined sensing node SOC (i.e., the page buffer unit PBU may not be electrically connected to the cache unit CU). Alternatively or additionally, the page buffer unit PBU may also not be electrically connected to an adjacent page buffer unit PBU. In some example embodiments, the data sensing period 71 may include a precharge period for performing the operation of precharging the voltage of the bit line BL or the voltage of the sensing node SO to a precharge level, a development period for performing the operation of electrically connecting the bit line BL to the sensing node SO and developing the voltage of the sensing node SO, and a sensing period for performing the operation of sensing the voltage of the sensing node SO.

[0104] During data transfer period 72, the transfer control signal SO_PASS can be activated, and the first transfer transistor TR and the second transfer transistor TR' can be turned on. Therefore, the page buffer unit PBU can be electrically connected to the combined sensing node SOC (i.e., the page buffer unit PBU can be electrically connected to the cache unit CU). Optionally or additionally, the page buffer unit PBU can be electrically connected to an adjacent page buffer unit PBU. In some example embodiments, data transfer period 72 may include a period for performing an operation to dump read data stored in S-LATCH SL to C-LATCH CL, a period for performing an operation to dump programming data stored in C-LATCH CL to S-LATCH SL (data dump operation), or a period for transferring data stored in C-LATCH CL to data input / output circuitry, etc. Data transfer period 72 may partially overlap with the data output period.

[0105] Data dump operations are performed sequentially at each level of the page buffer unit (PBU), and when data dump operations are performed sequentially at each level of the page buffer unit (PBU), such as Figure 14As shown, the transmission control signal SO_PASS can be repeatedly activated and deactivated. In some example embodiments, when a data dump operation is performed in a page buffer unit in the third level (e.g., Figure 5 The PBU2 in the third level and the cache latch corresponding to the page buffer unit in the third level (e.g., Figure 5 When CL2 is executed, the transfer control signal SO_PASS is applied to the page buffer unit in the third level (e.g., ...). Figure 5 From PBU2 in level 2 to the page buffer unit in level 8 (e.g., ... Figure 5 PBU7 in the middle). Optionally or additionally, when a data dump operation is performed in a page buffer unit in the fourth level (e.g., Figure 5 The PBU3 in the fourth level and the cache latch corresponding to the page buffer unit in the fourth level (e.g., Figure 5 When CL3 is executed between the two levels, the transfer control signal SO_PASS is applied to the page buffer unit in the fourth level (e.g., ...). Figure 5 From PBU3 in level 3 to the page buffer unit in level 8 (e.g., ... Figure 5 (PBU7 in the middle).

[0106] Figure 8 This is a timing diagram of another example of the voltage level of the transmission control signal according to the core operation sequence in the example embodiment.

[0107] Refer to together Figure 6 and Figure 8 The core operation sequence can represent the operation of the page buffer PB. In some example embodiments, the core operation sequence can be a bit line setting period 81, a forced dump period 82, a bit line forced period 83, a data transfer period or a data dump period 84, and a mass bit count (MBC) period 85.

[0108] During the bit line setup period 81, the transmission control signal SO_PASS can be activated, and the first transmission transistor TR and the second transmission transistor TR' can be turned on. In some example embodiments, the sensing node SO and the combined sensing node SOC can be electrically connected to each other, so that data can be dumped from the main latch (e.g., S-LATCHSL, F-LATCHFL, M-LATCHML, or L-LATCHLL) included in the page buffer unit PBU to C-LATCHCL.

[0109] During the forced dump period 82 and the bit line forced period 83, the transfer control signal SO_PASS can be deactivated, and the first transfer transistor TR and the second transfer transistor TR' can be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the cache unit CU, and may also not be electrically connected to the adjacent page buffer unit PBU. During the forced dump period 82, when programming is performed, a dump operation can be performed to select the bit line BL to be forced to a bias lower than the supply voltage level. In some example embodiments, data can be dumped from F-LATCH FL to S-LATCH SL. During the bit line forced period 83, the voltage applied to the bit line BL can vary depending on the value stored in F-LATCH FL during programming execution.

[0110] During data transfer period 84, the transfer control signal SO_PASS can be activated, and the first transfer transistor TR and the second transfer transistor TR' can be turned on. In some example embodiments, during data transfer period 84, a dump operation can be performed such that data stored in the S-LATCH SL of a memory cell MC that has failed due to a programming verification operation and is connected to the memory cell MC that will be programmed to the target programming state when programming is performed is marked as logic low. In some example embodiments, because the sensing node SO and the combined sensing node SOC are electrically connected to each other, data can be dumped from C-LATCH CL to the master latch (e.g., S-LATCH SL).

[0111] During the quality bit counting period 85, the transmission control signal SO_PASS can be deactivated, and the first transmission transistor TR and the second transmission transistor TR' can be turned off. Therefore, the page buffer unit PBU can be de-electrically connected to the cache unit CU, and also de-electrically connected to adjacent page buffer units. During the quality bit counting period 85, the number of S-LATCH SLs marked as logic low in the previous data transmission period 84 can be counted.

[0112] Figure 9 This is a plan view of the page buffer circuit according to an example embodiment.

[0113] Refer to together Figure 3 and Figure 9The first semiconductor layer L1 may include a memory cell array 100, and the memory cell array 100 may include a plurality of memory cells MC respectively connected to a plurality of bit lines BL extending in the first horizontal direction HD1. That is, the plurality of memory cells MC may be connected to corresponding bit lines in the plurality of bit lines BL extending in the first horizontal direction HD1. In some example embodiments, the plurality of bit lines BL may be implemented as a first metal layer M1. In some example embodiments, the first metal layer M1 may be formed by using a dual patterning technique (DPT).

[0114] The second semiconductor layer L2 may include a page buffer circuit 210a, and a first lower metal layer LM0 extending in the first horizontal direction HD1 may be above the page buffer circuit 210a. A third lower metal layer LM2 extending in the first horizontal direction HD1 may be above the first lower metal layer LM0. Although not shown, a second lower metal layer extending in the second horizontal direction HD2 may also be disposed between the first lower metal layer LM0 and the third lower metal layer LM2. In some example embodiments, the first lower metal layer LM0 and the third lower metal layer LM2 may be formed without using DPT, so the spacing of the metal patterns included in each of the first lower metal layer LM0 and the third lower metal layer LM2 may be greater than the spacing of the metal patterns included in the first metal layer L1.

[0115] Page buffer circuit 210a may include first page buffer units PBU0 to eighth page buffer units PBU7 and first cache units CU0 to eighth cache units CU7 arranged on the first horizontal direction HD1. The first page buffer units PBU0 to eighth page buffer units PBU7 may be in the main region MR, and the first cache units CU0 to eighth cache units CU7 may be in the cache region CR, with the main region MR and the cache region CR being adjacent to each other on the first horizontal direction HD1. The first lower metal layer LM0 and the third lower metal layer LM2 may be used to transmit control signals to each of the transistors included in the first page buffer units PBU0 to eighth page buffer units PBU7 and the first cache units CU0 to eighth cache units CU7, or may be used to connect each transistor to a power supply terminal or a ground terminal.

[0116] Figure 10A This illustrates an example embodiment. Figure 9 A circuit diagram of an example page buffer circuit.

[0117] In the following text, we will refer to... Figure 9 and Figure 10A The configuration of the page buffer circuit 210a is described in detail.

[0118] Each page buffer unit may include two transfer transistors. Therefore, the page buffer circuit 210a may include 16 transfer transistors TR0, TR0', ..., TR7, TR7', and the 16 transfer transistors TR0, TR0', ..., TR7, TR7' may be connected in series with each other.

[0119] In some example embodiments, the first page buffer unit PBU0 may include a first transfer transistor TR0 and a second transfer transistor TR0' connected in series. In some example embodiments, the first transfer transistor TR0 may be adjacent to a first boundary of the first page buffer unit PBU0, and the second transfer transistor TR0' may be adjacent to a second boundary of the first page buffer unit PBU0, with the first and second boundaries facing each other. In some example embodiments, the first and second transfer transistors TR0 and TR0' may be implemented as NMOS transistors; therefore, the first and second transfer transistors TR0 and TR0' may be located at opposite ends of the P-well of the first page buffer unit PBU0, but the inventive concept is not limited thereto. Alternatively, another semiconductor device (in some example embodiments, a PMOS transistor) may be arranged between the first boundary of the first page buffer unit PBU0 and the first transfer transistor TR0. Similarly, another semiconductor device (in some example embodiments, a PMOS transistor) may be arranged between the second boundary of the first page buffer unit PBU0 and the second transfer transistor TR0'.

[0120] In some example embodiments, the first page buffer unit PBU0 may further include a plurality of transistors arranged in a first horizontal direction between the first transfer transistor TR0 and the second transfer transistor TR0' (e.g., Figure 6 (S-LATCHSL, F-LATCHFL, M-LATCHML and L-LATCHLL, first transistor NM1 to sixth transistor NM6, etc.). In the following description, the configuration of the first page buffer unit PBU0 will be described with emphasis, and each of the second page buffer units PBU1 to the eighth page buffer units PBU7 can be configured to be substantially the same as the first page buffer unit PBU0.

[0121] The first transfer transistor TR0 may include a source S0, a drain D0, and a gate G0. The source S0 of the first transfer transistor TR0 may be connected to a first terminal (e.g., Figure 6 The first transmission transistor TR0 can be connected to the first sensing node SO0, and the drain D0 of the first transmission transistor TR0 can be connected to the first sensing node SO0. The transmission control signal SO_PASS[7:0] can be applied to the gate G0 of the first transmission transistor TR0.

[0122] The second transmission transistor TR0' may include a source S0', a drain D0', and a gate G0'. The source S0' of the second transmission transistor TR0' may be connected to the first sensing node SO0, and the drain D0' of the second transmission transistor TR0' may be connected to a second terminal (in some example embodiments, Figure 6 (SOC_D in the middle). The transmission control signal SO_PASS[7:0] can be applied to the gate G0' of the second transmission transistor TR0'.

[0123] The second page buffer unit PBU1 may include a first transfer transistor TR1 and a second transfer transistor TR1' connected in series. The first transfer transistor TR1 may include a source S1, a drain D1, and a gate G1, and the second transfer transistor TR1' may include a source S1', a drain D1', and a gate G1'. The transfer control signal SO_PASS[7:0] may be applied to the gate G1 of the first transfer transistor TR1 and the gate G1' of the second transfer transistor TR1', respectively.

[0124] The eighth page buffer unit PBU7 may include a first transmission transistor TR7 and a second transmission transistor TR7' connected in series. The first transmission transistor TR7 may include a source S7, a drain D7, and a gate G7, and the second transmission transistor TR7' may include a source S7', a drain D7', and a gate G7'. The transmission control signal SO_PASS[7:0] may be applied to the gate G7 of the first transmission transistor TR7 and the gate G7' of the second transmission transistor TR7', respectively. However, the inventive concept is not limited thereto, and in some example embodiments, the combined sensing node transmission control signal SOC_PASS may be applied to the gate G7' of the second transmission transistor TR7'.

[0125] The first cache unit CU0 may include a monitoring transistor NM7a, and the monitoring transistor NM7a may include a source S, a drain D, and a gate G (see reference). Figure 9 In some example embodiments, the monitoring transistor NM7a may correspond to... Figure 6 The source S of the monitoring transistor NM7a can be connected to the combined sensing node SOC, and the cached monitoring signal MON_C[7:0] can be applied to the gate G of the monitoring transistor NM7a.

[0126] Although not shown, the first cache unit CU0 may also include a plurality of transistors arranged on the first horizontal direction HD1 (e.g., including...). Figure 6(Multiple transistors in the C-LATCH CL). Each of the second cache units CU1 to the eighth cache units CU7 may have a configuration substantially the same as that of the first cache unit CU0. The monitoring transistors NM7a to NM7h included in each of the first cache units CU0 to the eighth cache units CU7 may be connected in parallel to the combined sensing node SOC. The source of each of the monitoring transistors NM7a to NM7h may be connected in parallel to the combined sensing node SOC.

[0127] In the first page buffer unit PBU0, the drain D0 of the first transfer transistor TR0 and the source S0' of the second transfer transistor TR0' can be connected to each other via a first wire or a first metal pattern MT0a. The first metal pattern MT0a can correspond to the first sensing node SO0, and therefore the first metal pattern MT0a can be referred to as the first sensing node line. In the second page buffer unit PBU1, the drain D1 of the first transfer transistor TR1 and the source S1' of the second transfer transistor TR1' can be connected to each other via a first wire or a first metal pattern MT0b. The first metal pattern MT0b can correspond to the second sensing node SO1, and therefore the first metal pattern MT0b can be referred to as the second sensing node line.

[0128] In the eighth page buffer unit PBU7, the drain D7 of the first transfer transistor TR7 and the source S7' of the second transfer transistor TR7' can be connected to each other via a first metal pattern MT0c. The first metal pattern MT0c can correspond to the eighth sensing node SO7 and is therefore referred to as the eighth sensing node line. In the eighth page buffer unit PBU7, the drain D7' of the second transfer transistor TR7' and the source S of the monitoring transistor NM7a of the first cache unit CU0 can be connected to each other via a first metal pattern MT0d. In some example embodiments, the first metal pattern MT0d can also be connected to the precharge circuit SOC_PRE. The first metal pattern MT0d can correspond to the combined sensing node SOC and is therefore referred to as the combined sensing node line. In some example embodiments, the first metal patterns MT0a, MT0b, MT0c, and MT0d can be implemented as a first lower metal layer LM0 and can occupy a trace of the first lower metal layer LM0.

[0129] The drain D0' of the second transmission transistor TR0' of the first page buffer unit PBU0 and the source S1 of the first transmission transistor TR1 of the second page buffer unit PBU1 can be connected to each other via a second wire or a second metal pattern MT1a. Therefore, the second metal pattern MT1a can be referred to as a node connection line. In some example embodiments, the second metal pattern MT1a can be implemented as a third lower metal layer LM2 and can occupy a trace of the third lower metal layer LM2. However, the inventive concept is not limited to this, and the second metal pattern MT1a can be implemented as a second lower metal layer.

[0130] exist Figure 10A In some example embodiments, when the transmission control signal SO_PASS is activated, the first transmission transistors TR0 to TR7 and the second transmission transistors TR0' to TR7' can be turned on. Therefore, the first transmission transistors TR0 to TR7 and the second transmission transistors TR0' to TR7' included in the respective first page buffer units PBU0 to eighth page buffer units PBU7 can be connected in series with each other, and all of the first sensing nodes SO0 to eighth sensing nodes SO7 can be connected to the combined sensing node SOC. The first sensing node SO0 and the second sensing node SO1 can be connected to each other via the first metal patterns MT0a and MT0b and the second metal pattern MT1a, and the eighth sensing node SO7 and the combined sensing node SOC can be connected to each other via the first metal patterns MT0c and MT0d.

[0131] The first metal patterns MT0a, MT0b, and MT0c corresponding to the first sensing node line, the second sensing node line, and the eighth sensing node line, respectively, the second metal pattern MT1a corresponding to the node connection line, and the first metal pattern MT0d corresponding to the combined sensing node line can constitute data transmission lines. As described above, according to some example embodiments, it is not necessary to separately require eight data transmission lines for connecting the first page buffer unit PBU0 to the eighth page buffer unit PBU7 to the first cache unit CU0 to the eighth cache unit CU7, and the sensing node line included in each of the first page buffer unit PBU0 to the eighth page buffer unit PBU7 can be used as a data transmission line. Therefore, because the number of metal lines required for the wiring of the page buffer circuit 210a can be reduced, the layout complexity can be reduced, and the size of the page buffer circuit 210a can be reduced.

[0132] Each of the first page buffer unit PBU0 to the eighth page buffer unit PBU7 may further include a corresponding precharge transistor among the first precharge transistor PM0 to the eighth precharge transistor PM7. In the first page buffer unit PBU0, the first precharge transistor PM0 may be connected (e.g., directly connected to) between the first sensing node SO0 and a voltage terminal to which a precharge level can be applied, and may include a gate to which a load signal LOAD can be applied. The first precharge transistor PM0 may precharge the first sensing node SO0 to a precharge level in response to the load signal LOAD.

[0133] The main region MR may include contact regions THVa and THVd. Contact region THVa may be located between the first page buffer unit PBU0 and the second page buffer unit PBU1, and contact region THVd may be located between the seventh page buffer unit (e.g., PBU6) and the eighth page buffer unit PBU7. First line contact CT0 and second line contact CT1, respectively connected to the first and second bit lines, may be located in contact region THVa. Eighth line contact CT7 may be located in contact region THVd. That is, first line contact CT0 and second line contact CT1 may be connected to the corresponding first and second bit lines, and both may be located in contact region THVa. First line contact CT0 may be connected to the first page buffer unit PBU0, and second line contact CT1 may be connected to the second page buffer unit PBU1.

[0134] Page buffer circuit 210a may further include a precharge circuit SOC_PRE between the eighth page buffer unit PBU7 and the first cache unit CU0. The precharge circuit SOC_PRE may include a precharge transistor PMA and a shield transistor NMa for precharging the combined sensing node SOC. The precharge transistor PMA may be driven by the combined sensing node load signal SOC_LOAD, and when the precharge transistor PMA is turned on, the combined sensing node SOC can be precharged to the precharge level. The shield transistor NMa may be driven by the combined sensing node shield signal SOC_SHLD, and when the shield transistor NMa is turned on, the combined sensing node SOC can be discharged to ground.

[0135] As the transistor width WD decreases due to process miniaturization, the area occupied by the page buffer circuit 210a can be reduced. In some example embodiments, the transistor width WD may correspond to the size of the gate G0 of the first transfer transistor TR0 in the second horizontal direction HD2. As the transistor width WD decreases, the size of the first page buffer cell PBU0 in the second horizontal direction HD2 can be reduced. However, although the transistor width WD decreases, the spacing of the first lower metal layer LM0 may not decrease. Therefore, the number of wirings (i.e., the number of metal patterns) on the first lower metal layer LM0 of the first page buffer cell PBU0, whose size is reduced in the second horizontal direction HD2, can also be reduced. In some example embodiments, the number of metal patterns on the first lower metal layer LM0 corresponding to the first page buffer cell PBU0 can be reduced from six to four.

[0136] In this way, the sensing reliability of the first page buffer unit PBU0 decreases when the number of metal patterns corresponding to the first page buffer unit PBU0 in the first lower metal layer LM0 decreases. In some example embodiments, during sensing operation, to reduce or prevent coupling between the first sensing node SO0 and adjacent nodes, the metal pattern adjacent to the first sensing node SO0 is used as a shield line, and a fixed bias can be applied to the shield line. However, when the metal pattern corresponding to the shield line is removed due to the reduction of metal patterns, voltage variations at the first sensing node SO0 may occur due to coupling between the first sensing node SO0 and adjacent nodes, thus potentially degrading the sensing reliability of the first page buffer unit PBU0.

[0137] However, according to some example embodiments, such as in Figure 10A In this design, by separately arranging the first page buffer unit PBU0 and the first cache unit CU0, the degree of freedom of the metal patterns in the first lower metal layer LM0 and the third lower metal layer LM2 on the first page buffer unit PBU0 can be increased. Therefore, at least one of the metal patterns in the first lower metal layer LM0 and the third lower metal layer LM2 can be used as a shielding line for the first sensing node SO0. Thus, the increase in voltage fluctuation at the first sensing node SO0 can be reduced or prevented, thereby reducing or preventing a decrease in the sensing reliability of the first page buffer unit PBU0.

[0138] On the other hand, in the structure where the first page buffer unit PBU0 to the eighth page buffer unit PBU7 are separated from the first cache unit CU0 to the eighth cache unit CU7, when the eight signal lines for connecting the first page buffer unit PBU0 to the eighth page buffer unit PBU7 to the first cache unit CU0 to the eighth cache unit CU7 respectively are arranged, the size of the page buffer circuit 210a in the second horizontal direction HD2 can be increased again.

[0139] However, according to some example embodiments, such as in Figure 10A In this embodiment, the first sensing nodes SO0 to the eighth sensing nodes SO7 can be interconnected using the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' included in the first page buffer units PBU0 to the eighth page buffer units PBU7, and the first sensing nodes SO0 to the eighth sensing nodes SO7 can be connected to the first cache units CU0 to the eighth cache units CU7 respectively via the combined sensing node SOC. In some example embodiments, because the sensing node lines for connecting the first and second transfer transistors to each other are implemented using a metal pattern (e.g., MT0a and MT0b) of a trace of the first lower metal layer LM0, the increase in size of the page buffer circuit 210a in the second horizontal direction HD2 can be reduced or prevented.

[0140] Figure 10B This is a circuit diagram illustrating an example of a page buffer circuit according to an exemplary embodiment.

[0141] Reference Figure 10B The page buffer circuit 210b may include a first page buffer unit PBU0' to an eighth page buffer unit PBU7' disposed on the first horizontal direction HD1 and a first cache unit CU0 to an eighth cache unit CU7 disposed on the first horizontal direction HD1.

[0142] When the first page buffer unit PBU0' to the eighth page buffer unit PBU7' are connected to Figure 10AWhen comparing the first page buffer units PBU0' to the eighth page buffer unit PBU7' in the page buffer circuit 210a, each of the first page buffer units PBU0' to the eighth page buffer unit PBU7' includes a corresponding transfer transistor among the first transfer transistors TR01 to the eighth transfer transistors TR71. The first transfer transistors TR01 to the eighth transfer transistors TR71 are commonly connected to the data transmission line DTL, and each of the first transfer transistors TR01 to the eighth transfer transistors TR71 is connected to a corresponding sensing node among the first sensing nodes SO0 to the eighth sensing nodes SO7. The data transmission line DTL extends in the first horizontal direction HD1. The first cache units CU0' to the eighth cache units CU7 are commonly connected to the data transmission line DTL. The data transmission line DTL can be provided by using a metal layer on the first cache units CU0' to the eighth cache units CU7.

[0143] The bits of the transmission control signal SO_PASS[7:0] can be applied to the gates of the first transmission transistor TR01 to the eighth transmission transistor TR71.

[0144] Figure 11 It is a timing diagram of the voltage levels of multiple transmission control signals according to the core operation sequence in an example embodiment.

[0145] Refer to together Figure 10A and Figure 11 The core operation sequence may include a data sensing period 111 for performing data sensing operations and a data dumping period or data transmission period 112 for performing data dumping operations. In the following description, the transmission control signal SO_PASS[7:0] will include the first transmission control signal SO_PASS corresponding to the first page buffer unit PBU0 to the eighth page buffer unit PBU7, respectively. <0> Up to the eighth transmission control signal SO_PASS <7> .

[0146] During the data sensing period 111, the first transmission control signal SO_PASS <0> Up to the eighth transmission control signal SO_PASS <7> All of them can be deactivated, and all of the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' in the first page buffer units PBU0 to the eighth page buffer units PBU7 can be turned off. Therefore, the first page buffer units PBU0 to the eighth page buffer units PBU7 may not be electrically connected to each other, and the first sensing nodes SO0 to the eighth sensing nodes SO7 may be insulated from each other. Alternatively or additionally, the first sensing nodes SO0 to the eighth sensing nodes SO7 may not be electrically connected to the combined sensing node SOC (i.e., the first page buffer units PBU0 to the eighth page buffer units PBU7 may not be electrically connected to the first cache units CU0 to the eighth cache units CU7).

[0147] During data transfer period 112, in order to individually control the connection between the first page buffer units PBU0 to the eighth page buffer units PBU7 and the first cache units CU0 to the eighth cache units CU7, the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' in the first page buffer units PBU0 to the eighth page buffer units PBU7 can be selectively turned on. Therefore, the amount of current consumed during the data dump operation can be reduced. Data transfer period 112 may include the first data transfer period 1121 to the eighth data transfer period 1128.

[0148] During the first data transmission period 1121, the first transmission control signal SO_PASS <0> Up to the eighth transmission control signal SO_PASS <7> All of them can be activated, therefore, all of the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' in the first page buffer unit PBU0 to the eighth page buffer unit PBU7 can be turned on and connected in series. At this time, the first sensing node SO0 can be connected to the combined sensing node SOC via the second sensing node SO1 to the eighth sensing node SO7, and the data dump operation can be performed in the main latch in the first page buffer unit PBU0 (e.g., Figure 6 One of S-LATCH SL, F-LATCH FL, M-LATCH ML, and L-LATCH LL) in the cache latch (e.g., in the first cache unit CU0) and the cache latch (e.g., Figure 6 Execute between C-LATCH CL in the middle.

[0149] During the second data transmission period 1122, the first transmission control signal SO_PASS <0> It can be deactivated, and the second transmission control signal SO_PASS <1> Up to the eighth transmission control signal SO_PASS <7> They can be activated. Therefore, all of the first transfer transistors TR1 to TR7 and the second transfer transistors TR1' to TR7' included in the second page buffer units PBU1 to the eighth page buffer units PBU7 can be turned on and connected in series. In some example embodiments, the second sensing node SO1 can be connected to the combined sensing node SOC via the third sensing node SO2 to the eighth sensing node SO7, and data dumping operations can be performed between the main latch in the second page buffer unit PBU1 and the cache latch in the second cache unit CU1. In some example embodiments, current consumption can be reduced because the first transfer transistor TR0 and the second transfer transistor TR0' included in the first page buffer unit PBU0 are turned off.

[0150] During the eighth data transmission period 1128, the first transmission control signal SO_PASS <0> Up to the seventh transmission control signal SO_PASS <6> It can be deactivated, and only the eighth transmission control signal SO_PASS is used. <7> It can be activated. Therefore, the first transfer transistor TR7 and the second transfer transistor TR7' included in the eighth page buffer unit PBU7 can be turned on and connected in series. In some example embodiments, the eighth sensing node SO7 can be connected to the combined sensing node SOC, and the data dump operation can be performed between the main latch in the eighth page buffer unit PBU7 and the cache latch in the eighth cache unit CU7. In some example embodiments, because the first transfer transistors TR0 to TR6 and the second transfer transistors TR0' to TR6' included in the first page buffer units PBU0 to the seventh page buffer units PBU6 are turned off, current consumption can be reduced.

[0151] Figure 12 This is a timing diagram illustrating an example of a data dump operation of a page buffer circuit according to an example embodiment.

[0152] Refer to together Figure 6 , Figure 10A and Figure 12 Data transfer operations between multiple page buffer units PBU0 to PBU7 and multiple cache units CU0 to CU7 in the page buffer circuit 210a can be performed sequentially.

[0153] During the period from the first time point t0 to the second time point t1, data can be dumped between the first page buffer unit PBU0 and the first cache unit CU0. At the first time point t0, the transfer control signal SO_PASS[7:0] can be switched to a logic high level as an enable level, and all of the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' in the first page buffer unit PBU0 to the eighth page buffer unit PBU7 can be turned on. In some example embodiments, the transfer control signal SO_PASS[7:0] can remain at a logic high level until the data dump operation is completed between the first page buffer unit PBU0 to the eighth page buffer unit PBU7 and the first cache unit CU0 to the eighth cache unit CU7.

[0154] At a first time point t0, the load signal LOAD can transition to a logic low level as an enable level, and all precharge transistors PM0 to PM7 in the first page buffer unit PBU0 to the eighth page buffer unit PBU7 can be turned on, and the first sensing node SO0 to the eighth sensing node SO7 can be precharged to the precharge level. Alternatively or additionally, at the first time point t0, the combined sensing node load signal SOC_LOAD can transition to a logic low level as an enable level, and the precharge transistor PMa in the precharge circuit SOC_PRE can be turned on, and the combined sensing node (SOC) can be precharged to the precharge level. Next, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic high level, and the ground control signal SOGND[7:0] applied to the first page buffer unit PBU0 can transition to a logic high level as an enable level. In some example embodiments, the first sensing node SO0 and S-LATCH SL included in the first page buffer unit PBU0 can be electrically connected to each other, and data can be dumped between the first sensing node SO0 and S-LATCH SL included in the first page buffer unit PBU0.

[0155] During the period from the second time point t1 to the third time point t2, data can be dumped between the second page buffer unit PBU1 and the second cache unit CU1. At the second time point t1, the load signal LOAD and the combined sensor node load signal SOC_LOAD can transition to a logic low level as an enable level, and the first sensor nodes SO0 to the eighth sensor nodes SO7 and the combined sensor node SOC can be precharged to a precharge level. Next, the load signal LOAD and the combined sensor node load signal SOC_LOAD can transition to a logic high level, and the ground control signal SOGND[7:0] applied to the second page buffer unit PBU1 can transition to a logic high level as an enable level. In some example embodiments, the second sensor node SO1 and S-LATCH SL included in the second page buffer unit PBU1 can be electrically connected to each other, and data can be dumped between the S-LATCH SL included in the second page buffer unit PBU1 and the second cache unit CU1. During the period from the third time point t2 to the fourth time point t3, data can be dumped between the third page buffer unit PBU2 and the third cache unit CU2, and during the period from the fourth time point t3 to the fourth time point, data can be dumped between the fourth page buffer unit PBU3 and the fourth cache unit CU3.

[0156] Figure 13 This is a circuit diagram illustrating an example of a cache unit according to an exemplary embodiment.

[0157] Reference Figure 6 and Figure 13 The cache unit CU may include a monitoring transistor NM7 and a C-LATCH CL, and the C-LATCH CL may include a first inverter INV1 and a second inverter INV2, a dump transistor 132, and transistors 131, 133 to 135. The monitoring transistor NM7 may be driven based on the cache monitoring signal MON_C and may control the connection between the sensing node SOC and the C-LATCH CL.

[0158] The first inverter INV1 can be connected between the first node ND1 and the second node ND2 (e.g., directly between the first node ND1 and the second node ND2), and the second inverter INV2 can be connected between the second node ND2 and the first node ND1 (e.g., directly between the second node ND2 and the first node ND1). Therefore, the first inverter INV1 and the second inverter INV2 can form a latch. Transistor 131 may include a gate connected to the combined sensing node SOC. Dump transistor 132 may be driven by the dump signal Dump_C, and dump transistor 132 may transfer data stored in C-LATCH CL to the main latch (S-LATCH SL in the page buffer unit PBU in some example embodiments). Transistor 133 may be driven by the data signal DI, transistor 134 may be driven by the data inversion signal nDI, and transistor 135 may be driven by the write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first node ND1 and the second node ND2 can be determined based on the data signal DI and the data inversion signal nDI, respectively.

[0159] The cache unit CU can be connected to the data I / O line (or data I / O terminal) RDi via transistors 136 and 137. Transistor 136 may include a gate connected to the second node ND2 and can be turned on or off based on the voltage level of the second node ND2. Transistor 137 may be driven by the read control signal DIO_R. When the read control signal DIO_R is activated and transistor 137 is turned on, the voltage level of the input / output terminal RDi can be determined to be "1" or "0" based on the state of C-LATCH CL. In one example, the cache unit CU may include transistor 137.

[0160] Figure 14 This is a timing diagram illustrating an example of a data dump operation of a page buffer circuit 210a according to some exemplary embodiments of the inventive concept. See also... Figure 10A , Figure 13 and Figure 14 During the data dump operation of the page buffer circuit 210a, the transfer control signal SO_PASS[7:0] can be maintained at a logic high level as an enable level, and all of the first transfer transistors TR0 to TR7 and the second transfer transistors TR0' to TR7' can be turned on. Therefore, the first sensing nodes SO0 to the eighth sensing nodes SO7 can be connected to the combined sensing node SOC, and can be connected to the first cache unit CU0 to the eighth cache unit CU7 via the combined sensing node SOC. During the first time period 151 to the fourth time period 154, data can be transferred between the first page buffer unit to the fourth page buffer unit (e.g., ...). Figure 21PBU0 to PBU3) and the first to fourth cache units (e.g., Figure 21 The data is sequentially dumped between CU0 to CU3. In the fifth period 155, the data stored in the first cache unit CU0 to the eighth cache unit CU7 can be output via the data input / output line.

[0161] During the first time period 151, a data dump operation can be performed between the first page buffer unit PBU0 and the first cache unit CU0. The first time period 151 can correspond to the time period from the first time point t0 to the sixth time point t5, and the operation of the page buffer circuit 210a during the first time period 151 will be described below. The operation of the page buffer circuit 210a during the second time period 152 to the fourth time period 154 can correspond to the operation of the page buffer circuit 210a during the first time period 151.

[0162] At the first time point t0, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic low level as an enable level, and all precharge transistors PM0 to PM7 and PMa can be turned on, and the first sensing node SO0 to the eighth sensing node SO7 and the combined sensing node SOC can be precharged at the precharge level. At the second time point t1, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic high level as a disable level. The period from the first time point t0 to the second time point t1 can be referred to as the precharge period.

[0163] At the third time point t2, the first ground control signal SOGND[7:0] applied to the first page buffer unit PBU0 can be changed to a logic high level as an enable level, and at the fifth time point t4, the first ground control signal SOGND[7:0] can be changed to a logic low level. At the fourth time point t3, the first dump signal Dump_C[7:0] and the data signal DI applied to the first cache unit CU0 can be changed to a logic high level as an enable level. In one example, the conduction interval of the second dump transistor of the second cache unit CU1 can overlap with the conduction interval of the first dump transistor of the first cache unit CU0.

[0164] When the data dump operation between the first page buffer unit PBU0 to the eighth page buffer unit PBU7 and the first cache unit CU0 to the eighth cache unit CU7 is completed, in the fifth period 155, the read control signal DIO_R[7:0] can be activated to a logic high level as an enable level. Therefore, the data stored in each of the first cache unit CU0 to the eighth cache unit CU7 can be output via the data input / output lines.

[0165] Figure 14 This is a timing diagram illustrating an example of data dumping and data output operations of a page buffer circuit according to an example embodiment.

[0166] Refer to together Figure 10A , Figure 13 and Figure 14 The data dumping and data output operations of the page buffer circuit 210a may include a first time period 151 to a fifth time period 155. During the first time period 151 to the fourth time period 154, data can be transferred between the first page buffer unit and the fourth page buffer unit (e.g., ...). Figure 21 PBU0 to PBU3) and the first to fourth cache units (e.g., Figure 21 The data is sequentially dumped between CU0 and CU3. In the third period 153, the third page buffer unit (e.g., ...) is... Figure 21 The data dump operation of PBU2 and the first cache latch unit (e.g., in the PBU2) and the first cache latch unit (e.g., Figure 21 The data output operations of CU0 in the fourth time period 154 can be performed simultaneously. In the fourth time period 154, the fourth page buffer unit (e.g., Figure 21 The data dump operation of PBU3 and the second cache latch unit (e.g., in the PBU3) and the second cache latch unit (e.g.) Figure 21 Data output operations of CU1 can be performed simultaneously.

[0167] During the first time period 151, a data dump operation can be performed between the first page buffer unit PBU0 and the first cache unit CU0. The first time period 151 can correspond to the time period from the first time point t0 to the sixth time point t5, and the operation of the page buffer circuit 210a during the first time period 151 will be described below. The operation of the page buffer circuit 210a during the second time period 152 to the fourth time period 154 can correspond to the operation of the page buffer circuit 210a during the first time period 151.

[0168] At the first time point t0, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic low level as an enable level, and all precharge transistors PM0 to PM7 and PMa can be turned on, and the first sensing node SO0 to the eighth sensing node SO7 and the combined sensing node SOC can be precharged at the precharge level. Next, the transmission control signal SO_PASS[7:0] can transition to a logic high level as an enable level, and all of the first transmission transistors TR0 to TR7 and the second transmission transistors TR0' to TR7' can be turned on. At the second time point t1, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic high level as a disable level. The period from the first time point t0 to the second time point t1 can be referred to as the precharge period.

[0169] At the third time point t2, the first ground control signal SOGND[7:0] applied to the first page buffer unit PBU0 can be changed to a logic high level as an enable level, and at the fourth time point t3, the first dump signal Dump_C[7:0] and the data signal DI applied to the first cache unit CU0 can be changed to a logic high level as an enable level. At the fifth time point t4, the transmission control signal SO_PASS[7:0], the first ground control signal SOGND[7:0], the first dump signal Dump_C[7:0], and the data signal DI can all be changed to a logic low level as a disable level.

[0170] When the data dump operation between the first page buffer unit PBU0 to the third page buffer unit PBU2 and the first cache unit CU0 to the third cache unit CU2 is completed, in the third period 153, the read control signal DIO_R[0] can be activated as a logic high level as an enable level. Therefore, the data stored in the first cache unit CU0 can be output via the data I / O line. Alternatively or additionally, in the fourth period 154, the read control signal DIO_R[1] can be activated as a logic high level as an enable level. Therefore, the data stored in the second cache unit CU1 can be output via the data I / O line. Alternatively or additionally, in the fifth period 155, the read control signal DIO_R[7] can be activated as a logic high level as an enable level. Therefore, the data stored in the eighth cache unit CU7 can be output via the data I / O line.

[0171] and Figure 14 The descriptions related to timing diagrams in [the text] can be similarly applied to [the text]. Figure 10B The page buffer circuit 210b in the middle.

[0172] Figure 15AAn example operation of a page buffer circuit according to an example embodiment is shown.

[0173] Refer to together Figure 1 , Figure 5 , Figure 6 and Figure 15A During the data sensing phase 161, page buffer units PBU0 to PBU7 sense the data stored in the memory units via bit line BL and store the sensed data in the corresponding sense latches. During the data transfer phase 162, the sensed data is sequentially dumped from the sense latches of page buffer unit PBU0 and page buffer unit PBU1 to the first cache latch CL0 and the second cache latch CL1. The data sequentially dumped to the first cache latch CL0 and the second cache latch CL1 is sequentially moved to register 270 based on the column address C_ADDR selected in the data output operation. Figure 15A The PRL in the PRL corresponds to register 270 and is provided to the outside of the non-volatile memory device 10 via data I / O circuit 250.

[0174] After the data is sequentially dumped to the first cache latch CL0 and the second cache latch CL1, the state generator 225 in the control circuit 220 changes the state signal RnB from logic low to logic high at the first time point t11. After the state signal RnB changes from logic low to logic high, the data sequentially dumped to the first cache latch CL0 and the second cache latch CL1 is output in parallel via data I / O lines I / O[7:0] at the second time point t12. During the period 163 when the data is output in parallel via data I / O lines I / O[7:0], data is dumped from the third page buffer unit PBU2 to the third cache latch CL2.

[0175] During period 164, when data is dumped to the third cache latch CL2 via data I / O lines I / O[7:0], data is dumped from the fourth page buffer unit PBU3 to the fourth cache latch CL3. During period 165, when data is dumped to the fourth cache latch CL3 via data I / O lines I / O[7:0], data is dumped from the fifth page buffer unit PBU4 to the fifth cache latch CL4. During period 166, data is dumped to the eighth cache latch CL7 via data I / O lines I / O[7:0] before period 167 (i.e., the period following period 166).

[0176] In some example embodiments, when assuming 18KB of data is stored in the first page buffer unit PBU0 to the eighth page buffer unit PBU7, 2.25KB of data is dumped to the first cache latch CL0, and while the 2.25KB of data dumped to the first cache latch CL0 is sequentially output via register 270 through data I / O lines I / O[7:0] based on column address C_ADDR, 2.25KB of data is dumped from the second page buffer unit PBU1 to the second cache latch CL1.

[0177] Figure 15B An example operation of a page buffer circuit according to an example embodiment is shown.

[0178] Refer to together Figure 1 , Figure 5 , Figure 6 and Figure 15B During the data sensing phase 171, page buffer units PBU0 to PBU7 sense the data stored in the memory units via bit line BL and store the sensed data in the corresponding sense latches. During the data transfer phase 172, the sensed data is sequentially dumped from the sense latches of page buffer unit PBU0 and page buffer unit PBU1 to the first cache latch CL0 and the second cache latch CL1. The data sequentially dumped to the first cache latch CL0 and the second cache latch CL1 is sequentially moved to register 270 based on the column address C_ADDR selected in the data output operation. Figure 15B The PRL in the PRL corresponds to register 270 and is provided to the outside of the non-volatile memory device 10 via data I / O circuit 250.

[0179] After the sequential dumping of data to the first cache latch CL0 and the second cache latch CL1 is completed, the state generator 225 in the control circuit 220 transitions the state signal RnB from logic low to logic high at the first time point t11. After transitioning the state signal RnB from logic low to logic high, the data sequentially dumped to the first cache latch CL0 and the second cache latch CL1 is output in parallel via data I / O lines I / O[7:0] at the second time point t12. During each of the time periods 173, 174, and 175 in which data is output in parallel via data I / O lines I / O[7:0], data is sequentially dumped from each of the third page buffer unit PBU2 to the eighth page buffer unit PBU7 to the corresponding cache latch in the third cache latch CL2 to the eighth cache latch CL7.

[0180] In each of time periods 174, 175, and 176, data is sequentially dumped to the third cache latch CL2 through the eighth cache latch CL7 via the data I / O lines I / O[7:0].

[0181] Figure 16 The configuration of the data I / O lines corresponding to a group (mat) according to an example embodiment is shown.

[0182] Reference Figure 16 Group MAT can include even-numbered I / O lines Even corresponding to even-numbered bit lines and odd-numbered I / O lines Odd corresponding to odd-numbered bit lines. Even-numbered I / O lines Even can include column redundancy regions CR1 between subgroups SG11 and SG12 and subgroups SG13 and SG14. Odd-numbered I / O lines Odd can include column redundancy regions CR2 between subgroups SG21 and SG22 and subgroups SG23 and SG24.

[0183] Subgroup SG12 may include eight data I / O lines I / O_0 to I / O_7. Dump to Figure 5 Data from the first cache latch CL0 to the eighth cache latch CL7 is sequentially output via eight data I / O lines I / O_0 to I / O_7. Since the data dumped to the first cache latch CL0 is simultaneously output in parallel via the eight data I / O lines I / O_0 to I / O_7, therefore... Figure 15A The described operation is feasible.

[0184] Figure 17 The mapping between burst length and column address in a page buffer circuit according to an example embodiment is shown.

[0185] exist Figure 17 In this context, it is assumed that the page buffer unit and the cache latch corresponding to the page buffer unit are configured with 8 levels.

[0186] Reference Figure 17As column addresses C_ADDR (e.g., 0x00 to 0x30) increment sequentially, cache latches within a stage can be selected consecutively. Therefore, after dumping data stored in page buffer cells within a stage, 2.25KB of data can be output consecutively. However, when column addresses C_ADDR increment sequentially and stages including selected page buffer cells are changed consecutively, normal data output operations are ensured only after the data dump operation for the selected page buffer cell is complete. According to the example embodiment, when the column address increases by 2.25KB, the correlation between the burst length number BL_NO and the column address C_ADDR ensures that page buffer cells within a stage are selected consecutively, and data output operations can begin after the minimum data dump operation is completed. Therefore, the read interval of the non-volatile memory device 10 can be reduced.

[0187] Figure 18 This is a timing diagram illustrating the operation of a non-volatile memory device according to an example embodiment.

[0188] Reference Figure 1 , Figure 2 , Figure 5 and Figure 18 During the period when the status signal RnB has a logic high level indicating a ready state, the memory controller 40 provides the non-volatile memory device 10 with a read command sequence (first command sequence) 00h-ADDR1-30h including the first address ADDR1. When the non-volatile memory device 10 receives the read command sequence 00h-ADDR1-30h, the control circuit 220 changes the status signal RnB to a logic low level indicating a busy state at time t21. From time t21 to time t22, the page buffer circuit 210 senses data from the selected memory cell and latches the sensed data into the page buffer cell. From time t22 to time t23, each of the page buffer cells PBU0 to PBU4 in the page buffer circuit 210 sequentially dumps the latched data into the corresponding cache latches CL0 to CL4 (first data transfer operation).

[0189] Control circuit 220 changes the status signal RnB to a logic high level at time t23. Data can be output starting from the time point when the status signal RnB changes to a logic high level. When page buffer circuit 210 outputs data dumped to cache latches CL0 to CL4 (first data output operation Dout1), page buffer circuit 210 sequentially dumps the data latched in each of page buffer units PBU5 to PBU7 to the corresponding cache latches CL5 to CL7 starting from time t24 (second data transfer operation).

[0190] During the period when the status signal RnB is at a logic high level, the memory controller 40 provides the non-volatile memory device 10 with a random data output command sequence (second command sequence) 05h-ADDR21-E0h including the second address ADDR21. Since the data is dumped to cache latches CL5 to CL7 at time point t24, at time point t25, after a time interval tWHR2 after the time point from which the random data output command sequence 05h-ADDR21-E0h is received from the non-volatile memory device 10, the page buffer circuit 210 can output the data dumped to cache latches CL5 to CL7 (second data output operation Dout2) through the data I / O circuit 250, regardless of whether the column addresses in the first address ADDR1 and the second address ADDR21 belong to a contiguous address space.

[0191] exist Figure 18 In the table, the time interval from time point t21 to time point t23 corresponds to the reading time interval tR1.

[0192] Figure 19 This is a timing diagram illustrating the operation of a non-volatile memory device according to an example embodiment.

[0193] Reference Figure 1 , Figure 2 , Figure 5 and Figure 19 During the period when the status signal RnB has a logic high level indicating a ready state, the memory controller 40 provides the non-volatile memory device 10 with a read command sequence (first command sequence) 00h-ADDR1-30h including the first address ADDR1. When the non-volatile memory device 10 receives the read command sequence 00h-ADDR1-30h, the control circuit 220 changes the status signal RnB to a logic low level indicating a busy state at time t31. From time t31 to time t32, the page buffer circuit 210 senses data from the selected memory cell and latches the sensed data into the page buffer cell. From time t32 to time t33, the page buffer cell PBU0 in the page buffer circuit 210 dumps the latched data into the cache latch CL0 (first data transfer operation).

[0194] Control circuit 220 transitions the status signal RnB to a logic high level at time t33. Data can be output starting from the time point when the status signal RnB transitions to a logic high level. When page buffer circuit 210 outputs data dumped to cache latch CL0 (first data output operation Dout1), page buffer circuit 210 sequentially dumps the latched data in each of page buffer units PBU1 and PBU2 to the corresponding cache latches in the corresponding cache latches CL1 and CL2 starting from time t34 (second data transfer operation).

[0195] During the period when the status signal RnB is at a logic high level, the memory controller 40 provides the non-volatile memory device 10 with a random data output command sequence (second command sequence) 05h-ADDR22-E0h, including the second address ADDR22. The column address in the second address ADDR22 is contiguous with respect to the column address in the first address ADDR1. That is, the column addresses in the first address ADDR1 and the second address ADDR22 belong to a contiguous address space. Since the column addresses in the first address ADDR1 and the second address ADDR22 are consecutive, at time point t35 after the time interval tWHR2 elapses from the time point when the random data output command sequence 05h-ADDR22-E0h is received from the non-volatile memory device 10, the page buffer circuit 210 outputs the data dumped to the cache latches CL1 and CL2 through the data I / O circuit 250 (second data output operation Dout2), while the page buffer circuit 210 sequentially dumps the data latched in the page buffer units PBU3 and PBU4 to the cache latches CL3 and CL4 (third data transfer operation).

[0196] exist Figure 19 In the diagram, the time interval from time point t31 to time point t33 corresponds to the reading time interval tR2, and the reading time interval tR2 can be less than... Figure 18 The read interval tR1 in the data.

[0197] Figure 20 This is a timing diagram illustrating the operation of a non-volatile memory device according to an example embodiment.

[0198] Reference Figure 1 , Figure 2 , Figure 5 and Figure 20During the period when the status signal RnB has a logic high level indicating a ready state, the memory controller 40 provides the non-volatile memory device 10 with a read command sequence (first command sequence) 00h-ADDR1-30h including the first address ADDR1. When the non-volatile memory device 10 receives the read command sequence 00h-ADDR1-30h, the control circuit 220 changes the status signal RnB to a logic low level indicating a busy state at time t41. From time t41 to time t42, the page buffer circuit 210 senses data from the selected memory cell and latches the sensed data into the page buffer cell. From time t42 to time t43, the page buffer cell PBU0 in the page buffer circuit 210 dumps the latched data into the cache latch CL0 (first data transfer operation). The control circuit 220 changes the status signal RnB to a logic high level at time t43. Data can be output starting from the time point when the status signal RnB changes to a logic high level. When the page buffer circuit 210 outputs data that is dumped to the cache latch CL0, the page buffer circuit 210 sequentially dumps the data latched in each of the page buffer units PBU1 and PBU2 to the corresponding cache latches in the corresponding cache latches CL1 and CL2, starting from time point t44.

[0199] During the period when the status signal RnB is at a logic high level, the memory controller 40 provides the non-volatile memory device 10 with a random data output command sequence (second command sequence) 05h-ADDR23-E0h, including the second address ADDR23. The column address in the second address ADDR23 is non-contiguous relative to the column address in the first address ADDR1. That is, the column addresses in the first address ADDR1 and the second address ADDR23 belong to a non-contiguous address space. Since the column addresses in the first address ADDR1 and the second address ADDR23 are non-contiguous, at time point t45 after the non-volatile memory device 10 receives the random data output command sequence 05h-ADDR23-E0h, the page buffer circuit 210 dumps the data latched in the page buffer unit PBU3 to the cache latch CL3 (third data transfer operation). At time t46, after time intervals INT1 and tWHR2 from time t45, when the page buffer circuit 210 outputs data dumped to cache latches CL1, CL2 and CL3 through the data I / O circuit 250 (second data output operation Dout2), the page buffer circuit 210 sequentially dumps the data latched in page buffer units PBU4 and PBU5 to cache latches CL4 and CL5 (fourth data transfer operation).

[0200] exist Figure 20In the diagram, the time interval from time point t41 to time point t43 corresponds to the reading time interval tR2, and the reading time interval tR2 can be less than... Figure 18 The read interval tR1 in the data.

[0201] exist Figures 18 to 20 The document provides a description of how to determine whether column addresses are contiguous. It assumes a total column address space covering 16KB, divided into four column address spaces, each covering 4KB. When a column address in a read command sequence belongs to the first column address space and a column address in a random data output command sequence corresponds to a column address belonging to the second column address space, the column addresses in the first and second addresses are determined to be contiguous. When a column address in a read command sequence belongs to the first column address space and a column address in a random data output command sequence corresponds to a column address not belonging to the second column address space, the column addresses in the first and second addresses are determined to be non-contiguous.

[0202] exist Figures 18 to 20 In this process, the first data transfer operation can be performed by a subset of page buffer units selected from multiple page buffer units in page buffer circuit 210 based on the first column address included in the first address ADDR1. Page buffer circuit 210 performs both data transfer operations (data dump operations) and data output operations simultaneously, and thus can reduce the read time interval associated with read operations.

[0203] exist Figures 18 to 20 The text describes a non-volatile memory device 10 receiving a random data output command sequence 05h-ADDR21-E0h, 05h-ADDR22-E0h, or 05h-ADDR23-E0h after performing a first data output operation Dout1. However, in some example embodiments, the non-volatile memory device 10 receives the random data output command sequence 05h-ADDR21-E0h, 05h-ADDR22-E0h, or 05h-ADDR23-E0h before performing the first data output operation Dout1. In some example embodiments, the column address indicated by the random data output command sequence 05h-ADDR21-E0h, 05h-ADDR22-E0h, or 05h-ADDR23-E0h is the same as the column address in the read command sequence received prior to the random data output command sequence 05h-ADDR21-E0h, 05h-ADDR22-E0h, or 05h-ADDR23-E0h, and the non-volatile memory device 10 receives a random data output command sequence indicating another column address space.

[0204] Figure 21The arrangement of the first page buffer unit to the eighth page buffer unit and the first cache unit to the eighth cache unit in a page buffer circuit according to an example embodiment is shown.

[0205] Refer to together Figure 3 and Figure 21 The first semiconductor layer L1 may include a first metal layer M1 extending in the first horizontal direction HD1, and multiple bit lines BL may be implemented as the first metal layer M1. The second semiconductor layer L2 may include a first lower metal layer LM0 extending in the first horizontal direction HD1. In some example embodiments, the spacing of the first lower metal layer LM0 may be greater than the spacing of the first metal layer M1. In some example embodiments, the spacing of the first lower metal layer LM0 may be approximately twice the spacing of the first metal layer M1.

[0206] The second semiconductor layer L2 may include a page buffer circuit 210c, and the page buffer circuit 210c may be implemented in the form of a page buffer array including a plurality of columns 211a to 211d on the second horizontal direction HD2. Each of the plurality of columns 211a to 211d may include a first page buffer unit to an eighth page buffer unit and a first cache unit to an eighth cache unit. In some example embodiments, the configuration of each of the plurality of columns 211a to 211d may correspond to Figure 9 and 10A The page buffer circuit 210a is shown in the figure. As the width of the transistor decreases and the size of the first to eighth page buffer units in the second horizontal direction HD2 decreases, the page buffer circuit 210c can arrange more page buffer units in the same row. Therefore, the page buffer circuit 210c can include multiple columns 211a to 211d.

[0207] The first column 211a may include a first main region and a first cache region arranged on the first horizontal direction HD1, wherein the first page buffer unit PBU0 to the eighth page buffer unit PBU7 may be located in the first main region, and the first cache unit CU0 to the eighth cache unit CU7 may be located in the first cache region. The second column 211b may include a second main region and a second cache region arranged on the first horizontal direction HD1, wherein the first page buffer unit PBU0a to the eighth page buffer unit PBU7a may be located in the second main region, and the first cache unit CU0a to the eighth cache unit CU7a may be located in the second cache region. The third column 211c may include a third main region and a third cache region arranged on the first horizontal direction HD1, wherein the first page buffer unit PBU0b to the eighth page buffer unit PBU7b may be located in the third main region, and the first cache unit CU0b to the eighth cache unit CU7b may be located in the third cache region. The fourth column 211d may include a fourth main region and a fourth cache region arranged on the first horizontal direction HD1, the first page buffer unit PBU0c to the eighth page buffer unit PBU7c may be in the fourth main region, and the first cache unit CU0c to the eighth cache unit CU7c may be in the fourth cache region.

[0208] In the first column 211a, the sensing nodes of each of the first page buffer units PBU0 to the eighth page buffer units PBU7 can be jointly connected to the first combined sensing node SOC1, and the first cache units CU0 to the eighth cache units CU7 can be jointly connected to the first combined sensing node SOC1. In the second column 211b, the sensing nodes of each of the first page buffer units PBU0a to the eighth page buffer units PBU7a can be jointly connected to the second combined sensing node SOC2, and the first cache units CU0a to the eighth cache units CU7a can be jointly connected to the second combined sensing node SOC2. In the third column 211c, the sensing nodes of each of the first page buffer units PBU0b to the eighth page buffer units PBU7b can be jointly connected to the third combined sensing node SOC3, and the first cache units CU0b to the eighth cache units CU7b can be jointly connected to the third combined sensing node SOC3. In the fourth column 211d, the sensing nodes of each of the first page buffer unit PBU0c to the eighth page buffer unit PBU7c can be jointly connected to the fourth combined sensing node SOC4, and the first cache unit CU0c to the eighth cache unit CU7c can be jointly connected to the fourth combined sensing node SOC4.

[0209] Figure 22 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0210] Reference Figure 22 The non-volatile memory device 10a may include a memory cell array 100 and peripheral circuitry 200a. The non-volatile memory device 10a may correspond to... Figure 1 A modified example of the non-volatile memory device 10, and referring to Figures 1 to 21 The given description can also be applied to this embodiment.

[0211] and Figure 1 Compared to the non-volatile memory device 10, the peripheral circuitry 200a may also include a page buffer decoder (PBDEC) 213, an MBC 214, and a pass / fail check circuitry 215.

[0212] PBDEC 213 can generate a decoder output signal DS corresponding to the number of failure bits by using the page buffer signal PBS received from page buffer circuit 210. In some example embodiments, when the page buffer signal PBS is logic low, programming to the corresponding memory cell can be determined as a failure, and the data programmed into the corresponding memory cell can be determined as a failure bit. PBDEC 213 can receive a reference current from a current generator (not shown) and generate the decoder output signal DS based on the received reference current.

[0213] MBC 214 can receive the decoder output signal DS from PBDEC 213 and generate a counting result CNT based on the decoder output signal DS. In some example embodiments, MBC 214 may include an analog-to-digital converter that converts the analog-level decoder output signal DS into a counting result CNT as a digital value. MBC 214 may receive a reference current from a current generator (not shown) and generate the counting result CNT based on the received reference current.

[0214] The pass / fail check circuit 215 receives the count result CNT from the MBC 214, generates a pass signal PASS or a failure signal FAIL based on the count result CNT, and provides the generated pass signal PASS or failure signal FAIL to the control circuit 220. In some example embodiments, the pass / fail check circuit 215 generates a pass signal PASS when the count result CNT is less than or equal to a reference quantity. In some example embodiments, the pass / fail check circuit 215 generates a failure signal FAIL when the count result CNT is greater than a reference quantity.

[0215] Figure 23 This is a plan view illustrating the page buffer circuitry and page buffer decoder (PBDEC) according to an example embodiment.

[0216] Refer to together Figure 3 and Figure 23 The first semiconductor layer L1 may include first bit lines BL0 to BL7 extending in the first horizontal direction HD1, and the first bit lines BL0 to BL7 may be implemented as a first metal layer M1. In some example embodiments, the size of the page buffer circuit 210d in the second horizontal direction HD2 may correspond to the arrangement area of ​​the first bit lines BL0 to BL7; therefore, the page buffer circuit 210d may include an eight-level page buffer. The page buffer circuit 210d may correspond to... Figure 9 and Figure 10A A modified example of the page buffer circuit 210a shown in the figure, and referring to Figures 9 to 22 The given description can also be applied to this embodiment.

[0217] Page buffer circuit 210d may include first page buffer units PBU0 to eighth page buffer units PBU7 arranged along a first horizontal direction HD1, and each of the first page buffer units PBU0 to eighth page buffer units PBU7 may include a main unit (e.g., a corresponding one of MU0 to MU7) and a high-voltage unit (e.g., a corresponding one of HVU0 to HVU7). In some example embodiments, the first page buffer unit PBU0 may include a first main unit MU0 and a first high-voltage unit HVU0 arranged along the first horizontal direction HD1.

[0218] Page buffer circuit 210d may further include multiple contact regions THVa to THVd. In some example embodiments, the first contact region THVa may be located between the first page buffer unit PBU0 and the second page buffer unit PBU1, and within the first contact region THVa, a first bit line contact CT0 connected to the first bit line BL0 and a second bit line contact CT1 connected to the second bit line BL1 may be arranged. The first bit line contact CT0 may be connected to a high-voltage transistor (e.g., included in the first high-voltage unit HVU0). Figure 6 TR_hv in the second high voltage unit HVU1), and the second bit line contact CT1 can be connected to the high voltage transistor included in the second high voltage unit HVU1.

[0219] Page buffer circuit 210d may further include cache latch block 212, and cache latch block 212 may include first cache latches to eighth cache latches corresponding to the first page buffer unit PBU0 to the eighth page buffer unit PBU7 respectively (e.g., Figure 5 (CL0 to CLn in the middle). The page buffer circuit 210d may also include a combined sense node precharge circuit SOC_PRE between the eighth page buffer unit PBU7 and the cache latch block 212.

[0220] Optionally or additionally, PBDEC 213 may be adjacent to page buffer circuitry 210d in the first horizontal direction HD1. PBDEC 213 may determine the number of passing and failing cells during a programming verification operation. In some example embodiments, PBDEC 213 may include multiple transistors connected between the cache latch and the global data line. In some example embodiments, when a data dump operation from S-LATCH SL of each of the first page buffer units PBU0 to the eighth page buffer units PBU7 to PBDEC 213 is performed, the transfer control signal SO_PASS[7:0] may be activated, and the first and second transfer transistors may be turned on. Therefore, sense node lines and combined sense node lines may be used as data transfer lines, data dump operations may be performed sequentially between S-LATCH SL of the first page buffer units PBU0 to the eighth page buffer units PBU7 and PBDEC 213, and data dump operations may partially overlap with data output operations. Figure 23 In this context, CT can represent a bit line contact.

[0221] Figure 24 A page buffer circuit and PBDEC according to an example embodiment are shown.

[0222] Reference Figure 24 The page buffer circuit 210e may have a multi-level structure (in some example embodiments, including an 8-level structure from the first level STAGE0 to the eighth level STAGE7), wherein multiple page buffers are arranged along a first horizontal direction HD1. Alternatively or additionally, in the page buffer circuit 210e, multiple columns including a first column 211a and a second column 211b may be arranged along a second horizontal direction HD2.

[0223] PBDEC 213 may include multiple page buffer decoders, each comprising a first PBDEC 213a and a second PBDEC 213b respectively connected to a first column 211a and a second column 211b included in page buffer circuit 210e. The first PBDEC 213a may include an inverter 213a1 and transistors N01, N02, and N03 connected in series, and the second PBDEC 213b may include an inverter 213b1 and transistors N0a1, N0a2, and N0a3 connected in series. Each of the inverters 213a1 and 213b1 may receive a page buffer signal from its corresponding column, and a reference current signal REF_CUR may be applied to the gate of each of transistors N03 and N0a3.

[0224] In some example embodiments, the first PBDEC 213a and the second PBDEC 213b may include a first page buffer signal PBS1 and a second page buffer signal PBS2, respectively, from page buffer units PBU0 and PBU0a included in the first stage STAGE0. In some example embodiments, when a memory cell connected to page buffer unit PBU0 is determined to be a programming failure cell, a logic low level may be stored in the S-LATCH SL of page buffer unit PBU0. In some example embodiments, the first page buffer signal PBS1 may be a logic low level as the voltage level of the first sensing node SO0, and the voltage level of the first combined sensing node SOC1 may also be a logic low level. In some example embodiments, inverter 213a1 may output a logic high level signal, so transistor NO1 can be turned on, and then the first PBDEC 213a can operate as a current sink.

[0225] Transistor N03 can output a first signal (i.e., a reference current) to the wired or terminal WOR_OUT based on the reference current signal REF_CUR. In some example embodiments, the reference current may correspond to the current flowing through transistor N03 when transistor N03 is turned on according to the reference current signal REF_CUR. Similarly, transistor N0a3 can output a second signal (i.e., a reference current) to the wired or terminal WOR_OUT based on the reference current signal REF_CUR. The wired or terminal WOR_OUT can be connected together to the first PBDEC 213a and the second PBDEC 213b, so the first signal output from the first PBDEC 213a and the second signal output from the second PBDEC 213b can be accumulated in the wired or terminal WOR_OUT and generated as the decoder output signal DS. In some example embodiments, the decoder output signal DS may correspond to the current signal IWOR flowing through the wired or terminal WOR_OUT.

[0226] Figure 25 This is a cross-sectional view of a non-volatile memory device according to an example embodiment.

[0227] Reference Figure 25The non-volatile memory device or memory device 2000 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating / manufacturing an upper chip including a memory cell region or cell region CELL on a first wafer, fabricating / manufacturing a lower chip including a peripheral circuit region PERI on a second wafer separate from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of electrically connecting bonding metal formed on the topmost metal layer of the upper chip to bonding metal formed on the topmost metal layer of the lower chip. In some example embodiments, the bonding metal may include copper (Cu) using Cu-to-Cu bonding. However, example embodiments are not limited to this. In some example embodiments, the bonding metal may also be formed of aluminum (Al) and / or tungsten (W).

[0228] Each of the peripheral circuit region PERI and cell region CELL of the memory device 2000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0229] The Peripheral Circuit Region (PERI) may include a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210, first metal layers 2230a, 2230b, and 2230c connected to the plurality of circuit elements 2220a, 2220b, and 2220c, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c, respectively. In some example embodiments, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 2240a, 2240b, and 2240c may be formed of copper, which has a relatively low resistivity.

[0230] exist Figure 25 In some example embodiments shown, although only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, the example embodiments are not limited thereto, and one or more additional metal layers may be formed on the second metal layers 2240a, 2240b, and 2240c. At least a portion of the one or more additional metal layers formed on the second metal layers 2240a, 2240b, and 2240c may be formed of aluminum or the like, having a lower resistivity than the copper used to form the second metal layers 2240a, 2240b, and 2240c.

[0231] Interlayer insulating layer 2215 may be disposed on first substrate 2210 and cover multiple circuit elements 2220a, 2220b and 2220c, first metal layers 2230a, 2230b and 2230c and second metal layers 2240a, 2240b and 2240c. Interlayer insulating layer 2215 may include insulating material (such as silicon oxide, silicon nitride, etc.).

[0232] Lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI can be electrically bonded to the upper bonding metals 2371b and 2372b in the cell region CELL. The lower bonding metals 2271b and 2272b, as well as the upper bonding metals 2371b and 2372b, can be formed of aluminum, copper, and / or tungsten, etc. Furthermore, the upper bonding metals 2371b and 2372b in the cell region CELL can be referred to as the first metal pad, and the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI can be referred to as the second metal pad.

[0233] A cell region (CELL) may include at least one memory block. A cell region cell may include a second substrate 2310 and a common-source line 2320. On the second substrate 2310, multiple word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, and 2338 (e.g., 2330) may be stacked in a third direction VD (e.g., the z-axis direction) perpendicular to the upper surface of the second substrate 2310. At least one string select line and at least one ground select line may be arranged on and below the multiple word lines 2330, respectively, and the multiple word lines 2330 may be disposed between the at least one string select line and the at least one ground select line.

[0234] In the bit line bonding region BLBA, the channel structure CH may extend in a third direction VD (e.g., the z-axis direction) perpendicular to the upper surface of the second substrate 2310, and pass through multiple word lines 2330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. In some example embodiments, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In some example embodiments, the bit line 2360c may extend in a second direction HD2 (e.g., the y-axis direction) parallel to the upper surface of the second substrate 2310.

[0235] exist Figure 25In some example embodiments shown, the region provided with the channel structure CH, bit line 2360c, etc., can be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 2360c can be electrically connected to circuit element 2220c that provides page buffer 2393 in the peripheral circuit region PERI. Bit line 2360c can be connected to upper bonding metals 2371c and 2372c in the cell region CELL, and upper bonding metals 2371c and 2372c can be connected to lower bonding metals 2271c and 2272c, which are connected to circuit element 2220c of page buffer 2393.

[0236] In the word line bonding area WLBA, multiple word lines 2330 may extend in a first direction HD1 (e.g., the x-axis direction) parallel to the upper surface of the second substrate 2310 and perpendicular to the second direction HD2, and the multiple word lines 2330 may be connected to multiple unit contact plugs 2341, 2342, 2343, 2344, 2345, 2346, and 2347 (e.g., 2340). The multiple word lines 2330 and the multiple unit contact plugs 2340 may be connected to each other in a pad provided by at least a portion of the multiple word lines 2330 extending at different lengths in the first direction HD1. A first metal layer 2350b and a second metal layer 2360b may be sequentially connected to the upper portion of the multiple unit contact plugs 2340 connected to the multiple word lines 2330. Multiple cell contact plugs 2340 can be connected to the peripheral circuit area PERI in the word line bonding area WLBA via the upper bonding metals 2371b and 2372b of the cell area CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI.

[0237] Multiple unit contact plugs 2340 may be electrically connected to circuit elements 2220b forming the line decoder 2394 in the peripheral circuitry region PERI. In some example embodiments, the operating voltage of the circuit elements 2220b forming the line decoder 2394 may be different from the operating voltage of the circuit elements 2220c forming the page buffer 2393. In some example embodiments, the operating voltage of the circuit elements 2220c forming the page buffer 2393 may be greater than the operating voltage of the circuit elements 2220b forming the line decoder 2394.

[0238] A common-source electrode contact plug 2380 may be disposed in the external pad bonding region PA. The common-source electrode contact plug 2380 may be formed of a conductive material (such as a metal, metal compound, and / or polysilicon) and may be electrically connected to the common-source electrode 2320. A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on the upper portion of the common-source electrode contact plug 2380. An upper metal pattern 2371a is disposed between the second metal layer 2360a and the upper metal pattern 2372a. In some example embodiments, the region where the common-source electrode contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as the external pad bonding region PA.

[0239] Input / output pads 2205 and 2305 may be disposed in the external pad bonding region PA. A lower insulating film 2201 covering the lower surface of the first substrate 2210 may be formed below the first substrate 2210, and the first input / output pad 2205 may be formed on the lower insulating film 2201. The first input / output pad 2205 may be connected to at least one of a plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit region PERI via a first input / output contact plug 2203, and may be separated from the first substrate 2210 via the lower insulating film 2201. Alternatively or additionally, a side insulating film may be disposed between the first input / output contact plug 2203 and the first substrate 2210 to electrically isolate the first input / output contact plug 2203 from the first substrate 2210.

[0240] An upper insulating film 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and a second input / output pad 2305 may be disposed on the upper insulating layer 2301. The second input / output pad 2305 may be connected to at least one of a plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit region PERI via a second input / output contact plug 2303. In some example embodiments, the second input / output pad 2305 is electrically connected to circuit element 2220a.

[0241] According to an embodiment, the second substrate 2310 and the common source line 2320 may not be disposed in the region where the second input / output contact plug 2303 is disposed. Furthermore, the second input / output pad 2305 may not overlap with the word line 2330 in a third direction VD (e.g., the z-axis direction). The second input / output contact plug 2303 may be separated from the second substrate 2310 in a direction parallel to the upper surface of the second substrate 2310 and may pass through the interlayer insulation layer 2315 of the cell region CELL to connect to the second input / output pad 2305. In one example, the second input / output contact plug 2303 may be connected to the circuit element 2220a via lower metal patterns 2272a and 2271a.

[0242] According to embodiments, the first input / output pad 2205 and the second input / output pad 2305 may be selectively formed. In some example embodiments, the memory device 2000 may include only the first input / output pad 2205 disposed on the first substrate 2210 or the second input / output pad 2305 disposed on the second substrate 2310. Alternatively, the memory device 2000 may include both the first input / output pad 2205 and the second input / output pad 2305.

[0243] In each of the outer pad bonding region PA and bit line bonding region BLBA, which are respectively included in the cell region CELL and the peripheral circuit region PERI, the metal pattern disposed on the uppermost metal layer can be set as a dummy pattern (e.g., an electrically inert pattern), or the uppermost metal layer may not exist.

[0244] In the external pad bonding region PA, the memory device 2000 may include a lower metal pattern 2273a in the uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 2273a corresponds to the upper metal pattern 2372a formed in the uppermost metal layer of the cell region CELL and has the same or similar cross-sectional shape as the upper metal pattern 2372a of the cell region CELL, so that they can be connected to each other. In the peripheral circuit region PERI, the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding region PA, the upper metal pattern 2372a may be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 2273a of the peripheral circuit region PERI.

[0245] Lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 2371b and 2372b of the cell region CELL via Cu-to-Cu bonding.

[0246] Furthermore, in the bit line bonding region BLBA, the upper metal pattern 2392 can be formed in the uppermost metal layer of the cell region CELL. The upper metal pattern 2392 corresponds to the lower metal pattern 2252 formed in the uppermost metal layer of the peripheral circuit region PERI, and has the same or similar cross-sectional shape as the lower metal pattern 2252 of the peripheral circuit region PERI. Contacts may not be formed on the upper metal pattern 2392 formed in the uppermost metal layer of the cell region CELL. In one example, the lower metal pattern 2252 can be electrically connected to the circuit element 2220c via the lower metal pattern 2251.

[0247] In some example embodiments, a reinforcing metal pattern having the same or similar cross-sectional shape as the metal pattern formed in the uppermost metal layer of one region of the cell region (CELL) and the peripheral circuit region (PERI) may be formed in the uppermost metal layer of the other region of the cell region (CELL) and the peripheral circuit region (PERI). Contacts may not be formed on the reinforcing metal pattern.

[0248] Word line voltage can be applied to at least one memory block in the cell region CELL via the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI and the upper bonding metals 2371b and 2372b in the cell region CELL. Optionally or additionally, a page buffer circuit formed (configured) in the peripheral circuit region PERI can perform the above-described data transfer and data output operations simultaneously.

[0249] Figure 26 This is a block diagram illustrating a storage device including a non-volatile memory device according to an example embodiment.

[0250] Reference Figure 26 The storage device 3000 includes a plurality of non-volatile memory devices 3100 and a controller 3200. In some example embodiments, the storage device 3000 can be any storage device (such as an embedded multimedia card (eMMC), universal flash storage (UFS), solid-state drive or solid-state drive (SSD), etc.).

[0251] The controller 3200 can be connected to the non-volatile memory device 3100 via multiple channels CCH1, CCH2, CCH3, ..., CCHk (k is a positive integer). The controller 3200 may include one or more processors 3210, buffer memory 3220, error correction code (ECC) engine 3230, host interface 3250, and non-volatile memory (NVM) interface 3260.

[0252] Buffer memory 3220 can store data used to drive controller 3200. ECC engine 3230 can calculate error correction code values ​​for the data to be programmed during programming operations and can use the error correction code values ​​to correct errors in the read data during read operations. In data recovery operations, ECC engine 3230 can correct errors in the data recovered from non-volatile memory device 3100. Host interface 3250 can provide an interface with external devices. Non-volatile memory interface 3260 can provide an interface with non-volatile memory device 3100.

[0253] Each non-volatile memory device 3100 may correspond to a non-volatile memory device according to an example embodiment and may optionally be supplied with an external high voltage VPP.

[0254] Various package types or package configurations can be used to package a non-volatile memory device or storage device according to the example embodiments.

[0255] The foregoing is illustrative of some exemplary embodiments and should not be construed as limiting them. Although several exemplary embodiments have been described, it will be readily understood by those skilled in the art that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

Claims

1. A non-volatile memory device, comprising: an array of memory cells including a plurality of memory cells; and a page buffer circuit including a plurality of page buffer cells and a plurality of cache latches, the plurality of page buffer cells arranged along a first horizontal direction and connected to each of the plurality of memory cells by a plurality of bit lines, the plurality of cache latches spaced apart from the plurality of page buffer cells along the first horizontal direction, the plurality of cache latches corresponding to respective ones of the plurality of page buffer cells, each of the plurality of page buffer cells including a transfer transistor connected to each sense node and driven in response to a transfer control signal, and the page buffer circuit configured to perform a data transfer operation based on performing a first data output operation, the first data output operation to output data from a first portion of the plurality of cache latches to a data input / output line, the data being data provided from a first portion of the plurality of page buffer cells for use in the first data output operation, the data transfer operation configured to flush sensed data from a second portion of the plurality of page buffer cells to a second portion of the plurality of cache latches, wherein the page buffer circuit is configured to output the data from the first portion of the cache latches concurrently with flushing the sensed data from the second portion of the page buffer cells to the second portion of the cache latches.

2. The nonvolatile memory device of claim 1, wherein, the page buffer circuit configured to perform a first data transfer operation during a busy state indicated by a status signal, the first data transfer operation to flush sensed data from the first portion of the page buffer cells to the first portion of the cache latches, wherein the status signal indicates an operating state of the non-volatile memory device, and wherein the page buffer circuit is configured to perform a second data transfer operation concurrently with the page buffer circuit performing the first data output operation during a ready state indicated by the status signal, the second data transfer operation to flush sensed data from the second portion of the page buffer cells to the second portion of the cache latches.

3. The nonvolatile memory device of claim 2, wherein, the first portion of the page buffer cells to perform the first data transfer operation and the first portion of the page buffer cells selected from among the plurality of page buffer cells based on a first column address included in a first command sequence input to the non-volatile memory device prior to a data sense period.

4. The non-volatile memory device of claim 3, wherein, the second column address included in a second command sequence input to the non-volatile memory device prior to the first data output operation and the first column address and the second column address belonging to a contiguous address space, The page buffer circuit is configured to, during the ready state indicated by the status signal, perform a second data output operation for outputting data transferred by the second data transfer operation after the non-volatile memory device receives the second command sequence while the page buffer circuit performs the third data transfer operation, and wherein the second command sequence corresponds to a random data output command sequence. 5.The non-volatile memory device of claim 3, wherein, based on the second column address being included in a second command sequence input to the non-volatile memory device before the first data output operation and the first column address and the second column address belonging to non-continuous address spaces, the page buffer circuit is configured to, during the ready state indicated by the status signal, perform a second data output operation for outputting data transferred by the second data transfer operation after the non-volatile memory device receives the second command sequence while the page buffer circuit performs the fourth data transfer operation after performing the third data transfer operation. 6.The non-volatile memory device of claim 3, wherein, in the data transfer period, transfer transistors included in each of the plurality of page buffer units are connected in series with each other between the plurality of page buffer units and the plurality of cache latches, such that sense nodes included in each of the plurality of page buffer units are electrically connected to each other, and wherein, in the data transfer period, data transfer operations between the plurality of page buffer units and the plurality of cache latches are sequentially performed.

7. The nonvolatile memory device of claim 6, wherein, The plurality of page buffer units includes: a first page buffer unit including a first transfer transistor connected between a first sense node and a first terminal, a second transfer transistor connected between the first sense node and a second terminal, a first main latch connected to the first sense node, and a first transistor connected between the first sense node and the first main latch; and a second page buffer unit including a third transfer transistor connected between a second sense node and the second terminal, a fourth transfer transistor connected between the second sense node and a third terminal, a second main latch connected to the second sense node, and a second transistor connected between the second sense node and the second main latch. 8.The non-volatile memory device of claim 7, wherein, in the data transfer period, the first transistor and the second transistor are sequentially turned on, and data stored in the first main latch and the second main latch are sequentially transferred to the first cache latch and the second cache latch, respectively.

9. The nonvolatile memory device of claim 7, wherein, The plurality of cache latches includes: a first cache latch including a first dump transistor driven based on a first dump signal and a third transistor driven based on a first read control signal, the first cache latch corresponding to the first page buffer unit; and a second cache latch including a second dump transistor driven based on a second dump signal and a fourth transistor driven based on a second read control signal, the second cache latch corresponding to the second page buffer unit, wherein, in the data transfer period, the first dump transistor and the second dump transistor are sequentially turned on, and data stored in the first main latch and the second main latch is sequentially transferred to the first cache latch and the second cache latch, respectively, and wherein the turn-on interval of the second dump transistor overlaps the turn-on interval of the first dump transistor.

10. The nonvolatile memory device of claim 9, wherein, The page buffer circuit further includes a precharge transistor configured to precharge a combined sense node between the second page buffer unit and the first cache latch, and the precharge transistor is turned on in a precharge period before the first dump transistor or the second dump transistor is turned on, and the precharge transistor precharges the combined sense node to a precharge level.

11. The nonvolatile memory device of claim 7, wherein, based on the first to fourth transfer transistors being turned on, the first to fourth transfer transistors being connected in series with each other, and the first and second sense nodes being electrically connected to each other, data is transferred from the first cache latch among the plurality of cache latches to the first main latch or from the first main latch to the first cache latch.

12. The nonvolatile memory device of claim 7, wherein, based on the third and fourth transfer transistors being turned on, the third and fourth transfer transistors being connected in series such that data is transferred from the second main latch to the second cache latch among the plurality of cache latches.

13. The nonvolatile memory device of any one of claims 1 to 12, wherein, The page buffer circuit further includes a plurality of additional page buffer units arranged along a first horizontal direction, and a plurality of additional cache latches arranged along the first horizontal direction and corresponding to each of the plurality of additional page buffer units, the plurality of page buffer units and the plurality of additional page buffer units are adjacent to each other along a second horizontal direction perpendicular to the first horizontal direction, and the plurality of cache latches and the plurality of additional cache latches are adjacent to each other along the second horizontal direction.

14. The nonvolatile memory device of any one of claim 1 to claim 12, wherein, the memory cell array is on the first semiconductor layer, the page buffer circuit is on the second semiconductor layer, the first semiconductor layer and the second semiconductor layer are stacked vertically, and the plurality of bit lines extend along the first horizontal direction.

15. The nonvolatile memory device of any one of claim 1 to claim 12, further comprising: a memory cell region including the memory cell array and the first metal pad; and a peripheral circuit region including the page buffer circuit and the second metal pad, the peripheral circuit region being connected to the memory cell region through the second metal pad and the first metal pad, and wherein the memory cell region is provided on a first wafer, and the peripheral circuit region is provided on a second wafer.

16. A nonvolatile memory device, the nonvolatile memory device comprising: a first semiconductor layer including a plurality of memory cells connected to each of a plurality of bit lines extending along a first horizontal direction; and a second semiconductor layer arranged in a direction perpendicular to the first semiconductor layer and including a page buffer circuit, wherein the page buffer circuit includes: a main region including a plurality of page buffer units arranged along a first horizontal direction; and a cache region adjacent to the main region in the first horizontal direction, the cache region including a plurality of cache latches arranged along the first horizontal direction and commonly connected to a combined sense node, the plurality of cache latches corresponding to respective ones of the plurality of page buffer units, wherein each of the plurality of page buffer units includes a pass transistor connected to each sense node and driven based on a pass control signal, and wherein the page buffer circuit is configured to perform a data transfer operation concurrently with performing a first data output operation, the first data output operation for outputting data provided from a first portion of the plurality of page buffer units to a first portion of the plurality of cache latches to a data input / output line, the data transfer operation for dumping sensed data from a second portion of the plurality of page buffer units to a second portion of the plurality of cache latches.

17. The nonvolatile memory device of claim 16, wherein, the page buffer circuit is configured to perform a first data transfer operation during which the status signal indicates a busy state, the first data transfer operation for dumping sensed data from the first portion of the page buffer units to the first portion of the cache latches, wherein the status signal indicates an operating state of the non-volatile memory device, and wherein the page buffer circuit is configured to perform a second data transfer operation concurrently with performing a first data output operation during which the status signal indicates a ready state, the second data transfer operation for dumping sensed data from the second portion of the page buffer units to the second portion of the cache latches.

18. The nonvolatile memory device of claim 16 or claim 17, wherein, the second semiconductor layer further includes a page buffer decoder adjacent to the plurality of cache latches along the first horizontal direction, in a signal transfer period, the pass transistors included in each of the plurality of page buffer units are connected in series with each other between the plurality of page buffer units and the page buffer decoder such that the sense nodes included in each of the plurality of page buffer units are connected to the page buffer decoder.

19. A page buffer circuit, the page buffer circuit comprising: a plurality of page buffer units; and a plurality of cache latches commonly connected to the plurality of page buffer units via a combined sense node, the plurality of cache latches corresponding to respective ones of the plurality of page buffer units, wherein each of the plurality of page buffer units includes a pair of pass transistors and a sense node for connecting the pair of pass transistors to each other, and in a data transfer period, the sense nodes included in each of the plurality of page buffer units are connected to the combined sense node between the plurality of page buffer units and the plurality of cache latches, and the plurality of page buffer units are electrically connected to the plurality of cache latches, and wherein the page buffer circuit is configured to perform a data transfer operation to dump sensed data from a second portion of the plurality of page buffer units to a second portion of the plurality of cache latches concurrently with the page buffer units performing the first data output operation to output data provided from a first portion of the plurality of page buffer units from a first portion of the plurality of cache latches to the data input / output line.

20. The page buffer circuit of claim 19, wherein, the page buffer circuit is configured to perform a first data transfer operation to dump sensed data from the first portion of the plurality of page buffer units to the first portion of the plurality of cache latches during the busy state indicated by the status signal, wherein the status signal indicates an operating state of the non-volatile memory device, and wherein the page buffer circuit is configured to perform a second data transfer operation to dump sensed data from the second portion of the plurality of page buffer units to the second portion of the plurality of cache latches concurrently with the page buffer circuit performing the first data output operation to output data provided from the first portion of the plurality of page buffer units from the first portion of the plurality of cache latches to the data input / output line during the ready state indicated by the status signal.

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