Methods and systems for verifying memory devices

Abstract

This invention relates to a method for verifying a memory device. The method includes verifying a second memory device based on one or more first microcode instructions stored in a predetermined portion of the verification of a first memory device to detect the operating state of the second memory device. Furthermore, the method includes receiving one or more second microcode instructions after verifying the second memory device. Finally, the first memory device is verified based on the one or more second microcode instructions stored in the second memory device to detect the operating state of the first memory device.

Description

Technical Field

[0001] This disclosure relates to the testing of semiconductor-based memory devices. Specifically, but not exclusively, this disclosure relates to a method for verifying memory devices. Background Technology

[0002] Volatile memory devices are memory devices that store data while powered on. Semiconductor memory devices such as static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM) are examples of volatile memory.

[0003] Before storing data, semiconductor-based volatile memory devices are periodically tested or verified. This testing can be performed using external or internal test procedures. However, in some cases, semiconductor memory devices contain embedded memory components that are hardwired onto the chip and cannot be tested externally. Such embedded memories can only be tested using internal procedures. Therefore, a robust built-in self-test procedure is needed in the art to test embedded memory components.

[0004] The information disclosed in the background section of this disclosure is intended only to enhance the understanding of the general background of this disclosure and should not be construed as an admission or any form of advice that such information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] This document discloses a method for verifying a memory device, which includes verifying a second memory device based on one or more first microcode instructions stored in a predetermined portion of the verification of a first memory device to detect the operating state of the second memory device. Furthermore, the method includes receiving one or more second microcode instructions after verifying the second memory device. Finally, the first memory device is verified based on one or more second microcode instructions stored in the second memory device to detect the operating state of the first memory device.

[0006] Embodiments of this disclosure provide a test system for verifying a memory device, the test system including a processor and a memory communicatively coupled to the processor. The memory stores processor instructions, which, when executed, cause the processor to perform the following operations: verify a second memory device based on one or more first microcode instructions stored in a predetermined portion of the verified first memory device to detect the operational state of the second memory device. Furthermore, the instructions cause the processor to perform the following operations: after verifying the second memory device, receive one or more second microcode instructions. Finally, the instructions cause the processor to perform the following operations: verify the first memory device based on one or more second microcode instructions stored in the second memory device to detect the operational state of the first memory device.

[0007] Embodiments of this disclosure provide a method for verifying the memory of an electronic device, the electronic device including a first memory device and a second memory device. The method may include verifying a predetermined portion of the first memory device using one or more predetermined microcode instructions; storing one or more first microcode instructions in a predetermined portion of the first memory device, at least in part, based on verifying the predetermined portion of the first memory device; verifying a second memory device using one or more first microcode instructions; storing one or more second microcode instructions in a second memory device, at least in part, based on verifying the second memory device; and verifying the first memory device using one or more second microcode instructions.

[0008] The foregoing description of the invention is merely illustrative and not intended to be limiting in any way. Other aspects, embodiments, and features, in addition to the illustrative aspects, embodiments, and features described above, will become clear from reference to the accompanying drawings and the following detailed description. Attached Figure Description

[0009] The novel features and characteristics of this disclosure are set forth in the appended claims. However, the disclosure itself, its preferred modes of use, further objects and advantages, can be best understood by referring to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the principles disclosed. In the drawings, the leftmost numeral of the reference numerals first appears in the drawing. One or more embodiments will now be described by way of example only with reference to the drawings, wherein similar reference numerals denote similar elements, and in the drawings:

[0010] Figure 1 An exemplary environment for verifying a memory device according to some embodiments of this disclosure is shown;

[0011] Figure 2A flowchart illustrating method steps for verifying a memory device according to some embodiments of the present disclosure is shown;

[0012] Figure 3A An exemplary diagram is shown illustrating a portion of a first memory device according to some embodiments of the present disclosure;

[0013] Figure 3B An exemplary diagram of an MBIST for verifying hardwired connections of a portion of a first memory device, according to some embodiments of the present disclosure, is shown.

[0014] Figure 3C Exemplary diagrams illustrating the verification of a second memory device according to some embodiments of the present disclosure are shown; and

[0015] Figure 3D An exemplary diagram illustrating the verification of a first memory device according to some embodiments of the present disclosure is shown.

[0016] Those skilled in the art will recognize that any block diagram herein represents a conceptual diagram of an illustrative system that specifically implements the principles of this subject matter. Similarly, it will be appreciated that any flowchart, flow diagram, state transition diagram, pseudocode, etc., represents various processes that can be substantially represented in a computer-readable medium and executed by a computer or processor, regardless of whether such a computer or processor is explicitly shown. Detailed Implementation

[0017] Embodiments of this disclosure provide a method for verifying a memory device. The memory device is periodically tested or verified before data is stored in it. Testing of the memory device can be performed using an external tester, such as an automated test equipment (ATE). Testing can also be performed internally within the memory device.

[0018] Complex system-on-chip (SoC) architectures (e.g., ASIC chips) can have large amounts of memory. Embedded memory can include static random access memory (SRAM), dynamic random access memory (DRAM), cache, register files, and flash memory. The embedded memory of an SoC chip can reside inside the chip. Therefore, it may not be possible to access the embedded memory from outside the device for testing. As a result, the embedded memory array on the SoC can be tested using a Memory Built-in Self-Test (MBIST) system.

[0019] An MBIST system may include an SRAM component for generating test patterns based on microcode stored in SRAM. Embodiments of this disclosure can be used to test or verify SRAM associated with an MBIST system deployed in a SoC. An exemplary method includes verifying a second memory device to detect the operational state of the second memory device based on one or more first microcode instructions stored in a predetermined portion of the verified first memory device. Additionally, the method may include receiving one or more second microcode instructions after verifying the second memory device. Finally, the first memory device may be verified to detect the operational state of the first memory device based on one or more second microcode instructions stored in the second memory device.

[0020] In this document, the term "exemplary" means "used as an example, instance, or illustration." Any embodiment or implementation of the subject matter described herein as "exemplary" should not be construed as preferred or advantageous over other embodiments.

[0021] While various modifications and alternative forms of this disclosure may be made, specific embodiments thereof have been shown by way of example in the accompanying drawings and will be described in detail below. However, it should be understood that the drawings are not intended to limit this disclosure to the specific forms disclosed, but rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of this disclosure.

[0022] The terms “comprising,” “including,” “containing,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a setup, apparatus, or method that includes a list of components or steps may include not only those components or steps but also other components or steps not expressly listed or inherent to such setup, apparatus, or method. In other words, without further limitations, one or more elements in a system or apparatus that begin with “comprising…” or “including…” do not exclude the presence of other elements or additional elements in the system or apparatus.

[0023] In the following detailed description of embodiments of this disclosure, reference is made to the accompanying drawings, which form a part of the present invention, in which specific embodiments in which this disclosure may be practiced are illustrated by way of example. These embodiments have been described in sufficient detail to enable those skilled in the art to practice this disclosure, and it should be understood that other embodiments may be utilized and changes may be made without departing from the scope of this disclosure. Therefore, the following description should not be considered limiting.

[0024] Figure 1 An exemplary environment for verifying a memory device is shown according to some embodiments of this disclosure.

[0025] This disclosure discloses a method for verifying or testing a memory device (101). The memory device (101) may be semiconductor-based. In an exemplary embodiment, one or more memory devices are embedded in a system-on-a-chip (SoC). An SoC is an integrated circuit that integrates one or more components of a computer system or other electronic system. The one or more components include a central processing unit (CPU), memory, input / output ports, and auxiliary storage devices. Furthermore, the SoC may include at least one of digital-analog mixed-signal processing capabilities and radio frequency signal processing capabilities. The memory device (101) in the SoC detects manufacturing defects and performs robust testing on large blocks of memory after manufacturing. The one or more memory devices in the SoC are verified using a memory-embedded self-test system. The one or more memory devices in the SoC are verified during at least one of the following: when the SoC boots up before a user application begins or an offline self-test is run, an online (i.e., runtime) self-test triggered by a user application, and a shutdown self-test performed at the end of the user application.

[0026] In an exemplary embodiment, such as Figure 1 As shown, the memory device (101) includes a first memory device (103). The first memory device (103) may include at least one of the following: static random access memory (SRAM), dynamic random access memory (DRAM), one or more SRAM chips, one or more DRAM chips, etc. The first memory device (103) is verified using a test system (102). Figure 1 As shown, the test system (102) may include at least one of hardwired memory, a built-in self-test (MBIST) (105), and a configurable MBIST (106). The hardwired MBIST (105) is a hardware implementation of a memory testing technique. The configurable MBIST (106) is implemented using at least one of a microcode-based MBIST and a processor-based MBIST. The microcode-based MBIST is used to verify a memory device (101) using a controller or processor and memory for storing a set of predefined instructions or for generating microcode for a selected test technique. The processor-based MBIST is used to verify one or more memory devices in a SoC. The processor-based MBIST executes assembly language to generate test patterns for verifying one or more memory devices. The microcode-based MBIST and the processor-based MBIST include a second memory device (104) (e.g., SRAM, etc.) for storing assembly language or microcode associated with a selected test technique for verifying a first memory device (103).

[0027] In an exemplary embodiment, the memory device (101) may be a high-bandwidth memory (HBM), but this disclosure is not limited thereto. Figure 1 As shown, one or more DRAM chips stacked in three dimensions can be represented as a high-bandwidth memory. Furthermore, the HBM may include a memory controller (not shown in the figure) and a test system (102).

[0028] In an exemplary embodiment, a test system (102) is used to verify a predetermined portion (107) of a first memory device (103) using a hard-wired MBIST (105). For example, the predetermined portion (107) may include one of the following: a DRAM chip of the first memory device (103), a portion of at least one DRAM chip (e.g., 50% of the memory cells), a number of memory cells for storing one or more first microcode instructions, etc. Verifying the predetermined portion (107) includes detecting one of the following: correct operation of the predetermined portion (107) of the first memory device (103), or one or more errors in the predetermined portion (107) of the first memory device (103). After successfully verifying the predetermined portion (107) of the first memory device (103), the test system (102) may use an IEEE 1500 bus interface to receive one or more first microcode instructions. Furthermore, the test system (102) stores one or more first microcode instructions in the predetermined portion (107) of the first memory device (103).

[0029] Furthermore, in an exemplary embodiment, the test system (102) verifies the second memory device (104) based on one or more first microcode instructions stored in a predetermined portion (107) of the verified memory device (103). The second memory device (104) can be verified by the test system (102) using one or more first microcode instructions via a configurable MBIST (106). Verifying the second memory device (104) includes detecting the operating state of the second memory device (104). Detecting the operating state includes detecting one of the following: the second memory device (104) is operating correctly, or one or more errors exist in the second memory device (104). After successfully verifying the second memory device (104), the test system (102) can receive one or more second microcode instructions using an IEEE 1500 bus interface. The test system (102) stores one or more second microcode instructions in the second memory device (104). In another embodiment, the test system (102) can obtain one or more first microcode instructions from the first memory device (103). Alternatively or additionally, the test system (102) then stores one or more first microcode instructions in a second memory device (104). The one or more first microcode instructions indicate one or more second microcode instructions.

[0030] Furthermore, in an exemplary embodiment, the test system (102) verifies the first memory device (103) based on one or more second microcode instructions stored in the second memory device (104). A configurable MBIST (106) of the test system (102) can be used to verify the first memory device (103) using one or more second microcode instructions. Verifying the first memory device (103) includes detecting the operational state of the first memory device (103). Detecting the operational state may include detecting one of the following: correct operation of the first memory device (103), or one or more errors in the first memory device (103).

[0031] In an exemplary embodiment, one or more errors may include at least one of the following: fixed fault, transition fault, coupling fault, inverse coupling fault, idempotent coupling fault, state coupling fault, neighborhood pattern sensitive fault, address decoder fault, etc.

[0032] In an exemplary embodiment, one or more first microcode instructions and one or more second microcode instructions may be associated with one or more testing techniques. The one or more testing techniques may include at least one of the following: chessboard technique, sliding diagonal technique, butterfly technique, movement-based testing technique, etc.

[0033] In an exemplary embodiment, a binary string of 1s and 0s is used to indicate one or more first microcode instructions and one or more second microcode instructions. For example, “0111010”, “10010011”, etc.

[0034] Figure 2 A flowchart illustrating method steps for verifying a memory device (101) according to some embodiments of the present disclosure is shown.

[0035] The order in which method 200 can be described is not intended to be construed as limiting, and any number of the described method blocks can be combined in any order to implement the method. Additionally or alternatively, individual blocks can be removed from the method without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

[0036] In operation 201, the test system (102) detects the operating status of the second memory device (104) by verifying the second memory device (104) based on one or more first microcode instructions in a verified predetermined portion (107) stored in the first memory device (103).

[0037] In an exemplary embodiment, such as Figure 3AAs shown, the test system (102) uses a hard-wired MBIST (105) to verify a predetermined portion (107) of the first memory device (103). As... Figure 3B As shown, the hard-wired MBIST (105) executes one or more predefined microcode instructions to detect one of the following: correct operation of a predetermined portion (107) of the first memory device (103), or one or more errors in the predetermined portion (107) of the first memory device (103). The predetermined portion (107) comprises a portion of the first memory device (103). The size of the predetermined portion (107) may be equal to the size of one or more first microcode instructions to be stored in the first memory device (103). The first memory device (103) includes one or more SRAM chips, one or more DRAM chips, high-bandwidth memory, combinations thereof, etc.

[0038] In an exemplary embodiment, the hard-wired MBIST (105) is a hardware implementation of the selected memory testing technique. For example... Figure 3B As shown, memory testing techniques can be stored in the form of a finite state machine (FSM) (301), which can be hardwired. The FSM is used to generate one or more predefined microcode instructions using a controller (302) and a pattern generator (303). Those skilled in the art will recognize different implementations of the hardwired MBIST (105).

[0039] In some examples, one or more predefined microcode instructions may be provided to a predetermined portion (107) of the first memory device (103). The first memory device (103) performs read or write operations based on one or more predefined microcode instructions. For example, one or more predefined microcode instructions may instruct the first memory device (103) to write a logic 0 to a memory cell in the predetermined portion (107) and to read a data value stored in that memory cell. Figure 3B As shown, the comparator (304) receives the result of executing one or more predefined microcode instructions in the predetermined part (107).

[0040] The comparator (304) compares one or more predefined microcode instructions with the result of execution received from a predetermined portion (107) of the first memory device (103). The result of the comparison indicates that the predetermined portion (107) of the first memory device (103) is functioning correctly or that one or more errors are detected in the predetermined portion (107). For example, if the data value read from the predetermined portion (107) indicates logic 0 and one or more predefined microcode instructions indicate the data value as logic 1, then the comparator (304) detects one or more errors. Alternatively, if the data value read from the predetermined portion (107) indicates logic 0 and one or more predefined microcode instructions indicate the data value as logic 0, then the comparator (304) detects that the memory cell in the predetermined portion of the first memory device (103) is functioning correctly.

[0041] In an exemplary embodiment, after verifying a predetermined portion (107) of the first memory device (103), the test system (102) uses a bus interface (108) to receive one or more first microcode instructions. According to one example, the bus interface (108) may be an IEEE 1500 bus interface. Figure 3C As shown, one or more first microcode instructions are stored in a predetermined portion (107) of the first memory device (103). Furthermore, the test system (102) uses a configurable MBIST (106) to verify the second memory device (104). The configurable MBIST (106) retrieves one or more first microcode instructions from the first memory device (103). Additionally, as... Figure 3C As shown, the configurable MBIST (106) provides one or more microcode instructions to the second memory device (104).

[0042] The second memory device (104) executes one or more first microcode instructions and provides the result of the execution to a configurable MBIST (106). The one or more first microcode instructions may include reading a binary logic value of 0 or 1 from one or more memory cells in the first memory device (103) or writing a binary logic value of 0 or 1 to one or more memory cells in the first memory device (103). The configurable MBIST (106) detects the operating state of the second memory device (104) based on the result of the execution. The operating state includes one of the following: the second memory device (104) is operating correctly, or one or more errors occur in the second memory device (104). When the result of the execution matches one or more first microcode instructions, the operating state is detected as operating correctly. When the result of the execution does not match one or more first microcode instructions, the operating state is detected as one or more errors occur in the second memory device (104).

[0043] Refer again Figure 2 In operation 202, after verifying the second memory device (104), the configurable MBIST (106) of the test system (102) receives one or more second microcode instructions.

[0044] In an exemplary embodiment, the configurable MBIST (106) receives one or more second microcode instructions by retrieving one or more first microcode instructions from a first memory device (103). The one or more first microcode instructions indicate one or more second microcode instructions. Furthermore, the one or more second microcode instructions are stored in a second memory device (104). In another exemplary embodiment, the configurable MBIST (106) uses a bus interface (108) to receive one or more second microcode instructions. Furthermore, as... Figure 3D As shown, one or more second microcode instructions are stored in a second memory device (104).

[0045] Return to reference Figure 2 In operation 203, the test system (102) verifies the first memory device (103) based on one or more second microcode instructions stored in the second memory device (104) to detect the operating status of the first memory device (103).

[0046] In an exemplary embodiment, the configurable MBIST (106) of the test system (102) verifies the first memory device (103) by retrieving one or more second microcode instructions from the second memory device (104). Furthermore, as... Figure 3D As shown, the configurable MBIST (106) provides one or more second microcode instructions to the first memory device (103). The first memory device (103) executes the one or more second microcode instructions and provides the result of the execution to the configurable MBIST (106). The configurable MBIST (106) detects an operating state including one of the following: correct operation of the first memory device (103) or one or more errors in the first memory device (103). When the result of the execution matches one or more second microcode instructions, the operating state can be detected as correct operation. When the result of the execution does not match one or more second microcode instructions, the operating state can be detected as one or more errors in the first memory device (103).

[0047] The method for verifying memory device (101) includes testing and verifying a first memory device (103) using a configurable MBIST (106). The configurable MBIST (106) can be used to test and verify a second memory device (104) associated with the configurable MBIST (106). The method for verifying memory device (101) eliminates the need for additional hardware for testing the second memory device (104). One or more testing techniques are used to test and verify the first memory device (103) and the second memory device (104) by generating random patterns based on one or more first microcode instructions and one or more second microcode instructions. Furthermore, the configurable MBIST (106) can be used to generate complex patterns to detect one or more errors in memory device (101).

[0048] Therefore, embodiments of this disclosure provide a method for verifying the memory (e.g., memory device (101)) of an electronic device, the memory (e.g., memory device (101)) including a first memory device (103) and a second memory device (104). The method may include verifying a predetermined portion (107) of the first memory device (103) using one or more predetermined microcode instructions; storing one or more first microcode instructions in the predetermined portion (107) of the first memory device (103) at least in part based on verifying the predetermined portion (107) of the first memory device (103); verifying the second memory device (104) using one or more first microcode instructions; storing one or more second microcode instructions in the second memory device (104) at least in part based on verifying the second memory device (104); and verifying the first memory device (103) using one or more second microcode instructions.

[0049] Unless otherwise expressly stated, the terms “an embodiment,” “an exemplary embodiment,” “an embodiment,” “multiple embodiments,” “the embodiment,” “the multiple embodiments,” “one or more embodiments,” “some embodiments,” and “an embodiment” mean “one or more (but not all) embodiments of this disclosure.”

[0050] Unless otherwise expressly stated, the terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to.”

[0051] Unless otherwise expressly stated, an enumeration of items does not imply that any or all items are mutually exclusive. Unless otherwise expressly stated, the terms “a,” “an,” and “the” mean “one or more.”

[0052] The description of exemplary embodiments in which multiple components communicate with each other does not imply the use or requirement of all such components. Rather, a variety of optional components are described to illustrate a variety of possible embodiments of this disclosure.

[0053] When a single device or item is described herein, it will be apparent that more than one device and / or item (whether or not it collaborates) may be used in place of the single device and / or item. Similarly, in cases where more than one device or item is described herein (whether or not it collaborates), it will be apparent that a single device / item may be used in place of the more than one device or item, or that a different number of devices / items may be used in place of the number of devices or items shown. The functionality and / or features of a device may alternatively be implemented by one or more other devices not explicitly described as having such functionality / features. Therefore, other embodiments of this disclosure do not necessarily need to include the device itself.

[0054] Figure 2 The operations illustrated demonstrate specific events occurring in a particular order. In alternative embodiments, specific operations may be performed, modified, or removed in a different order. Furthermore, steps may be added to the above logic while still conforming to the described embodiments. Additionally, the operations described herein may occur sequentially or may be processed in parallel. Furthermore, operations may be performed by a single processing unit or by distributed processing units.

[0055] Finally, the language used in this specification has been chosen primarily for readability and instruction purposes, and is not intended to define or limit the subject matter of the invention. Therefore, it is intended that the scope of this disclosure be limited not by this specific embodiment, but by any of the claims issued based on this application. Accordingly, the disclosure of embodiments of this disclosure is intended to illustrate, and not limit, the scope of the disclosure as set forth in the appended claims.

[0056] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for illustrative purposes and are not intended to be limiting; the true scope is indicated by the appended claims.

[0057] Figure label:

[0058] Appendix Number describe 101 memory devices 102 Test System 103 First memory device 104 Second memory device 105 hard-wired MBIST 106 Configurable MBIST 107 Reservation portion 301 Hardwired finite state machines 302 controller 303 Pattern Generator 304 Comparator.

Claims

1. A method for verifying a memory device, the method comprising: The test system verifies the second memory device based on one or more first microcode instructions stored in a predetermined portion of the first memory device for verification, in order to detect the operating status of the second memory device; After verifying the second memory device, the test system receives one or more second microcode instructions; as well as The test system verifies the first memory device based on one or more second microcode instructions stored in the second memory device to detect the operating status of the first memory device.

2. The method of claim 1, wherein, The verified predetermined portion of the first memory device is verified through a process including the following operations: Execute one or more predefined microcode instructions to detect one of the following: The correct operation of the verified predetermined portion of the first memory device; or One or more errors in the verified predetermined portion of the first memory device.

3. The method of claim 1, wherein, Verifying the second memory device includes: Obtain the one or more first microcode instructions from the first memory device; and Execute one or more first microcode instructions to detect the operating state of the second memory device, the operating state of the second memory device including one of the following: The second memory device is functioning correctly; or One or more errors in the second memory device.

4. The method of claim 1, wherein, Verifying the first memory device includes: Obtain the one or more second microcode instructions from the second memory device; and Execute the one or more second microcode instructions to detect the operating state of the first memory device, the operating state of the first memory device including one of the following: The first memory device is functioning correctly; or One or more errors in the first memory device.

5. The method of claim 2, wherein, The one or more errors include unit failures.

6. The method of claim 1, wherein, The first memory device includes one or more dynamic random access memory (DRAM) chips.

7. The method of claim 1, wherein, The second memory device is static random access memory (SRAM).

8. The method of claim 1, wherein, Receiving the one or more second microcode instructions includes one of the following: The one or more first microcode instructions are retrieved from the first memory device, wherein the one or more first microcode instructions indicate the one or more second microcode instructions stored in the second memory device; or The IEEE 1500 bus interface is used to receive the one or more second microcode instructions, wherein the one or more second microcode instructions are stored in the second memory device.

9. A test system for verifying a memory device, the test system comprising: processor; as well as A memory communicatively coupled to the processor, wherein the memory stores processor instructions that, when executed, cause the processor to perform the following operations: The second memory device is verified based on one or more first microcode instructions stored in a predetermined portion of the first memory device for verification, so as to detect the operating state of the second memory device. After verifying the second memory device, receive one or more second microcode instructions; and The first memory device is verified based on one or more second microcode instructions stored in the second memory device to detect the operating status of the first memory device.

10. The test system of claim 9, wherein, The verified predetermined portion of the first memory device is verified using a process that includes the following operations: Execute one or more predefined microcode instructions to detect one of the following: The correct operation of the verified predetermined portion of the first memory device; or One or more errors in the verified predetermined portion of the first memory device.

11. The testing system according to claim 9, wherein, The processor is configured to verify the second memory device using a process that includes the following operations: Obtain the one or more first microcode instructions from the first memory device; as well as Execute one or more first microcode instructions to detect the operating state of the second memory device, the operating state of the second memory device including one of the following: The second memory device is functioning correctly; or One or more errors in the second memory device.

12. The testing system according to claim 9, wherein, The processor is configured to verify the first memory device using a process that includes the following operations: Obtain the one or more second microcode instructions from the second memory device; as well as Execute the one or more second microcode instructions to detect the operating state of the first memory device, the operating state of the first memory device including one of the following: The first memory device is functioning correctly; or One or more errors in the first memory device.

13. The testing system according to claim 10, wherein, The processor is configured to detect one or more errors, including any unit failure.

14. The testing system according to claim 9, wherein, Receiving the one or more second microcode instructions includes one of the following: The one or more first microcode instructions are retrieved from the first memory device, wherein the one or more first microcode instructions indicate the one or more second microcode instructions stored in the second memory device; or The IEEE 1500 bus interface is used to receive the one or more second microcode instructions, wherein the one or more second microcode instructions are stored in the second memory device.

15. A method for verifying the memory of an electronic device including a first memory device and a second memory device, the method comprising: Use one or more predetermined microcode instructions to verify a predetermined portion of the first memory device; One or more first microcode instructions are stored in the predetermined portion of the first memory device, at least in part based on verification of the predetermined portion of the first memory device; The second memory device is verified using one or more first microcode instructions; At least in part based on verifying the second memory device, one or more second microcode instructions are stored in the second memory device; as well as The first memory device is verified using one or more second microcode instructions.

16. The method according to claim 15, wherein, Verifying the predetermined portion of the first memory device includes: Use a controller and a pattern generator to generate the one or more predefined microcode instructions; To perform read or write operations based on one or more predefined microcode instructions; Compare the one or more predetermined microcode instructions with the result of the execution; and The operating state of the predetermined portion of the first memory device is determined based on whether the execution result matches one or more predetermined microcode instructions.

17. The method according to claim 15, wherein, The size of the predetermined portion is equal to the size of the one or more predetermined microcode instructions.

18. The method according to claim 15, wherein, Verifying the second memory device includes: Obtain the one or more first microcode instructions from the predetermined portion of the first memory device; and Execute one or more first microcode instructions to detect the operating state of the second memory device.

19. The method according to claim 15, wherein, Verifying the first memory device includes: Obtain the one or more second microcode instructions from the second memory device; and Execute one or more second microcode instructions to detect the operating state of the first memory device.

20. The method of claim 15, further comprising: Receive one or more second microcode instructions from the bus interface.

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