Semiconductor structure and method of manufacturing the same

Abstract

The present application provides a semiconductor structure and a manufacturing method thereof. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned mask layer has an opening, which includes a main body portion and two extension portions at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer and a third sacrificial layer on the insulating layer. The first sacrificial layer is filled in the extension portions of the opening, and defines a notch in the main body portion of the opening. The second sacrificial layer is formed in the notch defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer in the extension portions. The manufacturing method of the semiconductor structure provided by the embodiments of the present application can improve the yield and reliability of the semiconductor structure without significantly increasing the complexity of the process and the production cost.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a method for manufacturing the semiconductor structure using a self-aligned double patterning process. Background Art

[0002] With the increasing demand for miniaturization, increasing the density of semiconductor devices has become an important issue. In the process of semiconductor devices, spacer patterning and self-aligned double patterning (SADP) processes can be used to increase the density of semiconductor devices and reduce the critical dimensions of semiconductor devices.

[0003] The existing SADP process generally includes the following steps: using a first mask to form a first pattern consisting of a mandrel; conformally forming a spacer material to cover the mandrel; removing the spacer material and the mandrel on top of the mandrel to leave a second pattern consisting of the spacer material; etching the film layer below using the second pattern as a mask; and performing an end cut step using the second mask to cut the multiple ring-shaped second patterns into multiple parallel lines.

[0004] However, the existing SADP process requires at least two masks, resulting in higher production costs. Furthermore, if the alignment between the second mask and the second pattern deviates, one end of the annular second pattern may not be removed. This prevents the formation of the desired number of parallel lines, reducing product yield and reliability. Furthermore, ensuring perfect alignment between the second mask and the second pattern generally increases process complexity.

[0005] Therefore, in the art, there is still a need for semiconductor devices with high yield and high reliability and methods for manufacturing the same. Summary of the Invention

[0006] An embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can improve the yield and reliability of the semiconductor structure without significantly increasing the complexity of the process and the production cost.

[0007] One embodiment of the present application discloses a method for manufacturing a semiconductor structure. The method includes forming an insulating layer on a substrate, and forming a patterned mask layer on the insulating layer. The patterned mask layer has an opening, and the opening includes a main portion and two extension portions respectively located at two ends of the main portion. Each of the extension portions has a first width, and the main portion has a second width greater than the first width. The method also includes conformally forming a first sacrificial layer on the insulating layer and the patterned mask layer, forming a second sacrificial layer on the first sacrificial layer, and forming a third sacrificial layer on the first sacrificial layer located in the extension portions. The first sacrificial layer fills in the extension portions of the opening, and the first sacrificial layer defines a recess in the main portion of the opening. The first sacrificial layer and the second sacrificial layer are formed of different materials, and the second sacrificial layer and the third sacrificial layer are formed of different materials.

[0008] Another embodiment of the present application discloses a semiconductor structure. The semiconductor structure includes a substrate, an insulating layer formed on the substrate, and a plurality of pairs of line structures formed in the insulating layer in parallel. Each pair of line structures includes a first line structure and a second line structure. An end portion of the first line structure and an end portion of the second line structure have a first spacing, and a central portion of the first line structure and a central portion of the second line structure have a second spacing greater than the first spacing.

[0009] In the method for manufacturing a semiconductor structure provided by the embodiments of the present application, by changing the shape of the opening and controlling the loading effect during etching the sacrificial layer, a plurality of parallel trenches can be formed. Since it can be ensured that adjacent trenches do not connect to each other, the yield and reliability can be greatly improved. Furthermore, in the method for manufacturing a semiconductor structure provided by the embodiments of the present application, only one mask is needed. Therefore, the production cost and the complexity of the process can be greatly reduced. In addition, such a manufacturing method can be easily integrated into the existing process without the need for additional replacement or modification of production equipment. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B are cross-sectional schematic views of semiconductor structures at various stages of the process according to some embodiments of the present application.

[0011] Figure 1C 、 Figure 2C 、 Figure 3C 、 Figure 4C 、 Figure 5C 、 Figure 6C 、 Figure 7C 、 Figure 8C 、 Figure 9C and Figure 10C Schematic top views of semiconductor structures at various stages of the process according to some embodiments of the present invention.

[0012] Figure 11 Schematic top views of semiconductor structures according to other embodiments of the present invention.

[0013]

Explanation of symbols

[0014] 100: semiconductor structure;

[0015] 100': transfer structure;

[0016] 102:Substrate;

[0017] 104: insulating layer;

[0018] 112: patterned mask layer;

[0019] 114: first sacrificial layer;

[0020] 115: Open your mouth;

[0021] 115a: main body;

[0022] 115b: extension;

[0023] 116: second sacrificial layer;

[0024] 118: third sacrificial layer;

[0025] 125: groove;

[0026] 125a: first groove;

[0027] 125b: second groove;

[0028] 130: linear structure;

[0029] D1: first distance;

[0030] D2: second distance;

[0031] S1: first spacing;

[0032] S2: second spacing;

[0033] S3: third spacing;

[0034] S4: fourth spacing;

[0035] W1: first width;

[0036] W2: second width;

[0037] W3: third width. DETAILED DESCRIPTION

[0038] In order to make the above and other objects, features and advantages of the present application more comprehensible, preferred embodiments will be described below with reference to the accompanying drawings, in which:

[0039] Herein, the terms "about" and "approximately" shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. A quantity described as being "about" a certain value means implicitly that the exact value can or can not be included in the range.

[0040] The present application provides a method for fabricating a semiconductor structure, Figure 1C Figure 2C Figure 3C Figure 4C Figure 5C Figure 6C Figure 7C Figure 8C Figure 9C and Figure 10C Top view schematic diagrams of a semiconductor structure 100 according to some embodiments of the present application at various stages of the process. Figure 1A Figure 2A Figure 3A Figure 4A Figure 5A Figure 6A Figure 7A Figure 8A Figure 9A Figure 10A are drawn along the section line I-I' in Figure 1C Figure 2C Figure 3C Figure 4C Figure 5C Figure 6C Figure 7C Figure 8C Figure 9C and Figure 10C Figure 1B Figure 2B Figure 3B Figure 4B Figure 5B ,​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B and Figure 10B Along the Figure 1C 、 Figure 2C 、 Figure 3C 、 Figure 4C 、 Figure 5C 、 Figure 6C 、 Figure 7C 、 Figure 8C 、 Figure 9C and Figure 10C The section line II-II' is drawn in FIG.

[0041] Please also refer to Figure 1A 、 Figure 1B and Figure 1C , forming an insulating layer 104 on the substrate 102, and forming a patterned mask layer 112 on the insulating layer 104. The patterned mask layer 112 has a plurality of openings 115. Each opening 115 includes a main body 115a and two extensions 115b located at both ends of the main body 115a. Figure 1C In the embodiment, the main body 115a is approximately rectangular or hexagonal in shape, and the two extensions 115b extend outward along the long axis of the main body 115a. The extensions 115b are approximately rectangular in shape, with their long axes aligned with the long axis of the main body 115a. Along the short axis of the main body 115a, the width of the main body 115a is greater than the width of the extensions 115b.

[0042] The material of substrate 102 may include silicon, gallium arsenide, gallium nitride, silicon germanium, silicon-on-insulator (SOI), other suitable materials, or combinations thereof. In the present embodiment, substrate 102 is a silicon substrate. In some embodiments, other structures may also be formed in substrate 102, such as isolation structures, p-type implanted regions, or n-type implanted regions (not shown). The material of insulating layer 104 may include polysilicon, oxides, nitrides, oxynitrides, carbon-based materials (e.g., diamond-like carbon films), other suitable insulating materials, or combinations thereof. In the present embodiment, insulating layer 104 is silicon nitride.

[0043] The patterned mask layer 112 can be formed using conventional methods. For example, a mask layer is formed on the insulating layer 104, and then a patterning process is performed using a mask (not shown) to form the patterned mask layer 112. The material of the patterned mask layer 112 may include polysilicon, oxide, nitride, oxynitride, carbon-based materials (e.g., diamond-like carbon film), photoresist, other suitable mask materials, or combinations thereof. In the present embodiment, the patterned mask layer 112 is polysilicon. In one embodiment, the insulating layer 104 and the patterned mask layer 112 are formed of different materials.

[0044] Please also refer to Figure 2A 、 Figure 2B and Figure 2C A first sacrificial layer 114 is conformally formed on the insulating layer 104 and the patterned mask layer 112, filling the opening 115. Because the width of the main portion 115a is greater than the width of the extension 115b, the first sacrificial layer 114 has already filled the extension 115b of the opening 115 before the first sacrificial layer 114 fills the main portion 115a of the opening 115. Next, a second sacrificial layer 116 is formed on the first sacrificial layer 114, filling the recess defined by the first sacrificial layer 114 in the main portion 115a.

[0045] The material of the first sacrificial layer 114 may include polysilicon, oxide, nitride, oxynitride, or a combination thereof. In the present embodiment, the first sacrificial layer 114 is silicon oxide. The material of the second sacrificial layer 116 may include polysilicon, oxide, nitride, oxynitride, carbon-based materials (e.g., diamond-like carbon film), photoresist, or a combination thereof. In the present embodiment, the material of the second sacrificial layer 116 is polysilicon. The first sacrificial layer 114 and the second sacrificial layer 116 may be independently formed by a suitable deposition process, such as a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof.

[0046] Please also refer to Figure 3A 、 Figure 3B and Figure 3C A first etch-back process is performed on the second sacrificial layer 116 to remove the second sacrificial layer 116 located in the extension portion 115 b while retaining a portion of the second sacrificial layer 116 located in the main portion 115 a. After the first etch-back process, a portion of the first sacrificial layer 114 located in the main portion 115 a is covered by the second sacrificial layer 116, while the first sacrificial layer 114 located in the extension portion 115 b is not covered by the second sacrificial layer 116.

[0047] The first etch-back process may include a dry etch process, a wet etch process, or a combination thereof. In this embodiment, the first etch-back process is a dry etch process. Furthermore, in order to selectively remove the second sacrificial layer 116 while retaining the first sacrificial layer 114, the etch selectivity of the first etch-back process can be improved. The first sacrificial layer 114 and the second sacrificial layer 116 are formed of different materials. In some embodiments, in the first etch-back process, the ratio (R2a / R1a) of the etch rate R2a of the second sacrificial layer 116 relative to the etch rate R1a of the first sacrificial layer 114 is 5-20.

[0048] Please also refer to Figure 4A 、 Figure 4B and Figure 4CAfter the first etching process, a second etching process is performed on the first sacrificial layer 114 to remove a portion of the first sacrificial layer 114. The second etching process can include a non-isotropic etching process. In the present embodiment, the second etching process is a dry etching process. Furthermore, in order to selectively remove the first sacrificial layer 114 and retain the patterned mask layer 112 and the second sacrificial layer 116, the etching selectivity of the second etching process can be increased. The first sacrificial layer 114 and the patterned mask layer 112 are formed of different materials. In some embodiments, in the second etching process, the ratio R2b / R1b of the etching rate R2b of the first sacrificial layer 114 relative to the etching rate R1b of the patterned mask layer 112 is 5-20, and the ratio R2b / R3b of the etching rate R2b of the first sacrificial layer 114 relative to the etching rate R3b of the second sacrificial layer 116 is 5-20.

[0049] After the second etching process, in the extension portion 115b, the top surface of the first sacrificial layer 114 and the top surface of the patterned mask layer 112 have a first distance D1, and in the main body portion 115a, the top surface of the first sacrificial layer 114 and the top surface of the patterned mask layer 112 have a second distance D2. Due to the effect of the loading effect, the first distance D1 is greater than the second distance D2, which will be described in detail below.

[0050] Please refer to Figure 5A , Figure 5B and Figure 5C After the second etching process, a third sacrificial layer 118 is formed on the patterned mask layer 112, the first sacrificial layer 114 and the second sacrificial layer 116. The material of the third sacrificial layer 118 can include polysilicon, oxide, nitride, oxynitride, carbon-based material (e.g., diamond-like carbon film), photoresist or a combination thereof. In the present embodiment, the material of the third sacrificial layer 118 is silicon nitride. The third sacrificial layer 118 can be formed by a suitable deposition process, such as a chemical vapor deposition process, an atomic layer deposition process or a combination thereof.

[0051] Please refer to Figure 6A , Figure 6B and Figure 6C A third etching process is performed on the third sacrificial layer 118 to remove a portion of the third sacrificial layer 118 located in the main body portion 115a and retain the third sacrificial layer 118 located in the extension portion 115b. After the third etching process, the second sacrificial layer 116 located in the main body portion 115a is exposed.

[0052] The third etch-back process may include an isotropic etching process. In this embodiment, the third etch-back process is a wet etching process. Furthermore, in order to selectively remove the third sacrificial layer 118 while retaining the first sacrificial layer 114 and the second sacrificial layer 116, the etching selectivity of the third etch-back process can be improved. The first sacrificial layer 114 and the third sacrificial layer 118 are formed of different materials, and the second sacrificial layer 116 and the third sacrificial layer 118 are formed of different materials. In some embodiments, in the third etch-back process, the ratio R3c / R1c of the etching rate R3c of the third sacrificial layer 118 to the etching rate R1c of the first sacrificial layer 114 is 5-20.

[0053] Since the first distance D1 is greater than the second distance D2, the thickness of the third sacrificial layer 118 located in the extension portion 115b is greater than the thickness of the third sacrificial layer 118 located in the main portion 115a. After the third etch-back process, the first sacrificial layer 114 located in the extension portion 115b is covered by the third sacrificial layer 118, and a portion of the first sacrificial layer 114 located in the main portion 115a is not covered by the third sacrificial layer 118. Figure 6A and Figure 6B For more details, please refer to Figure 6C Since the thickness of the third sacrificial layer 118 gradually decreases from the extension portion 115b to the main portion 115a, the third sacrificial layer 118 also extends from the extension portion 115b to the main portion 115a. After the third back etching process, the third sacrificial layer 118 is formed as follows Figure 6C The pattern shown.

[0054] Please also refer to Figure 7A 、 Figure 7B and Figure 7C , a first etching process is performed using the third sacrificial layer 118 and the second sacrificial layer 116 as masks to remove the portion of the first sacrificial layer 114 located in the main body portion 115a and not covered by the second sacrificial layer 116. That is, the patterns of the third sacrificial layer 118 and the second sacrificial layer 116 are transferred to the first sacrificial layer 114. After the first etching process, a portion of the insulating layer 104 located in the main body portion 115a is exposed, as shown in FIG. Figure 7C drawn.

[0055] The first etching process may include an anisotropic etching process. In the present embodiment, the first etching process is a dry etching process. Furthermore, in order to selectively remove the first sacrificial layer 114 while retaining the patterned mask layer 112, the second sacrificial layer 116, and the third sacrificial layer 118, the etching selectivity of the first etching process can be improved. In some embodiments, in the first etching process, the ratio R2d / R1d of the etching rate R2d of the first sacrificial layer 114 to the etching rate R1d of the patterned mask layer 112 is 5-20, the ratio R2d / R3d of the etching rate R2d of the first sacrificial layer 114 to the etching rate R3d of the second sacrificial layer 116 is 5-20, and the ratio R2d / R4d of the etching rate R2d of the first sacrificial layer 114 to the etching rate R4d of the third sacrificial layer 118 is 5-20.

[0056] Please also refer to Figure 8A 、 Figure 8B and Figure 8C , a second etching process is performed using the first sacrificial layer 114 as a mask to remove the third sacrificial layer 118 located in the extension portion 115b, and to remove the portion of the insulating layer 104 located in the main portion 115a and not covered by the second sacrificial layer 116. After the second etching process, a portion of the substrate 102 located in the main portion 115a is exposed, and the first sacrificial layer 114 located in the extension portion 115b is exposed. In other words, after the second etching process, the first trench 125a and the second trench 125b are formed on both sides of the insulating layer 104 located in the main portion 115a, as shown in FIG. Figure 8C drawn.

[0057] The second etching process may include an anisotropic etching process. In the present embodiment, the second etching process is a dry etching process. Furthermore, in order to selectively remove the insulating layer 104 and the third sacrificial layer 118 while retaining the patterned mask layer 112, the first sacrificial layer 114, and the second sacrificial layer 116, the etching selectivity of the second etching process can be improved. The material of the insulating layer 104 is different from the material of the second sacrificial layer 116 and the patterned mask layer 112, and the material of the third sacrificial layer 118 is different from the material of the second sacrificial layer 116 and the patterned mask layer 112. For example, in the second etching process, the etching rate of the insulating layer 104 may be the same as or similar to the etching rate of the third sacrificial layer 118, and the etching rate of the insulating layer 104 is greater than the etching rate of any one of the patterned mask layer 112, the first sacrificial layer 114, and the second sacrificial layer 116.

[0058] Please also refer to Figure 9A 、 Figure 9B and Figure 9CA third etching process is performed to selectively remove the second sacrificial layer 116 and the patterned mask layer 112. The third etching process can include a dry etching process, a wet etching process, or a combination thereof. In the present embodiment, the third etching process is a dry etching process. Furthermore, in order to maintain the shapes of the first trench 125a and the second trench 125b, the etching rate of the second sacrificial layer 116 can be the same as or similar to the etching rate of the patterned mask layer 112, and the etching rates of the second sacrificial layer 116 and the patterned mask layer 112 are much greater than the etching rate of the insulating layer 104 during the third etching process.

[0059] Referring to Figure 10A , Figure 10B and Figure 10C , a fourth etching process is performed to selectively remove the first sacrificial layer 114. The fourth etching process can include a dry etching process, a wet etching process, or a combination thereof. In the present embodiment, the fourth etching process is a dry etching process. Furthermore, in order to maintain the shapes of the first trench 125a and the second trench 125b, the etching rate of the first sacrificial layer 114 is much greater than the etching rate of the insulating layer 104 during the fourth etching process.

[0060] Next, a filling material is filled into the first trench 125a and the second trench 125b, and a planarization process (e.g., a chemical mechanical polishing process) is performed as needed to form a line structure 130. In some embodiments, the filling material is a conductive material (e.g., a metal, an alloy, or a combination thereof), and the line structure 130 is a conductive line. In other embodiments, the filling material is an insulating material (e.g., an oxide, a nitride, or an oxynitride), and the line structure 130 is an isolation structure. Thereafter, other existing processes can be performed to complete the semiconductor structure 100.

[0061] In the method of manufacturing the semiconductor structure 100 provided in the present embodiment, by forming an opening with a specific shape and controlling the loading effect during etching of the sacrificial layer, the self-aligned double patterning process can be simplified.

[0062] More specifically, referring to Figure 1C , the opening 115 includes a main portion 115a and an extension portion 115b. The extension portion 115b has a first width W1, and the main portion 115a has a second width W2, which is greater than the first width W1. Thus, as shown in Figure 3C , when the first sacrificial layer 114 fills the extension portion 115b, the main portion 115a is not yet completely filled, leaving a small recess (i.e., the range filled by the second sacrificial layer 116) in the main portion 115a. That is, the first sacrificial layer 114 is formed around the main portion 115a and surrounds the recess.

[0063] Referring toFigure 4A and Figure 4B Afterwards, the first sacrificial layer 114 in the extension portion 115b has a first width W1, and the first sacrificial layer 114 in the main portion 115a has a third width W3, with the first width W1 being greater than the third width W3. During the second etch-back process, due to the loading effect, the etch rate of the first sacrificial layer 114 in the extension portion 115b is greater than the etch rate of the first sacrificial layer 114 in the main portion 115a. Therefore, the etch depth of the first sacrificial layer 114 in the extension portion 115b (i.e., the first distance D1) is greater than the etch depth of the first sacrificial layer 114 in the main portion 115a (i.e., the second distance D2).

[0064] In addition, since the third sacrificial layer 118 may form Figure 6C The illustrated pattern, therefore, can form a plurality of substantially parallel and linear trenches 125 (ie, the first trenches 125 a and the second trenches 125 b ) in the first sacrificial layer 114 even without performing an end cutting step.

[0065] In order to ensure that the first sacrificial layer 114 forms a recess in the main body portion 115a for filling the second sacrificial layer 116 (eg Figure 2B As shown, the trench 125 has an appropriate width to facilitate subsequent filling of the filling material and device miniaturization. The ratio W2 / W1 of the second width W2 to the first width W1 can be adjusted to a specific range. In some embodiments, the ratio W2 / W1 of the second width W2 to the first width W1 is 1.5-4.0.

[0066] A larger ratio (W1 / W3) of the first width W1 to the third width W3 can increase the loading effect. Specifically, the difference in etching rate between the first sacrificial layer 114 located in the extension portion 115b and the first sacrificial layer 114 located in the main portion 115a can be increased. The ratio (W1 / W3) of the first width W1 to the third width W3 can be adjusted to a specific range. In some embodiments, the ratio (W1 / W3) of the first width W1 to the third width W3 is 1.2-2.0.

[0067] In order to avoid removing all of the third sacrificial layer 118 in the third etch-back process and to ensure that the thickness of the first sacrificial layer 114 is sufficient to protect the insulating layer 104 located at the extension portion 115b in the second etch process, thereby ensuring that the first trench 125a and the second trench 125b are separated from each other, the ratio D1 / D2 of the first distance D1 to the second distance D2 can be adjusted to a specific range. Figure 4A and Figure 4BIn some embodiments, the ratio D1 / D2 of the first distance D1 to the second distance D2 is 1.1-4.0. In other embodiments, the ratio D1 / D2 of the first distance D1 to the second distance D2 is 2.0-3.0. In this way, the first trench 125a and the second trench 125b are not in communication with each other, and an additional end cut step can be eliminated.

[0068] Referring to Figure 6A , Figure 6B and Figure 6C In some embodiments, a transfer structure 100' for fabricating a semiconductor structure 100 is provided. The transfer structure 100' includes an insulating layer 104 formed on a substrate 102, a patterned mask layer 112, a first sacrificial layer 114, a second sacrificial layer 116, and a third sacrificial layer 118. The patterned mask layer 112 has an opening 115. The opening 115 includes a main portion 115a and two extension portions 115b located at two ends of the main portion 115a, respectively. The first sacrificial layer 114 is formed on the insulating layer 104. The first sacrificial layer 114 forms a recess in the main portion 115a. The maximum height of the first sacrificial layer 114 in the main portion 115a is greater than the maximum height of the first sacrificial layer 114 in the extension portions 115b. The second sacrificial layer 116 is formed in the recess defined by the first sacrificial layer 114. The third sacrificial layer 118 is formed on the first sacrificial layer 114 in the extension portions 115b, and a portion of the first sacrificial layer 114 in the main portion 115a is not covered by the third sacrificial layer 118. The first sacrificial layer 114 and the second sacrificial layer 116 are formed of different materials. The second sacrificial layer 116 and the third sacrificial layer 118 are formed of different materials. Other details of the transfer structure 100' of the present embodiment or the fabrication method thereof have been described in the previous embodiments, and thus will not be repeated here.

[0069] Through the transfer structure 100' of the present embodiment, the pattern of the second sacrificial layer 116 can be transferred to the insulating layer 104 in subsequent first and second etching processes to form the first and second trenches 125a and 125b as shown in Figure 8C . In this way, the plurality of trenches 125 arranged in parallel with each other can be formed without an additional end cut step. Therefore, the production cost and the process complexity can be greatly reduced.

[0070] Referring to Figure 10C In some embodiments, a semiconductor structure 100 is provided. In one embodiment, the semiconductor structure 100 is a bit line or other conductive line of a dynamic random access memory. In one embodiment, the semiconductor structure 100 is an isolation structure of a dynamic random access memory. However, the present application is not limited thereto. The semiconductor structure 100 includes a plurality of trenches 125 (labeled in Figure 9CThe groove 125 has a third width W3 (marked at Figure 4B The third width W3 is defined by the distance between the patterned mask layer 112 and the second sacrificial layer 116 in the transfer structure 100 ′. The semiconductor structure 100 includes a linear structure 130 formed in the trench 125 .

[0071] The linear structures 130 are substantially arranged in parallel. Two linear structures 130 located in the same opening 115 constitute a pair of linear structures 130. Figure 9C and Figure 10C As shown, in one opening 115, the positions of the linear structures 130 correspond to the positions of the first groove 125a and the second groove 125b. Therefore, the two linear structures 130 corresponding to the first groove 125a and the second groove 125b can be respectively referred to as the first linear structure and the second linear structure. In one linear structure 130, the two ends extend in the same direction. On the same side (for example, Figure 10C In the embodiment of the present invention, the ends of two adjacent linear structures 130 extend in opposite directions. Within a pair of linear structures 130, the ends of the linear structures 130 have a first spacing S1, while the center of the linear structures 130 has a second spacing S2 that is greater than the first spacing S1. Within a different pair of linear structures 130, the ends of the linear structures 130 have a third spacing S3, while the center of the linear structures 130 has a fourth spacing S4 that is less than the third spacing S3. Because the thickness of the third sacrificial layer 118 gradually decreases from the extension portion 115b to the main body 115a, both ends of the same linear structure 130 have a gradually narrowing width.

[0072] If the linear structure 130 is a conductive circuit, in order to avoid short circuits between the linear structures 130, the ratio S1 / S2 of the first spacing S1 to the second spacing S2 can be adjusted to a specific range of 0.40-0.98. Figure 10C In some embodiments, a ratio S1 / S2 of the first spacing S1 to the second spacing S2 is 0.40-0.98.

[0073] The first spacing S1 can be adjusted by controlling the loading effect of the second and third etch-back processes. More specifically, in some embodiments, during the second etch-back process, a ratio R1 / R2 of an etch rate R1 of the first sacrificial layer 114 located in the extension portion 115b relative to an etch rate R2 of the first sacrificial layer 114 located in the main portion 115a is in the range of 1.5-5.0.

[0074] In addition to adjusting the ratio W1 / W3 of the first width W1 to the third width W3, the difference between the etch rate R1 of the first sacrificial layer 114 located in the extension portion 115b and the etch rate R2 of the first sacrificial layer 114 located in the main portion 115a can also be adjusted by controlling the etching parameters of the second etch-back process (e.g., etching gas, etching time, etc.). During the second etch-back process, if the difference between the etch rate R1 of the first sacrificial layer 114 located in the extension portion 115b and the etch rate R2 of the first sacrificial layer 114 located in the main portion 115a increases, the first spacing S1 will decrease.

[0075] On the other hand, in some embodiments, during the third etch-back process, a ratio (R3 / R4) of the etch rate R3 of the third sacrificial layer 118 in the main portion 115a relative to the etch rate R4 of the third sacrificial layer 118 in the extension portion 115b is in the range of 1.5-2.0. In addition to adjusting the ratio (W1 / W3) of the first width W1 to the third width W3, the difference between the etch rate R3 of the third sacrificial layer 118 in the main portion 115a and the etch rate R4 of the third sacrificial layer 118 in the extension portion 115b can also be adjusted by controlling etching parameters of the third etch-back process (e.g., etching solution composition, etching solution concentration, etching solution temperature, etching time, etc.). During the third etch-back process, if the difference between the etch rate R3 of the third sacrificial layer 118 in the main portion 115a and the etch rate R4 of the third sacrificial layer 118 in the extension portion 115b increases, the first distance S1 increases.

[0076] When the linear structures 130 are conductive lines, if the first spacing S1 is sufficiently large (for example, the ratio S1 / S2 of the first spacing S1 to the second spacing S2 is greater than 0.70), short circuits between the linear structures 130 can be avoided. This can further improve product yield and reliability.

[0077] Figure 11 Schematic top views of semiconductor structures according to other embodiments of the present invention. Figure 11 The linear structure 130 is shown Figure 10C The illustrated linear structures 130 are similar, differing in the shape of the ends of the linear structures 130. In this embodiment, both ends of the linear structures 130 are smoothly curved, thereby preventing interference or short circuits between the endpoints of the linear structures 130. The shape of the ends of the linear structures 130 can be adjusted by controlling the etching parameters of the second etching process (e.g., etching gas, etching time, etc.) or the etching parameters of the third etching process (e.g., etching solution composition, etching solution concentration, etching solution temperature, etching time, etc.).

[0078] In summary, in the manufacturing method of the semiconductor structure provided in the embodiment of the present invention, by designing the pattern of the opening of the patterned mask layer of the transfer structure, a plurality of parallel grooves can be formed in a self-aligned manner. Therefore, the yield and reliability of the semiconductor structure can be greatly improved. Furthermore, the shape and spacing of the ends of the linear structure can be adjusted by controlling the load effect during the etching of the sacrificial layer. In this way, the yield and reliability of the semiconductor structure can be further improved. In addition, in the manufacturing method provided in the embodiment of the present invention, only one mask is required, and no end cutting step is required. Furthermore, such a manufacturing method can be easily integrated into an existing process. Therefore, the production cost and process complexity can be greatly reduced.

[0079] Although the present invention has been disclosed above with respect to several preferred embodiments, they are not intended to limit the present invention. Any person skilled in the art may make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming an insulating layer on a substrate; forming a patterned mask layer on the insulating layer, wherein the patterned mask layer has an opening, wherein the opening comprises: a main body; and Two extension portions, respectively located at two ends of the main portion, wherein each extension portion has a first width, and the main portion has a second width greater than the first width; Conformally forming a first sacrificial layer on the insulating layer and the patterned mask layer, wherein the first sacrificial layer fills the extension portion of the opening and defines a recess in the main portion of the opening; forming a second sacrificial layer in the recess defined by the first sacrificial layer; forming a third sacrificial layer on the first sacrificial layer located on the extension portion, wherein the first sacrificial layer and the second sacrificial layer are formed of different materials, and the second sacrificial layer and the third sacrificial layer are formed of different materials; and An etching process is performed to transfer the pattern of the second sacrificial layer to the insulating layer, so as to form a first trench and a second trench on both sides of the insulating layer located at the main body portion.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: A ratio of the second width to the first width is 1.5 to 4.

0.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: Forming the second sacrificial layer includes: forming the second sacrificial layer on the first sacrificial layer; and A first etch-back process is performed on the second sacrificial layer to remove the second sacrificial layer located at the extension portion and retain the second sacrificial layer located at the main portion.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: It further includes performing a second back-etching process after the first back-etching process to remove a portion of the first sacrificial layer, wherein after the second back-etching process, in the extension portion, a top surface of the first sacrificial layer and a top surface of the patterned mask layer have a first distance D1, and in the main body portion, the top surface of the first sacrificial layer and the top surface of the patterned mask layer have a second distance D2, and the ratio D1 / D2 of the first distance D1 to the second distance D2 is 1.1 to 4.

0.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: Forming the third sacrificial layer includes: After the second etch-back process, forming the third sacrificial layer on the second sacrificial layer; and A third etch-back process is performed on the third sacrificial layer to remove a portion of the third sacrificial layer located at the main portion and retain the third sacrificial layer located at the extension portion, so that a top surface of the third sacrificial layer is lower than a top surface of the patterned mask layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The etching process includes: performing a first etching process to remove a portion of the first sacrificial layer using the second sacrificial layer and the third sacrificial layer as masks; and A second etching process is performed to remove the third sacrificial layer, and a portion of the insulating layer located in the main body is removed using the first sacrificial layer as a mask, wherein after the second etching process, the first groove and the second groove are respectively formed on both sides of the insulating layer located in the main body.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: Also includes: performing a third etching process to remove the second sacrificial layer and the patterned mask layer; as well as A fourth etching process is performed to remove the first sacrificial layer.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first groove and the second groove are arranged in parallel, one end of the first groove and one end of the second groove have a first spacing S1, a center part of the first groove and a center part of the second groove have a second spacing S2, and the second spacing S2 is greater than the first spacing S1.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: A ratio S1 / S2 of the first interval S1 to the second interval S2 is 0.40 to 0.

98.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: One end portion of the first groove has a gradually narrowing width.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein: One end of the first groove is in a smooth curve shape.

12. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method further includes filling a conductive material into the first trench to form a conductive circuit.

13. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method further includes filling an insulating material into the first trench to form an isolation structure.

14. A semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 13, characterized in that: include: a substrate; an insulating layer formed on the substrate and comprising a plurality of self-aligned and parallel trenches; and Multiple pairs of linear structures are formed in parallel in the multiple grooves of the insulating layer, each of the multiple pairs of linear structures includes a first linear structure and a second linear structure, an end of the first linear structure and an end of the second linear structure have a first spacing S1, a center portion of the first linear structure and a center portion of the second linear structure have a second spacing S2, and the second spacing S2 is greater than the first spacing S1.

15. The semiconductor structure according to claim 14, wherein: A ratio S1 / S2 of the first interval S1 to the second interval S2 is 0.40 to 0.

98.

16. The semiconductor structure according to claim 14, wherein: One end portion of the first linear structure has a gradually narrowing width.

17. The semiconductor structure according to claim 14, wherein: The end portion of the first linear structure is in a smooth curve shape.

18. The semiconductor structure according to claim 14, wherein: The first linear structure is a conductive circuit.

19. The semiconductor structure according to claim 14, wherein: The first linear structure is an isolation structure.

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