Structure with poly crystalline active region fill shape and related methods

Abstract

The present disclosure relates to a structure having poly active region fill shapes and related methods. A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer located above the semiconductor substrate, and a SOI layer located above the buried insulator layer. At least one poly active region fill shape is located in the SOI layer. A poly isolation region can be located in the semiconductor substrate below the buried insulator layer. Where at least one poly active region fill shape is provided, the at least one poly active region fill shape is laterally aligned over the poly isolation region. Where a poly isolation region is provided, the poly isolation region can extend to different depths in the semiconductor substrate.

Description

Technical Field

[0001] This disclosure relates to integrated circuit (IC) structures, and more specifically, to various structures including polycrystalline active region filling shapes and optionally polycrystalline isolation regions located below the polycrystalline active region filling shapes, to reduce harmonic and parasitic losses of radio frequency (RF) devices in semiconductor-on-insulator (SOI) applications. Background Technology

[0002] In integrated circuit (IC) architectures, active devices are electrically isolated by dielectrics. Dielectrics can be provided at multiple locations. Dielectric trench isolation typically isolates active devices laterally. In radio frequency (RF) device applications such as switches, power amplifiers, and other devices, additional isolation regions are advantageous for reducing harmonics and parasitic losses. One current approach creates a semiconductor-on-insulator (SOI) substrate with a trap-rich polycrystalline isolation layer located between a buried insulator and a semiconductor substrate. This polycrystalline isolation layer ultimately lies beneath the RF active device to provide additional isolation. In this case, the polycrystalline isolation layer has a uniform depth within the substrate. In another approach, after device formation, a polycrystalline isolation region is created in the semiconductor substrate (processed wafer) beneath the device. The process etches trenches between adjacent active devices and through various layers to reach the underlying semiconductor substrate, including gate and active region fill shapes, trench isolation, and buried insulator layers. The process then implants dopants into the semiconductor substrate to create the polycrystalline isolation region and refills the trenches with a dielectric, leaving only the dielectric above the polycrystalline isolation region. This process is both expensive and time-consuming, and it introduces a high risk of defects into active devices. Summary of the Invention

[0003] One aspect of this disclosure relates to a structure comprising: a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer disposed on the semiconductor substrate, and an SOI layer disposed on the buried insulator layer; and at least one polycrystalline active region filling shape disposed in the SOI layer.

[0004] Another aspect of this disclosure includes a structure comprising: a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer disposed above the semiconductor substrate, and an SOI layer disposed above the buried insulator layer; at least one polycrystalline active region filling shape disposed in the SOI layer; a first active device and a second active device located on opposite sides of the at least one polycrystalline active region filling shape; and a polycrystalline isolation region disposed in the semiconductor substrate below the buried insulator layer, wherein the polycrystalline isolation region extends to a first depth in the semiconductor substrate at a first location and to a second depth in the semiconductor substrate at a second location, wherein the first depth is greater than the second depth.

[0005] Another aspect of this disclosure relates to a method comprising: forming a mask including an opening that exposes a region located above at least one single-crystal active region filling shape in a semiconductor-on-insulator (SOI) layer, the SOI layer being located above a buried insulating layer, the buried insulating layer being located above a single-crystal semiconductor substrate, wherein each single-crystal active region filling shape includes a cap located thereon; converting each of the at least one single-crystal active region filling shape into a corresponding polycrystalline active region filling shape; and removing the mask.

[0006] The above and other features of this disclosure will become apparent from the following more specific description of embodiments thereof. Attached Figure Description

[0007] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein like reference numerals denote like elements, and wherein:

[0008] Figure 1 A cross-sectional view of a preliminary structure for a method according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A cross-sectional view of the formation of a mask and the implantation of a single-crystal active region filling shape and a semiconductor substrate according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of the polycrystalline active region filling shape and the polycrystalline isolation region according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a structure including a polycrystalline isolation region located below a polycrystalline filling shape, according to an embodiment of the present disclosure, is shown.

[0012] Figure 5A cross-sectional view of a structure according to other embodiments of the present disclosure is shown, including a polycrystalline isolation region located below the polycrystalline fill shape and having alternating dopants in the fill shape.

[0013] Figure 6 A cross-sectional view of the polycrystalline active region filling shape according to other embodiments of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of a structure including a polycrystalline filled shape and having optional alternating dopants in the filled shape, according to other embodiments of the present disclosure, is shown.

[0015] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, the same reference numerals represent the same elements between the figures. Detailed Implementation

[0016] In the following description, reference is made to the accompanying drawings, which form a part of this disclosure, and specific exemplary embodiments in which the present teachings can be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0017] It will be understood that when an element, such as a layer, region, or semiconductor substrate, is referred to as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intermediate elements present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements present.

[0018] References to "one embodiment" or "embodiment" and other variations thereof in this specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of any of the following, such as "A / B," "A and / or B," and "at least one of A and B," is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B and / or C” and “at least one of A, B and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). This can be readily apparent to those skilled in the art to many of the listed items.

[0019] Embodiments of this disclosure provide a structure for a semiconductor-on-insulator (SOI) substrate. In some embodiments, such a structure may include polycrystalline isolation regions and polycrystalline active region fill shapes to reduce harmonic and parasitic losses in, for example, radio frequency (RF) applications. In other embodiments, such a structure may include only polycrystalline active region fill shapes to reduce harmonic and parasitic losses in, for example, radio frequency (RF) applications. The SOI substrate includes a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. According to embodiments of this disclosure, polycrystalline active region fill shapes and polycrystalline isolation regions can be formed by implanting through single-crystal active region fill shapes and buried insulator layers into a single-crystal semiconductor substrate located below the buried insulator layer, and subsequent thermal cycling. In the case of using only polycrystalline active region fill shapes, they can be formed by implanting only through single-crystal active region fill shapes and possibly into the buried insulator layer, and subsequent thermal cycling. In either case, implantation transforms the single-crystal material into a crystallographically disordered material, which, after subsequent thermal cycling, forms polycrystalline active region filling shapes and / or polycrystalline isolation regions in the semiconductor substrate. Therefore, this process allows for the creation of polycrystalline devices in a semiconductor substrate without etching trenches, implanting, and refilling the trenches, and without removing the active region filling shapes from the SOI layer. This process also eliminates the cost of fabricating SOI substrates with trap-rich isolation regions. When providing polycrystalline silicon isolation regions, the polycrystalline active region filling shapes are laterally aligned above the polycrystalline isolation regions, and the polycrystalline isolation regions are not located below the active devices. When multiple spaced-apart active region filling shapes are implanted in appropriate locations, the polycrystalline isolation regions extend to different depths in the semiconductor substrate.

[0020] Referring to the accompanying drawings, embodiments of the method according to this disclosure will now be described. Figure 1 A cross-sectional view of the preliminary structure 100 is shown. The preliminary structure 100 includes a semiconductor-on-insulator (SOI) substrate 102, which includes a semiconductor substrate 104, a buried insulating layer 106 above the semiconductor substrate 104, and an SOI layer 108 above the buried insulating layer 106. The semiconductor substrate 104 and the SOI layer 108 comprise single-crystal materials, such as, but not limited to, silicon, germanium, silicon-germanium, silicon carbide, and materials substantially composed of materials having the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4Those comprising one or more III-V compound semiconductors with defined compositions, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 is the total relative molar amount). Other suitable substrates include those having the composition Zn. A1 Cd A2 Se B1 Te B2 The semiconductor is a group II-VI compound semiconductor, where A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). Furthermore, some or all of the semiconductor material may be strained. For example, the SOI layer 108 may be strained.

[0021] The buried insulating layer 106 may comprise any suitable dielectric material, including but not limited to: carbon-doped silica materials; fluorinated silicate glass (FSG); organic polymer thermosetting materials; silica carbon; SiCOH dielectrics; fluorine-doped silica; spin-coated glass; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and mixtures or copolymers of HSQ and MSQ; benzocyclobutene (BCB)-based polymer dielectrics; and any silicon-containing low-k dielectric. Examples of spin-coated low-k films with SiCOH-type components using silsesquioxane chemistry include HOSP. TM (Available from Honeywell), JSR 5109 and 5108 (Available from Japan Synthetic Rubber), Zirkon TM (Available from Shipley Microelectronics, a division of Rohm and Haas), and porous low-k (ELk) materials (available from Applied Materials). Examples of carbon-doped silica materials or organosilanes include Black Diamond. TM (Available from Applied Materials) and Coral TM (Available from Lam Research). An example of HSQ material is FOX. TM (Available from Dow Corning). In one embodiment, the buried insulating layer 106 comprises silicon oxide. The SOI substrate 102 can be formed using any semiconductor manufacturing process now known or developed in the future.

[0022] SOI layer 108 is segmented to create multiple single-crystal active segment 110 therein. Although specific locations of the active segment 110 will be described, it is clear that other locations are also possible. Figure 1 The diagram illustrates forming a first device active region 112 on one side of at least one single-crystal active region filling shape 118 (hereinafter referred to as "single-crystal filling shape 118") and forming a second device active region 114 on the opposite side of the single-crystal filling shape 118. Therefore, the SOI layer 108 includes a first device active region 112 and a second device active region 114. Each of the active regions 112 and 114 will ultimately be used to create an active device. For example, the first device active region 112 can be used for radio frequency (RF) devices, such as, but not limited to, switches or power amplifiers, and the second device active region 114 can be used for complementary metal-oxide-semiconductor (CMOS) devices, such as, but not limited to, transistors. The active region segment 110 can be formed in the SOI layer 108 using any semiconductor fabrication techniques now known or developed thereafter, such as depositing a blanket single-crystal SOI layer 108 and patterning / etching an SOI layer.

[0023] Etching generally refers to the removal of material from a substrate (or a structure formed on the substrate) and is typically performed using an in-place mask to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are generally two types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., acid), where the solvent can be selected based on its ability to selectively dissolve a given material (e.g., oxide) while leaving other materials (e.g., polycrystalline silicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically isotropically etches homogeneous materials (e.g., oxides), but it can also anisotropically etch single-crystal materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates electrically neutral high-energy radicals that react on the wafer surface. Because neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching uses high-energy ions from rare gases to bombard a wafer. These ions approach the wafer from roughly one direction, making the process highly anisotropic. Reactive ion etching (RIE) operates under conditions between sputtering and plasma etching and can be used to create deep, narrow features, such as STI trenches.

[0024] SOI layer 108 may also include active region segments 110 in the form of single-crystal fill shapes 118 (four are shown, but there may be more or fewer). Active regions 112, 114 (and single-crystal fill shapes 118) are electrically isolated from each other by one or more trench isolations 120 (e.g., shallow trench isolations). The single-crystal fill shapes 118 are positioned within the active region layer (i.e., SOI layer 108) to improve pattern density (active and fill) to aid in patterning the active layer (e.g., endpoint detection, slope, critical size control, etc.) and planarizing the trench isolations 120 (e.g., reducing dishing that may occur in the dielectric of the trench isolations 120 during planarization). Dishing can cause numerous problems in subsequent processing, such as misalignment, underfill, non-planarity, etc. The single-crystal fill shapes 118 may have any lateral shape required to provide the desired increase in density.

[0025] The trench isolation 120 comprises trenches etched through the SOI layer 108 and filled with an insulating material such as an oxide to isolate a region of the SOI layer 108 from its adjacent regions (e.g., active regions 112, 114 and adjacent single-crystal fill shape 118). Each trench isolation 120 may be formed of any material now known or later developed for providing electrical insulation, and by way of example such material may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) comprising atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H), thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or layers thereof. In a non-limiting example, trench isolation 120 comprises the same material as buried insulation layer 106.

[0026] The preliminary structure 100 also includes a cap 122 located above each active segment 110. The cap 122 may include a material that is harder than the trench isolation 120 material to protect the active segment 110 during subsequent processing. In a non-limiting example, the cap 122 may include a silicon oxide layer 124 located beneath the silicon nitride layer 125.

[0027] Figures 2 to 4 A cross-sectional view of a method according to an embodiment of the present disclosure is shown, wherein a polycrystalline active region filling shape and a polycrystalline isolation region are formed. Figure 2A mask 126 is shown formed over a preliminary structure 100. Mask 126 may include any mask material now known or developed later. Common masking materials are photoresists (photoresists) and nitrides. Nitrides are generally considered "hard masks." The mask may include a developable organic planarization layer (OPL) on the layer to be etched, a developable antireflective coating (ARC) on the developable OPL, and a photoresist mask layer on the developable ARC layer. Mask 126 includes an opening 128. The opening 128 exposes a region on at least one single-crystal fill shape 118 of the SOI layer 108 above the buried insulator layer 106 above the single-crystal semiconductor substrate 104. As noted, each single-crystal fill shape 118 includes a cap 122. Mask 126 covers first and second active regions 112, 114 located in the SOI layer 108.

[0028] Figure 2 and Figure 3 The images together show cross-sectional views of each single-crystal filling shape 118 being converted into a corresponding polycrystalline active region filling shape 130 and the upper portion 132 of the single-crystal semiconductor substrate 104 being converted into a polycrystalline isolation region 134. Figure 2 This shows the dopant ( Figure 2 The dopant (arrow in the figure) is implanted into the active segment 110, which is separate from other regions. As shown, the dopant is implanted into the single-crystal filled shape 118 and the single-crystal semiconductor substrate 104. Implantation, or doping, is a process of introducing impurities (dopants) into a material. Ion implanters are typically used for actual implantation. An inert carrier gas, such as nitrogen, is typically used to introduce the impurity source (dopant). The dose and energy levels suitable for a particular SOI substrate 102 and the desired doping and / or the final doping level can be specified. The doping level can be determined by the amount of dopant per square centimeter (cm²). 2 The dosage is specified by the number of atoms and the energy level (in keV, or kiloelectron volts), thus obtaining the dosage per cubic centimeter (cm³). 3 The doping level (concentration in the substrate) refers to the number of atoms. The number of atoms is usually specified using exponential notation, where a number like "3E15" represents 3 multiplied by 10 to the power of 15, or "3" followed by 15 zeros (3,000,000,000,000,000). From this perspective, per cubic centimeter (cm³) 3 There are approximately 1E23 (100,000,000,000,000,000,000) hydrogen and oxygen atoms in water. An example of doping is the implantation of approximately 1E12 to 1E13 atoms per cm³. 2 A dose between 40 and 80 keV of argon (Ar) is used to produce 1E17 to 1E18 atoms / cm². 3 The doping level. In this case, such as Figure 3As shown, the injection is performed to damage the single-crystal material to which it is applied. Figure 3 One or more thermal cycles are also shown, such as annealing as indicated by the arrows, which reorder the damaged and disordered crystallographic material into a polycrystalline material. Thermal cycles may include one or more intentionally added recrystallization anneals shortly after implantation, or normal high-temperature (>600°C) processes associated with semiconductor manufacturing. In this way, the process transforms each single-crystal fill shape 118 into a corresponding polycrystalline active region fill shape 130, and transforms the upper portion 132 of the single-crystal semiconductor substrate 104 into a polycrystalline isolation region 134. The implanted dopant may include any material capable of producing a polycrystalline material, including but not limited to: germanium (Ge); rare gases such as argon (Ar) or xenon (Xe); or combinations of the previously listed materials, such as Ge-Ar or Ge-Xe.

[0029] like Figure 3 As shown, the injection extends through the buried insulating layer 106 and into the single-crystal semiconductor substrate 104, i.e., the mask 126 ( Figure 2 The uncovered areas. Because mask 126 covers the active regions 112 of the first device and 114 of the second device, the polysilicon isolation region 134 is not located in the areas not covered by the first and second devices 152 and 124. Figure 4Below the cap 122 and the single-crystal fill shape 118, the formation of the polycrystalline isolation region 134 is influenced, i.e., by affecting the penetration depth of the implantation. For example, the polycrystalline active region fill shape 130 (hereinafter referred to as "polycrystalline fill shape 130") is laterally aligned above the polycrystalline isolation region 134. That is, the polycrystalline isolation region 134 extends laterally to the same distance from either side of the outermost polycrystalline fill shape 133. In addition, the width W1 of the polycrystalline isolation region 134 is greater than the width W2 of the polycrystalline fill shape 130 (i.e., from the outermost edge of the outermost fill shape to the outermost edge of the opposite outermost fill shape). There may be a gap 136 between at least two polycrystalline fill shapes 130 (as shown). In this case, a unique shape is created in the polycrystalline isolation region 134 because the polycrystalline fill shape 130 changes the penetration degree of the dopant at its location. As shown, the conversion results in the upper portion 132 of the single-crystal semiconductor substrate 104 being converted into a polycrystalline isolation region 134, which extends to a first depth D1 in the semiconductor substrate 104. The polycrystalline isolation region 134 may be located at a first position laterally aligned with the spacing 136 between at least two polycrystalline fill shapes 130. The polycrystalline isolation region 134 may extend to a second depth D2 in the semiconductor substrate 104 at a second position not laterally aligned with the spacing 136 between at least two polycrystalline fill shapes 130. As shown, the first depth D1 is greater than the second depth D2. Therefore, the polycrystalline isolation region 134 may include a deeper region 140 and a shallower region 142, which is formed by the single-crystal fill shape 118 (… Figure 2 This is due to the positioning of the polycrystalline isolation region 134. In a non-limiting example shown, the polycrystalline isolation region 134 includes a serrated pattern with alternating deeper regions 140 and shallower regions 142. By combining control over implantation, thermal cycling, and dopant selection, the single-crystal fill shape 118 can be shaped, spaced, and / or positioned in any manner to create a polycrystalline isolation region 134 with any desired shape, depth, and / or width. In this way, the isolation characteristics of the polycrystalline isolation region 134 can be customized.

[0030] Figure 3 The removal of mask 126 is also shown. Figure 3 Mask 126 can be removed using any suitable removal process, such as wet etching suitable for the mask material.

[0031] Figure 4A cross-sectional view of structure 150 after subsequent conventional device formation, according to an embodiment of the present disclosure, is shown. Subsequent processing may include any now-known or later-developed front-end process (FEOL) semiconductor manufacturing process to form devices, such as first active device 152 and second active device 154. Subsequent processing (shown in part only) may also include any mid-end process (MOL) or back-end process (BEOL) processing, such as for interconnects. Processes may include, for example, cap removal, source / drain formation, gate 156 formation (forming active and dummy-fill gates over active region fill shape 130 by gate-first or alternative metal gate processing), interlayer dielectric formation, and interconnect formation (the last one not shown). Active gate 156 is shown to form first active device 152, for example, an RF device, and second active device 154, for example, a CMOS device.

[0032] like Figure 4 As shown, according to one embodiment, structure 150 includes an SOI substrate 102, as described herein. Structure 150 also includes a polycrystalline fill shape 130 located in the SOI layer 108 and a polycrystalline isolation region 134 located in a semiconductor substrate 104 beneath a buried insulating layer 106. A first active device 152 and a second active device 154 are located on opposite sides of the polycrystalline fill shape 130. In a non-limiting example, the first active device 152 may include, for example, an RF device, and the second active device 154 may include a CMOS device. In either case, the polycrystalline isolation region 134 provides RF isolation for sensitive device structures (e.g., RF switches, power amplifiers, etc.) without requiring aggressive etching / implantation and refilling processes, thereby significantly reducing complexity, defect risk, and cost. The polycrystalline isolation region 134 also reduces the size of the conventional single-crystal active region fill shape 118 ( Figure 2 Eddy currents in passive components (inductors, transmission lines, metal-insulator-metal (MIM) capacitors) are used to provide an improved quality (Q) factor.

[0033] Structure 150 also has a laterally aligned polycrystalline fill shape 130 above the polycrystalline isolation region 134. Unlike conventional SOI substrates with a trap-rich polycrystalline isolation layer of uniform thickness located between the buried insulator and the semiconductor substrate, the polycrystalline isolation region 134 is not located on the first and second active devices 152, 154. Figure 4 Below. (e.g.) Figure 3As shown, the width W1 of the polycrystalline isolation region 134 is greater than the width W2 of the polycrystalline fill shape 130. With a gap 136 between at least two polycrystalline fill shapes 130, the polycrystalline isolation region 134 extends to a first depth D1 in the semiconductor substrate 104 at a first location laterally aligned with the gap 136 between the at least two polycrystalline fill shapes 130, and extends to a second depth D2 in the semiconductor substrate 104 at a second location not laterally aligned with the gap 136 between the at least two polycrystalline active region fill shapes 130. As indicated, the first depth D1 is greater than the second depth D2. In a non-limiting example, the polycrystalline fill shape 130 and the polycrystalline isolation region 134 may include any dopant described herein, such as argon, xenon, germanium, or combinations thereof.

[0034] Figure 5 A cross-sectional view of another embodiment is shown, wherein at least two polycrystalline active region fill shapes 130 have alternating opposite p-type and n-type doping. Doping can be applied in any manner now known or later developed, for example, by ion implantation during source / drain formation. In a non-limiting example, p-type dopants may include boron (B) and indium (In); and n-type dopants may include phosphorus (P), arsenic (As), and antimony (Sb). Alternating doping improves harmonics by alternating S / D implantation types between fill shapes. In either case, each fill shape 130 is dielectrically separated, thereby creating islands of alternating p-type and n-type doping. In other embodiments, each polycrystalline fill shape 130 may include its own p / n junction, thereby creating p / n junction islands. Dopant can be formed in the fill shape in any manner now known or later developed, for example, by masked ion implantation.

[0035] refer to Figure 2 , Figure 6 and Figure 7 Alternative embodiments according to this disclosure will be described below. In this embodiment, a transition occurs for each single-crystal filling shape 118 to the corresponding polycrystalline active region filling shape 130, but the transition from the upper portion 132 of the single-crystal semiconductor substrate 104 to the polycrystalline isolation region is omitted, as... Figures 3 to 5 As shown. Figure 2 This demonstrates the implantation of dopants into ( Figure 2 (The arrow in the image) indicates the active segment 110, excluding other regions. For example... Figure 6 As shown, dopants are implanted into the single-crystal filled shape 118, but with... Figures 3 to 5 In contrast to the previous embodiment, the dopant was not implanted into the single-crystal semiconductor substrate 104. In this case, as... Figure 6 As shown, the injection has sufficient energy to fill the single-crystal shape 118, but insufficient energy to impact the single-crystal substrate 104. As in the foregoing embodiments, Figure 6 One or more thermal cycles are also shown, such as annealing as indicated by the arrows, which reorder the damaged and disordered crystallographic material into a polycrystalline material. As noted, the thermal cycles may include one or more intentionally added recrystallization anneals shortly after implantation, or normal high-temperature (>600°C) processes associated with semiconductor manufacturing. In this way, the process converts each single-crystal fill shape 118 into a corresponding polycrystalline active region fill shape 130. The single-crystal semiconductor substrate 104 remains single-crystal. As noted, the implanted dopant may include any material capable of producing a polycrystalline material, including but not limited to: germanium (Ge); rare gases, such as argon (Ar) or xenon (Xe); or combinations of the previously listed materials, such as Ge-Ar or Ge-Xe.

[0036] Figure 7 A cross-sectional view of structure 250 after subsequent conventional device formation, according to an alternative embodiment of the present disclosure, is shown. (See also: Regarding...) Figure 5 As indicated, subsequent processing may include any now-known or later-developed front-end process (FEOL) semiconductor manufacturing process to form devices, such as the first active device 152 and the second active device 154. Subsequent processing (shown in part only) may also include any mid-end process (MOL) or back-end process (BEOL) processing, for example, for interconnects. As indicated, processing may include, for example, cap removal, source / drain formation, gate 156 formation (forming active and dummy-filled gates over the active region fill shape 130 via a gate-first or alternative metal gate process), interlayer dielectric formation, and interconnect formation (the last one not shown). Active gate 156 is shown to form a first active device 152, for example, an RF device, and a second active device 154, for example, a CMOS device.

[0037] like Figure 7 As shown, according to one embodiment, structure 250 includes an SOI substrate 102, as described herein. Structure 250 also includes a polycrystalline fill shape 130 located in the SOI layer 108. Here, the polycrystalline isolation region located in the semiconductor substrate 104 is omitted. Figures 4 to 5 The first active device 152 and the second active device 154 are located on opposite sides of the polycrystalline fill shape 130. In a non-limiting example, the first active device 152 may include, for example, an RF device, and the second active device 154 may include a CMOS device. In either case, the polycrystalline fill shape 130 provides RF isolation for sensitive device structures (e.g., RF switches, power amplifiers, etc.) without requiring aggressive etching / implantation and refilling processes, thereby significantly reducing complexity, defect risk, and cost. The polycrystalline fill shape 130 also reduces the conventional single-crystal active region fill shape 118 ( Figure 2Eddy currents in passive components (inductors, transmission lines, metal-insulator-metal (MIM) capacitors) are used to provide an improved quality (Q) factor.

[0038] Figure 7 Another alternative embodiment is also shown, wherein at least two polycrystalline active region fill shapes 130 optionally have alternating opposite p-type and n-type doping applied to structure 250. As noted, doping can be applied in any manner now known or later developed, for example, by ion implantation during source / drain formation. The p-type and n-type dopants can include any of the foregoing elements. As noted, alternating doping improves harmonics by alternating S / D implantation types between fill shapes. In either case, each fill shape 130 is dielectrically separated, thereby creating islands of alternating p-type and n-type doping. Each polycrystalline fill shape 130 can include its own p / n junction, thereby creating p / n junction islands. Dopant can be formed in the fill shape in any manner now known or later developed, for example, by masked ion implantation.

[0039] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the said feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that an event or condition subsequently described may or may not occur, and the description includes instances where the event occurs and instances where the event does not occur.

[0041] As used throughout the specification and claims, approximate language may be used to modify any quantitative representation that may vary within permissible ranges without causing a change in the essential function it relates to. Therefore, values ​​modified by one or more terms such as “approximately,” “about,” and “substantially” are not limited to the specified precise values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Range limitations may be combined and / or interchanged herein and throughout the specification and claims, and such ranges are identified as including all subranges contained herein unless otherwise indicated by context or language. Unless otherwise dependent on the precision of the instrument used to measure the value, “approximately” applied to a particular value within a range simultaneously modifies two values ​​representing + / - 10% of said value.

[0042] All means or steps plus functional elements in the claims are intended to include any structure, material, action, and equivalent for performing a function in combination with other claimed elements of the specific claims. The description of this disclosure has been given for purposes of illustration and description, but it is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of this disclosure and to enable others skilled in the art to understand various embodiments of this disclosure with various modifications suitable for the contemplated particular purpose.

Claims

1. An integrated circuit structure, comprising: Semiconductor-on-insulator (SOI) substrate, comprising a semiconductor substrate, a buried insulator layer on the semiconductor substrate, and an SOI layer on the buried insulator layer; as well as The filling shape of at least one polycrystalline active region located in the SOI layer.

2. The integrated circuit structure according to claim 1, further comprising: The polycrystalline isolation region located in the semiconductor substrate beneath the buried insulating layer. The filling shape of at least one of the polycrystalline active regions is laterally aligned above the polycrystalline isolation region.

3. The integrated circuit structure according to claim 2, further comprising: A first active device and a second active device are located on opposite sides of the filling shape of the at least one polycrystalline active region.

4. The integrated circuit structure according to claim 3, wherein, The first active device includes a radio frequency (RF) device, and the second active device includes a complementary metal-oxide-semiconductor (CMOS) device.

5. The integrated circuit structure according to claim 3, wherein, The polycrystalline isolation region is not located below the first active device and the second active device.

6. The integrated circuit structure according to claim 2, wherein, The width of the polycrystalline isolation region is greater than the width of the filling shape of the at least one polycrystalline active region.

7. The integrated circuit structure according to claim 2, wherein, The at least one polycrystalline active region filling shape includes at least two polycrystalline active region filling shapes spaced apart therebetween.

8. The integrated circuit structure according to claim 7, wherein, The polycrystalline isolation region extends into the semiconductor substrate at a first location laterally aligned with the interval between the at least two polycrystalline active region filling shapes, and extends into the semiconductor substrate at a second location not laterally aligned with the interval between the at least two polycrystalline active region filling shapes, wherein the first depth is greater than the second depth.

9. The integrated circuit structure according to claim 7, wherein, The at least two polycrystalline active regions have alternating opposite p-type and n-type doping shapes.

10. The integrated circuit structure according to claim 2, wherein, The at least one polycrystalline active region filling shape and the polycrystalline isolation region include dopants selected from argon, xenon, germanium, or combinations thereof.

11. An integrated circuit structure, comprising: Semiconductor-on-insulator (SOI) substrate, comprising a semiconductor substrate, a buried insulator layer on the semiconductor substrate, and an SOI layer on the buried insulator layer; At least one polycrystalline active region filling shape is located in the SOI layer; A first active device and a second active device, the first active device and the second active device being located on opposite sides of the filling shape of the at least one polycrystalline active region; as well as A polycrystalline isolation region located in the semiconductor substrate beneath the buried insulator layer. The polycrystalline isolation region extends to a first depth in the semiconductor substrate at a first location and to a second depth in the semiconductor substrate at a second location, wherein the first depth is greater than the second depth.

12. The integrated circuit structure according to claim 11, wherein, The polycrystalline isolation region is not located below the first active device and the second active device.

13. The integrated circuit structure according to claim 11, wherein, The width of the polycrystalline isolation region is greater than the width of the filling shape of the at least one polycrystalline active region.

14. The integrated circuit structure according to claim 11, wherein, The at least one polycrystalline active region filling shape includes at least two polycrystalline active region filling shapes spaced apart therebetween.

15. The integrated circuit structure according to claim 14, wherein, The at least two polycrystalline active regions have alternating opposite p-type and n-type doping shapes.

16. The integrated circuit structure according to claim 11, wherein, The at least one polycrystalline active region filling shape and the polycrystalline isolation region include dopants selected from argon, xenon, germanium, or combinations thereof.

17. A method for forming an integrated circuit structure, comprising: A mask is formed including an opening that exposes a region above at least one single-crystal active region filling shape in a semiconductor-on-insulator (SOI) layer, the SOI layer being above a buried insulator layer being above a single-crystal semiconductor substrate, wherein each single-crystal active region filling shape includes a cap thereon. Each of the at least one single-crystal active region filling shapes is converted into a corresponding polycrystalline active region filling shape; as well as Remove the mask.

18. The method of claim 17, further comprising: Before forming the mask, a first device active region is formed on one side of the at least one single-crystal active region filling shape and a second device active region is formed on the opposite side of the at least one single-crystal active region filling shape, wherein the mask covers the first device active region and the second device active region.

19. The method according to claim 18, wherein, The conversion further includes: converting the upper part of the single-crystal semiconductor substrate into a polycrystalline isolation region, and The width of the polycrystalline isolation region is greater than the width of the filling shape of the at least one polycrystalline active region, and The polycrystalline isolation region is not located below the active regions of the first device and the second device.

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