Storage system including a decoupling device having a plurality of unit capacitors

Abstract

A storage system including a decoupling device having a plurality of unit capacitors is provided. A storage system according to an embodiment of the present disclosure includes a storage device, a control device, and a decoupling device arranged on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an internal voltage. The decoupling device is connected to the control device and decouples the internal voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each unit capacitor includes a plurality of capacitor elements, a first terminal, and a second terminal. Some unit capacitors are selectively connected to each other to constitute decoupling capacitors having various capacitances.

Description

Technical Field

[0001] The present disclosure generally relates to a memory system including a decoupling capacitor having a plurality of unit capacitors and a method of manufacturing the memory system. Background Art

[0002] As electronic systems become smaller and smaller, the size of memory systems used by the electronic systems also becomes smaller and smaller. In particular, the thickness of memory systems installed in mobile devices is becoming thinner and thinner. Summary of the invention

[0003] Embodiments of the present disclosure are directed to a storage system including a decoupling device having a plurality of unit capacitors formed in a semiconductor substrate.

[0004] A storage system according to an embodiment of the present disclosure may include a storage device, a control device, and a decoupling device arranged on a circuit substrate. The storage device may receive and store data from the control device. The control device may generate an internal voltage. The decoupling device may be connected to the control device and decouple the internal voltage. The decoupling device may include a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each unit capacitor may include a plurality of capacitor elements, a first terminal, and a second terminal. Some unit capacitors may be selectively connected to each other to form decoupling capacitors having various capacitances.

[0005] A storage system according to an embodiment of the present disclosure may include a storage device, a control device, and a decoupling device disposed on a circuit substrate. The control device may include: a first power pad, a second power pad, a ground pad, and an internal voltage pad to provide some voltage generated in the control device to the storage device; an external input / output pad that communicates with an external system; and an internal input / output pad that communicates with the storage device. The decoupling device may include a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each unit capacitor may include a first electrode pad and a second electrode pad. The first power pad of the control device may be electrically connected to the first electrode pad of one unit capacitor. The second power pad of the control device may be electrically connected to the first electrode pads of two unit capacitors. The ground pad of the control device may be electrically connected to the second electrode pad of the unit capacitor in common. Each unit capacitor may include a capacitor element formed in a recess formed in a base substrate, and a lower electrode, a capacitor dielectric layer, an upper electrode, a first terminal connected to the upper electrode, and a second terminal connected to the lower electrode shared by the capacitor element. Some unit capacitors may be selectively connected to each other to constitute decoupling capacitors with various capacitances.

[0006] A storage system according to an embodiment of the present disclosure may include: a storage device; a control device electrically connected to the storage device; and a decoupling device electrically connected to a power pad and a ground pad of the control device. The decoupling device may include a plurality of unit capacitors. Each unit capacitor may include: a buffer insulating layer formed on a base substrate; a recess vertically penetrating the buffer insulating layer to extend into the base substrate, wherein the recesses are arranged to be spaced apart from each other, and wherein the recesses are formed in a hole shape; a lower electrode including a lower electrode pattern formed on an inner wall and a bottom of the recess, and including a lower main connector formed on an upper surface of the buffer insulating layer to be electrically connected to the lower electrode pattern; a capacitor dielectric layer including a dielectric pattern formed on a lower electrode pattern formed in the recess, and including a dielectric connection pattern formed on the lower main connector to be physically connected to the dielectric pattern; an upper electrode including an upper electrode pattern formed on a dielectric pattern in the recess to fill the recess, and an upper main connector formed on the dielectric connection pattern to be horizontally connected to the upper electrode pattern; and a passivation layer located on the upper electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a diagram schematically showing a layout of a storage system according to one embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A Side view of the storage system.

[0009] Figure 2 is a perspective view showing electrical connection between a control device and a decoupling device of a storage system according to one embodiment of the present disclosure.

[0010] Figure 3 is a top view showing electrical connections of power pads, ground pads, internal voltage pads, external input / output pads, wires, and substrate interconnects of a control device according to one embodiment of the present disclosure.

[0011] Figure 4 is a top view schematically showing electrical connections among a first decoupling pad, a second decoupling pad, a conductive line, and a substrate interconnection of a decoupling device according to an embodiment of the present disclosure.

[0012] Figure 5 is a top view schematically showing a wafer on which a plurality of unit capacitors are formed according to one embodiment of the present disclosure.

[0013] Fig. 6A and Figure 6B are respectively along Figure 5 A longitudinal cross-sectional view is taken along line II' to schematically illustrate the structure of one unit capacitor of the decoupling device according to an embodiment of the present disclosure.

[0014] Fig. 7A is a side cross-sectional view showing a recessed portion of a unit capacitor according to one embodiment of the present disclosure, and Figure 7B and Figure 7C is a cross-sectional view or a plan view showing a recessed portion of a unit capacitor.

[0015] Fig. 8A is a side cross-sectional view showing a lower electrode of a unit capacitor according to one embodiment of the present disclosure, and FIG. 8B to FIG. 8E is a cross-sectional view or a plan view showing a lower electrode of a unit capacitor according to an embodiment of the present disclosure.

[0016] Fig.9A is a side cross-sectional view showing a capacitor dielectric layer of a unit capacitor according to one embodiment of the present disclosure, and FIG. 9B to FIG. 9D is a cross-sectional view or a plan view showing a capacitor dielectric layer of a unit capacitor according to an embodiment of the present disclosure.

[0017] Fig. 10A is a side cross-sectional view showing an upper electrode of a unit capacitor according to one embodiment of the present disclosure, and FIG. 10B to FIG. 10E is a cross-sectional view or a plan view showing an upper electrode of a unit capacitor according to an embodiment of the present disclosure.

[0018] Fig.11 is a layout view or a top view showing a first electrode through hole and a first electrode pad of a first terminal and a second electrode through hole and a second electrode pad of a second terminal of a unit capacitor according to one embodiment of the present disclosure.

[0019] Fig.12 is a schematic layout diagram showing a storage system according to one embodiment of the present disclosure.

[0020] Fig.13 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to one embodiment of the present disclosure is shown.

[0021] Fig.14 A block diagram illustrating another electronic system including a semiconductor package according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] Various examples and embodiments of the disclosed technology are described in detail below with reference to the accompanying drawings. The drawings may not necessarily be drawn to scale, and in some cases, the proportions of at least some structures in the drawings may be exaggerated in order to clearly illustrate some features of the described examples or embodiments. When presenting a specific example with two or more layers in a multilayer structure in the drawings or descriptions, the relative positioning relationship of these layers or the arrangement order of the layers shown reflects the specific implementation of the described or illustrated examples, and different relative positioning relationships or arrangement orders of the layers may be adopted. In addition, the examples of the described or illustrated multilayer structures may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0023] Figure 1A FIG. 1 is a diagram schematically showing a layout of a storage system 100 according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A side view of a storage system 100 is shown. Figure 1B Shown in Figure 1A All devices.

[0024] Reference Figure 1A and Figure 1B The memory system 100 according to one embodiment of the present disclosure may include a memory device 20, a control device 30, a decoupling device 40, and a molding layer 65 disposed on a circuit substrate 10. The memory system 100 may further include a support member 15 disposed on the circuit substrate 10 to support the memory device 20.

[0025] The circuit substrate 10 may include a printed circuit board (PCB). In one embodiment, the circuit substrate 10 may include a redistribution layer (RDL) formed on a silicon substrate.

[0026] The storage device 20 may include a plurality of memory devices 21 stacked in a staircase manner. For example, the memory device 21 may include a NAND flash memory device. The memory device 21 of the storage device 20 may be electrically connected to the circuit substrate 10 through a wire W. The storage device 20 may store data received from the control device 30 or provide the stored data to the control device 30.

[0027] The control device 30 may communicate with the storage device 20 based on a signal transmitted from an external system. For example, the control device 30 may receive data from the external system and transmit the data to the storage device 20. The control device 30 may receive data from the storage device 20 and transmit the data to the external system. The control device 30 may receive power from the external system and generate various internal voltages used in the storage system 100. For example, the control device 30 may receive an external voltage (VDD or VCC) from the external system and generate an internal power supply voltage (VDDi), an internal data power supply voltage (VDDiQ), a reference voltage (Vref), and other internal voltages. The control device 30 may provide some of the various internal voltages generated to the storage device 20. The control device 30 may be electrically connected to the circuit substrate 100 through a wire W.

[0028] The decoupling device 40 may be electrically connected to the circuit substrate 10 through a wire W. The decoupling device 40 may be electrically connected to the control device 30. Some of the various internal voltages generated by the control device 30 may be shared with the decoupling device 40. That is, the decoupling device 40 may decouple some of the various internal voltages generated by the control device 30.

[0029] The support element 15 may include a dummy chip, an insulating dam or an insulating column. The support element 15 may separate the storage device 20 from the circuit substrate 10. The storage device 20 may be stacked on the support element 15. The control device 30 and the decoupling device 40 may be arranged in a space S provided by the storage device 20 and the support element 15. In one embodiment, the space S may be filled with a film over die (FOD), a film on wire (FOW) or an underfill material. In one embodiment, the support element 15 may be omitted.

[0030] The molding layer 65 may cover and surround surfaces of the circuit substrate 10 and the memory device 20. The molding layer 65 may include epoxy molding compound (EMC).

[0031] Figure 2 is a perspective view showing electrical connection between the control device 30 and the decoupling device 40 of the storage system 100 according to one embodiment of the present disclosure.

[0032] Reference Figure 2 , the control device 30 and the decoupling device 40 are arranged and mounted on the circuit substrate 10 to be electrically connected to substrate interconnections 71-75 respectively through wires W. The substrate interconnections 71-75 may include a power interconnection 71, a ground interconnection 72, an internal voltage interconnection 73, an external input / output interconnection 74, and an internal input / output interconnection 75.

[0033] The control device 30 may include a power pad 31, a ground pad 32, an internal voltage pad 33, an external input / output pad 34, and an internal input / output pad 35. For ease of illustration, the number of each of the pads 31-35 has been simplified. That is, the control device 30 may actually include more pads 31-35 than the number shown. The power pad 31, the ground pad 32, and the internal voltage pad 33 may provide the storage device 20 with various voltages generated in the control device 30.

[0034] The decoupling device 40 may include a first decoupling pad 41 and a second decoupling pad 42 .

[0035] The power pad 31 and the internal voltage pad 33 of the control device 30 may be electrically connected to the first decoupling pad 41 of the decoupling device 40 through the wire W, the power interconnect 71 and the internal voltage interconnect 73 .

[0036] The ground pad 32 of the control device 30 may be electrically connected to the second decoupling pad 42 of the decoupling device 40 through the wire W and the ground interconnect 72. Therefore, the decoupling device 40 may decouple various internal voltages of the control device 30.

[0037] The external input / output pads 34 and the internal input / output pads 35 of the control device 30 may be electrically connected to the external system and the memory device 20 through the wires W, the external input / output interconnects 74 , and the internal input / output interconnects 75 .

[0038] The power interconnect 71, the ground interconnect 72, the internal voltage interconnect 73, the external input / output interconnect 74, and the internal input / output interconnect 75 may be buried and embedded in the circuit substrate 10. In one embodiment, one power interconnect 71 may be connected to the memory device 20. For example, one power interconnect 71 may transmit and provide a reference voltage to the memory device 20.

[0039] Figure 3 1 is a top view showing the electrical connections of power pads 31a-31c, ground pads 32a-32c, internal voltage pads 33, external input / output pads 34a and 34b, internal input / output pads 35a-35c, wires W, and substrate interconnects 71a-71c, 72a-72c, 73a and 73b, 74a and 74b, and 75a-75c of a control device 30 according to an embodiment of the present disclosure.

[0040] Reference Figure 3, the power supply pads 31a-31c of the control device 30 can transmit the power supply voltage. The grounding pads 32a-32c of the control device 30 can transmit the grounding voltage. The internal voltage pad 33 of the control device 30 can be electrically connected to one of the power supply pads 31a-31c to transmit the internal voltage. For example, the internal voltage provided by the internal voltage pad 33 can be provided to the control device 30 again. The internal voltage pad 33 can be arranged adjacent to the external input / output pads 34a and 34b. The internal voltage provided by the internal voltage pad 33 can be used as the highest voltage (e.g., VDDiQ) of the external data signal provided by the external input / output pads 34a and 34b. Therefore, the internal voltage pad 33 is arranged adjacent to the external input / output pads 34a and 34b for data input / output, so that the internal voltage can be used as the maximum voltage of the external data signal without voltage noise or with minimum voltage noise. The external input / output pads 34a and 34b of the control device 30 may transmit electrical signals for communicating with an external system. The internal input / output pads 35a-35c of the control device 30 may transmit electrical signals for communicating with the storage device 20.

[0041] The power pads 31a-31c may be electrically connected to the power interconnects 71a-71c, respectively, through the wires W. The ground pads 32a-32c may be electrically connected to the ground interconnects 72a-72c, respectively, through the wires W. The internal voltage pad 33 may be electrically connected to the internal voltage interconnects 73a-73b through the wires W. The first internal voltage interconnect 73a may be electrically connected to the internal voltage pad 33 through the wires W. The second internal voltage interconnect 73b may electrically connect the first internal voltage interconnect 73a to one of the power interconnects 71a-71c. The external input / output pads 34a and 34b and the internal input / output pads 35a-35c may be electrically connected to the external input / output interconnects 74a and 74b and the internal input / output interconnects 75a-75c, respectively, through the wires W. The ground interconnects 72a-72c may be integrated and connected as one. Therefore, the ground pads 32a-32c may be electrically connected to each other through the ground interconnections 72a-72c.

[0042] Figure 4 is a top view schematically showing electrical connections of first decoupling pads 41 a - 41 f , second decoupling pads 42 a - 42 f , wires W, and substrate interconnects 71 a - 71 c and 72 of a decoupling device 40 according to an embodiment of the present disclosure.

[0043] Reference Figure 4, the decoupling device 40 may include a plurality of unit capacitors 40a-40f. The plurality of unit capacitors 40a-40f may have the same specifications. For example, the plurality of unit capacitors 40a-40f may have the same size, the same structure, and the same unit capacitance. Each of the plurality of unit capacitors 40a-40f may include a first decoupling pad 41a-41f and a second decoupling pad 42a-42f. The first decoupling pad 41a-41f and the second decoupling pad 42a-42f of the unit capacitor 40a-40f may have a capacitive connection. Therefore, the first decoupling pad 41a-41f and the second decoupling pad 42a-42f can be formed as an electrode pair of each of the unit capacitors 40a-40f, respectively.

[0044] Some of the unit capacitors 40a-40f may be selectively connected so that decoupling capacitors C1-C3 having various capacitances may be constructed or formed. For example, the first decoupling pad 41a of the first unit capacitor 40a may be electrically connected to the first power interconnect 71a. The second decoupling pad 42a of the first unit capacitor 40a may be electrically connected to the ground interconnect 72. Therefore, the first unit capacitor 40a may constitute a first decoupling capacitor C1 having a unit capacitance.

[0045] The first decoupling pad 41b of the second unit capacitor 40b and the first decoupling pad 41c of the third unit capacitor 40c can be connected to the second power interconnect 71b in common. That is, the first decoupling pad 41b of the second unit capacitor 40b and the first decoupling pad 41c of the third unit capacitor 40c can be electrically connected to each other through the second power interconnect 71b. The second decoupling pad 42b of the second unit capacitor 40b and the second decoupling pad 42c of the third unit capacitor 40c can be connected to the ground interconnect 72 in common. Therefore, the second unit capacitor 40b and the third unit capacitor 40c can be connected in parallel between the second power interconnect 71b and the ground interconnect 72. Therefore, the second unit capacitor 40b and the third unit capacitor 40c can constitute a second decoupling capacitor C2 with twice the unit capacitance.

[0046] The first decoupling pad 41d of the fourth unit capacitor 40d to the first decoupling pad 41f of the sixth unit capacitor 40f may be connected in common to the third power interconnect 71c. That is, the first decoupling pad 41d of the fourth unit capacitor 40d to the first decoupling pad 41f of the sixth unit capacitor 40f may be electrically connected to each other through the third power interconnect 71c. The second decoupling pad 42d of the fourth unit capacitor 40d to the second decoupling pad 42f of the sixth unit capacitor 40f may be connected in common to the ground interconnect 72. Therefore, the fourth unit capacitor 40d to the sixth unit capacitor 40f may be connected in parallel between the third power interconnect 71c and the ground interconnect 72. Therefore, the fourth unit capacitor 40d to the sixth unit capacitor 40f may constitute a third decoupling capacitor C3 having a triple unit capacitance.

[0047] The decoupling capacitors C1 to C3 including one or more unit capacitors 40a-40f may have a capacitance equal to an integer multiple of the unit capacitance. In this embodiment, the decoupling device 40 is shown as having six unit capacitors 40a-40f for constituting three decoupling capacitors C1 to C3, but is not limited thereto. In various embodiments, the decoupling device 30 may include more than Figure 4 The unit capacitors 40a-40f shown are a larger number of unit capacitors. Therefore, a large number of decoupling capacitors with various capacitances can be constructed in various ways and included in one decoupling device 40.

[0048] Reference Figure 3 and Figure 4 , the first power pad 31a of the control device 30 and the first decoupling pad 41a of the first unit capacitor 40a of the decoupling device 40 can be electrically connected to each other through the first power interconnect 71a. The second power pad 31b of the control device 30 and the first decoupling pad 41b of the second unit capacitor 40b of the decoupling device 40 and the first decoupling pad 41c of the third unit capacitor 40c can be electrically connected to each other through the second power interconnect 71b. The third power pad 31c of the control device 30 and the first decoupling pad 41d of the fourth unit capacitor 40d to the first decoupling pad 41f of the sixth unit capacitor 40f of the decoupling device 40 can be electrically connected to each other through the third power interconnect 71c. The ground pads 32a-32c of the control device 30 and the second decoupling pad 42a of the first unit capacitor 40a to the second decoupling pad 42f of the sixth unit capacitor 40f of the decoupling device 40 can be electrically connected to each other through the ground interconnect 72. For example, all the ground pads 32a-32c of the control device 30 and the second decoupling pads 42a-42f of all the unit capacitors 40a-40f of the decoupling device 40 may be electrically connected to each other.

[0049] The first decoupling capacitor C1 may decouple the first voltage of the control device 30, the second decoupling capacitor C2 may decouple the second voltage of the control device 30, and the third decoupling capacitor C3 may decouple the third voltage of the control device 30. The decoupling device 40 according to one embodiment of the present disclosure may decouple various electric powers (e.g., voltages) of the control device 30. The first voltage to the third voltage may be different voltages from each other.

[0050] Figure 5 FIG. 4 is a top view schematically showing a wafer WF on which a plurality of unit capacitors 40U are formed according to an embodiment of the present disclosure. Figure 5 , a plurality of unit capacitors 40U may be integrated on a wafer WF through a semiconductor manufacturing process. The plurality of unit capacitors 40U may be separated from each other in the row direction and the column direction by scribe lanes SL. Figure 4 The unit capacitors 40a-40f shown may be some of the plurality of unit capacitors 40U. That is, the plurality of unit capacitors 40U may be manufactured by sawing or cutting the plurality of unit capacitors 40U into a single chip. Figure 4 A decoupling device 40 is shown. Figure 4 and Figure 5 , the decoupling device 40 can be manufactured by sawing or cutting a portion of the wafer WF along the scribe line SL so that six unit capacitors 40U constitute a single chip. In the present disclosure, it has been described that one decoupling device 40 includes six unit capacitors 40U, but as described above, it is not limited thereto. For example, one decoupling device 40 may include any number of unit capacitors 40U.

[0051] Fig. 6A and Figure 6B Along the Figure 5 The longitudinal cross-sectional view taken along the line II' of FIG. 1 schematically shows the structure of a unit capacitor 40U of the decoupling device 40 according to an embodiment of the present disclosure. Fig. 6A, a unit capacitor 40U according to one embodiment of the present disclosure may include a plurality of capacitor elements 90 formed in a base substrate 91, and a first terminal 95 and a second terminal 96 formed on the base substrate 91. The unit capacitor 40U may include a lower electrode 90a, a capacitor dielectric layer 90b, and an upper electrode 90c shared by or forming the capacitor element 90. The first terminal 95 may include a first electrode through hole 95v and a first electrode pad 95p. The second terminal 96 may include a second electrode through hole 96v and a second electrode pad 96p. In one embodiment, the second terminal 96 may also include an intermediate through hole 96v' and an intermediate pad 96p'. The unit capacitor 40U may also include a buffer insulating layer 92, an interlayer insulating layer 93, and a passivation layer 99. Further reference is made to Figure 2 and Figure 4 , the first terminal 95 and the second terminal 96 may correspond to the first decoupling pads 41 and 41a-41f and the second decoupling pads 42 and 42a-42f. "First" and "second" can be interchanged.

[0052] The base substrate 91 may include a semiconductor substrate such as a silicon wafer. In one embodiment, the base substrate 91 may include an insulating layer formed on the semiconductor substrate. The insulating layer may include a silicon oxide layer or a silicon nitride layer.

[0053] Each capacitor element 90 may be formed in a recess R formed in a base substrate 91. Specifically, a lower electrode 90a of each capacitor element 90 may be conformally formed on the inner wall and bottom surface of the recess R, the recess R vertically penetrates a buffer insulating layer 92 formed on the base substrate 91, and extends vertically downward in the base substrate 91. The lower electrode 90a may be formed to extend horizontally on the surface of the buffer insulating layer 92. The capacitor dielectric layer 90b may be conformally formed on the surface of the lower electrode 90a. The upper electrode 90c may be conformally formed on the surface of the capacitor dielectric layer 90b. The upper electrode 90c may completely fill the recess R. For example, in the recess R, the lower electrode 90a and the capacitor dielectric layer 90b may have a cylindrical shape, and the upper electrode 90c may have a columnar shape.

[0054] The lower electrode 90a and the upper electrode 90c may include a metal compound such as a metal silicide. For example, the lower electrode 90a and the upper electrode 90c may include one of titanium silicide (TiSi), tungsten silicide (WSi), nickel silicide (NiSi), cobalt silicide (CoSi) or other metal silicides. In one embodiment, the lower electrode 90a and the upper electrode 90c may include a metal. For example, the lower electrode 90a and the upper electrode 90c may include one of a metal such as tungsten (W), titanium (Ti), nickel (Ni), cobalt (Co) or copper (Cu). The capacitor dielectric layer 90b may include a single insulating layer or multiple insulating layers. For example, the capacitor dielectric layer 90b may include one of hafnium oxide (HfO2), aluminum oxide (Al2O3), silicon oxide (SiO2), silicon nitride (SiN), titanium oxide (TiO), zirconium oxide (ZrO) or other insulating materials.

[0055] The buffer insulating layer 92 may be formed on the base substrate 91 to separate and electrically insulate the upper portion of the lower electrode 90a from the base substrate 91. In addition, the buffer insulating layer 92 may be used as an etching mask for forming the recess R. The interlayer insulating layer 93 may surround the side surfaces of the lower electrode 90a, the capacitor dielectric layer 90b, and the upper electrode 90c located on the base substrate 91 and the buffer insulating layer 92. The interlayer insulating layer 93 may also surround the exposed portion of the lower electrode 90a and the side surfaces of the middle through hole 96v' and the middle pad 96p' of the second terminal 96. The passivation layer 99 may be formed on the surface of the upper electrode 90c and the upper surface of the interlayer insulating layer 93. The passivation layer 99 may surround the side surfaces of the first electrode through hole 95v and the second electrode through hole 96v, and expose the first electrode pad 95p and the second electrode pad 96p. The buffer insulating layer 92 and the interlayer insulating layer 93 may include at least one of a silicon oxide layer, a silicon nitride layer, or other silicon-based insulating material layers. The passivation layer 99 may include at least one of silicon nitride, aluminum oxide, or a polymer resin such as polyimide.

[0056] Reference Figure 6B , a unit capacitor 40U according to one embodiment of the present disclosure may include a plurality of capacitor elements 90 formed in a base substrate 91 , and a first terminal 95 and a second terminal 96 formed on the base substrate 91 . Fig. 6A Compared to the unit capacitor 40U shown in FIG. 1 , the second electrode through hole 96v of the second terminal 96 can be directly connected to the lower electrode 90a of the capacitor element 90. For example, the Fig. 6A The second electrode through hole 96v of the second terminal 96 may vertically penetrate the passivation layer 99 and the interlayer insulating layer 93.

[0057] The unit capacitor 40U according to one embodiment of the present disclosure includes a plurality of capacitor elements 90 having a columnar shape extending vertically in a base substrate 91, so that the unit capacitor 40U can have a high capacitance in a small footprint. Therefore, the size of the unit capacitor 40U can be smaller than that of a multilayered ceramic capacitor / condenser (MLCC). Specifically, since the vertical thickness of the unit capacitor 40U can be greatly reduced, the unit capacitor 40U can be more applied to mobile devices.

[0058] Fig. 7A is a side cross-sectional view showing a recess R of a unit capacitor 40U according to one embodiment of the present disclosure, and Figure 7B and Figure 7C 40U is a cross-sectional view or a plan view showing the recess R of the unit capacitor 40U. Fig. 7A and Figure 7B , the recesses R of the unit capacitor 40U may be periodically arranged to be spaced apart from each other at regular intervals in a two-dimensional array (e.g., in the row direction and the column direction). In a top view, the recess R may have a circular shape. In a side view, the recess R may have a hole shape extending from the surface of the base substrate 91 to the inside. Fig. 7A and Figure 7C In a top view, the recesses R may be arranged in a straight line shape or in a segment shape extending parallel to each other in one direction. In a side view, the recesses R may have a groove shape formed in the base substrate 91 .

[0059] Fig. 8A is a side cross-sectional view showing a lower electrode 90a of a unit capacitor 40U according to one embodiment of the present disclosure, and FIG. 8B to FIG. 8E 4 is a cross-sectional view or a plan view showing a lower electrode 90a of a unit capacitor 40U according to an embodiment of the present disclosure. A dotted line indicates a continuation of the illustrated pattern.

[0060] Reference Fig. 8A and Figure 8B, the lower electrode 90a of the unit capacitor 40U may include a lower electrode pattern 90a1 filling the recess R and a lower main connector 90a2 electrically connecting the lower electrode pattern 90a1. In a cross-sectional view or a plan view, the lower electrode pattern 90a1 may have a ring shape formed in the recess R. In a cross-sectional view or a plan view, the lower main connector 90a2 may have a segmented shape connecting the lower electrode pattern 90a1 in a row direction and a column direction. The row direction may be a first horizontal direction, and the column direction may be a second horizontal direction. The row direction and the column direction (i.e., the first horizontal direction and the second horizontal direction) may be perpendicular to each other. The lower main connector 90a2 may be arranged in a mesh shape. Further reference is made to Fig. 6A or Figure 6B , the lower main connector 90 a 2 may be formed on the buffer insulating layer 92 .

[0061] Reference Figure 8C , the lower electrode 90a of the unit capacitor 40U may include a lower electrode pattern 90a1, a lower main connector 90a2 and a lower sub-connector 90a3. The lower sub-connector 90a3 may have a segmented shape or a straight line shape electrically connected to the lower main connector 90a2 in the row direction and the column direction. The lower sub-connector 90a3 may be arranged in a mesh shape. The lower main connector 90a2 and the lower sub-connector 90a3 may form a mesh shape separately or together. The lower sub-connector 90a3 may be formed at the same level as the lower main connector 90a2. The lower sub-connector 90a3 may have a wider width than the lower main connector 90a2.

[0062] Reference Fig.8D , the lower electrode 90a of the unit capacitor 40U may include a lower electrode pattern 90a1 and a lower connector 90a4. The lower connector 90a4 may have a plate shape. That is, further referring to Fig. 6A , Figure 6B and Fig. 8A , the lower connector 90 a 4 may be integrally formed on the buffer insulating layer 92 .

[0063] Reference Fig. 8E , the lower electrode 90a of the unit capacitor 40U may include a lower electrode pattern 90a1 formed in a recess R having a groove shape and a lower connector 90a4 having a plate shape. That is, further referring to Figure 7C , the lower electrode pattern 90a1 may be formed in the recess R having a groove shape.

[0064] Fig.9A is a side cross-sectional view showing a capacitor dielectric layer 90b of a unit capacitor 40U according to one embodiment of the present disclosure, and FIG. 9B to FIG. 9D is a cross-sectional view or a plan view showing a capacitor dielectric layer 90b of a unit capacitor 40U according to an embodiment of the present disclosure. Fig.9A and Fig. 9B , the capacitor dielectric layer 90b of the unit capacitor 40U may have a dielectric pattern 90b1 formed on an inner wall of the lower electrode pattern 90a1 in the recess R. The dielectric pattern 90b1 may have a ring shape in a cross-sectional view or a plan view.

[0065] Reference Fig. 9C The capacitor dielectric layer 90b of the unit capacitor 40U may include a dielectric pattern 90b1 and a dielectric connection pattern 90b2. The dielectric connection pattern 90b2 may be integrally formed on Fig. 6A or Figure 6B The buffer insulating layer 92 and the lower electrode 90a are shown to physically connect the dielectric pattern 90b1. The dielectric connection pattern 90b2 may have a plate shape. Therefore, the dielectric pattern 90b1 may be physically connected and integrated into one body.

[0066] Reference Fig.9D , the capacitor dielectric layer 90b of the unit capacitor 40U may include a dielectric pattern 90b1 and a dielectric connection pattern 90b2 formed on the inner wall of the lower electrode pattern 90a1 formed in the groove-shaped recess R. Further referring to Fig. 6A , 6B and FIG. 8B to FIG. 8E , the dielectric connection pattern 90b2 may be integrally formed on the lower main connector 90a2, the lower connector 90a4, and the lower sub-connector 90a3 of the lower electrode 90a.

[0067] Fig. 10A is a side cross-sectional view showing an upper electrode 90c of a unit capacitor 40U according to one embodiment of the present disclosure, and FIG. 10B to FIG. 10E is a cross-sectional view or a plan view showing an upper electrode 90c of a unit capacitor 40U according to an embodiment of the present disclosure. Fig. 10A and Fig. 10B , the upper electrode 90c of the unit capacitor 40U may include an upper electrode pattern 90c1 filling the inside of the dielectric pattern 90b1 in the recess R and an upper main connector 90c2 electrically connecting the upper electrode pattern 90c1. In a cross-sectional view or a plan view, the upper electrode pattern 90c1 may have a circular shape formed in the dielectric pattern 90b1 in the recess R. In a cross-sectional view or a plan view, the upper main connector 90c2 may have a segmented shape or a mesh shape connecting the upper electrode pattern 90c1 in the row direction and the column direction. Further reference Fig. 6A and Figure 6B as well as 9A to 9D , the upper main connector 90c2 may be integrally formed on the dielectric pattern 90b1 and the dielectric connection pattern 90b2.

[0068] Reference Fig. 10C, the upper electrode 90c of the unit capacitor 40U may include an upper electrode pattern 90c1, an upper main connector 90c2, and an upper sub-connector 90c3. The upper sub-connector 90c3 may have a segmented shape or a straight line shape directly connected to the upper main connector 90c2 in the row direction and the column direction. The upper sub-connector 90c3 may be arranged in a mesh shape. The upper main connector 90c2 and the upper sub-connector 90c3 may be formed at the same level. The upper main connector 90c2 and the upper sub-connector 90c3 may form a mesh shape separately or together.

[0069] Reference Fig. 10D , the upper electrode 90c of the unit capacitor 40U may include an upper electrode pattern 90c1 and an upper connector 90a4. The upper connector 90a4 may have a plate shape. That is, further referring to Fig. 9B and Fig. 9C , the upper connector 90a4 may be integrally formed on the dielectric connection pattern 90b2 of the capacitor dielectric layer 90b.

[0070] Reference Fig.10E , the upper electrode 90c of the unit capacitor 40U may include an upper electrode pattern 90c1 formed in a groove-shaped recess R and an upper connector 90c4 in a plate shape. That is, further referring to Figure 7C , the upper electrode pattern 90c1 may be formed in the groove-shaped recess R. Further referring to Fig.9D , the upper electrode pattern 90c1 may be formed on the inner wall of the dielectric pattern 90b1 in the recess R, and the upper connector 90c4 may be formed on the dielectric connection pattern 90b2.

[0071] Fig.11 is a layout diagram or a top view showing the first electrode through hole 95v and the first electrode pad 95p of the first terminal 95 and the second electrode through hole 96v and the second electrode pad 96p of the second terminal 96 of the unit capacitor 40U according to one embodiment of the present disclosure. Fig.11 , the first electrode through hole 95v and the first electrode pad 95p of the first terminal 95 of the unit capacitor 40U may vertically overlap.

[0072] Fig.12 2 is a schematic layout diagram showing a storage system 200 according to an embodiment of the present disclosure. Fig.12 The storage system 200 may include storage devices 20a and 20b, a control device 30, a decoupling device 40, a buffer memory 50, and a power supply device 60 disposed on a circuit substrate 10. The storage devices 20a and 20b may include a first storage device 20a and a second storage device 20b. Each of the first storage device 20a and the second storage device 20b may independently communicate with the control device 30. Further reference is made to Figure 1B, each of the first storage device 20a and the second storage device 20b may include a plurality of stacked NAND flash memory devices. For example, the controller 30 may temporarily store data in the buffer memory 50 before the data is input to the storage device 20, or temporarily store data output from the storage device 20. The power supply device 60 may include a power management integrated circuit (PMIC). The power supply device 60 may appropriately convert, distribute, and control various electric powers. Figure 1A and Figure 1B In this embodiment, the control device 30 and the decoupling device 40 may be electrically connected.

[0073] Fig.13 A block diagram showing an electronic system including a memory card 7800 is shown, and the memory card 7800 adopts at least one of the semiconductor packages according to the described embodiments. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages 100 and 101 according to the described embodiments.

[0074] The memory 7810 may include a nonvolatile memory device to which the technology of one embodiment of the present disclosure is applied. The memory controller 7820 may control the memory 7810 to read out stored data or store data in response to a read / write request from the host 7830 .

[0075] Fig.14 A block diagram showing an electronic system 8710 including at least one of the semiconductor packages 100 and 101 according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other through a bus 8715 that provides a path for data movement.

[0076] In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages 100 and 101 according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, and the like.

[0077] The memory 8713 may include a volatile memory device such as a DRAM device, and / or a non-volatile memory device such as a flash memory device. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state drive (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0078] The electronic system 8710 may further include an interface 8714 configured to send and receive data to and from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired transceiver or a wireless transceiver.

[0079] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0080] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), enhanced time division multiple access (E-TDMA), wideband code division multiple access (WCDMA), CDMA2000, long term evolution (LTE), or wireless broadband Internet (Wibro) technology.

[0081] According to an embodiment of the present disclosure, a memory system may include a decoupling capacitor having a thinner vertical thickness than a multilayer ceramic capacitor / capacitor (MLCC), and thus, the memory system may be miniaturized and thinned to be suitable for a mobile device.

[0082] Although the present disclosure contains many details, these details should not be interpreted as limitations on the scope of the present teachings or the scope of the content claimed, but should be interpreted as descriptions of features that may be specific to a particular embodiment of the present teachings. Certain features described in the context of different embodiments in this patent document can also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features from the claimed combination can be deleted from the combination, and the claimed combination can involve a sub-combination or a variation of a sub-combination.

[0083] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed to obtain the desired results. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments. Only a few embodiments and examples are described. Based on what is described and shown in this patent document, other embodiments, enhancements, and variations can be derived.

[0084] CROSS-REFERENCE TO RELATED APPLICATIONS

[0085] This application claims priority to Korean Patent Application No. 10-2020-0104581, filed on August 20, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A storage system, comprising a storage device, a control device and a decoupling device arranged on a circuit substrate, wherein: The storage device is configured to receive and store data from the control device; The control device is configured to generate an internal voltage; The decoupling device is connected to the control device and decouples the internal voltage; The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors; Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal; and Some of the unit capacitors are selectively connected to each other to constitute the decoupling capacitors having various capacitances.

2. The storage system according to claim 1, wherein: The capacitor element includes a lower electrode formed in a recess formed in a base substrate, a capacitor dielectric layer, and an upper electrode; The first terminal is connected to the upper electrode; and The second terminal is connected to the lower electrode.

3. The storage system according to claim 2, wherein: The recesses have a hole shape extending from the surface to the inside of the base substrate, and are periodically arranged to be spaced apart from each other.

4. The storage system according to claim 2, wherein: The lower electrode comprises: a lower electrode pattern formed on an inner wall of the recess; and A lower connector is formed on the buffer insulating layer on the base substrate to horizontally extend and electrically connect the lower electrode patterns.

5. The storage system according to claim 4, wherein: The lower connector comprises: a lower main connector electrically connected to the lower electrode pattern; and A lower sub-connector is electrically connected to the lower main connector.

6. The storage system according to claim 5, wherein: The lower main connector and the lower sub-connector are both formed in a mesh shape.

7. The storage system according to claim 4, wherein: The capacitor dielectric layer includes a dielectric pattern formed on an inner wall of the lower electrode pattern in the recess.

8. The storage system according to claim 7, wherein: The upper electrode comprises: an upper electrode pattern formed on an inner wall of the dielectric pattern to fill the recess; and An upper connector is formed on the buffer insulating layer on the base substrate to horizontally extend and electrically connect the upper electrode patterns.

9. The storage system according to claim 8, wherein: The upper connector comprises: an upper main connector, the upper main connector being directly electrically connected to the upper electrode pattern; and An upper sub-connector, the upper sub-connector is directly and electrically connected to the upper main connector.

10. The storage system according to claim 9, wherein: The first terminal includes an electrode through hole and an electrode pad, The electrode through hole vertically overlaps the upper connector, and The electrode through-hole vertically extends to electrically connect the upper connector to the electrode pad.

11. A storage system, comprising a storage device, a control device and a decoupling device arranged on a circuit substrate, in, The control device comprises: a first power pad, a second power pad, a ground pad and an internal voltage pad for providing some voltages generated in the control device to the storage device; external input / output pads for communicating with an external system; and an internal input / output pad, the internal input / output pad being used to communicate with the storage device, wherein: The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors; Each of the unit capacitors includes a first electrode pad and a second electrode pad; The first power supply pad of the control device is electrically connected to the first electrode pad of one of the unit capacitors; The second power supply pad of the control device is electrically connected to the first electrode pads of the two unit capacitors; The ground pad of the control device is commonly electrically connected to the second electrode pad of the unit capacitor; Each of the unit capacitors includes a capacitor element formed in a recess formed in a base substrate, and a lower electrode, a capacitor dielectric layer, an upper electrode, a first terminal connected to the upper electrode, and a second terminal connected to the lower electrode shared by the capacitor elements; and Some of the unit capacitors are selectively connected to each other to constitute the decoupling capacitors having various capacitances.

12. The storage system according to claim 11, wherein: The control device also includes a third power supply pad; The third power supply pad is electrically connected to the first electrode pad of at least one of the unit capacitors of the decoupling capacitor; and The third power supply pad is disposed adjacent to one of the external input / output pads.

13. The storage system according to claim 11, wherein: Each of the unit capacitors has a unit capacitance; and The capacitance of the decoupling capacitor is equal to an integral multiple of the unit capacitance.

14. The storage system according to claim 11, wherein: One of the first power pad and the second power pad is electrically connected to the memory device.

15. A storage system, comprising: Storage device; a control device, the control device being electrically connected to the storage device; as well as A decoupling device, the decoupling device being electrically connected to a power pad and a ground pad of the control device, wherein the decoupling device comprises a plurality of unit capacitors, wherein each of the unit capacitors comprises: a buffer insulating layer formed on a base substrate; a recessed portion vertically penetrating the buffer insulating layer to extend into the base substrate, wherein the recessed portions are arranged to be spaced apart from each other, and wherein the recessed portion is formed in a hole shape; a lower electrode including a lower electrode pattern formed on an inner wall and a bottom of the recess, and including a lower main connector formed on an upper surface of the buffer insulating layer to be electrically connected to the lower electrode pattern; a capacitor dielectric layer including a dielectric pattern formed on the lower electrode pattern formed in the recess, and including a dielectric connection pattern formed on the lower main connector to be physically connected to the dielectric pattern; an upper electrode including an upper electrode pattern formed on the dielectric pattern in the recess to fill the recess, and including an upper main connector formed on the dielectric connection pattern to be horizontally connected to the upper electrode pattern; and A passivation layer is located on the upper electrode.

16. The storage system according to claim 15, wherein: Each of the unit capacitors comprises: a first terminal including a first electrode pad formed on the passivation layer and including a first electrode through hole vertically overlapping the first electrode pad to connect the upper electrode to the first electrode pad; and A second terminal includes a second electrode pad formed on the passivation layer and includes a second electrode through hole vertically overlapping the second electrode pad.

17. The storage system according to claim 16, wherein: The first terminal is electrically connected to one of the power supply pads of the control device; and The second terminal is electrically connected to one of the ground pads of the control device.

18. The storage system according to claim 15, wherein: The lower electrode pattern has a ring shape formed in the recess; The lower main connector has a mesh shape; the dielectric pattern having a ring shape in the lower electrode pattern in the recess; The upper electrode has a circular shape filling the inside of the dielectric pattern in the recess; and The upper main connector has a mesh shape.

19. The storage system according to claim 15, wherein: Each of the unit capacitors comprises: a lower sub-connector electrically connected to the lower main connector; and an upper sub-connector, the upper sub-connector being electrically connected to the upper main connector, wherein the lower sub-connector and the lower main connector together form a lower mesh shape, Wherein, the upper sub-connector and the upper main connector together form an upper mesh shape.

20. The storage system of claim 16, wherein: The second terminal includes a middle through hole and a middle pad located between the lower electrode and the second electrode through hole; The middle through hole electrically connects the lower electrode to the middle pad; The middle pad electrically connects the middle via to the second electrode via; and The second electrode through hole electrically connects the intermediate pad to the second electrode pad.

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