Semiconductor devices and methods

Abstract

The present disclosure relates to semiconductor devices and methods. Disclosed are semiconductor devices having improved gate electrode structures and methods of forming the same. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer, an n-type work function layer over the high-k dielectric layer, a reactive-resistant layer over the n-type work function layer, the reactive-resistant layer including a dielectric material, a p-type work function layer over the reactive-resistant layer, the p-type work function layer covering a top surface of the reactive-resistant layer, and a conductive capping layer over the p-type work function layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material onto a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing minimum feature sizes, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a gate structure located on a semiconductor substrate, the gate structure comprising: a high-k dielectric layer; an n-type work function layer located on the high-k dielectric layer; an anti-reaction layer located on the n-type work function layer, the anti-reaction layer comprising a dielectric material; a p-type work function layer located on the anti-reaction layer, the p-type work function layer covering a top surface of the anti-reaction layer; and a conductive cap layer located on the p-type work function layer.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first channel region located in an n-type region; a second channel region located in a p-type region; a first gate stack located above the first channel region, the first gate stack comprising: a first gate dielectric layer located above the first channel region; an n-type metal layer located above and in contact with the first gate dielectric layer, the n-type metal layer comprising aluminum; a dielectric layer located above the n-type metal layer; a first p-type metal layer located above the n-type metal layer and the dielectric layer; and a first metal cap layer located above the first p-type metal layer; and a second gate stack located above the second channel region, the second gate stack comprising: a second gate dielectric layer located above the second channel region; a second p-type metal layer located above and in contact with the second gate dielectric layer; and a second metal cap layer located above the second p-type metal layer.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a gate stack on a semiconductor substrate, wherein forming the gate stack comprises: depositing an n-type work function layer on the semiconductor substrate; depositing a dielectric layer on the n-type work function layer; forming a first mask layer on the dielectric layer; etching back the n-type work function layer and the dielectric layer; depositing a p-type work function layer on the n-type work function layer and the dielectric layer; and selectively depositing a metal cap layer on the p-type work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field effect transistor (nanoFET) is shown in a three-dimensional view in accordance with some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 12E 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 20C 、 Figure 20D 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 22A 、 Figure 22B 、 Figure 22C 、 Figure 22D 、 Figure 22E 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 23D 、 Figure 23E 、 Figure 23F 、 Figure 23G 、 Figure 23H 、 Figure 24A 、 Figure 24B 、 Figure 25A 、 Figure 25B 、 Figure 26A and Figure 26B is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET, according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0012] Various embodiments provide a method for forming an improved gate electrode for a semiconductor device and a semiconductor device formed by the method. The method includes removing a sacrificial gate stack to form an opening, depositing a gate dielectric layer in the opening, depositing an n-type work function layer on the gate dielectric layer, and depositing an anti-reaction layer on the n-type work function layer. A photoresist material, such as a bottom anti-reflective coating (BARC) material, is deposited on the anti-reaction layer, etched back, and used as a mask for etching back the anti-reaction layer and the n-type work function layer. The BARC material is removed and a p-type work function layer is deposited on the n-type work function layer, the anti-reaction layer, and the gate dielectric layer. The p-type work function layer is etched back, and a metal cap layer is selectively deposited on the p-type work function layer. The anti-reaction layer can be included in the n-type gate electrode to provide a threshold voltage (Vt) boost. The anti-reaction layer can hinder the selective deposition of the metal cap layer. The p-type work function layer is deposited on the anti-reaction layer to allow the metal cap layer to be selectively deposited thereon. The metal cap layer is included to reduce gate resistance. Including an anti-reactive layer and a metal capping layer improves device performance.

[0013] Some embodiments discussed herein are described in the context of dies including nanoFETs. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, etc.) in place of or in combination with nanoFETs.

[0014] Figure 1 An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) in a three-dimensional view according to some embodiments is shown. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) located above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as the channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. Shallow trench isolation (STI) regions 68 are provided between adjacent fins 66, and the fins 66 may protrude from between adjacent STI regions 68 above adjacent STI regions 68. Although the STI regions 68 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer to only the semiconductor substrate or a combination of a semiconductor substrate and an STI region. In addition, although the bottom portion of the fin 66 is illustrated as a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to the portion extending between adjacent STI regions 68.

[0015] Gate dielectric layer 101 extends along the top and side surfaces of fin 66 and the top, side, and bottom surfaces of nanostructure 55. Gate electrode 103 is located over gate dielectric layer 101. Epitaxial source / drain regions 92 are disposed on fin 66 on opposite sides of gate dielectric layer 101 and gate electrode 103.

[0016] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 103 and is oriented, for example, perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanoFETs. Cross section BB' is parallel to cross section AA' and extends through epitaxial source / drain regions 92 of multiple nanoFETs. Cross section CC' is perpendicular to cross section AA' and parallel to the longitudinal axis of fins 66 of the nanoFETs and is oriented, for example, in the direction of current flow between epitaxial source / drain regions 92 of the nanoFETs. For clarity, subsequent figures refer to these reference cross sections.

[0017] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate use in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0018] Figures 2 to 26B is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET, according to some embodiments. Figures 2 to 5 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 20C 、 Figure 21A 、 Figure 21C 、 Figure 22A 、 Figure 22C 、 Figure 23A 、 Figure 23C 、 Figure 24A 、 Figure 25A and Figure 26A Shown Figure 1 Reference section AA' shown in . Figure 6B 、 Figure 7B、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 11C 、 Figure 12B 、 Figure 12E 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 20B 、 Figure 20D 、 Figure 21B 、 Figure 21D 、 Figure 22B 、 Figure 22D 、 Figure 22E 、 Figure 23B 、 Figure 23D 、 Figure 23E 、 Figure 23F 、 Figure 23G 、 Figure 23H 、 Figure 24B 、 Figure 25B and Figure 26B Shown Figure 1 Reference section BB' shown in . Figure 6C 、 Figure 7C 、 Figure 8C 、 Figure 9C 、 Figure 12C and Figure 12D Shown Figure 1 Reference section CC' shown in .

[0019] exist Figure 2 In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0020] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] Further in Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For the purpose of illustration and as discussed in more detail below, the first semiconductor layers 51 will be removed and the second semiconductor layers 53 will be patterned to form the channel regions of the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 can be removed and the second semiconductor layer 53 can be patterned to form the channel regions of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form the channel regions of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a nanoFET channel region in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a nanoFET channel region in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a nanoFET channel region in both the n-type region 50N and the p-type region 50P.

[0022] For illustrative purposes, the multilayer stack 64 is shown as including three layers each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material (e.g., silicon germanium, etc.), and the second semiconductor layer 53 may be formed of a second semiconductor material (e.g., silicon, silicon carbon, etc.). For illustrative purposes, the multilayer stack 64 is shown as having a bottommost semiconductor layer formed of a first semiconductor material. In some embodiments, the multilayer stack 64 may be formed such that the bottommost layer is formed of a second semiconductor material.

[0023] The first semiconductor material and the second semiconductor material can be materials with high etching selectivity relative to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment in which the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0024] According to some embodiments, Figure 3 In the embodiment of the present invention, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and define second nanostructures 54A-54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructures 55.

[0025] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, a smaller pitch than would otherwise be obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0026] Figure 3 Fins 66 in n-type region 50N and p-type region 50P are shown as having substantially equal widths for illustrative purposes. In some embodiments, the width of fins 66 in n-type region 50N can be greater or less than the width of fins 66 in p-type region 50P. Furthermore, while each of fins 66 and nanostructures 55 is shown as having a uniform width, in other embodiments, fins 66 and / or nanostructures 55 can have tapered sidewalls such that the width of fins 66 and / or nanostructures 55 continuously increases in a direction toward substrate 50. In such embodiments, each nanostructure 55 can have a different width and be trapezoidal in shape.

[0027] exist Figure 4 , a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins in the fin 66. The insulating material can be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can first be formed along the surface of the substrate 50, the fin 66, and the nanostructure 55. Thereafter, a filler material, such as those discussed above, can be formed over the liner.

[0028] A removal process is then applied to the insulating material to remove excess insulating material on the nanostructures 55. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the nanostructures 55 so that the top surfaces of the nanostructures 55 and the insulating material are flush after the planarization process is completed.

[0029] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 and the nanostructures 55 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 can have a flat surface as shown, a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surface of the STI region 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, such as an etching process that is selective for the material of the insulating material (e.g., an etching process that etches the material of the insulating material at a faster rate than the material of the fins 66 and the nanostructures 55). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) can be used.

[0030] The above about Figures 2 to 4 The process described is only one example of how the fins 66 and nanostructures 55 may be formed. In some embodiments, the fins 66 and / or nanostructures 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and / or subsequent implantation, but in situ and implantation doping may be used together.

[0031] Additionally, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructures 52) and the second semiconductor layer 53 (and the resulting second nanostructures 54) are illustrated and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. In some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0032] Further in Figure 4In the embodiment having different well types, the different implantation steps of the n-type region 50N and the p-type region 50P can be implemented using a photoresist or other mask (not shown separately). For example, a photoresist can be formed over the fins 66 and the STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., and the concentration of the n-type impurity implanted in the region ranges from about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0033] After or before the implantation of the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., and the concentration of the p-type impurity implanted in this region is from about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0034] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growing material of the epitaxial fin may be doped in situ during growth, which may avoid implantation, but in situ and implantation doping may be used together.

[0035] exist Figure 5, a dummy dielectric layer 70 is formed on the fins 66 and / or nanostructures 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited over the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. Dummy gate layer 72 can be made of other materials that have high etch selectivity relative to etching of the isolation regions. Mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across n-type region 50N and p-type region 50P. Note that dummy dielectric layer 70 is shown as covering only fin 66 and nanostructure 55 for illustrative purposes only. In some embodiments, dummy dielectric layer 70 can be deposited such that dummy dielectric layer 70 covers STI region 68, such that dummy dielectric layer 70 extends between dummy gate layer 72 and STI region 68.

[0036] Figures 6A to 26B Various additional steps in fabricating example devices are shown. Figures 6A to 26B Features in the n-type region 50N or the p-type region 50P are shown. Figures 6A to 6C In the embodiment, the mask layer 74 (see Figure 5 ) is patterned to form mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectric 71, respectively. Dummy gates 76 cover the respective channel regions of fins 66 and the portion of second nanostructure 54 where the channel region is formed. The pattern of mask 78 can be used to separate each dummy gate 76 from adjacent dummy gates 76. The longitudinal direction of dummy gates 76 can be perpendicular to the longitudinal direction of each fin in fin 66.

[0037] exist 7A to 7C in Figures 6A to 6C A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. The first spacer layer 80 and the second spacer layer 82 will be patterned later to act as spacers for forming self-aligned source / drain regions. 7A to 7CIn the embodiment of the present invention, a first spacer layer 80 is formed on: the top surface of the STI region 68; the side surfaces of the fin 66, the dummy gate dielectric 71, and the dummy gate 76; and the top and side surfaces of the nanostructure 55 and the mask 78. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a deposition technique such as thermal oxidation or by CVD, ALD, etc. The second spacer layer 82 can be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc. The first spacer layer 80 and the second spacer layer 82 may include a low-k dielectric material.

[0038] After forming the first spacer layer 80 and before forming the second spacer layer 82, implantation for lightly doped source / drain (LDD) regions (not separately shown) may be performed. In embodiments with different device types, similar to the above, Figure 4 As discussed above, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurities may be implanted into the exposed fins 66 and the exposed nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurities may be implanted into the exposed fins 66 and the exposed nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed above, and the p-type impurity may be any of the p-type impurities discussed above. The lightly doped source / drain regions may have a density ranging from about 1x10 15 atoms / cm 3 to about 1x10 19 atoms / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0039] exist Figures 8A to 8C, the first spacer layer 80 and the second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83, respectively. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can act as an etch stop layer when patterning the second spacer layer 82. The second spacer layer 82 can act as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer. The remaining portion of the second spacer layer 82 forms a second spacer 83, such as Figure 8B and Figure 8C The second spacer 83 then acts as a mask while etching the exposed portion of the first spacer layer 80 to form the first spacer 81, as shown. Figure 8B and Figure 8C shown.

[0040] like Figure 8B As shown, first spacers 81 and second spacers 83 are disposed on sidewalls of mask 78, dummy gate 76, and dummy gate dielectric 71. In some embodiments, top surfaces of first spacers 81 and second spacers 83 may be disposed below the top surface of mask 78. Top surfaces of first spacers 81 and second spacers 83 may be disposed flush with or above the top surface of mask 78. In some embodiments, second spacers 83 may be removed from above first spacers 81 adjacent to mask 78, dummy gate 76, and dummy gate dielectric 71. Figure 8C As shown, first spacers 81 and second spacers 83 are disposed on sidewalls of the fins 66 and / or the nanostructures 55 .

[0041] Note that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, and so on. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0042] exist Figures 9A to 9CIn the embodiment of the present invention, a first recess 87 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will subsequently be formed in the first recess 87. The first recess 87 can extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. In some embodiments, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 87. In some embodiments, the top surface of the STI region 68 can be above or below the bottom surface of the first recess 87. The first recess 87 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process (e.g., RIE, NBE, etc.). The first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, the nanostructure 55, and the substrate 50 during the etching process used to form the first recess 87. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55 and / or the fin 66. A timed etching process can be used to stop etching after the first recess 87 reaches a desired depth.

[0043] exist Figure 10A and Figure 10B In FIG. 8 , the sidewall portions of the layers of the multilayer stack 64 formed of the first semiconductor material (eg, the first nanostructure 52 ) exposed by the first recess 87 are etched to form sidewall recesses 88 . Figure 10B The sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are shown as straight, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process (e.g., wet etching, etc.). In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 may be etched using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0044] exist Figures 11A to 11C In the embodiment, the first inner spacer 90 is formed in the side wall groove 88. Figure 10A and Figure 10B An internal spacer layer (not separately shown) is deposited over the structure shown to form a first internal spacer 90. The first internal spacer 90 acts as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. As will be discussed in detail below, the source / drain regions will be formed in the first recess 87, and the first nanostructure 52 will be replaced by the gate structure.

[0045] The inner spacer layer can be deposited by a conformal deposition process (e.g., CVD, ALD, etc.). The inner spacer layer can include a material such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer can then be anisotropically etched to form the first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are illustrated as being flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 can extend beyond or be recessed from the sidewalls of the second nanostructure 54.

[0046] Furthermore, although the outer sidewall of the first inner partition 90 is Figure 11B , but the outer sidewall of the first inner spacer 90 may be concave or convex. As an example, Figure 11C An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. The inner spacer layer can be etched by an anisotropic etching process (e.g., RIE, NBE, etc.). The first inner spacer 90 can be used to prevent the subsequent source / drain regions (e.g., as described below with respect to the source / drain region) formed by a subsequent etching process (e.g., an etching process for forming a gate structure) from being etched. 12A to 12E The epitaxial source / drain regions 92 discussed above may cause damage.

[0047] exist 12A to 12E In the embodiment, epitaxial source / drain regions 92 are formed in the first recesses 87. In some embodiments, the epitaxial source / drain regions 92 can apply strain to the second nanostructure 54, thereby improving performance. Figure 12B As shown, epitaxial source / drain regions 92 are formed in first recesses 87 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 and second spacers 83 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and first inner spacers 90 are used to separate epitaxial source / drain regions 92 from first nanostructures 52 by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed resulting nanoFET.

[0048] The epitaxial source / drain regions 92 in the n-type region 50N (e.g., an NMOS region) can be formed by masking the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first recess 87 of the n-type region 50N. The epitaxial source / drain regions 92 can include any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 92 can have surfaces that are raised from the corresponding upper surfaces of the nanostructure 55 and can have small facets.

[0049] The epitaxial source / drain regions 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first recess 87 of the p-type region 50P. The epitaxial source / drain regions 92 can include any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can include a material that applies compressive strain to the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 92 can also have surfaces that protrude from the corresponding upper surfaces of the nanostructure 55 and can have small facets.

[0050] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a density of about 1x10 19 atoms / cm 3 to about 1x10 21 atoms / cm 3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0051] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, the facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, e.g., Figure 12C In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown in FIG. Figure 12DAs shown. Figure 12C and Figure 12D In the embodiment shown, first spacers 81 can be formed above the top surface of STI regions 68 and can prevent epitaxial growth. In some embodiments, first spacers 81 can cover portions of the sidewalls of nanostructures 55, further preventing epitaxial growth. In some embodiments, the spacer etch used to form first spacers 81 can be tuned to remove spacer material to allow epitaxial source / drain regions 92 to extend to the top surface of STI regions 68.

[0052] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0053] Figure 12E An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave and the outer sidewalls of the first inner spacer 90 are concave. The first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. Figure 12E As shown, epitaxial source / drain regions 92 can be formed in contact with the first inner spacer 90. The epitaxial source / drain regions can extend beyond the sidewalls of the second nanostructure 54.

[0054] exist Figure 13A and Figure 13B In the first interlayer dielectric (ILD) 96 is deposited on Figure 12A and Figure 12B. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacers 81. The CESL 94 may include a dielectric material having a different etch rate than the material overlying the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0055] exist Figure 14A and Figure 14B During the planarization process, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation range. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 can remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0056] In addition, Figure 14A and Figure 14B In the embodiment, the first ILD 96 and the CESL 94 are etched back and a protective layer 97 is formed over the first ILD 96 and the CESL 94. The first ILD 96 and the CESL 94 can be etched back using an anisotropic etching process (e.g., RIE, NBE, etc.) or an isotropic etching process (e.g., a wet etching process). The protective layer 97 can then be deposited over the resulting structure using CVD, PECVD, ALD, sputtering, etc., and planarized using a process such as CMP. Figure 14A and Figure 14BAs shown, after planarization of the protective layer 97, the top surface of the protective layer 97 may be flush with the top surfaces of the first spacer 81, the second spacer 83, and the dummy gate 76. The protective layer 97 may be formed of a material such as silicon nitride, silicon oxide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, a combination thereof, or a multilayer thereof. The protective layer 97 may be formed over the first ILD 96 and the CESL 94 to protect the first ILD 96 and the CESL 94 from subsequent etching processes.

[0057] exist Figure 15A and Figure 15B In one or more etching steps, dummy gate 76 and mask 78 (if present) are removed, thereby forming second recesses 98. Portions of dummy gate dielectric 71 in second recesses 98 are also removed. In some embodiments, dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etches dummy gate 76 at a faster rate than protective layer 97, first spacer 81, second spacer 83, nanostructures 55, or STI regions 68. Each of second recesses 98 exposes and / or covers portions of nanostructures 55, which subsequently serve as channel regions in the completed nanoFET. The portions of nanostructures 55 that serve as channel regions are positioned between adjacent pairs of epitaxial source / drain regions 92. During removal, dummy gate dielectric 71 can serve as an etch stop when etching dummy gate 76. Dummy gate dielectric 71 can then be removed after dummy gate 76 is removed.

[0058] exist Figure 16A and Figure 16B , first nanostructure 52 is removed, thereby extending second recess 98. First nanostructure 52 can be removed by performing an isotropic etching process (e.g., wet etching, etc.) using an etchant that is selective to the material of first nanostructure 52, while second nanostructure 54, substrate 50, and STI region 68 remain relatively unetched compared to first nanostructure 52. In embodiments where first nanostructure 52 comprises, for example, SiGe and second nanostructures 54A-54C comprise, for example, Si or SiC, first nanostructure 52 can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0059] exist 17A to 23HIn the embodiment of the present invention, a gate dielectric layer and a gate electrode for replacing the gate are formed in the second groove 98. The gate electrode formed in the n-type region 50N includes an anti-reaction layer that provides a threshold voltage (Vt) boost. An n-type work function layer is formed on the anti-reaction layer, and a p-type work function layer is formed on the anti-reaction layer and the n-type work function layer, the p-type work function layer covering the anti-reaction layer and the n-type work function layer. A metal cap layer is then formed on the p-type work function layer. The formation of a p-type work function layer covering the anti-reaction layer allows the metal cap layer to be selectively deposited. The metal cap layer reduces the gate resistance. Therefore, the device performance can be improved.

[0060] The formation of the gate dielectric layer in the n-type region 50N and the p-type region 50P can occur simultaneously, so that the gate dielectric in each region is formed of the same material. The formation of the gate electrode can occur simultaneously, so that the gate electrode in each region is formed of the same material. In some embodiments, the gate dielectric layer in each region can be formed by different processes, so that the gate dielectric layer can be a different material and / or can have a different number of layers. The gate electrode in each region can be formed by different processes, so that the gate electrode can be a different material and / or have a different number of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas. In the following description, at least portions of the gate electrode of the n-type region 50N and the gate electrode of the p-type region 50P are formed separately.

[0061] exist Figure 17A and Figure 17B , a gate dielectric layer 100 is conformally deposited in the second recess 98 in the n-type region 50N and the p-type region 50P. The gate dielectric layer 100 may be formed on the top and side surfaces of the fin 66 and the top, side, and bottom surfaces of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on: the top surfaces of the protective layer 97, the second spacer 83, and the STI region 68; the top and side surfaces of the first spacer 81; and the side surfaces of the first inner spacer 90. The gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. In some embodiments, the gate dielectric layer 100 may include a first gate dielectric layer (e.g., including silicon oxide, etc.) and a second gate dielectric layer (e.g., including metal oxide, etc.) located above the first gate dielectric layer. In some embodiments, the second gate dielectric layer includes a high-k dielectric material. In these embodiments, the second gate dielectric layer can have a k value greater than about 7.0 and can include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In some embodiments, the first gate dielectric layer can be referred to as an interfacial layer, and the second gate dielectric layer can be referred to as a high-k gate dielectric layer.

[0062] The structure of the gate dielectric layer 100 can be the same or different in the n-type region 50N and the p-type region 50P. For example, the p-type region 50P can be masked or exposed while the gate dielectric layer 100 is formed in the n-type region 50N. In embodiments where the p-type region 50P is exposed, the gate dielectric layer 100 can be simultaneously formed in the p-type region 50P. The gate dielectric layer 100 can be formed by methods such as molecular beam deposition (MBD), ALD, CVD, and PVD.

[0063] exist Figure 18A and Figure 18B In the embodiment of the present invention, a first conductive material 102 is conformally deposited over the gate dielectric layer 100 in the n-type region 50N. While the first conductive material 102 is deposited in the n-type region 50N, the p-type region 50P may be masked. In some embodiments, the first conductive material 102 is an n-type work function layer and may include AlCu, TiAlC, TiAlN, TiAl, Al, TaAl, TaAlC, Ti, Al, Mg, Zn, other suitable n-type work function materials, combinations thereof, or the like. In some embodiments, the first conductive material 102 may include an aluminum-based material. The first conductive material 102 may be deposited by ALD, CVD, PVD, or the like. The first conductive material 102 may be deposited to a thickness ranging from approximately 1 nm to approximately 4 nm.

[0064] In some embodiments, before depositing the anti-reactive layer 104, an intermediate layer (not separately shown) may be formed on the first conductive material 102. The intermediate layer may include a barrier layer, a diffusion layer, an adhesion layer, a combination thereof, or multiple layers. In some embodiments, the intermediate layer may include a material containing chlorine (Cl), etc. The intermediate layer may be deposited by ALD, CVD, PVD, etc.

[0065] In addition, Figure 18A and Figure 18B In the embodiment, the anti-reaction layer 104 is conformally deposited on the first conductive material 102 in the n-type region 50N. While the anti-reaction layer 104 is deposited in the n-type region 50N, the p-type region 50P may be masked. The anti-reaction layer 104 may protect the first conductive material 102 from oxidation. The anti-reaction layer 104 may be formed of a material different from the material of the first conductive material 102. In some embodiments, the anti-reaction layer 104 may include a dielectric material. In some embodiments, the anti-reaction layer 104 may include a silicon-based material. In some embodiments, the anti-reaction layer 104 may include silicon (Si), silicon oxide (SiO x), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiC), combinations thereof or multilayers thereof, etc. However, any suitable material may be used. The anti-reaction layer 104 may be formed by using a deposition process such as ALD, CVD, PVD, etc. The anti-reaction layer 104 may be deposited to a thickness in a range from about 0.3 nm to about 5 nm. The thickness of the anti-reaction layer 104 may be between 10% and 50% of the thickness of the first conductive material 102. This ratio allows for space saving while still effectively preventing or reducing oxidation of the first conductive material 102.

[0066] In some embodiments, the anti-reactive layer 104 can be formed in situ after forming the first conductive material 102 without moving the intermediately formed device. Thus, the anti-reactive layer 104 can be formed on the first conductive material 102 without breaking the vacuum of the deposition tool or apparatus (e.g., a process chamber). In some embodiments, the intermediately formed device can be moved to another process chamber within the same tool without breaking the vacuum. Since the vacuum is maintained, oxidation of the first conductive material 102 can be eliminated or significantly reduced.

[0067] The inclusion of the anti-reactive layer 104 provides a threshold voltage boost for the gate electrode in the n-type region 50N, allowing the threshold voltage to be appropriately adjusted for the thinner thickness of the first conductive material 102. This allows for more space for depositing the subsequently formed metal fill. For example, in some embodiments, the combined thickness of the first conductive material 102 and the thickness of the anti-reactive layer 104 can be between 50% and 80% of the thickness of the first conductive material that would exhibit the same or similar threshold voltage without the anti-reactive layer 104.

[0068] exist Figure 19A and Figure 19B In the embodiment, a first mask layer 106 is formed in the second groove 98 above the anti-reactive layer 104. The first mask layer 106 can be deposited by spin coating or the like. The first mask layer 106 can include a polymer material, such as polymethyl acrylate, polymaleimide (poly(maleimide)), novolacs, polyethers (poly(ether)s), combinations thereof, etc. In some embodiments, the first mask layer 106 can be a bottom anti-reflective coating (BARC) material. Figure 19A and Figure 19B As shown, first mask layer 106 may fill portions of second recesses 98 that extend between vertically adjacent ones of second nanostructures 54 and between second nanostructures 54 and fins 66 .

[0069] After depositing the first mask layer 106, the first mask layer 106 can be etched back so that the top surface of the first mask layer 106 is lower than the top surface of the protective layer 97 and higher than the top surface of the second nanostructure 54. The first mask layer 106 can be etched using one or more etching processes, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), a combination thereof, or the like. The first mask layer 106 can be etched back using an etching process that is selective for the material of the first mask layer 106 (e.g., etches the material of the first mask layer 106 at a faster rate than the material of the anti-reactive layer 104). The top surface of the first mask layer 106 can be disposed above the top surface of the second nanostructure 54C by a distance D1 ranging from about 5 nm to about 20 nm. The top surfaces of the first spacers 81, the second spacers 83, and the protective layer 97 can be disposed above the top surface of the second nanostructure 54C by a distance D2 ranging from about 25 nm to about 120 nm. The ratio of the distance D1 to the distance D2 may be in the range of from about 5 to about 24.

[0070] exist Figure 20A and Figure 20B , the anti-reactive layer 104 and the first conductive material 102 are etched. The anti-reactive layer 104 and the first conductive material 102 can be etched by one or more etching processes, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), a combination thereof, and the like. In some embodiments, the anti-reactive layer 104 can be etched by a first etching process using the first mask layer 106 as a mask. The first etching process can expose the top portion and the sidewall portion of the first conductive material 102. The first conductive material 102 can then be etched by a second etching process using the anti-reactive layer 104 and the first mask layer 106 as masks. In some embodiments, the first etching process and the second etching process can be isotropic wet etching processes. In some embodiments, the anti-reactive layer 104 and the first conductive material 102 can be etched simultaneously. Figure 20B As shown, the anti-reactive layer 104 and the first conductive material 102 can be etched so that the top surfaces of the anti-reactive layer 104 and the first conductive material 102 are flush with the top surface of the first mask layer 106 and each other. In some embodiments, the top surfaces of the anti-reactive layer 104 and the first conductive material 102 can be disposed at different levels.

[0071] Figure 20C and Figure 20DAn embodiment is shown in which the first conductive material 102 and the anti-reactive layer 104 are etched back to form a planar region adjacent to the first spacer 81 and the second spacer 83. In some embodiments, the first conductive material 102 may be etched back before depositing the anti-reactive layer 104, the anti-reactive layer 104 may be deposited, and a first mask layer 106 may be formed and used to etch the anti-reactive layer 104. Figure 20C As shown, the top surface of the anti-reaction layer 104 may be flush with the top surface of the first mask layer 106. Figure 20D As shown, top surfaces of the first conductive material 102 and the anti-reactive layer 104 may be planar and may extend between opposing side surfaces of the gate dielectric layer 100. A top surface of the anti-reactive layer 104 may be disposed above a top surface of the first conductive material 102.

[0072] exist Figure 21A and Figure 21B In the embodiment, the first mask layer 106 is removed and a second conductive material 108 is formed over the anti-reaction layer 104, the first conductive material 102 and the gate dielectric layer 100 in the n-type region 50N. Figure 21C and Figure 21D In the embodiment, a second conductive material 108 is formed on the gate dielectric layer 100 in the p-type region 50P. Figure 21A and Figure 21B An n-type region 50N is shown, and Figure 21C and Figure 21D A p-type region 50P is shown. The first mask layer 106 may be removed by plasma ashing, an etching process such as an isotropic or anisotropic etching process, or the like.

[0073] The second conductive material 108 may fill the second recess 98 and extend over the gate dielectric layer 100 on the protective layer 97. The second conductive material 108 may be conformally deposited by a process such as ALD, CVD, PVD, etc. In some embodiments, the second conductive material 108 is a p-type work function layer, which may include W, Cu, TiN, Ti, Pt, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, Mo, MoSi2, WN, WCN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, other suitable n-type work function materials, combinations thereof, etc. After filling the second groove 98, a planarization process such as CMP may be performed to remove excess portions of the second conductive material 108 that are located above the top surfaces of the protective layer 97, the first spacer 81, and the second spacer 83. The bottom surface of the second conductive material 108 in the p-type region 50P may be flush with the bottom surface of the first conductive material 102 in the n-type region 50N and lower than the bottom surface of the second conductive material 108 in the n-type region 50N.

[0074] like Figure 21A and Figure 21B As shown, a second conductive material 108 can be deposited on top of the first conductive material 102 and the anti-reactive layer 104. The second conductive material 108 can cover the anti-reactive layer 104. Subsequently, a conductive capping material can be selectively deposited on the second conductive material 108. Because the anti-reactive layer 104 is formed of a dielectric material, the anti-reactive layer 104 can hinder the selective deposition of the conductive capping material. Forming the second conductive material 108 on the anti-reactive layer 104 facilitates the subsequent deposition of the conductive capping material for reducing gate resistance while providing the anti-reactive layer 104 with an increased threshold voltage. This improves device performance.

[0075] In some embodiments, a glue layer (not separately shown) may be deposited on the anti-reaction layer 104, the first conductive material 102, and the gate dielectric layer 100 in the n-type region 50N, and on the gate dielectric layer 100 in the p-type region 50P before forming the second conductive material 108 to improve adhesion between the second conductive material 108 and the underlying structure. The glue layer may further prevent diffusion between the second conductive material 108 and the underlying structure. The glue layer may include any acceptable material to promote adhesion and prevent diffusion. For example, the glue layer may be formed of a metal or metal nitride, such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, etc. The glue layer may be deposited by ALD, CVD, PVD, etc.

[0076] exist Figures 22A to 22E In the embodiment, the first spacer 81 , the second spacer 83 , the gate dielectric layer 100 and the second conductive material 108 are etched back to form a third recess 110 . Figure 22A 、 Figure 22B and Figure 22E An n-type region 50N is shown according to various embodiments, and Figure 22C and Figure 22D The p-type region 50P is shown. The first spacer 81, the second spacer 83, the gate dielectric layer 100, and the second conductive material 108 can be etched using a suitable etching process (e.g., an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc.). In some embodiments, the first spacer 81, the second spacer 83, the gate dielectric layer 100, and the second conductive material 108 can be etched by a plurality of selective etching processes to control the height of each of the first spacer 81, the second spacer 83, the gate dielectric layer 100, and the second conductive material 108. Figures 22A to 22E In the illustrated embodiment, the top surface of the second conductive material 108 in the n-type region 50N can be flush with the top surface of the second conductive material 108 in the p-type region 50P. The height of the second conductive material 108 in the p-type region 50P can be equal to the combined height of the first conductive material 102, the anti-reaction layer 104, and the second conductive material 108 in the n-type region 50N.

[0077] like 22A to 22D As shown, the first spacer 81, the second spacer 83, the gate dielectric layer 100, and the second conductive material 108 may be etched so that the top surfaces of the first spacer 81 and the second spacer 83 are flush with each other and are disposed above the top surfaces of the gate dielectric layer 100 and the second conductive material 108 that are flush with each other. Figure 22B In the cross-sectional view shown, the second conductive material 108 may be T-shaped. Figure 22E As shown, the first spacers 81, the second spacers 83, the gate dielectric layer 100, and the second conductive material 108 can be etched so that the top surfaces of the first spacers 81, the second spacers 83, and the gate dielectric layer 100 are flush with each other and are disposed above the top surface of the second conductive material 108. The top surfaces of the first spacers 81, the second spacers 83, and / or the gate dielectric layer 100 can be disposed at a height H1 above the top surface of the second conductive material 108 and / or the gate dielectric layer 100, with the height H1 ranging from about 0 nm to about 10 nm. The height H1 can be used to control the thickness of a subsequently formed conductive capping material, which can be used to reduce gate resistance and improve device performance.

[0078] exist 23A to 23HIn the embodiment shown in FIG. 1 , a conductive capping material 112 is formed in the third recess 110 above the second conductive material 108 . Figure 23A 、 Figure 23B and Figures 23E to 23H shows an n-type region 50N according to various embodiments, while Figure 23C and Figure 23D A p-type region 50P is shown. The conductive capping material 112 can be formed by a selective deposition process. For example, the conductive capping material 112 can be selectively deposited on the second conductive material 108 using a process such as ALD. In some embodiments, the second conductive material 108 can also extend above the top surface of the gate dielectric layer 100. In some embodiments, the conductive capping material 112 can include a conductive material such as tungsten (W), cobalt (Co), ruthenium (Ru), etc.

[0079] like Figure 23A and Figure 23B As shown, a conductive capping material 112 can be deposited over the second conductive material 108, wherein the second conductive material 108 separates the conductive capping material 112 from the anti-reactive layer 104. Because the anti-reactive layer 104 is formed of a dielectric material, the anti-reactive layer 104 can hinder the selective deposition of the conductive capping material 112. Therefore, the second conductive material 108 is deposited over the anti-reactive layer 104 to cover the anti-reactive layer 104. This facilitates the deposition of the conductive capping material 112, which reduces device defects caused by the deposition of the conductive capping material 112 and reduces costs.

[0080] In embodiments where the conductive capping material 112 includes tungsten, the conductive capping material 112 can be deposited using a tungsten chloride (WCl5) precursor, a hydrogen (H2) reducing gas, and an argon (Ar) carrier gas at a temperature in a range of about 300° C. to about 500° C. and a process pressure in a range of about 10 Torr to about 50 Torr. The tungsten chloride precursor can be supplied at a temperature in a range of about 100° C. to about 150° C. The conductive capping material 112 can be deposited to a thickness T1 in a range of about 2 nm to about 5 nm. In some embodiments, the conductive capping material 112 can further include chlorine at an atomic concentration in a range of about 0.5% to about 5%. The gate dielectric layer 100, the first conductive material 102, the anti-reaction layer 104, the second conductive material 108, and the conductive capping material 112 in the n-type region 50N, and the gate dielectric layer 100, the second conductive material 108, and the conductive capping material 112 in the p-type region 50P can be collectively referred to as a "gate structure." The first conductive material 102, anti-reaction layer 104, second conductive material 108, and conductive capping material 112 in the n-type region 50N, and the second conductive material 108 and conductive capping material 112 in the p-type region 50P can be collectively referred to as a "gate electrode." Including the conductive capping material 112 having a specified thickness can reduce the resistance of the gate structure, which improves device performance.

[0081] like 23A to 23D As shown, the conductive capping material 112 can extend along the top surface of the gate dielectric layer 100 and the second conductive material 108 between the opposite side surfaces of the second spacer 83. The top surfaces of the conductive capping materials in the n-type region 50N and the p-type region 50P can be flush with each other and with the top surfaces of the first spacer 81 and the second spacer 83. Figure 23E In the embodiment shown, the top surface of the gate dielectric layer 100 is flush with the top surfaces of the second spacer 83 and the first spacer 81 and is higher than the top surface of the second conductive material 108. The conductive capping material 112 extends along the top surface of the second conductive material 108 between the opposite side surfaces of the gate dielectric layer 100. Figure 23F In the illustrated embodiment, the top surfaces of the second conductive material 108 and the gate dielectric layer 100 are flush with the top surfaces of the second spacer 83 and the first spacer 81. The conductive capping material 112 may extend along the top surfaces of the second conductive material 108 and the gate dielectric layer 100, and the top surfaces of the second spacer 83 and the first spacer 81 may be free of the conductive capping material 112. In some embodiments, the conductive capping material 112 may also extend along the top surfaces of the second spacer 83 and the first spacer 81 between opposing side surfaces of the CESL 94.

[0082] exist Figure 23GIn the illustrated embodiment, the anti-reactive layer 104 is omitted. The anti-reactive layer 104 may be omitted in embodiments where the first conductive material 102 has a sufficient thickness, the first conductive material 102 is formed of a material having a relatively low oxidation potential, or the threshold voltage is otherwise sufficiently large without the anti-reactive layer 104. Figure 23H Shown Figure 20C and Figure 20D An embodiment in which the anti-reactive layer 104 and the first conductive material 102 are straight lines extending between opposite side surfaces of the second spacer 83. Figure 23H As shown, the first conductive material 102, the anti-reactive layer 104, and the second conductive material 108 may have the same width as each other. Figure 23G and Figure 23H In embodiments, the conductive capping material 112 may extend along the top surfaces of the gate dielectric layer 100 and the second conductive material 108 between opposing side surfaces of the second spacer 83 .

[0083] exist Figure 24A and Figure 24B In the embodiment, a second ILD 114 is deposited over the protection layer 97 , the first spacer 81 , the second spacer 83 , the CESL 94 , and the conductive capping material 112 to fill the third groove 110 . Figure 24A and Figure 24B An n-type region 50N is shown; however, a second ILD 114 may also be formed over the p-type region 50P. In some embodiments, the second ILD 114 is a flowable film formed by FCVD. In some embodiments, the second ILD 114 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD, PECVD, etc. After depositing the second ILD 114, the second ILD 114 is planarized and the protective layer 97 is removed. The second ILD 114 may be planarized by a process such as CMP. The portion of the second ILD 114 disposed over the first ILD 96 and CESL 94 may be removed, and after planarization, the top surfaces of the first ILD 96 and CESL 94 may be flush with the top surface of the second ILD 114. The planarization process may further remove the protective layer 97.

[0084] exist Figure 25A and Figure 25B In the embodiment, the second ILD 114 , the first ILD 96 , and the CESL 94 are etched to form a fourth recess 116 that exposes the surface of the epitaxial source / drain regions 92 and / or the conductive capping material 112 . Figure 25A and Figure 25BAn n-type region 50N is shown; however, a fourth recess 116 may also be formed in the p-type region 50P. The fourth recess 116 may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the fourth recess 116 may be etched through the second ILD 114 and the first ILD 96 using a first etching process, and then the fourth recess 116 may be etched through the CESL 94 using a second etching process. A mask, such as a photoresist, may be formed and patterned over the first ILD 96, the CESL 94, and the second ILD 114 to shield portions of the first ILD 96, the CESL 94, and the second ILD 114 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the fourth recess 116 extends into the epitaxial source / drain region 92 and / or the conductive capping material 112, and the bottom of the fourth recess 116 may be flush with (e.g., at the same level, or having the same distance from the substrate 50) or lower than (e.g., closer to the substrate 50) the epitaxial source / drain region 92 and / or the conductive capping material 112. Although Figure 25B The fourth recess 116 is shown exposing the epitaxial source / drain regions 92 and the gate structure with the same cross-section. However, in some embodiments, the epitaxial source / drain regions 92 and the gate structure can be exposed with different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. After forming the fourth recess 116, a silicide region 118 is formed over the epitaxial source / drain regions 92. In some embodiments, the silicide region 118 is formed by first depositing a metal (not separately shown) (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) that reacts with the underlying semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions 92 over the exposed portions of the epitaxial source / drain regions 92 to form a silicide or germanide region, and then performing a thermal annealing process to form the silicide region 118. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although silicide region 118 is referred to as a silicide region, silicide region 118 may also be a germanide region or a silicon germanium region (e.g., a region containing both silicide and germanide). In an embodiment, silicide region 118 contains TiSi and has a thickness in a range from about 2 nm to about 10 nm.

[0085] exist Figure 26A and Figure 26B In the embodiment, source / drain contacts 120 and gate contact 122 are formed in the fourth recess 116 . Figure 26A and Figure 26BAn n-type region 50N is shown; however, source / drain contacts 120 and gate contact 122 may also be formed in p-type region 50P. Each of source / drain contacts 120 and gate contact 122 may include one or more layers, such as a barrier layer, a diffusion layer, and a fill material. For example, in some embodiments, each of source / drain contacts 120 and gate contact 122 includes a barrier layer and a conductive material overlying the barrier layer. Each of source / drain contacts 120 and gate contact 122 is electrically coupled to underlying conductive features (e.g., conductive capping material 112 and / or silicide region 118). Gate contact 122 is electrically coupled to the conductive capping material 112 of the gate structure, and source / drain contacts 120 are electrically coupled to silicide region 118 overlying epitaxial source / drain regions 92. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surfaces of CESL 94 , first ILD 96 , and second ILD 114 so that top surfaces of source / drain contacts 120 and gate contact 122 are flush with the top surfaces of CESL 94 , first ILD 96 , and second ILD 114 .

[0086] Embodiments can achieve advantages. For example, an anti-reactive layer 104 can be included on top of the first conductive material 102 to prevent oxidation of the first conductive material 102 and increase the threshold voltage of the device including the anti-reactive layer 104. The second conductive material 108 can then cover the surface of the anti-reactive layer 104, thereby providing a material on which a conductive capping material 112 can be selectively deposited. The conductive capping material 112 can then be used to reduce gate resistance. The increased threshold voltage and reduced gate resistance can improve the performance of semiconductor devices including the same anti-reactive layer 104 and / or conductive capping material 112.

[0087] According to one embodiment, a semiconductor device includes a gate structure located above a semiconductor substrate, the gate structure including: a high-k dielectric layer; an n-type work function layer located above the high-k dielectric layer; an anti-reaction layer located above the n-type work function layer, the anti-reaction layer comprising a dielectric material; a p-type work function layer located above the anti-reaction layer, the p-type work function layer covering a top surface of the anti-reaction layer; and a conductive cap layer located above the p-type work function layer. In one embodiment, the p-type work function layer is T-shaped in a cross-sectional view. In one embodiment, the anti-reaction layer comprises silicon. In one embodiment, the conductive cap layer comprises tungsten. In one embodiment, a top surface of the high-k dielectric layer is flush with a top surface of the p-type work function layer. In one embodiment, the semiconductor device further includes a gate spacer adjacent to the gate structure, the conductive cap layer extending between opposing side surfaces of the gate spacer, and a top surface of the gate spacer being flush with a top surface of the conductive cap layer. In an embodiment, the semiconductor device further includes a gate spacer adjacent to the gate structure, and a top surface of the p-type work function layer is flush with a top surface of the high-k dielectric layer and a top surface of the gate spacer.

[0088] According to another embodiment, a semiconductor device includes: a first channel region in an n-type region; a second channel region in a p-type region; a first gate stack located above the first channel region, the first gate stack comprising: a first gate dielectric layer located above the first channel region; an n-type metal layer located above and in contact with the first gate dielectric layer, the n-type metal layer comprising aluminum; a dielectric layer located above the n-type metal layer; a first p-type metal layer located above the n-type metal layer and the dielectric layer; and a first metal capping layer located above the first p-type metal layer; and a second gate stack located above the second channel region, the second gate stack comprising: a second gate dielectric layer located above the second channel region; a second p-type metal layer located above and in contact with the second gate dielectric layer; and a second metal capping layer located above the second p-type metal layer. In one embodiment, the combined height of the n-type metal layer, the dielectric layer, and the first p-type metal layer is equal to the height of the second p-type metal layer. In one embodiment, the dielectric layer and the first p-type metal layer are in contact with the first gate dielectric layer. In an embodiment, the dielectric layer comprises silicon. In an embodiment, the first metal cap layer and the second metal cap layer comprise chlorine. In an embodiment, a top surface of the first p-type metal layer is flush with a top surface of the second p-type metal layer, and a bottom surface of the second p-type metal layer is lower than a bottom surface of the first p-type metal layer. In an embodiment, the semiconductor device further comprises: a first gate spacer extending along a sidewall of the first gate stack; and a second gate spacer extending along a sidewall of the second gate stack, the top surface of the second gate spacer being flush with a top surface of the second metal cap layer, a top surface of the first gate spacer, and a top surface of the first metal cap layer.

[0089] According to another embodiment, a method includes forming a gate stack on a semiconductor substrate, wherein forming the gate stack includes: depositing an n-type work function layer on the semiconductor substrate; depositing a dielectric layer on the n-type work function layer; forming a first mask layer on the dielectric layer; etching back the n-type work function layer and the dielectric layer; depositing a p-type work function layer on the n-type work function layer and the dielectric layer; and selectively depositing a metal capping layer on the p-type work function layer. In an embodiment, the metal capping layer is deposited by atomic layer deposition using tungsten chloride as a precursor. In an embodiment, the n-type work function layer and the dielectric layer are etched back using the first mask layer as a mask, and the first mask layer is removed before depositing the p-type work function layer. In an embodiment, the method further includes etching back the dielectric layer to expose the n-type work function layer, the p-type work function layer being deposited in contact with the n-type work function layer and the dielectric layer. In an embodiment, the method further includes: forming a gate spacer adjacent to the sacrificial gate stack; removing the sacrificial gate stack to form a first opening, wherein the gate stack is formed in the first opening; planarizing the gate spacer and the p-type work function layer; and etching back the p-type work function layer after planarizing the gate spacer and the p-type work function layer. In an embodiment, the method further includes: etching back the gate spacer, wherein the metal capping layer is deposited between opposing side surfaces of the gate spacer.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0091] Example 1 is a semiconductor device, comprising: a gate structure located on a semiconductor substrate, the gate structure comprising: a high-k dielectric layer; an n-type work function layer located on the high-k dielectric layer; an anti-reaction layer located on the n-type work function layer, the anti-reaction layer comprising a dielectric material; a p-type work function layer located on the anti-reaction layer, the p-type work function layer covering the top surface of the anti-reaction layer; and a conductive cap layer located on the p-type work function layer.

[0092] Example 2 is the semiconductor device of Example 1, wherein the p-type work function layer is T-shaped in a cross-sectional view.

[0093] Example 3 is the semiconductor device of Example 1, wherein the anti-reaction layer includes silicon.

[0094] Example 4 is the semiconductor device of Example 1, wherein the conductive cap layer comprises tungsten.

[0095] Example 5 is the semiconductor device of Example 1, wherein a top surface of the high-k dielectric layer is flush with a top surface of the p-type work function layer.

[0096] Example 6 is the semiconductor device described in Example 5, further comprising: a gate spacer adjacent to the gate structure, wherein the conductive cap layer extends between opposite side surfaces of the gate spacer, and wherein a top surface of the gate spacer is flush with a top surface of the conductive cap layer.

[0097] Example 7 is the semiconductor device of Example 1, further comprising: a gate spacer adjacent to the gate structure, wherein a top surface of the p-type work function layer is flush with a top surface of the high-k dielectric layer and a top surface of the gate spacer.

[0098] Example 8 is a semiconductor device comprising: a first channel region located in an n-type region; a second channel region located in a p-type region; a first gate stack located above the first channel region, the first gate stack comprising: a first gate dielectric layer located above the first channel region; an n-type metal layer located above and in contact with the first gate dielectric layer, the n-type metal layer comprising aluminum; a dielectric layer located above the n-type metal layer; a first p-type metal layer located above the n-type metal layer and the dielectric layer; and a first metal cap layer located above the first p-type metal layer; and a second gate stack located above the second channel region, the second gate stack comprising: a second gate dielectric layer located above the second channel region; a second p-type metal layer located above and in contact with the second gate dielectric layer; and a second metal cap layer located above the second p-type metal layer.

[0099] Example 9 is the semiconductor device of Example 8, wherein a combined height of the n-type metal layer, the dielectric layer, and the first p-type metal layer is equal to a height of the second p-type metal layer.

[0100] Example 10 is the semiconductor device of Example 8, wherein the dielectric layer and the first p-type metal layer are in contact with the first gate dielectric layer.

[0101] Example 11 is the semiconductor device of Example 8, wherein the dielectric layer comprises silicon.

[0102] Example 12 is the semiconductor device of Example 8, wherein the first metal capping layer and the second metal capping layer contain chlorine.

[0103] Example 13 is the semiconductor device of Example 8, wherein the top surface of the first p-type metal layer is flush with the top surface of the second p-type metal layer, and wherein the bottom surface of the second p-type metal layer is lower than the bottom surface of the first p-type metal layer.

[0104] Example 14 is the semiconductor device described in Example 8, further including: a first gate spacer extending along the sidewall of the first gate stack; and a second gate spacer extending along the sidewall of the second gate stack, wherein the top surface of the second gate spacer is flush with the top surface of the second metal cap layer, the top surface of the first gate spacer and the top surface of the first metal cap layer.

[0105] Example 15 is a method for forming a semiconductor device, comprising: forming a gate stack above a semiconductor substrate, wherein forming the gate stack comprises: depositing an n-type work function layer above the semiconductor substrate; depositing a dielectric layer above the n-type work function layer; forming a first mask layer above the dielectric layer; etching back the n-type work function layer and the dielectric layer; depositing a p-type work function layer above the n-type work function layer and the dielectric layer; and selectively depositing a metal cap layer above the p-type work function layer.

[0106] Example 16 is the method of Example 15, wherein the metal capping layer is deposited by atomic layer deposition using tungsten chloride as a precursor.

[0107] Example 17 is the method of Example 15, wherein the n-type work function layer and the dielectric layer are etched back using the first mask layer as a mask, and wherein the first mask layer is removed before depositing the p-type work function layer.

[0108] Example 18 is the method of Example 15, further comprising etching back the dielectric layer to expose the n-type work function layer, wherein the p-type work function layer is deposited in contact with the n-type work function layer and the dielectric layer.

[0109] Example 19 is the method described in Example 15, further including: forming a gate spacer adjacent to the sacrificial gate stack; removing the sacrificial gate stack to form a first opening, wherein the gate stack is formed in the first opening; planarizing the gate spacer and the p-type work function layer; and etching back the p-type work function layer after planarizing the gate spacer and the p-type work function layer.

[0110] Example 20 is the method of Example 19, further comprising etching back the gate spacers, wherein the metal capping layer is deposited between opposing side surfaces of the gate spacers.

Claims

1. A semiconductor device comprising: A gate structure is located on the semiconductor substrate, and the gate structure includes: a high-k dielectric layer extending above the substrate to a first height; an n-type work function layer located above the high-k dielectric layer, the n-type work function layer extending above the substrate to a second height, the second height being less than the first height; an anti-reaction layer, located on the n-type work function layer, the anti-reaction layer comprising a dielectric material, and extending above the substrate to the second height; a p-type work function layer located on the anti-reaction layer, the p-type work function layer covering a top surface of the anti-reaction layer, the p-type work function layer extending above the substrate to a third height, the third height being greater than the second height; and The conductive cap layer is located on the p-type work function layer.

2. The semiconductor device according to claim 1, wherein The p-type work function layer is T-shaped in a cross-sectional view.

3. The semiconductor device according to claim 1, wherein The anti-reactive layer includes silicon.

4. The semiconductor device according to claim 1, wherein The conductive cap layer includes tungsten.

5. The semiconductor device according to claim 1, wherein A top surface of the high-k dielectric layer is flush with a top surface of the p-type work function layer.

6. The semiconductor device according to claim 5, further comprising: A gate spacer is adjacent to the gate structure, wherein the conductive capping layer extends between opposing side surfaces of the gate spacer, and wherein a top surface of the gate spacer is flush with a top surface of the conductive capping layer.

7. The semiconductor device according to claim 1 , further comprising: A gate spacer is adjacent to the gate structure, wherein a top surface of the p-type work function layer is flush with a top surface of the high-k dielectric layer and a top surface of the gate spacer.

8. A semiconductor device comprising: a first channel region located in the n-type region; a second channel region located in the p-type region; A first gate stack is located above the first channel region, and the first gate stack includes: a first gate dielectric layer, located above the first channel region; an n-type metal layer located on and in contact with the first gate dielectric layer, the n-type metal layer comprising aluminum; a dielectric layer, located on the n-type metal layer; a first p-type metal layer located on the n-type metal layer and the dielectric layer; and a first metal cap layer, located on the first p-type metal layer; and a second gate stack located above the second channel region, the second gate stack comprising: a second gate dielectric layer located above the second channel region; a second p-type metal layer located on and in contact with the second gate dielectric layer; and a second metal cap layer, located on the second p-type metal layer; The combined height of the n-type metal layer, the dielectric layer, and the first p-type metal layer is equal to the height of the second p-type metal layer.

9. The semiconductor device according to claim 8, wherein The dielectric layer and the first p-type metal layer are in contact with the first gate dielectric layer.

10. The semiconductor device according to claim 8, wherein The dielectric layer includes silicon.

11. The semiconductor device according to claim 8, wherein The first metallic capping layer and the second metallic capping layer contain chlorine.

12. The semiconductor device according to claim 8, wherein A top surface of the first p-type metal layer is flush with a top surface of the second p-type metal layer, and a bottom surface of the second p-type metal layer is lower than a bottom surface of the first p-type metal layer.

13. The semiconductor device according to claim 8, further comprising: a first gate spacer extending along a sidewall of the first gate stack; as well as A second gate spacer extends along a sidewall of the second gate stack, wherein a top surface of the second gate spacer is flush with a top surface of the second metal cap layer, a top surface of the first gate spacer, and a top surface of the first metal cap layer.

14. A method for forming a semiconductor device, comprising: A gate stack is formed on a semiconductor substrate, wherein forming the gate stack comprises: depositing an n-type work function layer on the semiconductor substrate; depositing a dielectric layer on the n-type work function layer; forming a first mask layer over the dielectric layer; Etching back the n-type work function layer and the dielectric layer; depositing a p-type work function layer over the n-type work function layer and the dielectric layer; and A metal capping layer is selectively deposited on the p-type work function layer.

15. The method according to claim 14, wherein The metal capping layer is deposited by atomic layer deposition using tungsten chloride as a precursor.

16. The method according to claim 14, wherein The n-type work function layer and the dielectric layer are etched back using the first mask layer as a mask, and wherein the first mask layer is removed before depositing the p-type work function layer.

17. The method according to claim 14, further comprising: The dielectric layer is etched back to expose the n-type work function layer, wherein the p-type work function layer is deposited in contact with the n-type work function layer and the dielectric layer.

18. The method according to claim 14, further comprising: forming a gate spacer adjacent to the sacrificial gate stack; removing the sacrificial gate stack to form a first opening, wherein the gate stack is formed in the first opening; planarizing the gate spacer and the p-type work function layer; and The p-type work function layer is etched back after planarizing the gate spacers and the p-type work function layer.

19. The method according to claim 18, further comprising: The gate spacers are etched back, wherein the metal capping layer is deposited between opposite side surfaces of the gate spacers.

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