Semiconductor structure and method of manufacturing the same

Abstract

Disclosed are semiconductor structures and methods of manufacturing the same. An exemplary semiconductor structure according to the present invention includes a substrate having a p-type well or an n-type well, a first base portion located above the p-type well, a second base portion located above the n-type well, a first plurality of channel members located above the first base portion, a second plurality of channel members located above the second base portion, an isolation member disposed between the first base portion and the second base portion, and a deep isolation structure disposed in the substrate below the isolation member.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved towards smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effect (SCE). Multi-gate devices generally refer to devices with a gate structure or a portion thereof positioned above more than one side of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a raised channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of a “fin” of semiconductor material extending from the substrate). The gate structure of an MBC transistor can extend partially or entirely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, an MBC transistor can also be called a gate-around transistor (SGT) or a gate-all-around (GAA) transistor.

[0004] While MBC transistors with chip channel structures typically offer excellent gate control and drive current, their wider chip channel structures can increase device width. This increased device width may make them less attractive in high-packaging-density applications such as memory applications. Improving MBC transistor packaging density can be challenging when forming isolation structures to separate different device regions. Although existing semiconductor devices are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0005] Some embodiments of this application provide a semiconductor structure including: a substrate, including a p-type well or an n-type well; a first base located above the p-type well; a second base located above the n-type well; a first plurality of channel members located above the first base; a second plurality of channel members located above the second base; an isolation member disposed between the first base and the second base; and a deep isolation structure disposed in the substrate below the isolation member.

[0006] Other embodiments of this application provide a semiconductor structure including: a substrate, including a p-type well or an n-type well; a first base located above the p-type well; a second base located above the n-type well; a first n-type epitaxial member located above the first base; a first p-type epitaxial member located above the second base; a first isolation member disposed between the first base and the second base; and a deep isolation structure disposed in the substrate directly below the first isolation member.

[0007] Further embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: receiving a workpiece including a first fin structure located above a p-type well region of a substrate and a second fin structure located above an n-type well region of the substrate, the first fin structure and the second fin structure being spaced apart by a junction trench; extending the junction trench further into the substrate to form a deep cavity; forming a deep isolation member in the deep cavity and forming an isolation member in the junction trench; and forming dielectric fins on the isolation members such that the dielectric fins are disposed between the first fin structure and the second fin structure. Attached Figure Description

[0008] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A flowchart of a method for forming a semiconductor device according to one or more aspects of the present invention is shown.

[0010] Figures 2 to 23 It is shown that, according to one or more aspects of the present invention, Figure 1 Partial perspective or cross-sectional view of the workpiece during each manufacturing stage of the method. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances of various components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Additionally, reference characters and / or letters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0012] For ease of description, spatial relative terms such as “below,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another, as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges of numerical values, the term is intended to include values ​​within a reasonable range, taking into account the variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having characteristics associated with the numerical value, the range of numerical values ​​covers a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer with a thickness of "about 5 nm" can cover a size range of 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0014] This invention generally relates to isolation structures for reducing bulk leakage, and more specifically to deep isolation structures disposed on trap junctions.

[0015] To improve drive current to meet design requirements, MBC transistors can include thin and wide nanoscale channel components. Such MBC transistors can also be referred to as nanosheet transistors. While nanosheet transistors offer satisfactory drive current and channel control, their wider nanosheet channel components may pose a challenge to further reducing cell size. In some exemplary structures, a herringbone or fork structure can be implemented to reduce cell size. In a herringbone or fork structure, adjacent stacks of channel components can be separated by dielectric fins (or hybrid fins). Since one end of the stack of channel components contacts the dielectric fin, the gate structure surrounding the stack of channel components does not extend between the channel components and the dielectric fin. Each dielectric fin is disposed on an isolation component such as a shallow trench isolation (STI) component. The STI component can also be disposed on the junction between the n-type well and the p-type well to reduce bulk leakage.

[0016] This invention provides a deep isolation structure disposed at a junction between a p-type well below an n-type device and an n-type well below a p-type device. In some embodiments, the deep isolation structure is formed by forming a notch along the junction. The notch may undercut the active regions of the n-type and p-type devices. In at least some embodiments, the n-type and p-type devices may be herringbone or fork-plate transistors. The deep isolation structure can better block bulk leakage paths between the n-type and p-type wells.

[0017] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1 A flowchart of a method 100 for forming a semiconductor device is shown. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. For additional embodiments of the method, additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved. For simplicity, not all steps are described in detail herein. The following is in conjunction with… Figures 1 to 23 Method 100 is described, showing partial cross-sectional views of a workpiece 200 at different stages of manufacturing according to an embodiment of method 100. Because a semiconductor device will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor device 200, depending on the context. Although embodiments including fishbone or fork-plate transistors are shown in the figures, the invention is not limited thereto and is applicable to other multi-gate devices such as MBC transistors or FinFETs. Figures 2 to 23 In this invention, the X, Y, and Z directions are perpendicular to each other and are used consistently. Furthermore, throughout the invention, similar reference numerals are used to denote similar components.

[0018] refer to Figure 1 and Figure 2 Method 100 includes block 102, in which workpiece 200 is received. For example... Figure 2 As shown, workpiece 200 includes a substrate 202 and a stack 204 disposed on the substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductor materials such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may include a plurality of n-type well regions and a plurality of p-type well regions. In the depicted embodiment, the substrate 202 includes a p-type well region 202P (or p-well 202P) and an n-type well region 202N (or n-well 202N). Figure 2 As shown, p-well 202P and n-well 202N are bonded to each other along well junction 2020. p-well 202P may be doped with a p-type dopant (i.e., boron (B)) and n-well 202N may be doped with an n-type dopant (i.e., phosphorus (P) or arsenic (As)). p-well 202P and n-well 202N can be formed using ion implantation or thermal diffusion.

[0019] Still referencing Figure 2 The stack 204 may include multiple channel layers 208 interleaved with multiple sacrificial layers 206. The channel layers 208 and sacrificial layers 206 may have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si), and the sacrificial layers 206 are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layers 206 allows for selective removal or recessing of the sacrificial layers 206 without substantially damaging the channel layers 208. Figure 2 In some of the presented embodiments, the workpiece 200 further includes a top sacrificial layer 206T disposed on the stack 204. The top sacrificial layer 206T is thicker than the other sacrificial layers 206 and serves to protect the stack 204 from damage during the manufacturing process. The top sacrificial layer 206T, the sacrificial layers 206, and the channel layer 208 can be deposited using epitaxial processes. The stack 204 can be epitaxially deposited using CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The sacrificial layers 206 and the channel layer 208 are deposited alternately and sequentially to form the stack 204. Figure 2Three (3) sacrificial layers 206 and three (3) channel layers 208 arranged alternately and vertically are shown for illustrative purposes only and are not intended to limit the specific content described in the claims. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 1 and 6.

[0020] refer to Figure 1 and Figure 3 Method 100 includes a block 104 in which a stack 204 and a substrate 202 are patterned to form fin structures 211 separated by trenches 212 or junction trenches 212J. To pattern the stack 204 and substrate 202, a first hard mask layer 210 is deposited over a top sacrificial layer 206T. The first hard mask layer 210 is then patterned as an etch mask to pattern portions of the top sacrificial layer 206, the stack 204, and the substrate 202. In some embodiments, the first hard mask layer 210 may be deposited using CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or a suitable deposition method. The first hard mask layer 210 may be a single layer or multiple layers. When the first hard mask layer 210 is multilayered, it may include pad oxide and pad nitride layers. In an alternative embodiment, the first hard mask layer 210 may include silicon (Si). The fin structure 211 can be patterned using suitable processes including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single direct-to-direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern a first hard mask layer 210, which can then be used as an etching mask to etch the stack 204 and the substrate 202 to form the fin structure 211. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0021] like Figure 3 As shown, each fin structure 211 includes a base 211B formed by a portion of the substrate 202 and a top 211T formed by the stack 204. The top 211T is disposed above the base 211B. The fin structure 211 extends longitudinally from the substrate 202 along the Y direction and perpendicularly along the Z direction. Along the X direction, the fin structure 211 is separated by trenches 212 and junction trenches 212J. Compared to the trenches 212, the junction trenches 212J are disposed on and along the well junction 2020. Figure 3 In some of the presented embodiments, the junction trench 212J is wider along the X direction than the trench 212 to provide a larger spacing. For example... Figure 3 As shown, junction trench 212J defines a first spacing S1, and trench 212 defines a second spacing S2. The first spacing S1 is larger than the second spacing S2. In some examples, the first spacing S1 is between about 20 nm and about 30 nm, and the second spacing S2 is between about 10 nm and about 20 nm. The wider junction trench 212J allows active regions, such as fin structures 211, on either side of the well junction 2020 to be further spaced apart to reduce bulk leakage.

[0022] refer to Figure 1 and Figure 4 Method 100 includes block 106 in which a pad 214 is formed along the sidewalls of fin structure 211. Pad 214 serves to protect the sidewalls of fin structure 211 from damage during block 108 (described below). In an exemplary process for forming pad 214, a dielectric material is conformally deposited over workpiece 200, including over trench 212 and junction trench 212J, by atomic layer deposition (ALD), chemical vapor deposition (CVD), or low-pressure CVD (LPCVD). The dielectric material for pad 214 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or combinations thereof. The deposited dielectric material is then anisotropically etched back to form pad 214. In some embodiments, the etch back may include a dry etching process using one or more fluorinated gases such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or nitrogen trifluoride (NF3). Figure 4 As shown, because the first gap S1 in the junction trench 212J is large, the dielectric material on the bottom surface of the junction trench 212J is removed to expose the substrate 202. That is, the pad 214 is only lined to the sidewalls of the junction trench 212J. The smaller second gap S2 of the trench 212 prevents the dielectric material from being removed from its bottom surface.

[0023] Reference Figure 1 and Figure 5Method 100 includes a block 108 in which a junction trench 212J extends into a substrate 202 to form a deep recess 216. With the trench 212 protected by a pad 214 and the substrate 202 exposed from the bottom surface of the junction trench 212J, an etch at block 108 is performed to expose the substrate 202 below the junction trench 212J. The etching of the exposed substrate 202 extends the junction trench 212J downward into the substrate 202 to form the deep recess 216. The deep recess 216 may also be referred to as a notch. The etching at block 108 can be performed using a dry etching process that tends towards anisotropy or a wet etching process that tends towards isotropy. Exemplary selective wet etching processes may include the use of ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), or a suitable wet etchant. Exemplary selective dry etching processes may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), argon (Ar), or mixtures thereof. Figure 5 In some of the presented embodiments, the etching process at block 108 is not entirely anisotropic, and the deep cavity 216 is undercut by the pad 214. As a result, the shape of the deep cavity 216 differs from the shape of the junction trench 212J. In some examples, the width of the widest portion of the deep cavity 216 is greater than the width of the junction trench 212J (including the pad 214). Before forming the deep cavity 216, it is positioned horizontally below the bottom surface of the trench 212 or junction trench 212J. Accordingly, the deep cavity 216 is positioned deeper within the substrate 202.

[0024] refer to Figure 1 , Figure 6 and Figure 7Method 100 includes a block 110 in which isolation components are formed in a deep recess 216 and a trench 212. The isolation components formed at block 110 may include an isolation component 218 located in the trench 212, a junction isolation component 218J located in a junction trench 212J, and a deep isolation component 220 located in the deep recess 216. Isolation components 218 and junction isolation components 218J may be collectively referred to as shallow trench isolation (STI) components. In an exemplary process for forming these isolation components, a dielectric material is deposited over a workpiece 200, and the trench 212, deep recess 216, and junction trench 212J are filled with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, or combinations thereof. In various examples, at block 110, dielectric material can be deposited using CVD, sub-atmospheric CVD (SACVD), flowable CVD (FCVD), ALD, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by chemical mechanical polishing (CMP) until the top sacrificial layer 206T is exposed, as shown. Figure 6 As shown. In some embodiments, the composition of the pad 214 and the dielectric material for the insulating member may be similar, and their boundaries are marked with dashed lines. For ease of illustration, the boundary between the pad 214 and the insulating member may be omitted in the following figures. Reference Figure 7 The planarized dielectric material and pads 214 are further recessed using dry etching, wet etching, and / or combinations thereof to form the final structure of the isolation component 218, the junction isolation component 218J, and the deep isolation component 220. Figure 7 As shown, the top 211T of the fin-like structure 211 rises above the isolation member 218 or the junction isolation member 218J, while the base 211B or most of it is surrounded by the isolation member 218 or the junction isolation member 218J. Figure 7 As shown, the deep isolation member 220 is disposed below the horizontal plane of the base 211B and can be low-cut below the base 211B adjacent to the well junction 2020. That is, a portion of the deep isolation member can extend below the adjacent base 211B. After the isolation member 218 and the junction isolation member 218J are formed, the top 211T is separated by the dielectric fin trench 222 and the junction dielectric fin trench 222J. The junction dielectric fin trench 222J is disposed directly above the well junction 2020.

[0025] refer to Figure 1 , Figure 8 , Figure 9 , Figure 10 and Figure 11 Method 100 includes block 112, at which dielectric fins are formed. Figure 11In the depicted embodiment, at block 112, dielectric fins 230 are formed in dielectric fin trench 222, and junction dielectric fins 230J are formed in junction dielectric fin trench 222J. Figure 8 , Figure 9 , Figure 10 and Figure 11 An exemplary process for forming dielectric fins is shown in the figure. (Reference) Figure 8 A first layer 224 and a second layer 226 are conformally deposited above workpiece 200, including in dielectric fin trenches 222 and junction dielectric fin trenches 222J. The first layer 224 can be conformally deposited using CVD, ALD, or a suitable method. The first layer 224 linings the sidewalls and bottom surfaces of the dielectric fin trenches 222 and junction dielectric fin trenches 222J. The second layer 226 is then conformally deposited over the first layer 224 using CVD, high-density plasma CVD (HDPCVD), and / or other suitable processes. In some examples, the dielectric constant of the second layer 226 is less than that of the first layer 224. The first layer 224 is silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. In one embodiment, the first layer 224 comprises silicon carbonitride. The second layer 226 may include silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, or a suitable dielectric material. In one embodiment, the second layer 226 includes silicon oxide. Figure 8 In some of the embodiments presented, due to the width difference, the second layer 226 completely fills the dielectric fin trench 222, but does not completely fill the junction dielectric fin trench 222J.

[0026] Reference Figure 9 The conformally deposited first layer 224 and second layer 226 are etched back to expose the top sacrificial layer 206T and remove the first layer 224 and second layer 226 located in the junction dielectric fin trench 222J. In some embodiments, the first layer 224 and second layer 226 can be etched back in a dry etching process using oxygen, nitrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. In some embodiments, the etch back may include a first stage targeting the second layer 226 and a second stage targeting the first layer 224. Figure 9 As shown, at the end of the etch-back process, the junction isolation component 218J is exposed in the junction dielectric fin trench 222J.

[0027] Now for reference Figure 10With the junction dielectric fin trench 222J exposed, a cladding layer 232 is deposited over the workpiece 200, including over the sidewalls of the junction dielectric fin trench 222J. In some embodiments, the cladding layer 232 may have a composition similar to that of the sacrificial layer 206 or the top sacrificial layer 206T. In one example, the cladding layer 232 may be formed of silicon germanium (SiGe). Their common composition allows for the selective and simultaneous removal of the sacrificial layer 206 and the cladding layer 232 in subsequent processes. In some embodiments, the cladding layer 232 may be conformally and epitaxially grown using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). Figure 10 As shown, the cladding layer 232 is selectively disposed on the exposed sidewall surface of the junction dielectric fin trench 222J. Depending on the degree of selective growth of the cladding layer 232, an etch-back process can be performed to expose the junction isolation component 218J. Still referring to... Figure 10 The third layer 234 and the fourth layer 236 are conformally deposited in the junction dielectric fin trench 222J. The composition and formation of the third layer 234 can be similar to those of the first layer 224. The fourth layer 236 may comprise silicon oxide or silicon oxide containing a dielectric material. In some embodiments, the fourth layer 236 may be deposited using CVD, HDPCVD, or flowable CVD (FCVD). In one embodiment, FCVD may be used to deposit the fourth layer 236. After depositing the third layer 234 and the fourth layer 236, a chemical mechanical polishing (CMP) process is used to planarize the workpiece 200 to expose the top sacrificial layer 206T.

[0028] refer to Figure 11After planarization, the first layer 224, the second layer 226, the third layer 234, and the fourth layer 236 are selectively etched back to form grooves, and a cap layer 240 is deposited in these grooves. In some embodiments, the selective etch back can be performed using a dry etching process, which may include oxygen, nitrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. The cap layer 240 may include silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. In some embodiments, the cap layer 240 may be deposited using CVD, HDPCVD, or a suitable deposition technique. After depositing the cap layer 240, the workpiece 200 is planarized using a CMP process to remove excess cap layer 240 located on the cladding layer 232 and the top sacrificial layer 206T. At this point, dielectric fins 230 and junction dielectric fins 230J are substantially formed. Each dielectric fin 230 includes a first layer 224, a second layer 226 above the first layer 224, and a cap layer 240 above the first layer 224 and the second layer 226. The junction dielectric fin 230J includes a third layer 234, a fourth layer 236, and a cap layer 240 above the third layer 234 and the fourth layer 236. Each dielectric fin 230 is positioned directly above the isolation member 218. The junction dielectric fin 230J is positioned directly above the junction isolation member 218J, which is positioned on the deep isolation member 220 above the well junction 2020.

[0029] refer to Figure 1 and Figure 12 Method 100 includes block 114, in which the top sacrificial layer 206T in the fin structure 211 is removed. At block 114, workpiece 200 is etched to selectively remove portions of the cladding layer 232 and the top sacrificial layer 206T to expose the topmost channel layer 208, substantially without damaging the dielectric fins 230 and the cap layer 240 of the junction dielectric fins 230J. Because the top sacrificial layer 206T and the cladding layer 232 are formed of silicon germanium (SiGe), the etching process at block 114 can be selective for silicon germanium (SiGe). In some examples, selective wet etching processes can be used to etch the cladding layer 232 and the top sacrificial layer 206T, including ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof. Figure 12 As shown, after removing the top sacrificial layer 206T and etching the cladding layer 232, the dielectric fins 230 and junction dielectric fins 230J rise above the topmost channel layer 208.

[0030] refer to Figure 1 , Figure 13 and Figure 14 Method 100 includes block 116 in which a dummy gate stack 250 is formed over the channel region of the fin structure 211. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 250 serves as a placeholder for the functional gate structure. Other processes and configurations are possible. Figure 13 As shown, the dummy gate stack 250 includes a dummy dielectric layer 242 and a dummy electrode 244 disposed above the dummy dielectric layer 242. For patterning purposes, a gate top hard mask 248 is deposited above the dummy gate stack 250. The gate top hard mask 248 may be multilayered and includes a silicon nitride mask layer 246 and a silicon oxide mask layer 247 located above the silicon nitride mask layer 246. The region of the fin structure 211 beneath the dummy gate stack 250 may be referred to as a channel region. Each channel region in the fin structure 211 is sandwiched between two source / drain regions for source / drain formation. In an exemplary process, the dummy dielectric layer 242 is blanket-deposited over the workpiece 200 by CVD. Then, a material layer for the dummy electrode 244 is blanket-deposited over the dummy dielectric layer 242. The dummy dielectric layer 242 and the material layer for the dummy electrode 244 are then patterned using a photolithography process to form the dummy gate stack 250. In some embodiments, the dummy dielectric layer 242 may include silicon oxide, and the dummy electrode 244 may include polysilicon.

[0031] refer to Figure 14 At block 116, at least one gate spacer 252 is formed along the sidewall of the dummy gate stack 250. The at least one gate spacer 252 may include two or more gate spacer layers. The dielectric material used for the at least one gate spacer 252 may be selected to allow selective removal of the dummy gate stack 250. Suitable dielectric materials may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride, and / or combinations thereof. In an exemplary process, at least one gate spacer 252 may be conformally deposited over workpiece 200 using CVD, sub-atmospheric CVD (SACVD), or ALD.

[0032] refer to Figure 1 and Figure 14 Method 100 includes a block 118 in which the source / drain regions of the fin structure 211 are recessed to form a source / drain groove 254. With a dummy gate stack 250 and at least one gate spacer 252 serving as an etching mask, the workpiece 200 is anisotropically etched to form the source / drain groove 254 (or source / drain trench 254) over the source / drain regions of the fin structure 211. Figure 14In the embodiment shown, the operation at block 118 can substantially remove the top 212T of the fin structure 211 in the source / drain region. In some other alternative embodiments, the source / drain trench 254 may extend into the base 211B. Anisotropic etching at block 118 may include a dry etching process. For example, the dry etching process may be implemented with hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof.

[0033] refer to Figure 1 , Figure 15 and Figure 16 Method 100 includes block 120, in which internal spacer components 258 are formed. (See reference) Figure 15 At block 120, the sacrificial layer 206 exposed in the source / drain trench 254 is selectively and partially recessed to form internal spacer recesses, while the exposed channel layer 208 is substantially unetched. Because the cladding layer 232 and the sacrificial layer 206 share a similar composition, the cladding layer 232 can also be etched at block 120. In embodiments where the channel layer 208 is substantially composed of silicon (Si), the sacrificial layer 206 is substantially composed of silicon germanium (SiGe), and the cladding layer 232 is substantially composed of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 and the cladding layer 232 may include a SiGe oxidation process, followed by SiGe oxide removal. In that embodiment, the SiGe oxidation process may include the use of ozone. In some other embodiments, selective recessing may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 206 and the cladding layer 232 is controlled by the duration of the etching process. Selective dry etching processes may include using one or more fluorine-based etchants such as fluorine gases or hydrofluorocarbons. Selective wet etching processes may include ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof (e.g., APM etching including an ammonium hydroxide-hydrogen peroxide-water mixture). After forming the internal spacer recesses, an internal spacer material layer is then conformally deposited over the workpiece 200 using CVD or ALD, including over and within the internal spacer recesses and over and within the spacers left by the removal of the overlay layer 232. The internal spacer material may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbide, or silicon oxynitride. After depositing the internal spacer material layer, the internal spacer material layer is etched back to form the internal spacer component 258, as shown below. Figure 16 As shown.

[0034] refer to Figure 1 and Figure 17 Method 100 includes block 122 in which n-type source / drain components 260N and p-type source / drain components 260P are formed. The n-type source / drain components 260N and p-type source / drain components 260P are selectively and epitaxially deposited on the exposed semiconductor surfaces of the substrate 202 and channel layer 208 in the source / drain trench 254. The n-type source / drain components 260N and p-type source / drain components 260P can be sequentially deposited using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In some embodiments, a first mask layer, such as a BARC layer, is deposited to selectively expose the source / drain trench 254 located above the p-well 202P, and then a p-type source / drain component 260P is deposited over the exposed channel layer 208 and substrate 202 above the n-well 202N. After the first mask layer is removed by ashing or stripping, a second mask layer, such as a BARC layer, is deposited to selectively expose the source / drain trench located above the n-well, and then an n-type source / drain component 260N is deposited over the substrate 202 and exposed channel layer above the p-well 202P. The second mask layer is then removed. The formation order of the p-type source / drain component 260P and the n-type source / drain component can be switched. The n-type source / drain component 260N may comprise silicon (Si) doped with an n-type dopant such as phosphorus (P) or arsenic (As). The p-type source / drain component 260P may include silicon germanium (SiGe) doped with p-type dopants such as boron (B) or gallium (Ga). The doping of the source / drain component can be performed in situ during deposition or off-situ using an implantation process such as a junction implantation process.

[0035] Still referencing Figure 1 and Figure 17Method 100 includes block 124 in which a contact etch stop layer (CESL) 262 and an interlayer dielectric (ILD) layer 264 are deposited. In some embodiments, prior to depositing CESL 262, a cap layer 240 of dielectric fins 230 and junction dielectric fins 230J is selectively etched back. In some examples, buffered hydrofluoric acid (BHF) or dilute hydrofluoric acid (DHF) can be used to selectively etch away the cap layer 240. After removing the cap layer 240, CESL 262 is first conformally deposited over workpiece 200, and then the ILD layer 264 is blanket-deposited over CESL 262. CESL 262 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. CESL 262 can be deposited using ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 264 comprises silicon oxide such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 264 can be deposited by spin coating, FCVD processes, or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 264, the workpiece 200 can be annealed to improve the integrity of the ILD layer 264. To remove excess material and expose the top surface of the dummy electrode 244 of the dummy gate stack 250, a planarization process (such as a chemical mechanical polishing (CMP) process) can be performed on the workpiece 200 to provide a flat top surface. The top surface of the dummy electrode 244 is exposed on this flat top surface.

[0036] refer to Figure 1 , Figure 18 , Figure 19 and Figure 20 Method 100 includes block 126, in which the dummy gate stack 250 is replaced with a combined gate structure. The operation at block 126 includes removing the dummy gate stack 250. Figure 18 (As shown), selectively remove the sacrificial layer 206 in the trench area to release the trench component 2080. Figure 19 As shown), and forming a combined gate structure 270 to surround and enclose each channel member 2080 (as shown), and forming a combined gate structure 270 to surround and enclose each channel member 2080. Figure 20 (As shown). Reference Figure 18The dummy gate stack 250 exposed at the end of block 124 is removed from workpiece 200 by a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer 242 and the dummy electrode 244 without substantially damaging the cap layer 240 and at least one gate spacer 252. Removal of the dummy gate stack 250 creates a gate trench 266 located above the channel region.

[0037] After the dummy gate stack 250 is removed, the channel layer 208, sacrificial layer 206, and cladding layer 232 in the channel region are exposed in the gate trench 266. (Reference) Figure 19 The exposed sacrificial layer 206 and cladding layer 232 located between channel layers 208 can be selectively removed to release channel layer 208 as channel member 2080. In the depicted embodiment, the channel member 2080 is like a sheet or nanosheet, and the channel member release process can also be referred to as a sheet formation process. Unlike the channel members of some MBC transistors, the channel member 2080 extends laterally from the sidewalls of the dielectric fin 230. Figure 19 As shown, after their release, the channel members 2080 are spaced apart from the junction dielectric fins 230J. The channel members 2080 are stacked perpendicularly along the Z-direction. Selective removal of the sacrificial layer 206 and the overlay layer 232 can be performed by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof (e.g., APM etching including an ammonium hydroxide-hydrogen peroxide-water mixture). In some alternative embodiments, selective removal includes silicon germanium oxidation, followed by silicon germanium oxide removal. For example, oxidation can be provided by ozone cleaning, and then the silicon germanium oxide can be removed by an etchant such as NH4OH. With the sacrificial layer 206 and the cladding layer 232 removed from the channel region, the dielectric fin 230, junction dielectric fin 230J, channel member 2080, top surface of base 211B, internal spacer member 258, and junction isolation member 218J are exposed in the gate trench 266.

[0038] refer to Figure 20A gate structure 270 is then deposited over the workpiece to surround and enclose each channel member 2080. The gate structure 270 may include an interface layer 267 on the channel member 2080 and the substrate 202, a gate dielectric layer 268 above the interface layer 267, and a gate electrode layer 269 above the gate dielectric layer 268. In some embodiments, the interface layer 267 comprises silicon oxide and may be formed due to a pre-cleaning process. An exemplary pre-cleaning process may include using RCASC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surfaces of the channel member 2080 and the substrate 202 to form the interface layer 267. The gate dielectric layer 268 is then deposited over the interface layer 267 using ALD, CVD, and / or other suitable methods. The gate dielectric layer 268 may include a high-k dielectric material. As used herein, high-k dielectric materials include dielectric materials with high dielectric constants, for example, those greater than that of thermally oxidized silicon. In one embodiment, the gate dielectric layer 268 may include hafnium oxide. Optionally, the gate dielectric layer 268 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After forming or depositing the interface layer 267 and the gate dielectric layer 268, a gate electrode layer 269 is deposited over the gate dielectric layer 268. The gate electrode layer 269 may be a multilayer structure comprising at least one work function layer and a metal filling layer. As an example, the at least one work function layer may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filling layer may comprise aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer 269 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Figure 20As shown, the gate structure 270 surrounds each channel member 2080. It is worth noting that because the channel member 2080 is in contact with the dielectric fin 230, the gate structure 270 does not extend between the dielectric fin 230 and the channel member 2080.

[0039] refer to Figure 1 , Figure 21 and Figure 22 Method 100 includes block 128 in which further processes are performed. These further processes may include, for example, planarization of the gate structure 270, etch-back of the gate structure 270, deposition of a metal capping layer 272, deposition of a self-aligned capping (SAC) layer 274, and formation of a gate dicing feature 276. (See reference...) Figure 21 A planarization process, such as CMP, can be performed on the workpiece 200 until the cap layer 240 is removed and the gate structure 270 is separated by the dielectric fins 230 and the junction dielectric fins 230J. Figure 21 In the planarization process, the gate structure 270 is separated into a first gate structure 270-1, a second gate structure 270-2, a third gate structure 270-3, and a fourth gate structure 270-4. The first gate structure 270-1 and the second gate structure 270-2 are separated by dielectric fins 230. The second gate structure 270-2 and the third gate structure 270-2 are separated by junction dielectric fins 230. The third gate structure 270-3 and the fourth gate structure 270-4 are separated by dielectric fins 230.

[0040] To create space for the metal capping layer 272, the first gate structure 270-1, the second gate structure 270-2, the third gate structure 270-3, and the fourth gate structure 270-4 can be selectively etched back. For example, selective etching of the gate structures can include a selective wet etching process using nitric acid, hydrochloric acid, sulfuric acid, ammonium hydroxide, hydrogen peroxide, or combinations thereof. The metal capping layer 272 is then deposited over the first gate structure 270-1, the second gate structure 270-2, the third gate structure 270-3, and the fourth gate structure 270-4. In some embodiments, the metal capping layer 272 can include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), cobalt (Co), or nickel (Ni), and can be deposited using PVD, CVD, or metal-organic chemical vapor deposition (MOCVD). In one embodiment, the metal capping layer 272 comprises tungsten (W) and is deposited by PVD. In some alternative embodiments, the deposition of the metal capping layer 272 via MOCVD can be selectively deposited on the first gate structure 270-1, the second gate structure 270-2, the third gate structure 270-3, and the fourth gate structure 270-4. After depositing the metal capping layer 272, a SAC layer 274 is deposited over the workpiece 200 via CVD, PECVD, or a suitable deposition process. The SAC layer 274 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. A photolithography and etching process is then performed to etch the deposited SAC layer 274 to form a gate cleaving opening to expose the top surfaces of the dielectric fins 230 and the junction dielectric fins 230J. Subsequently, a dielectric material is deposited and planarized via a CMP process to form gate cleaving features 276 within the gate cleaving opening. The dielectric material for the gate dicing component 276 can be deposited using HDPCVD, CVD, ALD, or a suitable deposition technique. In some examples, the gate dicing component 276 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. In some embodiments, the gate dicing component 276 and the SAC layer 274 may have different compositions to introduce etch selectivity.

[0041] Figure 23 It shows Figure 21A magnified partial cross-sectional view of the channel region of the semiconductor device 200. Each of the first gate structure 270-1, the second gate structure 270-2, the third gate structure 270-3, and the fourth gate structure 270-4 surrounds each of the vertically stacked members enclosing the channel member 2080. The first gate structure 270-1 and the second gate structure 270-2 are separated by dielectric fins 230. The second gate structure 270-2 and the third gate structure 270-3 are separated by junction dielectric fins 230J. The third gate structure 270-3 and the fourth gate structure 270-4 are separated by dielectric fins 230. The base 211B located below the channel member 2080 is separated by the isolation member 218 and the junction isolation member 218J, as well as the lower portion of the dielectric fins 230 and the junction dielectric fins 230J. When viewed along the Y direction, the deep isolation member 220 may have a raised shape. In some embodiments, as shown by dashed lines, the deep isolation member 220 undercuts the channel member 2080 surrounded by the second gate structure 270-2 and the third gate structure 270-3. The deep isolation member 220 also undercuts the base 211B located on both sides of the well junction 2020. In some examples, the deep isolation member 220 may have a first height H1 between about 10 nm and about 100 nm along the Z direction and a first width W1 between about 5 nm and about 50 nm along the X direction. The junction isolation member 218J may be wider than the isolation member 218. In some examples, the isolation member 218 may have a second width W2 between about 10 nm and about 20 nm, and the junction isolation member 218J may have a third width W3 between about 20 nm and about 30 nm. In one embodiment, the first width W1 is greater than the third width W3. In this embodiment, the first width W1 is between about 25 nm and about 50 nm. The isolation component 218 and the junction isolation component 218J may have a second height H2 between about 1 nm and about 20 nm. The deep isolation component 220 and the junction isolation component 218J work together to reduce bulk leakage across the well junction 2020, which is the boundary between the p-well 202P and the n-well 202N.

[0042] Still referencing Figure 23A first gate structure 270-1 controls a first n-type MBC transistor 302 disposed above the p-well 202P. The channel member 2080 of the first n-type MBC transistor 302 extends between two n-type source / drain components 260N. A second gate structure 270-2 controls a second n-type MBC transistor 304 disposed above the p-well 202P. The channel member 2080 of the second n-type MBC transistor 304 extends between two n-type source / drain components 260N. A third gate structure 270-3 controls a first p-type MBC transistor 306 disposed above the n-well 202N. The channel member 2080 of the first p-type MBC transistor 306 extends between two p-type source / drain components 260P. A fourth gate structure 270-4 controls a second p-type MBC transistor 308 disposed above the n-well 202N. The channel component 2080 of the second p-type MBC transistor 308 extends between two p-type source / drain components 260P. When viewed along the Y direction, each of the first gate structure 270-1, the second gate structure 270-2, the third gate structure 270-3, and the fourth gate structure 270-4 includes a fork-like or fishbone-like structure. For this reason, the first n-type MBC transistor 302, the second n-type MBC transistor 304, the first p-type MBC transistor 306, and the second p-type MBC transistor 308 can be referred to as fork transistors or fishbone transistors.

[0043] Based on the above discussion, the advantages provided by the present invention can be seen. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages herein, nor is any particular advantage necessary for all embodiments. For example, adjacent n-wells and p-wells located below a fishbone or fork-plate transistor are separated by a junction isolation component and a deep isolation component disposed below the junction isolation component. The deep isolation component may have a different shape than the junction isolation component. The deep isolation component works in conjunction with the junction isolation component to prevent bulk leakage across the well junction.

[0044] In one aspect, the present invention provides an embodiment of a semiconductor structure comprising a substrate having a p-type well or an n-type well, a first base above the p-type well, a second base above the n-type well, a first plurality of channel members above the first base, a second plurality of channel members above the second base, an isolation member disposed between the first base and the second base, and a deep isolation structure disposed in a substrate below the isolation member.

[0045] In some embodiments, the isolation member and the deep isolation structure extend through the junction between the p-type well and the n-type well. In some embodiments, the deep isolation structure includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbonitride. In some examples, the shape of the isolation member differs from the shape of the deep isolation structure. In some embodiments, the semiconductor structure may further include: a first gate structure surrounding each of the first plurality of channel members; a second gate structure surrounding each of the second plurality of channel members; and a first dielectric fin disposed between the first gate structure and the second gate structure. In some examples, the first dielectric fin is disposed on the isolation member. In some embodiments, a first portion of the first gate structure extends between the first dielectric fin and the first gate structure. In some embodiments, the semiconductor structure may further include a second dielectric fin contacting the sidewalls of the first plurality of channel members. In some embodiments, a second portion of the first gate structure extends between the first dielectric fin and a first base. In some examples, the semiconductor structure may further include a second dielectric fin contacting the first base.

[0046] In another aspect, the present invention provides an embodiment of a semiconductor structure comprising a substrate having a p-type well or an n-type well, a first base above the p-type well, a second base above the n-type well, a first n-type epitaxial member above the first base, a first p-type epitaxial member above the second base, a first isolation member disposed between the first base and the second base, and a deep isolation structure disposed in the substrate directly below the first isolation member.

[0047] In some embodiments, the semiconductor structure may further include a first dielectric fin disposed on a first isolation member. The first dielectric fin is sandwiched between a first n-type epitaxial member and a first p-type epitaxial member, and the width of the first dielectric fin is smaller than the width of the first isolation member. In some embodiments, the shape of the first isolation member differs from the shape of the deep isolation structure. In some examples, the semiconductor structure may further include a third base located above a p-type well, a second n-type epitaxial member located above the third base, and a second isolation member disposed between the first base and the third base. The width of the first isolation member is larger than the width of the second isolation member. In some examples, the semiconductor structure may further include a second dielectric fin disposed above the second isolation member. The second dielectric fin is sandwiched between the first n-type epitaxial member and the second n-type epitaxial member, and the width of the second dielectric fin is substantially the same as the width of the second isolation member.

[0048] In another aspect, the present invention provides an embodiment of a method comprising: receiving a workpiece including a first fin structure located above a p-type well region of a substrate and a second fin structure located above an n-type well region of the substrate, the first fin structure and the second fin structure being separated by a junction trench, extending the junction trench further into the substrate to form a deep cavity, forming a deep isolation member in the deep cavity and forming an isolation member in the junction trench, and forming a dielectric fin on the isolation member, such that the dielectric fin is disposed between the first fin structure and the second fin structure.

[0049] In some embodiments, the method may further include forming a liner along the sidewalls of the junction trench before extending the junction trench. In some embodiments, forming the deep isolation member and the isolation member includes depositing dielectric material in the deep cavity and junction trench and etching back the liner and dielectric material to expose the sidewalls of the first fin structure and the second fin structure. In some examples, the method may further include depositing a semiconductor overlay layer over the sidewalls of the first fin structure and the second fin structure before forming the dielectric fin. In some examples, after forming the dielectric fin, the dielectric fin is spaced apart from the first fin structure and the second fin structure by the semiconductor overlay layer.

[0050] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: Substrates, including p-type wells or n-type wells; The first base is located above the p-type well; The second base is located above the n-type well; The first plurality of channel components are located above the first base, and the first plurality of channel components are stacked on top of each other in the vertical direction; A second plurality of channel components are located above the second base, and the second plurality of channel components are stacked on top of each other in the vertical direction; An isolation component is disposed between the first base and the second base; as well as A deep isolation structure is disposed in the substrate below the isolation component. The isolation component and the deep isolation structure have an intersection point, and at a position between the intersection point and the adjacent sidewall of the isolation component, the deep isolation structure and the isolation component overlap in the vertical direction and are spaced apart from each other.

2. The semiconductor structure according to claim 1, wherein, The isolation component and the deep isolation structure extend through the junction between the p-type well and the n-type well.

3. The semiconductor structure according to claim 1, wherein, The deep isolation structure includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbonitride.

4. The semiconductor structure according to claim 1, wherein, The shape of the isolation component is different from the shape of the deep isolation structure.

5. The semiconductor structure according to claim 1, further comprising: A first gate structure surrounds and encloses each of the first plurality of channel members; A second gate structure surrounds and encloses each of the second plurality of channel members; as well as The first dielectric fin is disposed between the first gate structure and the second gate structure.

6. The semiconductor structure according to claim 5, wherein, The first dielectric fin is disposed on the isolation component.

7. The semiconductor structure according to claim 5, wherein, A first portion of the first gate structure extends between the first dielectric fin and the first gate structure.

8. The semiconductor structure according to claim 7, further comprising: The second dielectric fin contacts the sidewall of the first plurality of channel members.

9. The semiconductor structure according to claim 5, wherein, A second portion of the first gate structure extends between the first dielectric fin and the first base.

10. The semiconductor structure according to claim 9, further comprising: The second dielectric fin contacts the first base.

11. A semiconductor structure, comprising: Substrates, including p-type wells or n-type wells; The first base is located above the p-type well; The second base is located above the n-type well; The first n-type epitaxial component is located above the first base; The first p-type extension component is located above the second base; A first isolation component is disposed between the first base and the second base; A deep isolation structure is disposed in the substrate directly below the first isolation component; A first gate structure is disposed above the first base; A second gate structure is disposed above the second base; as well as The first dielectric fin is disposed on the first isolation component. In this configuration, a first portion of the first gate structure surrounds and encloses each of the first plurality of channel members above the first base, the first plurality of channel members being stacked on top of each other in the vertical direction; a first portion of the second gate structure surrounds and encloses each of the second plurality of channel members above the second base; and second portions of the first gate structure and the second gate structure extend continuously along the sidewalls of the first dielectric fin to the top surface of the first isolation member. The first isolation component and the deep isolation structure have an intersection point. At a position between the intersection point and the adjacent sidewall of the first isolation component, the deep isolation structure overlaps with the first isolation component in the vertical direction and is spaced apart from each other.

12. The semiconductor structure according to claim 11, wherein, The first dielectric fin is sandwiched between the first n-type epitaxial component and the first p-type epitaxial component. The width of the first dielectric fin is smaller than the width of the first isolation component.

13. The semiconductor structure according to claim 11, wherein, The shape of the first isolation component is different from the shape of the deep isolation structure.

14. The semiconductor structure according to claim 11, further comprising: The third base is located above the p-type well; The second n-type epitaxial component is located above the third base; as well as A second isolation component is disposed between the first base and the third base. The width of the first isolation component is greater than the width of the second isolation component.

15. The semiconductor structure according to claim 14, further comprising: The second dielectric fin is disposed above the second isolation component. The second dielectric fin is sandwiched between the first n-type epitaxial component and the second n-type epitaxial component. The width of the second dielectric fin is substantially the same as the width of the second isolation component.

16. A method for manufacturing a semiconductor structure, comprising: The workpiece includes a first fin structure located above a p-type well region of a substrate and a second fin structure located above an n-type well region of the substrate, the first fin structure and the second fin structure being separated by junction trenches. The junction trench is further extended into the substrate to form a deep cavity; A deep isolation component is formed in the deep recess and an isolation component is formed in the knot groove; Dielectric fins are formed on the isolation component, thereby disposing the dielectric fins between the first fin structure and the second fin structure; A first gate structure is formed above the first fin structure; as well as A second gate structure is formed above the second fin structure; In this configuration, a first portion of the first gate structure surrounds and encloses each of the first plurality of channel members of the first fin structure, the first plurality of channel members being stacked on top of each other in the vertical direction; a first portion of the second gate structure surrounds and encloses each of the second plurality of channel members of the second fin structure; and second portions of the first gate structure and the second gate structure extend continuously along the sidewalls of the dielectric fins to the top surface of the isolation member. The isolation component and the deep isolation component have an intersection point, and at a position between the intersection point and the adjacent sidewall of the isolation component, the deep isolation component overlaps with the isolation component in the vertical direction and is spaced apart from each other.

17. The method of claim 16, further comprising: Before extending the knot trench, a liner is formed along the sidewall of the knot trench.

18. The method of claim 17, wherein, The formation of the deep isolation component and the isolation component includes: Dielectric material is deposited in the deep cavity and the junction trench; and The pad and the dielectric material are etched back to expose the sidewalls of the first fin structure and the second fin structure.

19. The method of claim 18, further comprising: Prior to forming the dielectric fins, a semiconductor cladding layer is deposited over the sidewalls of the first fin structure and the second fin structure.

20. The method according to claim 19, wherein, After the dielectric fin is formed, the dielectric fin is spaced apart from the first fin structure and the second fin structure by the semiconductor coating layer.

Images