Semiconductor structure and manufacturing method thereof and flash memory

Abstract

The present invention provides a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, a plurality of first isolation structures, a gate structure and an oxide layer. The first isolation structure defines a first active area in the peripheral area of ​​the substrate. The oxide layer is arranged on the substrate in the first active area and is covered by the first isolation structure. The oxide layer and the first isolation structure define an opening exposing the substrate. The gate structure is arranged on the substrate in the first active area and includes a gate dielectric layer arranged on the substrate in the opening and a gate arranged on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than the width of the top surface of the first active area.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure having a gate dielectric layer in a peripheral region of a substrate and a manufacturing method thereof and a flash memory. Background Art

[0002] As semiconductor devices become smaller, the size of semiconductor components also decreases. For flash memory, the reduction in component size leads to increased process difficulty, making it impossible to increase the coverage area between the control gate and the floating gate, and thus unable to effectively improve the gate coupling ratio (GCR) of the memory structure.

[0003] In addition, for the peripheral area of ​​the substrate, when forming peripheral components (such as logic components), a gate dielectric layer is usually formed on the substrate in the active area first, and then a gate is formed on the gate dielectric layer. However, before forming the gate dielectric layer, the oxide layer on the substrate in the active area needs to be removed to define an opening with a bottom width greater than the top width of the active area and exposing the active area through an isolation structure. As a result, the gate dielectric layer subsequently formed in the opening often has a thinner thickness at the edge of the active area, resulting in uneven thickness of the gate dielectric layer, thereby affecting the performance of the component. Furthermore, since the gate dielectric layer at the edge of the active area is thinner, leakage current is likely to occur at the edge of the active area during the operation of the component. Summary of the invention

[0004] The present invention is directed to a semiconductor structure and a manufacturing method thereof and a flash memory, which can make the gate dielectric layer in the peripheral area of ​​the substrate have a uniform thickness, thereby avoiding the occurrence of leakage current.

[0005] According to an embodiment of the present invention, a semiconductor structure includes a substrate, a plurality of first isolation structures, an oxide layer and a gate structure. The substrate has a peripheral region. The plurality of first isolation structures define a first active region of the substrate in the peripheral region. The oxide layer is disposed on the substrate in the first active region. The oxide layer is covered by the plurality of first isolation structures, and the oxide layer and the plurality of first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active region and includes a gate dielectric layer and a gate. The gate dielectric layer is disposed on the substrate in the opening so that the oxide layer is located around the gate dielectric layer. The gate is disposed on the gate dielectric layer, and the width of the bottom surface of the gate is smaller than the width of the top surface of the first active region.

[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor structure includes the following steps. First, a plurality of first isolation structures are formed in a peripheral region of a substrate to define a first active region in the substrate between the plurality of first isolation structures. Next, an oxide layer is formed on the substrate in the first active region. The oxide layer is covered by the plurality of first isolation structures, and the oxide layer and the plurality of first isolation structures define an opening exposing the substrate. Thereafter, a gate structure is formed on the substrate in the first active region. In addition, the step of forming the gate structure includes the following steps. First, a gate dielectric layer is formed on the substrate in the opening so that the oxide layer is located around the gate dielectric layer. Thereafter, a gate is formed on the gate dielectric layer. The width of the bottom surface of the gate is smaller than the width of the top surface of the first active region.

[0007] According to an embodiment of the present invention, a flash memory comprises a substrate, a plurality of isolation structures, a memory structure and a gate structure. The substrate has a memory area and a peripheral area. The plurality of isolation structures define an active area of ​​the substrate. The memory structure is disposed on the substrate in the memory area. The memory structure comprises a tunneling dielectric layer, a floating gate, a conductive spacer, a control gate and an inter-gate dielectric layer. The tunneling dielectric layer is disposed on the substrate in the active area. The floating gate is disposed on the tunneling dielectric layer. The conductive spacer is disposed on the sidewall of the floating gate. The control gate covers the floating gate and the conductive spacer. The inter-gate dielectric layer is disposed between the control gate and the floating gate and between the control gate and the conductive spacer. The gate structure is disposed on the substrate in the active area in the peripheral area. The width of the bottom surface of the gate structure is smaller than the width of the top surface of the active area in the peripheral area.

[0008] Based on the above, in the peripheral region of the semiconductor structure of the present invention, an oxide layer is provided at the edge of the active region, so that the gate dielectric layer subsequently formed in the opening defined by the oxide layer can have a uniform thickness and can effectively avoid the generation of leakage current. In addition, in the flash memory of the present invention, a conductive spacer is provided on the sidewall of the floating gate in the memory structure, thereby improving the gate coupling rate of the memory structure. In addition, the width of the bottom surface of the gate structure in the peripheral region is smaller than the width of the top surface of the active region in the peripheral region, so that the gate dielectric layer in the gate structure can have a uniform thickness and can effectively avoid the generation of leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1J FIG. 4 is a cross-sectional schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0010] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0011] Figures 1A to 1J FIG. 4 is a cross-sectional schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present invention.

[0012] First, refer to Figure 1A , providing a substrate 100. The substrate 100 is, for example, a silicon substrate. The substrate 100 has a peripheral area 100a and a memory area 100b. The peripheral area 100a is a region for forming various peripheral components (such as logic components), and the memory area 100b is a region for forming various memory structures (such as flash memory cells). Next, an oxide material layer 102, a first conductive layer 104, and a first mask layer 106 are sequentially formed on the substrate 100. In the present embodiment, the first conductive layer 104 is, for example, a polysilicon layer, which is used to make a floating gate in a memory structure formed subsequently. In addition, in the present embodiment, the first mask layer 106 is, for example, a silicon oxide layer or a silicon nitride layer, but the present invention is not limited thereto. In other embodiments, the first mask layer 106 may also be a composite mask layer composed of a silicon nitride layer and a silicon oxide layer.

[0013] Next, refer to Figure 1B , the first conductive layer 104 and the first mask layer 106 in the peripheral area 100a are patterned to form a first stacked structure 108a on the oxide material layer 102 in the peripheral area 100a. In the present embodiment, only one first stacked structure 108a is shown, but the present invention is not limited thereto. In detail, in the present embodiment, a patterned photoresist layer (not shown) covering the memory area 100b and a portion of the peripheral area 100a is formed on the first mask layer 106, and then an anisotropic etching process (such as a reactive ion etching (RIE) process) is performed to remove a portion of the first conductive layer 104 and the first mask layer 106 in the peripheral area 100a to form a first patterned conductive layer 104a and a first patterned mask layer 106a in the peripheral area 100a. Thereafter, the patterned photoresist layer is removed. The method of patterning the first conductive layer 104 and the first mask layer 106 in the peripheral area 100a is well known to those skilled in the art, and the present invention is not limited thereto. The first patterned conductive layer 104a and the first patterned mask layer 106a form a first stacked structure 108a. Then, the first patterned conductive layer 104a in the first stacked structure 108a is partially removed so that the width of the first patterned conductive layer 104a is smaller than the width of the first patterned mask layer 106a. In the present embodiment, the method of removing part of the first patterned conductive layer 104a is, for example, a dry etching process.

[0014] Then, refer to Figure 1C , the first conductive layer 104 and the first mask layer 106 in the memory area 100b are patterned to form a second stacked structure 108b on the oxide material layer 102 in the memory area 100b. In the present embodiment, only three second stacked structures 108b are shown, but the present invention is not limited thereto. In detail, in the present embodiment, a patterned mask layer (not shown) covering the peripheral area 100a and a portion of the memory area 100b is formed, and then an anisotropic etching process (such as a reactive ion etching process) is performed to remove a portion of the first conductive layer 104 and the first mask layer 106 in the memory area 100b to form a second patterned conductive layer 104b and a second patterned mask layer 106b in the memory area 100b. Thereafter, the patterned mask layer is removed. The method of patterning the first conductive layer 104 and the first mask layer 106 in the memory area 100b is well known to those skilled in the art, and the present invention is not limited thereto. The second patterned conductive layer 104b and the second patterned mask layer 106b form a second stacked structure 108b.

[0015] Afterwards, an anisotropic etching process (e.g., reactive ion etching process) is performed using the first stacked structure 108a and the second stacked structure 108b as masks to partially remove the oxide material layer 102 and the substrate 100, so as to form a first trench 110a in the peripheral region 100a and a second trench 110b in the memory region 100b. In the peripheral region 100a, a first active region 100a' is defined between the first trenches 110a, and in the memory region 100b, a second active region 100b' is defined between the second trenches 110b. In addition, the oxide material layer 102 remaining on the substrate 100 in the first active region 100a' and the second active region 100b' is formed into an oxide layer 102a. At this time, the sidewall of the oxide layer 102a in the peripheral region 100a is aligned with the boundary of the top surface of the first active region 100a', and the sidewall of the oxide layer 102a in the memory region 100b is aligned with the boundary of the top surface of the second active region 100b'. In addition, the oxide layer 102a in the second active region 100b' and the second patterned conductive layer 104b can be used as a tunneling dielectric layer and a floating gate in the memory structure formed subsequently.

[0016] In this embodiment, since the component density in the memory area 100b is higher than that in the peripheral area 100a, after the above-mentioned anisotropic etching process is performed, the depth of the formed first trench 110a is greater than the depth of the second trench 110b.

[0017] Next, refer to Figure 1D, forming a first isolation structure 112a in the first trench 110a and forming a second isolation structure 112b in the second trench 110b. In the peripheral region 100a, the first isolation structure 112a covers a portion of the surface of the oxide layer 102a. In detail, in the present embodiment, after forming the first trench 110a and the second trench 110b, an isolation material layer is formed on the substrate 100, and the isolation material layer covers the first stacked structure 108a and the second stacked structure 108b and fills the first trench 110a and the second trench 110b. The isolation material layer is, for example, a spin-on glass (SOG) layer. Then, a planarization process (such as a chemical mechanical polishing (CMP) process) is performed to remove a portion of the isolation material layer until the top surface of the first stacked structure 108a and the top surface of the second stacked structure 108b are exposed. Then, a mask layer (such as a photoresist layer) is formed to cover the peripheral region 100a. Next, a dry etching process is performed using the mask layer and the second stacked structure 108b as masks to remove a portion of the second isolation structure 112b, so that the top surface of the second isolation structure 112b is lower than the top surface of the first isolation structure 112a. Thereafter, the mask layer is removed. Thus, a groove is formed on the second isolation structure 112b between the second stacked structures 108b.

[0018] Then, please refer to Figure 1E , a blanket dry etching process is performed to remove a portion of the first isolation structure 112a and a portion of the second isolation structure 112b, so that the top surface of the first isolation structure 112a and the top surface of the second isolation structure 112b are lowered to the same level and not lower than the top surface of the second patterned conductive layer 104b. In this embodiment, the top surface of the first isolation structure 112a and the top surface of the second isolation structure 112b are lowered to be coplanar with the top surface of the second patterned conductive layer 104b.

[0019] It is worth mentioning that, in this embodiment, although the component density in the memory area 100b is different from that in the peripheral area 100a, which will affect the etching rates in these two areas, Figure 1D In the above steps, the top surface of the second isolation structure 112b is appropriately lower than the top surface of the first isolation structure 112a. Figure 1E After the dry etching process, the top surface of the first isolation structure 112 a and the top surface of the second isolation structure 112 b can be lowered to the same level and can be easily controlled.

[0020] Afterwards, the first patterned mask layer 106a and the second patterned mask layer 106b are removed. Then, a protective layer 114 is formed on the first stacked structure 108a, the second stacked structure 108b, the first isolation structure 112a, and the second isolation structure 112b. In this embodiment, the protective layer 114 is, for example, a nitride layer, but the present invention is not limited thereto. In other embodiments, the protective layer 114 may also be a composite layer composed of an oxide layer and a nitride layer.

[0021] Next, refer to Figure 1F , a mask layer (e.g., a photoresist layer) is formed to cover the memory area 100b. Then, an anisotropic etching process (e.g., a reactive ion etching process) is performed using the mask layer as a mask to remove the protective layer 114 in the peripheral area 100a. Thereafter, the mask layer is removed. Then, the first patterned conductive layer 104a is removed to expose a portion of the oxide layer 102a. After exposing a portion of the oxide layer 102a, an ion implantation process may be performed to implant dopants into the substrate 100 in the peripheral area 100a to adjust the conductivity type of the substrate 100 in the first active area 100a'. Thereafter, a portion of the first isolation structure 112a in the peripheral area 100a may be removed to reduce the top surface height of the first isolation structure 112a, but the present invention is not limited thereto. In the present embodiment, since the protective layer 114 covers the memory area 100b, damage to the film layer in the memory area 100b may be avoided when the first patterned conductive layer 104a and a portion of the first isolation structure 112a are removed.

[0022] Then, refer to Figure 1G , remove the oxide layer 102a in the peripheral area 100a that is not covered by the first isolation structure 112a to expose a portion of the substrate 100. At this time, the remaining oxide layer 102a is located at the edge of the first active area 100a' and forms an oxide layer 116, and the oxide layer 116 is covered by the first isolation structure 112a. Next, a dielectric layer 118 is formed on the substrate 100 exposed by the first isolation structure 112a in the peripheral area 100a. In the present embodiment, the dielectric layer 118 is, for example, an oxide layer, which is used as a gate dielectric layer in a peripheral component (such as a logic component) formed subsequently. At this time, the oxide layer 116 is located around the dielectric layer 118. In addition, the thickness of the dielectric layer 118 may be greater than or equal to the thickness of the oxide layer 116, that is, the top surface of the oxide layer 116 is not higher than the top surface of the gate dielectric layer. Afterwards, a gate material layer 120 is formed on the substrate 100. The gate material layer 120 covers the protection layer 114, the first isolation structure 112a and the dielectric layer 118. In this embodiment, the gate material layer 120 is, for example, a polysilicon layer, which is used as a gate in a peripheral component (eg, a logic component) to be formed subsequently.

[0023] Next, refer to Figure 1H , remove the gate material layer 120 in the memory area 100b, and retain the gate material layer 120 in the peripheral area 100a. Then, remove the protective layer 114 to expose the second patterned conductive layer 104b and the second isolation structure 112b in the memory area 100b. After that, perform an etching process to remove a portion of the second isolation structure 112b so as to be moderately lower than the top surface of the second patterned conductive layer 104b, but not lower than the top surface of the oxide layer 102a. In this embodiment, after removing a portion of the second isolation structure 112b, the top surface of the second isolation structure 112b is coplanar with the top surface of the oxide layer 102a. In this way, the sidewall of the second patterned conductive layer 104b can be exposed to the maximum extent, so as to improve the gate coupling rate of the memory structure formed subsequently.

[0024] Afterwards, a conductive spacer 122 is formed on the sidewall of the second patterned conductive layer 104b. In the present embodiment, the material of the conductive spacer 122 is, for example, polysilicon. The conductive spacer 122 is formed by, for example, first conformally forming a spacer material layer on the substrate 100, and then performing an anisotropic etching process to remove part of the spacer material layer. At this time, the conductive spacer 122 is formed on the sidewall of the second patterned conductive layer 104b, so the bottom surface of the conductive spacer 122 will not be lower than the top surface of the oxide layer 102a.

[0025] In the present embodiment, depending on the spacing between adjacent second patterned conductive layers 104b and the thickness of the inter-gate dielectric layer and the control gate in the memory structure to be formed subsequently, the ratio of the width of the conductive spacer 122 (the thickness of the spacer material layer) to the width of the second patterned conductive layer 104b does not exceed 1:4.5. Preferably, the ratio of the width of the conductive spacer 122 to the width of the second patterned conductive layer 104b is between 1:9 and 1:4.5. For example, when the width of the second patterned conductive layer 104b is 45nm, the width of the conductive spacer 122 does not exceed 10nm, preferably between 5nm and 10nm. The conductive spacer 122 can be used to increase the size of the floating gate in the memory structure to be formed subsequently, so as to improve the gate coupling ratio of the memory structure. In other words, the conductive spacer 122 and the second patterned conductive layer 104b can also be regarded as a floating gate in the memory structure as a whole.

[0026] Then, refer to Fig. 1I, forming a dielectric layer 124 to cover the second patterned conductive layer 104b and the conductive spacer 122. In the present embodiment, the dielectric layer 124 is conformally formed on the substrate 100. In addition, in the present embodiment, the dielectric layer 124 is, for example, an oxide layer, but the present invention is not limited thereto. In other embodiments, the dielectric layer 124 may also be a composite dielectric layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, that is, a well-known ONO composite dielectric layer. Next, a second conductive layer 126 is formed on the dielectric layer 124. In the present embodiment, the second conductive layer 126 is, for example, a polysilicon layer, which is used to make a control gate in a memory structure formed subsequently.

[0027] Afterwards, refer to Figure 1J , remove the second conductive layer 126 and the dielectric layer 124 in the peripheral area 100a to expose the gate material layer 120. At this time, the second conductive layer 126 retained in the memory area 100b serves as the control gate in the memory structure. Then, the gate material layer 120 in the peripheral area 100a is patterned to form a gate 120a. The gate 120a includes a first portion 121a located on the dielectric layer 118 and a second portion 121b located on the first portion 121a, and the width of the first portion 121a is smaller than the width of the second portion 121b. In other words, in this embodiment, the width of the bottom surface of the gate 120a is smaller than the width of the top surface of the first active area 100a'. In this way, the fabrication of the semiconductor structure 10 of this embodiment is completed.

[0028] In the semiconductor structure 10 of the present embodiment, since a conductive spacer 122 is disposed on the sidewall of the floating gate (the second patterned conductive layer 104b) in the memory structure, when the device size is gradually reduced, the memory structure can still have a sufficient gate coupling ratio to avoid a decrease in the performance of the memory structure.

[0029] In addition, for the peripheral components of the peripheral area 100a, since the oxide layer 102a is provided at the edge of the first active area 100a', the gate dielectric layer (dielectric layer 118) subsequently formed in the opening defined by the oxide layer 102a can have a uniform thickness, which solves the problem of the conventional semiconductor structure that the thickness of the gate dielectric layer in the peripheral area is thinner at the edge of the active area, and thus effectively avoids the generation of leakage current.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, It is characterized in that include: a substrate having a peripheral region; A plurality of first isolation structures defining a first active area of ​​the substrate in the peripheral area; an oxide layer disposed on the substrate in the first active region, wherein a top surface of the oxide layer is covered by the first isolation structure, and an opening is defined in the oxide layer and the first isolation structure covering the oxide layer and exposes a portion of the substrate; as well as A gate structure, disposed on the substrate in the first active region, comprising: a gate dielectric layer disposed on the substrate in the opening so that the oxide layer is located around the gate dielectric layer; as well as The gate is disposed on the gate dielectric layer, and the width of the bottom surface of the gate is smaller than the width of the top surface of the first active region.

2. The semiconductor structure according to claim 1, It is characterized in that The gate has a first portion and a second portion, wherein the first portion is disposed on the gate dielectric layer, the second portion is disposed on the first portion, and a width of the first portion is smaller than a width of the second portion.

3. The semiconductor structure according to claim 2, It is characterized in that A sidewall of the first portion is aligned with a sidewall of the gate dielectric layer.

4. The semiconductor structure according to claim 1, It is characterized in that The top surface of the oxide layer is not higher than the top surface of the gate dielectric layer.

5. The semiconductor structure according to claim 1, It is characterized in that An outer sidewall of the oxide layer is aligned with a boundary of a top surface of the first active region.

6. The semiconductor structure according to claim 2, It is characterized in that A portion of the first isolation structure extends to be located between the oxide layer and the second portion of the gate.

7. The semiconductor structure according to claim 1, It is characterized in that The substrate has a memory region, and the semiconductor structure further comprises: a plurality of second isolation structures defining a second active region in the substrate in the memory region; and A memory structure is disposed on the substrate in the memory area and includes: a tunneling dielectric layer disposed on the substrate in the second active region; A floating gate is disposed on the tunneling dielectric layer; A conductive spacer disposed on a sidewall of the floating gate; a control gate covering the floating gate and the conductive spacer; and an inter-gate dielectric layer disposed between the control gate and the floating gate and between the control gate and the conductive spacer, The oxide layer and the tunnel dielectric layer are formed from the same layer.

8. The semiconductor structure according to claim 7, It is characterized in that A bottom surface of the conductive spacer is not lower than a top surface of the tunnel dielectric layer.

9. The semiconductor structure according to claim 7, It is characterized in that A ratio of a width of the conductive spacer to a width of the floating gate does not exceed 1:4.

5.

10. A method for manufacturing a semiconductor structure, It is characterized in that include: forming a plurality of first isolation structures in a peripheral region of the substrate to define a first active region in the substrate between the plurality of first isolation structures; forming an oxide layer on the substrate in the first active region, wherein the oxide layer is covered by the plurality of first isolation structures, and the oxide layer and the plurality of first isolation structures define an opening exposing the substrate; as well as A gate structure is formed on the substrate in the first active region, wherein the step of forming the gate structure comprises: forming a gate dielectric layer on the substrate in the opening so that the oxide layer is located around the gate dielectric layer; as well as A gate is formed on the gate dielectric layer, and a bottom surface of the gate has a width smaller than a top surface of the first active region.

11. The method for manufacturing a semiconductor structure according to claim 10, It is characterized in that The gate has a first portion and a second portion, wherein the first portion is disposed on the gate dielectric layer, the second portion is disposed on the first portion, and a width of the first portion is smaller than a width of the second portion.

12. The method for manufacturing a semiconductor structure according to claim 10, It is characterized in that Also includes: forming a plurality of second isolation structures in the memory region of the substrate to define a second active region in the substrate between the plurality of second isolation structures, wherein the depth of each of the plurality of second isolation structures is less than the depth of each of the plurality of first isolation structures; as well as forming a memory structure on the substrate in the memory region, wherein the memory structure comprises a tunneling dielectric layer and a floating gate disposed on the tunneling dielectric layer, The oxide layer and the tunnel dielectric layer are formed from the same layer.

13. The method for manufacturing a semiconductor structure according to claim 12, It is characterized in that The method for forming the plurality of first isolation structures, the plurality of second isolation structures, the oxide layer and the memory structure comprises: forming an oxide material layer, a first conductive layer, and a first mask layer in sequence on the substrate; Patterning the first conductive layer and the first mask layer in the peripheral region to form a first patterned conductive layer and a first patterned mask layer in the peripheral region, wherein the first patterned conductive layer and the first patterned mask layer constitute a first stacked structure; Partially removing the first patterned conductive layer in the first stacked structure; Patterning the first conductive layer and the first mask layer in the memory region to form a second patterned conductive layer and a second patterned mask layer in the memory region, wherein the second patterned conductive layer and the second patterned mask layer constitute a second stacked structure; Using the first stack structure and the second stack structure as masks, partially removing the oxide material layer and the substrate to form a first trench in the peripheral region and a second trench in the memory region, and forming the tunneling dielectric layer and the floating gate of the memory structure; forming the first isolation structure in the first trench and forming the second isolation structure in the second trench, wherein the first isolation structure covers a portion of the oxide material layer; removing the first patterned mask layer and the second patterned mask layer; removing the first patterned conductive layer; and The oxide material layer not covered by the first isolation structure is removed to form the oxide layer exposing a portion of the substrate.

14. The method for manufacturing a semiconductor structure according to claim 13, It is characterized in that The method for forming the memory structure further includes: After forming a gate material layer in the peripheral region, forming a conductive spacer on the sidewall of the second patterned conductive layer; forming a dielectric layer to cover the second patterned conductive layer and the conductive spacer; and A second conductive layer is formed on the dielectric layer.

15. The method for manufacturing a semiconductor structure according to claim 11, It is characterized in that A sidewall of the first portion is aligned with a sidewall of the gate dielectric layer.

16. The method for manufacturing a semiconductor structure according to claim 13, It is characterized in that The top surface of the oxide material layer is not higher than the top surface of the gate dielectric layer.

17. The method for manufacturing a semiconductor structure according to claim 13, It is characterized in that An outer sidewall of the oxide material layer is aligned with a boundary of a top surface of the first active region.

18. A flash memory, It is characterized in that include: A substrate having a memory region and a peripheral region; A plurality of isolation structures define an active area of ​​the substrate; A memory structure, disposed on the substrate in the memory area, comprising: a tunneling dielectric layer disposed on the substrate in the active region; A floating gate is disposed on the tunneling dielectric layer; A conductive spacer disposed on a sidewall of the floating gate; a control gate covering the floating gate and the conductive spacer; and an inter-gate dielectric layer disposed between the control gate and the floating gate and between the control gate and the conductive spacer; an oxide layer disposed on the substrate in the active area in the peripheral area, wherein a top surface of the oxide layer is covered by the isolation structure in the peripheral area, and an opening is defined in the oxide layer and the isolation structure covering the oxide layer and exposes a portion of the substrate; and A gate structure is disposed on the substrate in the active region in the peripheral region and partially located in the opening, wherein a width of a bottom surface of the gate structure is smaller than a width of a top surface of the active region in the peripheral region.

19. The flash memory according to claim 18, It is characterized in that A bottom surface of the conductive spacer is not lower than a top surface of the tunnel dielectric layer.

20. The flash memory according to claim 18, It is characterized in that A ratio of a width of the conductive spacer to a width of the floating gate does not exceed 1:4.5.

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