Sensing substrate and electronic devices

Abstract

A sensing substrate and an electronic device including the sensing substrate. The sensing substrate includes a sensing unit located on a base substrate. The sensing unit includes a sensing element and a conductive pattern. The sensing element is located on the base substrate and has a light incident surface and a backlight surface relative to each other, and a side surface located between the light incident surface and the backlight surface. The light incident surface is located on the side of the backlight surface facing away from the base substrate. The conductive pattern is located on the side of the sensing element facing away from the base substrate and has a hollow portion and a transparent conductive portion surrounding the hollow portion. The orthographic projection of the hollow portion on the base substrate is at least partially located within the orthographic projection of the sensing element on the base substrate, and the orthographic projection of the transparent conductive portion on the base substrate at least partially overlaps with the orthographic projection of the side surface of the sensing element on the base substrate. The sensing substrate can prevent the electronic device including the sensing substrate from experiencing image unevenness during imaging.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a sensing substrate and an electronic device including the sensing substrate. Background Art

[0002] Flat-panel X-ray detectors (FPXDs) convert invisible X-rays into digital signals that can ultimately be transformed into images. They have the advantage of a highly sensitive signal reading IC (Integrated Circuit) capable of detecting even subtle changes in electrical charge.

[0003] Amorphous silicon (a-Si) X-ray flat-panel detectors are one of the core detection and imaging components of digital radiography (DR) systems in the X-ray field. Compared with CMOS and CCD structures, they have longer X-ray irradiation life and stability, and are therefore gradually becoming the mainstream demand in the current and future markets.

[0004] One of the core technologies of a-Si FPXD lies in pixel design. A good pixel design can ensure that the proportion of the pixel area occupied by the effective photosensitive structure (also known as the pixel fill rate) is as large as possible. Under the condition of a certain pixel fill rate, the light transmittance on the light-entering side of the pixel should also be as large as possible. Therefore, the electrode on the light-entering side of the photosensitive structure is generally made of transparent conductive material. Summary of the Invention

[0005] An embodiment of the present disclosure provides a sensing substrate and an electronic device including the sensing substrate. The sensing substrate can prevent the electronic device from experiencing image unevenness during imaging.

[0006] An embodiment of the present disclosure provides a sensing substrate, comprising a base substrate and a sensing unit located on the base substrate. The sensing unit comprises: a sensing element located on the base substrate, wherein the sensing element has a light incident surface and a backlight surface opposite to each other, and a side surface located between the light incident surface and the backlight surface, wherein the light incident surface is located on a side of the backlight surface facing away from the base substrate; and a conductive pattern located on a side of the sensing element facing away from the base substrate, wherein the conductive pattern has a hollow portion and a transparent conductive portion surrounding the hollow portion, wherein an orthographic projection of the hollow portion on the base substrate is at least partially located within an orthographic projection of the sensing element on the base substrate, and the orthographic projection of the transparent conductive portion on the base substrate at least partially overlaps with an orthographic projection of the side surface of the sensing element on the base substrate.

[0007] For example, the orthographic projection of the side surface on the base substrate is located inside the orthographic projection of the transparent conductive portion on the base substrate.

[0008] For example, the orthographic projection of the transparent conductive portion on the base substrate is a closed frame structure.

[0009] For example, the conductive pattern is configured to be applied with a fixed voltage when the sensing element is in operation.

[0010] For example, the sensing substrate further includes a bias line layer, a first insulating layer, and a second insulating layer located on the base substrate, wherein the bias line layer includes a bias signal line, and the bias line layer includes a bias signal line. In a direction perpendicular to the base substrate, the first insulating layer is located between the sensing element and the conductive pattern; the second insulating layer is located between the bias signal line and the conductive pattern.

[0011] For example, the conductive pattern includes a conductive pattern extension portion extending beyond the light incident surface of the sensing element; the orthographic projection of the light incident surface of the sensing element on the base substrate has a recessed portion, and the recessed portion accommodates at least part of the orthographic projection of the conductive pattern extension portion on the base substrate.

[0012] For example, the bias signal line is electrically connected to the sensing element and to the conductive pattern.

[0013] For example, the second insulating layer includes a via hole passing through the second insulating layer, the conductive pattern is electrically connected to the bias signal line through the via hole, and the orthographic projection of the via hole on the base substrate at least partially overlaps with the orthographic projection of the transparent conductive portion of the conductive pattern on the base substrate.

[0014] For example, the bias signal line includes a bias line protruding portion that protrudes beyond the light incident surface of the sensing element, and the bias line protruding portion is electrically connected to the conductive pattern through the via hole.

[0015] For example, the sensing unit further includes a switching element, and an orthographic projection of the switching element on the substrate is at least partially located within an orthographic projection of the excess portion of the bias line on the substrate.

[0016] For example, the sensing substrate includes a plurality of sensing units spaced apart from each other, and the conductive patterns of the plurality of sensing units are independent of each other.

[0017] For example, the entire conductive pattern is separated from the bias signal line by the second insulating layer.

[0018] For example, the sensing substrate includes a plurality of sensing units spaced apart from each other and includes a plurality of first conductive bridges spaced apart from each other and a plurality of second conductive bridges spaced apart from each other located on the base substrate, each first conductive bridge extends along a first direction and electrically connects the conductive patterns of the sensing units adjacent in the first direction, each second conductive bridge extends along a second direction and electrically connects the conductive patterns of the sensing units adjacent in the second direction, and the second direction is different from the first direction.

[0019] For example, the conductive patterns of the multiple sensing units are arranged into multiple conductive pattern columns, multiple first conductive pattern rows and multiple second conductive pattern rows; adjacent conductive patterns in the same conductive pattern column are electrically connected through the first conductive bridge; adjacent conductive patterns in the same first conductive pattern row are electrically connected through the second conductive bridge; adjacent conductive patterns in the same second conductive pattern row are independent of each other; the multiple first conductive pattern rows and the multiple second conductive pattern rows are alternately arranged.

[0020] For example, the bias line layer includes a plurality of bias signal lines spaced apart from each other, and an orthographic projection of each bias signal line on the base substrate overlaps with an orthographic projection of first conductive bridges sequentially arranged along the first direction on the base substrate.

[0021] For example, the sensing substrate includes a sensing area and a border area surrounding the sensing area; in the border area, the sensing substrate includes a bias short-circuit ring located on the base substrate and a plurality of third conductive bridges spaced apart from each other, and the bias short-circuit ring is electrically connected to the conductive patterns of the sensing units adjacent to the bias short-circuit ring through the plurality of third conductive bridges.

[0022] For example, the sensing substrate further includes a binding area and a protective pattern, the bias line layer includes a bias line signal end located in the binding area, the protective pattern and the conductive pattern are located in the same layer and in the binding area, and the protective pattern is in direct contact with the bias line signal end.

[0023] For example, the sensing unit further includes a switch element, the switch element is electrically connected to the sensing element, and an orthographic projection of the switch element on the base substrate is outside an orthographic projection of the light incident surface of the sensing element on the base substrate.

[0024] For example, an orthographic projection of the conductive pattern on the base substrate overlaps with an orthographic projection of at least part of the switching element on the base substrate.

[0025] For example, the sensing element includes a first electrode and a second electrode arranged opposite to each other, the first electrode being located between the second electrode and the substrate in a direction perpendicular to the substrate; the sensing element also includes a semiconductor layer located between the first electrode and the second electrode in a direction perpendicular to the substrate, and the orthographic projection of the transparent conductive portion on the substrate at least partially overlaps with the orthographic projection of the side surface of the semiconductor layer on the substrate.

[0026] An embodiment of the present disclosure provides an electronic device, which includes the sensing substrate described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0028] Figure 1 A simplified cross-sectional diagram of a pixel structure of an X-ray flat panel detector.

[0029] Figure 2A A partial top view of the sensing substrate provided in an embodiment of the present disclosure Figure 1 .

[0030] Figure 2B For the Figure 2A Schematic diagram of the cross-section of the AB line and the MN line Figure 1 .

[0031] Figure 2C For the Figure 2A Schematic diagram of the cross-section of line AB and line MN in Figure 2.

[0032] Figure 3A A second partial top view of a sensing substrate provided in an embodiment of the present disclosure.

[0033] Figure 3B For the Figure 3A Schematic diagram of the cross-section of the AB and MN lines Figure 1 .

[0034] Figure 3C For the Figure 3A Schematic diagram of the cross-section of lines AB and MN in Figure 2.

[0035] Figure 4 for Figure 2A and Figure 3A Schematic diagram of the top view of the middle part of the structure.

[0036] Figure 5A A schematic top view of four sensing units in a sensing substrate provided in an embodiment of the present disclosure Figure 1 .

[0037] Figure 5B This is a schematic top view of the conductive patterns in the sensing substrate provided by an embodiment of the present disclosure being independent of each other.

[0038] Figure 6A FIG2 is a second schematic top view of four sensing units in a sensing substrate provided in an embodiment of the present disclosure.

[0039] Figure 6B A schematic top view of interconnected conductive patterns in a sensing substrate provided by an embodiment of the present disclosure.

[0040] Figure 7 A simplified top view of a sensing substrate provided in an embodiment of the present disclosure is shown.

[0041] Figure 8 A partial cross-sectional diagram of a binding region of a sensing substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0044] Figure 1 FIG. 1 is a simplified cross-sectional diagram of a pixel structure of an X-ray flat panel detector. Figure 1As shown, the X-ray flat panel detector includes a substrate BS and structures such as a photosensitive element LS0, a switch element T, and an insulating layer PVX located thereon. For example, the photosensitive element LS0 includes a first electrode E1 and a second electrode E2 arranged opposite to each other, and a PIN-type semiconductor layer PIN located therebetween, that is, an intrinsic semiconductor layer (i.e., an I-type semiconductor layer) is sandwiched between the P-type semiconductor layer and the N-type semiconductor layer. The second electrode E2 of the photosensitive element LS0 is electrically connected to the bias signal line BL so that a bias voltage is applied to the photosensitive element LS0 during operation, and this bias voltage sets the photosensitive element LS0 in a biased state. The first electrode E1 of the photosensitive element LS0 is electrically connected to the switch element T, and the read signal line RSL is electrically connected to the switch element T to read the output signal of the photosensitive element LS0. A light shielding structure SDM is provided on the upper side of the switch element T, and the light shielding structure SDM is provided on the same layer as the bias signal line BL.

[0045] The inventors of this application have noticed in their research that Figure 1 In the semiconductor layer, there is no protection above the PIN sidewall. When the product is disturbed by uneven external potential or affected by unevenly distributed charged ions, a new electric field is generated due to the mechanism of induced electrons. This electric field is superimposed on the original reverse bias electric field vector of the PIN, resulting in inconsistent electric fields between pixels. As a result, the amount of electron migration between different pixels is different within the same integration time. This manifests as uneven grayscale of the product image, that is, Mura appears on the image. On the other hand, the demand for image quality uniformity of X-ray flat-panel detector imaging also requires that the electrical differences of pixels at various positions on the entire detector be as small as possible. In this case, due to Figure 1 The top layer of the pixel structure shown is protected by an insulating layer PVX. Local static electricity residue is very likely to occur on the surface of the insulating layer PVX, which will affect the lateral electric field of the underlying PIN structure, thereby causing image unevenness due to static electricity distribution, which seriously affects the imaging quality.

[0046] In order to improve imaging quality, embodiments of the present disclosure provide a sensing substrate and an electronic device including the sensing substrate.

[0047] Figure 2A A partial top view of the sensing substrate provided in an embodiment of the present disclosure Figure 1 ; Figure 2B For the Figure 2A Schematic diagram of the cross-section of the AB line and the MN line Figure 1 ; Figure 2C For the Figure 2A Schematic diagram of the cross section of line AB and line MN in FIG2; Figure 3A A second partial top view of a sensing substrate provided in an embodiment of the present disclosure; Figure 3B For the Figure 3A Schematic diagram of the cross-section of the AB and MN lines Figure 1 ; Figure 3C For the Figure 3A Schematic diagram of the cross section of lines AB and MN in FIG2; Figure 4 for Figure 2A and Figure 3A Schematic diagram of the top view of the middle part of the structure.

[0048] like Figures 2A to 4 As shown, an embodiment of the present disclosure provides a sensing substrate, which includes a base substrate BS and a first insulating layer IL1 located on the base substrate BS. The sensing substrate also includes a sensing unit located on the base substrate BS, the sensing unit including a sensing element LS. The sensing element LS is located on the side of the first insulating layer IL1 facing the base substrate BS, that is, the sensing element LS is located between the first insulating layer IL1 and the base substrate BS in a direction perpendicular to the base substrate BS. The sensing element LS has a light incident surface SFE and a backlight surface SFB facing each other, and a side surface SFL located between the light incident surface SFE and the backlight surface SFB. The light incident surface SFE is located on the side of the backlight surface SFB facing away from the base substrate BS, that is, the backlight surface SFB is located between the light incident surface SFE and the base substrate BS in a direction perpendicular to the base substrate BS.

[0049] The sensing unit also includes a conductive pattern CP located on the side of the first insulating layer IL1 facing away from the base substrate BS. Specifically, the first insulating layer IL1 is located between the conductive pattern CP and the base substrate BS in a direction perpendicular to the base substrate BS. In this case, the conductive pattern CP is located on the side of the sensing element LS facing away from the base substrate BS. The conductive pattern CP includes a hollow portion HLP and a transparent conductive portion CDP surrounding the hollow portion HLP. The hollow portion HLP is an opening extending through the transparent conductive portion CDP. Specifically, the orthographic projection of the conductive pattern CP on the base substrate BS includes an outer edge CP1 and an inner edge CP2 located inward of the outer edge. The orthographic projection of the hollow portion HLP on the base substrate BS is the area enclosed by the inner edge CP2, and the orthographic projection of the transparent conductive portion CDP on the base substrate BS is the area between the inner edge CP2 and the outer edge CP1. The orthographic projection of the hollow portion HLP on the base substrate BS is at least partially located within the orthographic projection of the sensing element LS on the base substrate BS, and the orthographic projection of the transparent conductive portion CDP on the base substrate BS at least partially overlaps with the orthographic projection of the side surface SFL of the sensing element LS on the base substrate BS.

[0050] For example, Figure 2A and Figure 3A As shown, the orthographic projection of the transparent conductive portion CDP on the base substrate BS overlaps with the orthographic projection of the entire side surface SFL of the sensing element LS on the base substrate BS. That is, the orthographic projection of the side surface SFL on the base substrate BS is located inside the orthographic projection of the transparent conductive portion CDP on the base substrate BS.

[0051] In the disclosed embodiment, a conductive pattern CP is provided on the side of the first insulating layer IL1 facing away from the base substrate BS. The transparent conductive portion CDP of the conductive pattern CP at least partially overlaps the orthographic projection of the side surface SFL of the sensing element LS on the base substrate BS. Therefore, the transparent conductive portion CDP of the conductive pattern CP can shield the electric field of the underlying sensing element LS from static electricity. This design can theoretically provide effective electrostatic shielding for processes that may cause residual static electricity during the sensing substrate manufacturing process (such as washing, handling, and electrostatic discharge caused by poor equipment grounding). It also provides electrostatic protection for post-production processes of the sensing substrate (such as attaching an OCA (optical clear adhesive) layer and performing suction cup handling). Ultimately, this design significantly reduces the incidence of electrostatic mura and image non-uniformity, thereby improving product yield. Furthermore, this design has little impact on the photoelectric sensitivity of the sensing substrate. Furthermore, the conductive pattern CP can also facilitate the dissipation of locally generated static electricity. On the other hand, by providing the conductive pattern CP with a hollow portion HLP, the hollow portion HLP and the orthographic projection of the light incident surface SFE of the sensing element LS on the base substrate BS at least partially overlap, thereby improving the transmittance of the conductive pattern CP to light (especially visible light), thereby allowing more light to be sensed by the sensing element LS. In addition, in the subsequent process, the sensing substrate needs to be coated with resin and evaporated with scintillator materials such as cesium iodide. Since the conductive pattern CP in the embodiment of the present disclosure has a hollow portion HLP, the bonding force between the sensing substrate and the resin layer or the scintillator material such as cesium iodide in the embodiment of the present disclosure is better. For example, when the area of the conductive pattern CP is large, the bonding force between the sensing substrate and the resin layer or the cesium iodide layer may be poor. At this time, the patterned design of the conductive pattern CP (such as a hollow design) can reduce the coverage area of the conductive pattern CP on the sensing substrate, thereby ensuring the anti-static effect while improving the bonding force between the sensing substrate and the resin layer or the scintillator material such as cesium iodide.

[0052] In at least one embodiment, the sensing element LS may be a photodetection element, such as a photodiode. Figures 2B-2C and Figures 3B-3CAs shown, the sensing element LS includes a first electrode E1 and a second electrode E2 disposed opposite each other. The first electrode E1 is located between the second electrode E2 and the base substrate BS in a direction perpendicular to the base substrate BS. The light incident surface SFE of the sensing element LS is the surface of the second electrode E2 facing away from the base substrate BS, and the second electrode E2 is a transparent electrode. For example, the material of the second electrode E2 can be a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide). For example, the material of the first electrode E1 can be a metal or a transparent conductive oxide. The sensing element LS further includes a semiconductor layer SCL positioned between the first electrode E1 and the second electrode E2 in a direction perpendicular to the base substrate BS. A side surface SFL of the sensing element LS includes the side surface of the semiconductor layer SCL. This side surface forms an angle with the surface of the base substrate BS of, for example, 70°-90°, such as approximately 80°. The orthographic projection of the side surface of the semiconductor layer SCL on the base substrate BS at least partially overlaps with the orthographic projection of the transparent conductive portion CDP on the base substrate BS. For example, the entire orthographic projection of the side surface of the semiconductor layer SCL on the base substrate BS overlaps with the orthographic projection of the transparent conductive portion CDP on the base substrate BS. For example, the semiconductor layer SCL is a PIN-type semiconductor layer, meaning that the semiconductor layer SCL includes a P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer stacked in sequence. In other embodiments, the sensing element LS may also be a detection element of other types.

[0053] exist Figure 4 In FIG, LS1 represents the orthographic projection of the edge of the first electrode E1 on the base substrate BS, LS2 represents the orthographic projection of the edge of the second electrode E2 on the base substrate BS, and the area enclosed by LS2 represents the orthographic projection of the light incident surface of the sensing element LS on the base substrate BS. Figure 2A 、 Figure 3A and Figure 4 As shown, the conductive pattern CP blocks the orthographic projection LS2 of the edge of the second electrode E2 on the base substrate BS, which can achieve a better shielding effect.

[0054] For example, in some cases, in actual products, the second electrode E2 does not block the side surface of the semiconductor layer SCL. In this case, the orthographic projection of the side surface SFL of the semiconductor layer SCL on the base substrate BS is outside the orthographic projection of the second electrode E2 on the base substrate BS.

[0055] For example, in other cases, in actual products, the second electrode E2 does not cover the entire upper surface of the semiconductor layer SCL, which is the surface of the semiconductor layer SCL away from the substrate BS. Figures 2B-2CAs shown in 3B-3C, the upper surface of the semiconductor layer SCL has a portion extending beyond the second electrode E2, and the orthographic projection of this portion on the base substrate BS is outside the orthographic projection of the lower surface of the second electrode E2 (the surface of the second electrode E2 facing the base substrate BS) on the base substrate BS.

[0056] In at least one embodiment, the transparent conductive portion CDP of the conductive pattern CP may be made of a transparent conductive oxide, such as at least one or more of ITO (indium tin oxide), IZO (indium zinc oxide), and IGZO (indium gallium zinc oxide). In other words, the layer where the transparent conductive pattern CP is located is at least one or more of an ITO layer, an IZO layer, and an IGZO layer.

[0057] In at least one embodiment, Figure 2A and Figure 3A As shown, the orthographic projection of the transparent conductive portion CDP on the base substrate BS is a closed frame-like structure. This facilitates the transparent conductive portion CDP shielding more of the side surface SFL of the sensing element LS, thereby improving the shielding effect. In other embodiments, the orthographic projection of the transparent conductive portion CDP on the base substrate BS may also be non-enclosed.

[0058] For example, Figure 2A and Figure 3A As shown, the frame-shaped transparent conductive portion CDP includes a plurality of strip-shaped extensions, for example, at least one extending portion along a first direction ( Figure 2A and Figure 3A in the vertical direction) and in the second direction ( Figure 2A and Figure 3A In one embodiment, the present invention relates to a first extension portion, comprising two extension portions opposite to each other in a horizontal direction (in a horizontal direction in the first direction), and two extension portions extending along the second direction and opposite to each other in the first direction. Taking into account the process etching margin, in order to avoid the extension portion being too thin and affecting the resistance, for example, each extension portion includes an inner portion overlapping with the sensing element LS and an outer portion that does not overlap with the sensing element LS. For example, in the arrangement direction of the inner portion and the outer portion, the width of the inner portion is greater than the width of the outer portion. For example, in the arrangement direction of the inner portion and the outer portion, the width of the inner portion is approximately 6μm-8μm, for example, 7.15μm, and the width of the outer portion is approximately 2μm-3μm, for example, 2.65μm, so the total width of the extension portion is approximately 8μm-11μm, for example, 9.8μm.

[0059] For example, the inner edge CP2 of the orthographic projection of the conductive pattern CP on the base substrate BS is parallel to the edge LS1 or LS2 of the orthographic projection of the sensing element LS on the base substrate BS, and the distances between each position of the inner edge CP2 of the orthographic projection of the conductive pattern CP on the base substrate BS and the edge LS1 or LS2 of the orthographic projection of the sensing element LS on the base substrate BS are basically the same.

[0060] For example, the conductive pattern CP is located in a pixel region defined by the intersection of the data line DL and the gate line GL, and the orthographic projection of the conductive pattern CP on the base substrate BS does not overlap with the orthographic projection of the data line DL and the gate line GL on the base substrate BS.

[0061] In at least one embodiment, Figures 2A to 4 As shown, the sensing unit included in the sensing substrate also includes a switching element T ( Figure 2A and Figure 3A (not shown in the figure), the switch element T is electrically connected to the sensing element LS and is used to control the output of the electrical signal of the sensing element LS. The orthographic projection of the switch element T on the base substrate BS is located outside the orthographic projection of the light incident surface SFE of the sensing element LS on the base substrate BS. For example, in other embodiments, the orthographic projection of the switch element T on the base substrate BS may at least partially overlap with the orthographic projection of the sensing element LS on the base substrate BS. For example, the orthographic projection of the switch element T on the base substrate BS is located within the orthographic projection of the sensing element LS on the base substrate BS.

[0062] In at least one embodiment, Figures 2A to 3C As shown, the conductive pattern CP extends to the location of the switching element T so that the transparent conductive portion CDP of the conductive pattern CP has a larger area and thus has a smaller resistance. In other words, the orthographic projection of the conductive pattern CP on the base substrate BS overlaps with the orthographic projection of at least part of the switching element T on the base substrate BS. For example, the orthographic projection of the conductive pattern CP on the base substrate BS overlaps with the orthographic projection of the bias line extending portion BLE of the bias signal line BL (i.e., the portion of the bias signal line BL that blocks the switching element T) on the base substrate BS. The orthographic projection of the conductive pattern CP on the base substrate BS overlaps with the outer boundary of the bias line extending portion BLE or is slightly inside the outer boundary to avoid forming additional overlapping capacitance with the underlying metal layer.

[0063] For example, Figure 2A and Figure 3AAs shown, the switch element T is located in the area enclosed by the sensing element LS and the data line DL and gate line GL adjacent to the sensing element LS, and the transparent conductive portion CDP of the conductive pattern CP extends into this area. In at least one embodiment, the transparent conductive portion CDP does not overlap with either the data line DL or the gate line GL to avoid parasitic capacitance. For example, the distance between the transparent conductive portion CDP and the orthographic projection of the data line DL on the substrate BS is approximately 4μm-5μm, such as 4.35μm, which substantially does not affect the parasitic capacitance of the data line DL, thereby avoiding increased noise. For example, the distance between the transparent conductive portion CDP and the gate line GL is approximately 1μm-2μm, such as 1.25 microns. For example, the distance between the sensing element LS and the data line DL is greater than the distance between the sensing element LS and the gate line GL. Because the parasitic capacitance generated by the data line DL affects image noise, increasing the distance between the sensing element LS and the data line DL can reduce the parasitic capacitance. Accordingly, the distance between the transparent conductive portion CDP and the data line DL is greater than the distance between the transparent conductive portion CDP and the gate line GL.

[0064] For example, the switch element T may be a transistor (e.g., a thin film transistor) or other types of switching devices. For example, the thin film transistor may be an amorphous silicon thin film transistor, an oxide thin film transistor, or an LTPS thin film transistor. For example, the switch element T is a transistor. Figures 2A to 4 As shown, the switching element T includes a gate GE, an active layer ACT, and a source S and a drain D electrically connected to the active layer ACT. For example, the source S is electrically connected to the sensing element LS to receive the electrical signal output by the sensing element LS, and the electrical signal is output to the data line DL (as shown in FIG. 1 ) through the drain D. Figure 2A 、 Figure 3A and Figure 4 shown).

[0065] For example, the source S and drain D of the switching element T are located in the same layer (i.e., formed by the same thin film) to save process. For example, the source S of the switching element T and the first electrode E1 of the sensing element LS can be located in the same layer or in different layers (i.e., formed by different thin films). In the embodiment of the present disclosure, for example, after the layer where the source S and drain D are located is formed on the base substrate BS, a first passivation insulating layer PVX1 is also formed on the base substrate BS; for example, the first passivation insulating layer PVX1 can be an inorganic insulating layer, and the inorganic insulating layer includes a stack of one or more of silicon oxide, silicon nitride, and silicon oxynitride; in some examples, the first passivation insulating layer PVX1 can also be an organic insulating layer, or it can also be a multilayer stack structure of an inorganic insulating layer, an organic insulating layer, and an inorganic insulating layer to prevent the sensing element LS from affecting the switching element T and better ensure the performance of the switching element T. If the source S and the first electrode E1 are located in the same layer, it is necessary to etch away the material of the first passivation insulating layer PVX1 on the first electrode E1, which will cause the surface of the first electrode E1 to be relatively rough, thereby affecting the performance of the semiconductor layer SCL and further affecting the performance of the sensing element LS. Therefore, an optional approach is to locate the source S of the switching element T and the first electrode E1 of the sensing element LS in different layers. For example, Figures 2B-2C and Figures 3B-3C As shown, the source S of the switching element T and the first electrode E1 of the sensing element LS are located in different layers, the first electrode E1 is electrically connected to the source S through a via VH3 that penetrates the first passivation insulating layer PVX1, and the portion of the first electrode E1 located in the via VH3 is located on the side of the source S that is away from the substrate BS.

[0066] In at least one embodiment, in order to avoid the switch element T, the orthographic projection of the sensing element LS on the base substrate BS is recessed toward the center of the sensing element LS to form a notch (hereinafter referred to as a recessed portion) that accommodates at least a portion of the switch element T. For example, Figure 4 As shown, the orthographic projection of the light incident surface SFE of the sensing element LS on the substrate BS has a concave portion CVT. In at least one embodiment, the conductive pattern CP can extend into the concave portion CVT to have a larger area. For example, Figures 2A to 3C As shown, the conductive pattern CP includes a conductive pattern extension portion CEP extending beyond the light incident surface SFE of the sensing element LS; Figure 2A and Figure 3A As shown, the recessed portion (not marked in the figure) accommodates at least a portion of the orthographic projection of the conductive pattern extension portion CEP on the base substrate BS.

[0067] In at least one embodiment, the conductive pattern CP is configured to be applied with a fixed voltage when the sensing element LS is in operation. For example, the conductive pattern CP is electrically connected to a structure on the sensing substrate that can provide a fixed voltage, such as a bias signal line, so that the fixed voltage is applied to the conductive pattern CP through the structure to prevent the conductive pattern CP from being in a floating state.

[0068] For example, Figures 2A to 4 As shown, the sensing substrate further includes a bias line layer BLL located on the base substrate BS. The bias line layer BLL includes a bias signal line BL. The bias signal line BL is electrically connected to the sensing element LS. For example, the bias signal line BL is electrically connected to the sensing element LS through a via VH2 to provide a bias voltage to the sensing element LS. This bias voltage sets the sensing element LS in a biased state. For example, the bias signal line BL can be made of a material such as metal.

[0069] In at least one embodiment, Figure 2A and Figure 3A As shown, the bias signal line BL includes a bias line exceeding portion BLE that exceeds the light incident surface SFE of the sensing element LS; the bias line exceeding portion BLE blocks at least a portion of the switching element TFT, that is, the orthographic projection of the switching element T on the substrate BS is at least partially located within the orthographic projection of the bias line exceeding portion BLE on the substrate BS, so as to prevent the switching element T from being affected by light.

[0070] In at least one embodiment, the bias signal line BL is electrically connected to the conductive pattern CP. For example, the bias line extending portion BLE of the bias signal line BL is electrically connected to the conductive pattern CP. By electrically connecting the bias signal line BL to the conductive pattern CP, the bias voltage of the conductive pattern CP and the second electrode E2 of the sensing element LS can be made equal in potential, thereby preventing the generation of additional capacitance between the second electrode E2 and the conductive pattern CP.

[0071] In at least one embodiment, Figures 2B-2C and Figures 3B-3C As shown, the sensing substrate includes a second insulating layer IL2 located on the base substrate BS, and the second insulating layer IL2 is located between the bias signal line BL and the conductive pattern CP in a direction perpendicular to the base substrate BS. Figures 2B-2C as well as Figures 3B-3CThe illustrated embodiment uses as an example an arrangement in which the bias signal line BL is located on the side of the second insulating layer IL2 facing the base substrate BS, and the conductive pattern CP is located on the side of the second insulating layer IL2 facing away from the base substrate BS. In this case, the second insulating layer IL2 is located on the side of the first insulating layer IL1 facing away from the base substrate BS. In other embodiments, the positional relationship between the bias signal line BL and the conductive pattern CP may be reversed, in which case, for example, the second insulating layer IL2 and the first insulating layer IL1 may be the same insulating layer.

[0072] In some embodiments, the electrical connection between the bias signal line BL and the conductive pattern CP can be achieved through a via provided near the sensing element LS; alternatively, the bias signal line BL and the conductive pattern CP can both be electrically connected to a conductive structure in the border area of the sensing substrate, thereby achieving electrical connection through the conductive structure.

[0073] In at least one embodiment, Figures 2B-2C The bias signal line BL is electrically connected to the conductive pattern CP via a via VH1 extending through the second insulating layer IL2. For example, the conductive pattern extension CEP is filled into VH1 to electrically connect the bias line extending portion BLE. For example, the orthographic projection of the via VH1 on the substrate BS is located within the orthographic projection of the switch element T on the substrate BS. In the disclosed embodiment, the location where the conductive pattern CP is electrically connected to the bias signal line BL is located within the sensing unit region SR where the conductive pattern CP is located, which helps reduce voltage drop.

[0074] In at least another embodiment, the conductive pattern CP and the bias signal line BL may not be electrically connected through the via hole VH1. For example, Figures 3B-3C As shown, within the region SR where the sensing unit is located, the entire conductive pattern CP is separated from the bias signal line BL by the second insulating layer IL2. That is, within the region SR where the sensing unit is located, the conductive pattern CP and the bias signal line BL are not electrically connected via the via VH1. Instead, the entire surface of the conductive pattern CP facing the bias signal line BL and the entire surface of the bias signal line BL facing the conductive pattern CP are parallel to each other.

[0075] Figure 5A A schematic top view of four sensing units in a sensing substrate provided in an embodiment of the present disclosure Figure 1 ; Figure 5B A schematic top view of the conductive patterns in the sensing substrate provided in the embodiment of the present disclosure are independent of each other. Figure 5AAs shown in FIG, the sensing substrate includes a plurality of sensing units spaced apart from each other (four sensing units are shown in the figure, and the region where each sensing unit is located is represented by SR). When the electrical connection position between the conductive pattern CP and the bias signal line BL is located within the region SR where the conductive pattern CP is located (i.e., the conductive pattern CP and the bias signal line BL are electrically connected together through the via hole VH1), as shown in FIG. Figure 5A and Figure 5B As shown, the conductive patterns CP included in the multiple sensing units are independent of each other, that is, the orthographic projections of the conductive patterns CP included in the multiple sensing units on the base substrate BS are isolated from each other and are not connected together, so that the orthographic projection of the transparent conductive layer where the conductive pattern CP is located on the base substrate BS does not overlap with the orthographic projections of the gate line GL and the data line DL on the base substrate BS.

[0076] When the entire conductive pattern CP is separated from the bias line layer BLL by the second insulating layer IL2, a fixed voltage can be provided to the conductive pattern CP in the following manner: the conductive patterns CP of multiple sensing units on the sensing substrate are electrically connected to each other, and the conductive pattern CP included in the outermost sensing unit is electrically connected to the signal line in the border area that can provide a fixed voltage.

[0077] Figure 6A A second schematic top view of four sensing units in a sensing substrate provided in an embodiment of the present disclosure; Figure 6B A schematic top view of interconnected conductive patterns in a sensing substrate provided by an embodiment of the present disclosure.

[0078] In at least one embodiment, Figure 6A As shown, in a case where the entire conductive pattern CP is separated from the bias signal line BL by the second insulating layer IL2, the sensing substrate includes a plurality of sensing units spaced apart from each other and includes a plurality of first conductive bridges BDG1 spaced apart from each other and a plurality of second conductive bridges BDG2 spaced apart from each other on the base substrate BS ( Figure 6A Only one first conductive bridge BDG1 and one second conductive bridge BDG2 are shown for illustration purposes. The first conductive bridge BDG1 extends along a first direction and electrically connects the conductive patterns CP of adjacent sensing units in the first direction. Each second conductive bridge BDG2 extends along a second direction and electrically connects the conductive patterns CP of adjacent sensing units in the second direction, the second direction being different from the first direction. For example, the line width of the first conductive bridge BDG1 and the second conductive bridge BDG2 is 8μm-12μm, for example, approximately 10μm, to ensure reliable electrical connection.

[0079] In at least one embodiment, Figure 6BAs shown, the conductive patterns CP included in the plurality of sensing units in the sensing substrate may be arranged into a plurality of conductive pattern columns, a plurality of first conductive pattern rows, and a plurality of second conductive pattern rows. Figure 6B In the example, the extension direction of the conductive pattern column is along the first direction, and the extension direction of the conductive pattern row is along the second direction. Adjacent conductive patterns CP in the same conductive pattern column are connected together by a first conductive bridge BDG1. For example, the first conductive bridge BDG1 is directly connected to the conductive pattern CP adjacent to it (for example, located in the same layer) to simplify the process. Adjacent conductive patterns CP in the same first conductive pattern row are connected together by a second conductive bridge BDG2. For example, the second conductive bridge BDG2 is directly connected to the conductive pattern CP adjacent to it (for example, located in the same layer) to simplify the process. Adjacent conductive patterns CP in the same second conductive pattern row are independent of each other, that is, adjacent conductive patterns in the same second conductive pattern row are disconnected from each other and not directly connected. Multiple first conductive pattern rows and multiple second conductive pattern rows are alternately arranged.

[0080] It should be noted that the plurality of first conductive pattern rows and the plurality of second conductive pattern rows are alternately arranged, which means that there are one or more second conductive pattern rows between adjacent first conductive pattern rows.

[0081] For example, adjacent first conductive pattern rows are spaced apart by a certain period. For example, the period can be 2 to half the number of gate lines. For example, in some embodiments, the period is 6, that is, in the extension direction of the data line DL, 1 first conductive pattern row and 5 second conductive pattern rows constitute a period, so that there are 5 second conductive pattern rows between adjacent first conductive pattern rows. Alternatively, in other embodiments, the period is 64, that is, in the extension direction of the data line DL, 1 first conductive pattern row and 63 second conductive pattern rows constitute a period, so that there are 63 second conductive pattern rows between adjacent first conductive pattern rows.

[0082] When the conductive pattern CP is powered on, since the first conductive bridge BDG1 spans the gate line GL and the second conductive bridge BDG2 spans the data line DL, overlapping capacitance is generated, thereby generating noise. In particular, the overlap between the second conductive bridge BDG2 and the data line DL has a significant impact on product characteristics. Therefore, adjacent conductive patterns CP in the extension direction of the data line DL (i.e., the first direction) are connected by the first conductive bridge BDG1, while adjacent conductive patterns CP in the extension direction of the gate line GL are connected by the second conductive bridge BDG2, and the first conductive pattern rows and the second conductive pattern rows are arranged in a periodic manner, alternating between them. On the one hand, this can prevent the poor signal transmission caused by the broken conductive bridge from affecting the electrostatic shielding effect. On the other hand, this can reduce the resistivity and compensate for the voltage of the bias signal line BL to a certain extent, so that the voltage of the bias signal line BL does not decay with the resistance of the conductive pattern CP.

[0083] In at least one embodiment, Figure 6A As shown, the bias line layer includes a plurality of spaced-apart bias signal lines BL. The orthographic projection of each bias signal line BL on the base substrate BS overlaps with the orthographic projection of the first conductive bridges BDG1 arranged sequentially along the first direction on the base substrate BS. For example, the orthographic projection of each bias signal line BL on the base substrate BS completely overlaps with the orthographic projection of the first conductive bridges BDG1 arranged sequentially along the first direction on the base substrate BS to avoid generating additional capacitance. For example, the overlapping portion of each bias signal line BL and the first conductive bridge BDG1 has substantially the same line width. By overlapping the first conductive bridges BDG1 with the bias signal lines BL, additional overlap capacitance is avoided and the first conductive bridges BDG1 can be prevented from affecting transmittance.

[0084] In at least one embodiment, Figure 6B As shown, the sensing substrate includes a sensing area and a frame area surrounding the sensing area; in the frame area, the sensing substrate includes a bias short-circuit ring BLSR located on the base substrate BS. The bias short-circuit ring BLSR is located in the frame area and has a ring structure or a semi-ring structure surrounding the sensing area. The bias short-circuit ring BLSR connects two opposite ends of the same bias signal line BL in its extension direction, so that both ends of the bias signal line BL can receive the bias voltage. Figure 6B As shown, the sensing substrate also includes a plurality of third conductive bridges BDG3 located in the border area and spaced apart from each other, and the bias short-circuit ring BLSR is electrically connected to the conductive patterns CP of the sensing units adjacent to the bias short-circuit ring BLSR (i.e., the outermost sensing units) through the plurality of third conductive bridges BDG3.

[0085] In other embodiments, the conductive pattern CP may also be electrically connected to the bias shorting ring BLSR through other conductive structures, or the conductive pattern CP may also be electrically connected to a signal line capable of providing a fixed voltage other than the bias shorting ring BLSR.

[0086] exist Figures 6A-6B In the illustrated embodiment, in order to simplify the manufacturing process, the conductive pattern CP and the first to third conductive bridges BDG1 to BDG3 may be located in the same layer (ie, formed by the same thin film).

[0087] and Figures 6A-6B Compared with the embodiment shown, Figures 5A to 5B In the embodiment shown, since the position where the conductive pattern CP is electrically connected to the bias signal line BL (i.e., the position of the via hole VH1) is located in the region SR where the sensing unit where the conductive pattern CP is located is located, the conductive patterns CP are independent of each other, which can reduce the voltage drop. Figures 6A-6B Compared with the embodiment shown, Figures 5A to 5BThe illustrated embodiment does not require a bias shorting ring BLSR to be provided in the border region.

[0088] It should be noted that in Figure 5B and Figure 6B In the embodiment shown, the transparent conductive layer where the conductive pattern CP is located has a grid-shaped structure, that is, the transparent conductive layer includes a plurality of conductive patterns CP in a frame-shaped structure spaced apart from each other, and these conductive patterns CP can be independent of each other (eg Figure 5B as shown) or connected to each other through conductive bridges (as Figure 6B As shown). In at least another embodiment, the transparent conductive layer may also have a stripe-grid structure, that is, the transparent conductive layer includes a plurality of first extension bars extending along the first direction and arranged in sequence along the second direction, and a plurality of second extension bars extending along the second direction and arranged in sequence along the first direction, and a frame structure formed by two adjacent first extension bars and two adjacent second extension bars is a conductive pattern. Compared with the stripe-grid structure, the grid structure has a better shielding effect. In the embodiment of the present disclosure, the transparent conductive layer where the conductive pattern CP is located may also adopt other patterns other than the grid structure and the stripe-grid structure that try not to block the pixel photosensitive area.

[0089] In at least one embodiment, the conductive pattern CP can be formed using the same film as the original transparent conductive structure of the sensing substrate, so as to avoid adding an additional transparent conductive layer.

[0090] Figure 7 A simplified top view of a sensing substrate provided in an embodiment of the present disclosure; Figure 8 A partial cross-sectional diagram of a binding region of a sensing substrate according to an embodiment of the present disclosure.

[0091] For example, Figure 7 As shown, the sensing substrate includes a binding area, and the binding area is located in the frame area. In the case where the sensing substrate includes a bias shorting ring BLSR, for example, the binding area is located outside the bias shorting ring BLSR, and the bias shorting ring BLSR is electrically connected to the binding area through a bias signal input line BLI, and the bias signal input line BLI is connected to the bias signal line BL and is located in the same layer. It should be noted that Figure 7 The second conductive bridge BDG2 is schematically shown in FIG. 1 in the form of a line segment, but this does not represent the actual shape of the second conductive bridge BDG2 .

[0092] For example, Figure 8 As shown, the bias line layer BLL includes a bias line signal terminal BLT located in the bonding area. The bias line signal terminal BLT is Figure 7The bias signal input line BLI is located at the end of the binding area, and the bias line signal terminal BLT is also connected to the bias signal source of the circuit board. The conductive pattern layer includes a protection pattern PP located in the binding area. The protection pattern PP is in direct contact with the bias line signal terminal BLT to protect the bias signal terminal BLT. In the disclosed embodiment, the conductive pattern layer includes the protection pattern PP located in the binding area. In other words, the conductive pattern and the protection pattern PP located in the binding area of the sensing substrate are located in the same layer. Therefore, the conductive pattern and the protection pattern PP can be produced using the same mask plate, eliminating the need for a new transparent conductive layer or a separate mask plate.

[0093] For example, the thickness of the protection pattern PP is approximately For example Therefore, the thickness of the conductive pattern CP is also approximately For example

[0094] In at least one embodiment, the bias line signal terminal BLT is electrically connected to the signal read terminal SD1 via a via VH4 that penetrates the first passivation insulating layer PVX1, the buffer insulating layer BF, and the second passivation insulating layer PVX2. For example, the signal read terminal SD1 is used to charge the sensing element so as to read an electrical signal from the drain of the switching element electrically connected to the sensing element. A read IC (Integrated Circuit) is disposed in the binding area to record the amount of charge applied to the sensing element.

[0095] In at least one embodiment, in order to simplify the manufacturing process, the signal reading terminal SD1 and the source and drain of the switching element are located in the same layer, that is, formed by the same thin film.

[0096] In at least one embodiment, Figure 2B and Figure 3B As shown, the sensing substrate further includes a third insulating layer IL3 located on the base substrate BS, and the third insulating layer IL3 is located on the side of the conductive pattern CP away from the base substrate BS. For example, the third insulating layer IL3 may be an inorganic insulating layer, such as a silicon nitride layer, a silicon oxide layer, or a stacked structure of the two, or other types of inorganic insulating layers; or, the third insulating layer IL3 may be an organic insulating layer, such as a resin. Further covering the shielding layer with the third insulating layer IL3 will not cause etching damage to the conductive pattern CP, and can more effectively prevent shielding failure caused by charged ions carried by aqueous solutions, etc. from penetrating under the conductive pattern. In other embodiments, the conductive pattern CP may also be exposed on the outermost layer of the product, that is, the conductive pattern CP is located on the outermost side of the sensing substrate, such as Figure 2C and Figure 3C shown.

[0097] like Figure 3AAs shown, in the area shown by the dotted box in the lower right corner, that is, the position where the gate line GL and the data line DL overlap, the line width of the gate line GL and the data line DL becomes narrower, and an isolation layer (a small rectangular pattern in the figure) is set between the gate line GL and the data line DL to insulate the gate line GL and the data line DL. For example, the isolation layer is set on the same layer as the active layer ACT.

[0098] In at least one embodiment, Figures 2A-2B as well as Figure 8 The sensing substrate shown can be manufactured using the following steps S1-S15.

[0099] Step S1: forming a gate electrode layer, so that the gate electrode layer includes a gate line GL and a gate GE.

[0100] Step S2: forming a gate insulating layer GI.

[0101] Step S3: forming an active layer ACT.

[0102] Step S4: forming a source-drain electrode layer, so that the source-drain electrode layer includes a source electrode S, a drain electrode D, a data line DL and a signal reading terminal SD1, thereby obtaining a switching element T.

[0103] Step S5 : forming a first passivation insulating layer PVX1 , so that the first passivation insulating layer PVX1 has a via hole VH3 penetrating the first passivation insulating layer PVX1 , wherein the via hole VH3 exposes a portion of the surface of the source electrode S.

[0104] Step S6 : forming a first electrode E1 , so that the first electrode E1 is electrically connected to the source S of the switching element T through the via hole VH3 .

[0105] Step S7: forming a semiconductor layer SCL.

[0106] Step S8: forming the second electrode E2 to obtain the sensing element LS.

[0107] Step S9 : forming a buffer insulating layer BF covering the sensing element LS and the switching element T.

[0108] Step S10 : forming a first insulating layer IL1 covering the buffer insulating layer BF. For example, the first insulating layer IL1 is an organic insulating layer, such as a resin material, and has a relatively large thickness to have a substantially flat upper surface.

[0109] Step S11: A second passivation insulating layer PVX2 is formed overlying the first insulating layer IL1, thereby forming a via hole VH2 penetrating the second passivation insulating layer PVX2, the first insulating layer IL1, and the buffer insulating layer BF, as well as a via hole VH4 penetrating the second passivation insulating layer PVX2, the buffer insulating layer BF, and the first passivation insulating layer PVX1. For example, the second passivation insulating layer PVX2 may be an inorganic insulating layer, such as a silicon dioxide layer or a silicon nitride layer, to improve adhesion between the subsequently formed bias signal line BL and the first insulating layer IL1.

[0110] Step S12: forming a bias line layer BLL, including a bias signal line BL and a bias line signal terminal BLT, wherein the bias signal line BL is electrically connected to the second electrode E2 of the sensing element LS through the via VH2, and the bias line signal terminal BLT is electrically connected to the signal reading terminal SD1 through the via VH4.

[0111] Step S13 : forming a third passivation insulating layer PVX3 (ie, the second insulating layer IL2 ) covering the bias line layer BLL and a via hole VH1 penetrating the third passivation insulating layer PVX3 .

[0112] Step S14: A transparent conductive layer is formed on the third passivation insulating layer PVX3, so that the transparent conductive layer includes a conductive pattern CP and a protective pattern PP, the conductive pattern CP is electrically connected to the bias signal line BL through the via H1, the protective pattern PP directly contacts the bias line signal terminal BLT, and there is no third passivation insulating layer PVX3 between the protective pattern PP and the bias line signal terminal BLT.

[0113] For example, the conductive pattern CP can be produced using a mask process, i.e., a transparent conductive film is deposited on the third passivation insulating layer PVX3, a photoresist is then coated on the transparent conductive film, the photoresist is exposed and developed to form a photoresist pattern, and the transparent conductive film is then etched using the photoresist pattern as a mask to form the transparent conductive pattern CP and the protective pattern PP. Alternatively, the conductive pattern CP can be formed by lamination or other methods.

[0114] Step S15 : forming a third insulating layer IL3 covering the conductive pattern CP.

[0115] and Figure 2B Compared with the manufacturing method of the sensing substrate shown in FIG. Figure 2C The manufacturing method of the sensing substrate in the illustrated example does not include step S15 .

[0116] and Figure 2B Compared with the manufacturing method of the sensing substrate shown in FIG. Figures 3A-3B In the illustrated example of the manufacturing method of the sensing substrate, no via hole VH1 is formed in step S13 .

[0117] and Figure 3B Compared with the manufacturing method of the sensing substrate shown in FIG. Figure 3C The manufacturing method of the sensing substrate in the illustrated example does not include step S15 .

[0118] It should be noted that the order of some steps in the above manufacturing method can be adjusted as needed. For example, the order of steps S1 to S4 can be adjusted according to the specific structure of the switching element T. For example, the order of the steps for manufacturing the bias line layer and the transparent conductive layer can be interchanged.

[0119] At least one embodiment of the present disclosure further provides an electronic device, which includes the sensing substrate provided by any one of the above embodiments.

[0120] In different embodiments of the present disclosure, the electronic device is, for example, an X-ray detector, an optical fingerprint sensor, an image sensor, etc. The present disclosure does not limit the application field of the electronic device.

[0121] For example, the electronic device provided in at least one embodiment of the present disclosure is a detector, and also includes a scintillator coupled to a sensing substrate, which is used to convert rays (such as X-rays, β-rays or γ-rays, etc.) into light, and the sensing element LS in the sensing substrate is used to convert light into an electrical signal.

[0122] For example, the electronic device provided by the embodiment of the present disclosure may further include a processing circuit, which is used to receive the electrical signal output by the sensing element and process the electrical signal to obtain an image.

[0123] It should also be noted that the drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs; the embodiments of the present disclosure and the features in the embodiments can be combined with each other unless there is a conflict.

[0124] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A sensing substrate, comprising: a substrate, and A sensing unit located on the substrate, wherein the sensing unit comprises: a sensing element located on the base substrate, wherein the sensing element has a light incident surface and a backlight surface opposite to each other, and a side surface located between the light incident surface and the backlight surface, wherein the light incident surface is located on a side of the backlight surface facing away from the base substrate; and a conductive pattern located on a side of the sensing element facing away from the base substrate, wherein the conductive pattern has a hollow portion and a transparent conductive portion surrounding the hollow portion, an orthographic projection of the hollow portion on the base substrate is at least partially located within an orthographic projection of the sensing element on the base substrate, and the orthographic projection of the transparent conductive portion on the base substrate at least partially overlaps with an orthographic projection of the side surface of the sensing element on the base substrate. The sensing substrate also includes a bias line layer, a first insulating layer, and a second insulating layer located on the base substrate. The bias line layer includes a bias signal line. In a direction perpendicular to the base substrate, the first insulating layer is located between the sensing element and the conductive pattern; the second insulating layer is located between the bias signal line and the conductive pattern.

2. The sensing substrate according to claim 1, wherein: An orthographic projection of the side surface on the base substrate is located inside an orthographic projection of the transparent conductive portion on the base substrate.

3. The sensing substrate according to claim 1, wherein: The orthographic projection of the transparent conductive portion on the base substrate is a closed frame structure. The sensing substrate according to claim 1 , wherein: in, The conductive pattern is configured to be applied with a fixed voltage when the sensing element is in operation.

5. The sensing substrate according to claim 1, wherein The conductive pattern includes a conductive pattern extension portion extending beyond the light incident surface of the sensing element; The orthographic projection of the light incident surface of the sensing element on the base substrate has a recessed portion, and the recessed portion accommodates at least a portion of the orthographic projection of the conductive pattern extension portion on the base substrate. The sensing substrate according to claim 1 , wherein: The bias signal line is electrically connected to the sensing element and the conductive pattern.

7. The sensing substrate according to claim 6, wherein: The second insulating layer includes a via hole penetrating the second insulating layer, the conductive pattern is electrically connected to the bias signal line through the via hole, and the orthographic projection of the via hole on the base substrate at least partially overlaps with the orthographic projection of the transparent conductive portion of the conductive pattern on the base substrate.

8. The sensing substrate according to claim 7, wherein: The bias signal line includes a bias line protruding portion that protrudes beyond the light incident surface of the sensing element, and the bias line protruding portion is electrically connected to the conductive pattern through the via hole.

9. The sensing substrate according to claim 8, wherein: The sensing unit further includes a switching element, wherein an orthographic projection of the switching element on the substrate is at least partially located within an orthographic projection of the excess portion of the bias line on the substrate.

10. The sensing substrate according to claim 1, wherein The sensing substrate includes a plurality of sensing units spaced apart from each other, and conductive patterns of the plurality of sensing units are independent of each other.

11. The sensing substrate according to claim 1, wherein The entire conductive pattern is separated from the bias signal line by the second insulating layer.

12. The sensing substrate according to claim 11, wherein: The sensing substrate includes a plurality of sensing units spaced apart from each other and includes a plurality of first conductive bridges spaced apart from each other and a plurality of second conductive bridges spaced apart from each other on the base substrate. Each first conductive bridge extends along a first direction and electrically connects conductive patterns of adjacent sensing units in the first direction. Each second conductive bridge extends along a second direction and electrically connects conductive patterns of adjacent sensing units in the second direction, which is different from the first direction.

13. The sensing substrate according to claim 12, wherein: The conductive patterns of the plurality of sensing units are arranged into a plurality of conductive pattern columns, a plurality of first conductive pattern rows, and a plurality of second conductive pattern rows; Adjacent conductive patterns in the same conductive pattern column are electrically connected via the first conductive bridge; Adjacent conductive patterns in the same first conductive pattern row are electrically connected via the second conductive bridge; Adjacent conductive patterns in the same second conductive pattern row are independent of each other; The plurality of first conductive pattern rows and the plurality of second conductive pattern rows are alternately arranged.

14. The sensing substrate according to claim 12, wherein: The bias line layer includes a plurality of bias signal lines spaced apart from each other. The orthographic projection of each bias signal line on the substrate overlaps with the orthographic projection of the first conductive bridges sequentially arranged along the first direction on the substrate.

15. The sensing substrate according to claim 12, wherein: The sensing substrate includes a sensing area and a frame area surrounding the sensing area; In the frame area, the sensing substrate includes a bias short-circuit ring located on the base substrate and a plurality of third conductive bridges spaced apart from each other. The bias short-circuit ring is electrically connected to the conductive patterns of the sensing units adjacent to the bias short-circuit ring through the plurality of third conductive bridges.

16. The sensing substrate according to any one of claims 1 to 15, wherein: The sensing substrate further includes a binding area and a protection pattern. The bias line layer includes a bias line signal end located in the binding area. The protection pattern and the conductive pattern are located in the same layer and in the binding area. The protection pattern is in direct contact with the bias line signal end.

17. The sensing substrate according to any one of claims 1 to 8 and 10 to 15, wherein: The sensing unit further includes a switching element, The switch element is electrically connected to the sensing element, and an orthographic projection of the switch element on the base substrate is outside an orthographic projection of the light incident surface of the sensing element on the base substrate.

18. The sensing substrate according to claim 17, wherein: The orthographic projection of the conductive pattern on the base substrate overlaps with the orthographic projection of at least part of the switching element on the base substrate.

19. The sensing substrate according to any one of claims 1 to 15, wherein: The sensing element includes a first electrode and a second electrode arranged opposite to each other. The first electrode is located between the second electrode and the base substrate in a direction perpendicular to the base substrate; The sensing element further includes a semiconductor layer located between the first electrode and the second electrode in a direction perpendicular to the base substrate, and an orthographic projection of the transparent conductive portion on the base substrate at least partially overlaps with an orthographic projection of a side surface of the semiconductor layer on the base substrate.

20. An electronic device comprising the sensing substrate according to any one of claims 1 to 19.

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