Display device

Abstract

A display device is provided, the display device comprising: a display element layer including an emitting region and a non-emitting region surrounding the emitting region; a first conductive layer located in the non-emitting region; a first insulating layer located in the non-emitting region to cover the first conductive layer, the first insulating layer having an opening portion overlapping the emitting region in a plan view; a second conductive layer located on the first insulating layer; and a reflective pattern spaced apart from the second conductive layer and located on the first insulating layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0105622, filed on August 21, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Some exemplary embodiments of this disclosure relate to a display device. Background Technology

[0003] Typically, electronic devices that provide images to users (such as smartphones, digital cameras, laptops, navigation systems, and smart TVs) include display devices for displaying images. The display device generates images and provides these images to the user through a screen.

[0004] The display device includes a display panel for generating an image and an input sensing unit located on the display panel for detecting external input. The display panel includes an emitting region for generating light for displaying the image and a non-emitting region surrounding the emitting region. The input sensing unit includes a plurality of sensing electrodes for detecting external input. The sensing electrodes are located in the non-emitting region.

[0005] The light generated in the emission area travels to the left and right sides of the display device, excluding the front side. Therefore, there is a need for technology development to improve the brightness of the front side of the display device by increasing the amount of light traveling to the front side.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section need not constitute prior art. Summary of the Invention

[0007] Some exemplary embodiments of this disclosure include display devices capable of improving frontal brightness.

[0008] Some exemplary embodiments of the inventive concept include a display device comprising: a display element layer including an emitting region and a non-emitting region surrounding the emitting region; a first conductive layer located in the non-emitting region; a first insulating layer located in the non-emitting region to cover the first conductive layer, and an opening portion superimposed on the emitting region being defined in the first insulating layer when viewed from a plane; a second conductive layer located on the first insulating layer; and a reflective pattern spaced apart from the second conductive layer and located on the first insulating layer.

[0009] According to some exemplary embodiments of the inventive concept, a display device includes: a display element layer including an emitting region and a non-emitting region surrounding the emitting region; a thin film sealing layer located on the display element layer; an insulating layer located on the thin film sealing layer; a first insulating layer located directly on the insulating layer, and an opening portion overlapping the emitting region is defined in the first insulating layer; and a reflective pattern located on a side surface of the first insulating layer. Attached Figure Description

[0010] The accompanying drawings are included to provide a further understanding of embodiments according to the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate aspects of some exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0011] Figure 1 These are perspective views of display devices based on some exemplary embodiments of the inventive concept;

[0012] Figure 2 It is shown Figure 1 A diagram showing the folded state of the display device;

[0013] Figure 3 These are perspective views of display devices based on some exemplary embodiments of the inventive concept;

[0014] Figure 4 This illustrates some example embodiments. Figure 3 A diagram showing the folded state of the display device;

[0015] Figure 5 Based on some example embodiments Figure 1 A cross-sectional view of the display device shown;

[0016] Figure 6 Based on some example embodiments Figure 5 A cross-sectional view of the display panel shown;

[0017] Figure 7 Based on some example embodiments Figure 5 A floor plan of the display panel shown;

[0018] Figure 8 Based on some example embodiments Figure 7 An example cross-sectional view of one pixel is shown below;

[0019] Figure 9 Based on some example embodiments Figure 5 A plan view of the input sensing unit shown;

[0020] Figure 10 Based on some example embodiments Figure 9An enlarged view of the first region AA1 shown in the image;

[0021] Figure 11 It is based on some example embodiments along Figure 10 The sectional view shown is taken by line I-I'.

[0022] Figure 12 Based on some example embodiments Figure 9 An enlarged view of the second region AA2 shown in the image;

[0023] Figure 13 Based on some example embodiments Figure 12 An enlarged view of the emission area and the reflection pattern around the emission area shown;

[0024] Figure 14 It is based on some example embodiments along Figure 13 The sectional view shown is taken along line II-II'; and

[0025] Figures 15 to 19 This is a diagram illustrating a method of manufacturing a display device according to some example embodiments of an inventive concept. Detailed Implementation

[0026] In this specification, when an element (or region, layer, part, etc.) is referred to as "on" another element, "connected to" or "integrated into" another element, it means that the element can be placed directly on / directly connected to / directly integrated into other components, or a third component can be arranged between them.

[0027] The same reference numerals refer to the same elements. Furthermore, in the accompanying drawings, the thickness, proportions, and dimensions of the components are exaggerated for the sake of effective description.

[0028] "And / or" includes all of one or more combinations defined by the relevant components.

[0029] It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The terms above are used only to distinguish one component from another. For example, without departing from the scope of the inventive concept, a first component may be referred to as a second component, and vice versa. Unless otherwise stated, singular terms may include plural forms.

[0030] Furthermore, terms such as "below," "lower," "above," and "upper" are used to describe the relationships of the structures shown in the accompanying drawings. These terms are described as relative concepts based on the directions shown in the accompanying drawings.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. Furthermore, terms defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and unless interpreted in an idealized or overly formal sense, terms are hereby explicitly defined.

[0032] In various embodiments of the inventive concept, the terms "comprising," "including," and variations thereof specify properties, areas, fixed quantities, steps, processes, elements, and / or components, but do not exclude other properties, areas, fixed quantities, steps, processes, elements, and / or components.

[0033] In the following description, some exemplary embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.

[0034] Figure 1 This is a perspective view of a display device based on some exemplary embodiments of the inventive concept. Figure 2 It is shown Figure 1 The diagram shows the folded state of the display device.

[0035] Reference Figure 1 According to some exemplary embodiments of the inventive concept, the display device DD may have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, embodiments according to the inventive concept are not limited thereto, and the display device DD may have various shapes (such as circles and polygons). The display device DD may be a flexible display device.

[0036] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, in this specification, "when viewed from a plane" or "in a plan view" can mean a perspective view viewed from the third direction DR3 (i.e., a direction perpendicular or orthogonal to the plane defined by the first direction DR1 and the second direction DR2).

[0037] The display device DD may include a folded region FA and multiple non-folded regions NFA1 and NFA2. The non-folded regions NFA1 and NFA2 may include a first non-folded region NFA1 and a second non-folded region NFA2. The folded region FA may be located between the first non-folded region NFA1 and the second non-folded region NFA2. The folded region FA, the first non-folded region NFA1, and the second non-folded region NFA2 may be arranged in a first direction DR1.

[0038] For example, a folded region FA and two non-folded regions NFA1 and NFA2 are shown, but the number of folded regions FA and non-folded regions NFA1 and NFA2 is not limited thereto. For example, the display device DD may include more than two non-folded regions and multiple folded regions located between the non-folded regions.

[0039] The upper surface of the display device DD can be defined as a display surface DS, and can have a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the display device DD can be provided to the user through the display surface DS.

[0040] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image (or may be configured to display an image), and the non-display area NDA may not display an image (or may not be configured to display an image, for example, a border area). The non-display area NDA may surround the display area DA and may define the outline portion of the display device DD printed in a certain color (e.g., a set or predetermined color).

[0041] Reference Figure 2 The display device DD can be a foldable display device DD that can be folded or unfolded. For example, the folding region FA can be configured to be bent based on a folding axis FX parallel to the second direction DR2, such that the display device DD can be folded. The folding axis FX can be defined as a short axis parallel to the short side of the display device DD.

[0042] When the display device DD is folded, the first non-folded region NFA1 and the second non-folded region NFA2 face each other, and the display device DD can be folded inward to prevent the display surface DS from being exposed to the outside.

[0043] Figure 3 This is a perspective view of a display device based on some exemplary embodiments of the inventive concept. Figure 4 It is shown Figure 3 The diagram shows the folded state of the display device.

[0044] In addition to folding operations Figure 3 The display device DD_1 shown can have the same as Figure 1 The display device DD shown here has a basically the same structure. Therefore, the folding operation of the display device DD_1 will be described in detail below.

[0045] Reference Figure 3 and Figure 4The display device DD_1 may include a folded region FA' and multiple non-folded regions NFA1' and NFA2'. The non-folded regions NFA1' and NFA2' may include a first non-folded region NFA1' and a second non-folded region NFA2'. The folded region FA' may be located between the first non-folded region NFA1' and the second non-folded region NFA2'. The folded region FA', the first non-folded region NFA1', and the second non-folded region NFA2' may be arranged in a second direction DR2.

[0046] The folding region FA' is bent based on a folding axis FX' parallel to the first direction DR1, so that the display device DD_1 can be folded. The folding axis FX' can be defined as a major axis parallel to the long side of the display device DD_1. Figure 1 The display device DD shown can be folded based on its short axis, and unlike this, Figure 3 The display device DD_1 shown can be folded along its long axis. The display device DD_1 can be folded inward so that the display surface DS is not exposed to the outside.

[0047] Figure 5 It is shown through examples Figure 1 A cross-sectional view of the display device shown.

[0048] For example, in Figure 5 The image shows a cross-section of the display device DD as viewed from the first direction DR1.

[0049] Reference Figure 5 The display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, and a first adhesive layer AL1 to a third adhesive layer AL3.

[0050] The display panel DP can be a flexible display panel. In some exemplary embodiments of the inventive concept, the display panel DP can be a light-emitting display panel, but the embodiments according to this disclosure are not specifically limited. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. In an organic light-emitting display panel, the light-emitting layer can include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can include quantum dots, quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0051] The input sensing unit (ISP) can be located on the display panel (DP). The ISP may include multiple sensor units for detecting external input using a capacitive method. During the manufacture of the display device (DD), the ISP may be directly fabricated on the display panel (DP). However, embodiments of the inventive concept are not limited to this, and the ISP may be fabricated as a panel separate from the display panel (DP) and then attached to it by an adhesive.

[0052] An anti-reflective layer (RPL) can be located on the input sensing unit (ISP). The RPL reduces the reflectivity of external light incident on the display panel (DP) from above the display device (DD). For example, the RPL may include a phase delayer and / or a polarizer.

[0053] The window (WIN) can be located on the anti-reflective layer (RPL). The window (WIN) can protect the display panel (DP), input sensing unit (ISP), and anti-reflective layer (RPL) from external scratches and impacts.

[0054] The panel protective film (PPF) can be located below the display panel (DP). The PPF protects the lower part of the display panel (DP). The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET).

[0055] The first adhesive layer AL1 can be located between the display panel DP and the panel protective film PPF. The display panel DP and the panel protective film PPF can be adhered to each other through the first adhesive layer AL1.

[0056] The second adhesive layer AL2 can be located between the anti-reflective layer RPL and the input sensing unit ISP. The anti-reflective layer RPL and the input sensing unit ISP can be adhered to each other through the second adhesive layer AL2.

[0057] The third adhesive layer AL3 can be located between the window WIN and the anti-reflective layer RPL. The window WIN and the anti-reflective layer RPL can be adhered to each other through the third adhesive layer AL3.

[0058] Figure 6 It is shown through examples Figure 5 A cross-sectional view of the display panel shown.

[0059] For example, in Figure 6 The image shows a cross-section of the display panel DP as viewed from the first direction DR1.

[0060] Reference Figure 6The display panel DP may include a substrate SUB, a circuit element layer DP-CL on the substrate SUB, a display element layer DP-OLED on the circuit element layer DP-CL, and a thin film sealing layer TFE on the display element layer DP-OLED.

[0061] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include a flexible plastic material (such as polyimide (PI)). The display element layer DP-OLED may be located within the display area DA.

[0062] Multiple pixels can be located on the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor located on the circuit element layer DP-CL and a light-emitting element located on the display element layer DP-OLED and connected to the transistor. The construction of the pixel will be described in more detail below.

[0063] A thin-film sealing layer (TFE) can be located on the circuit element layer (DP-CL) to cover the display element layer (DP-OLED). The TFE can include an inorganic layer and an organic layer between the inorganic layers. The inorganic layer protects the pixels from moisture / oxygen. The organic layer protects the pixels (PX) from foreign matter such as dust particles.

[0064] Figure 7 yes Figure 5 The diagram shows a floor plan of the display panel.

[0065] Reference Figure 7 The display device DD includes a display panel DP, a scan driver SDV, a data driver DDV, a transmit driver EDV, and multiple first pads ("pad", also known as "solder pads" or "soldering pads") PD1.

[0066] The display panel DP may have a rectangular shape, having a long side extending in a first direction DR1 and a short side extending in a second direction DR2, but the shape of the display panel DP is not limited to this. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0067] The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a first power line PL1 and a second power line PL2, and a connecting line CNL. m and n are natural numbers.

[0068] Pixel PX can be located in the display area DA. Scan driver SDV and transmit driver EDV can each be located in the non-display area NDA adjacent to the long side of the display panel DP. Data driver DDV can be located in the non-display area NDA adjacent to one of the short sides of the display panel DP. When viewed from a flat surface, the data driver DDV can be adjacent to the bottom edge of the display panel DP.

[0069] Scan lines SL1 to SLm can extend in the second direction DR2 and can be connected to the pixel PX and the scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 to connect to the pixel PX and the data driver DDV. Transmit lines EL1 to ELm extend in the second direction DR2 and can be connected to the pixel PX and the transmit driver EDV.

[0070] The first power line PL1 may extend in the first direction DR1 and may be located in the non-display area NDA. The first power line PL1 may be located between the display area DA and the transmit driver EDV, but according to embodiments of this disclosure, it is not limited thereto, and according to some example embodiments, the first power line PL1 may be located between the display area DA and the scan driver SDV.

[0071] The connecting line CNL can extend along the second direction DR2 and can be arranged along the first direction DR1. The connecting line CNL can be connected to the first power line PL1 and the pixel PX. A first voltage can be applied to the pixel PX through the first power line PL1 and the connecting line CNL connected to each other.

[0072] The second power line PL2 can be located in the non-display area NDA. The second power line PL2 can extend along the long side of the display panel DP and along the other short side of the display panel DP on which the data driver DDV is not located. The second power line PL2 can be located outside the scan driver SDV and the transmit driver EDV.

[0073] According to some example embodiments, a second power line PL2 may extend toward the display area DA to connect to the pixel PX. A second voltage having a lower level than the first voltage can be applied to the pixel PX via the second power line PL2.

[0074] The first control line CSL1 can be connected to the scan driver SDV and extends towards the bottom of the display panel DP when viewed from a flat surface. The second control line CSL2 can be connected to the transmit driver EDV and extends towards the bottom of the display panel DP when viewed from a flat surface. The data driver DDV can be located between the first control line CSL1 and the second control line CSL2.

[0075] The first pad PD1 can be located on the display panel DP. The first pad PD1 can be closer to the bottom of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 can be connected to the first pad PD1. Data lines DL1 to DLn can be connected to the data driver DDV, and the data driver DDV can be connected to the first pad PD1 corresponding to the data lines DL1 to DLn.

[0076] According to some example embodiments, the display device DD may include a timing controller for controlling the operation of the scan driver SDV, the data driver DDV, and the transmit driver EDV, as well as a voltage generation unit for generating a first voltage and a second voltage. The timing controller and the voltage generation unit can be connected to a corresponding first pad PD1 via a printed circuit board.

[0077] The scan driver SDV generates multiple scan signals, which are applied to pixel PX via scan lines SL1 to SLm. The data driver DDV generates multiple data voltages, which are applied to pixel PX via data lines DL1 to DLn. The transmit driver EDV generates multiple transmit signals, which are applied to pixel PX via transmit lines EL1 to ELm.

[0078] A data voltage can be supplied to pixel PX in response to a scan signal. Pixel PX can display an image by emitting light with a brightness corresponding to the data voltage in response to an emission signal. The emission time of pixel PX can be controlled by the emission signal.

[0079] Figure 8 It is shown through examples Figure 7 The image shows a cross-section of one pixel.

[0080] Reference Figure 8 The pixel PX is located on the substrate SUB and may include a transistor TR and a light-emitting element OLED. The light-emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and an emitter layer EML. The first electrode AE ​​may be an anode electrode, and the second electrode CE may be a cathode electrode.

[0081] The transistor TR and the light-emitting element OLED can be located on the substrate SUB. For example, a transistor TR is shown, but essentially, a pixel PX can include multiple transistors and at least one capacitor for driving the light-emitting element OLED.

[0082] The display area DA may include an emitting area PA corresponding to a pixel PX and a non-emitting area NPA surrounding the emitting area PA. The light-emitting element OLED may be located in the emitting area PA.

[0083] The substrate SUB may include a flexible plastic substrate. For example, the substrate SUB may include transparent polyimide (PI). The buffer layer BFL may be located on the substrate SUB and may be an inorganic layer. A semiconductor pattern may be located on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, embodiments of the inventive concept are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

[0084] Semiconductor patterns can be doped with N-type or P-type dopants. The electrical properties of a semiconductor pattern can vary depending on whether it is doped. A semiconductor pattern can include highly doped and lightly doped regions. Highly doped regions have higher conductivity than lightly doped regions and can essentially serve as the source and drain electrodes of a transistor (TR). Lightly doped regions can essentially correspond to the active region (or channel) of a transistor.

[0085] The source region S, active region A, and drain region D of transistor TR can be formed by a semiconductor pattern. A first insulating layer INS1 can be located on the semiconductor pattern. The gate G of transistor TR can be located on the first insulating layer INS1. A second insulating layer INS2 can be located on the gate G. A third insulating layer INS3 can be located on the second insulating layer INS2.

[0086] The connecting electrode CNE is located between the transistor TR and the light-emitting element OLED to connect the transistor TR and the light-emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2.

[0087] The first connecting electrode CNE1 may be located on the third insulating layer INS3 and may be connected to the drain region D through the first contact hole CH1 defined in the first insulating layer INS1 to the third insulating layer INS3. The fourth insulating layer INS4 may be located on the first connecting electrode CNE1. The fifth insulating layer INS5 may be located on the fourth insulating layer INS4.

[0088] The second connecting electrode CNE2 may be located on the fifth insulating layer INS5. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through the second contact hole CH2 defined in the fourth insulating layer INS4 and the fifth insulating layer INS5. The sixth insulating layer INS6 may be located on the second connecting electrode CNE2. The first insulating layer INS1 to the sixth insulating layer INS6 may be inorganic or organic layers.

[0089] The first electrode AE ​​may be located on the sixth insulating layer INS6. The first electrode AE ​​may be connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the sixth insulating layer INS6. A pixel defining layer PDL that exposes a portion (e.g., a set or predetermined portion) of the first electrode AE ​​may be located on the first electrode AE ​​and the sixth insulating layer INS6. An opening PX_OP for exposing a portion (e.g., a set or predetermined portion) of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0090] The hole control layer (HCL) can be located on the first electrode (AE) and the pixel definition layer (PDL). The HCL can be commonly located in the emitter region (PA) and the non-emitter region (NPA). The HCL can include a hole transport layer and a hole injection layer.

[0091] The emitter layer (EML) can be located on the hole control layer (HCL). The emitter layer (EML) can be located in the region corresponding to the opening portion (PX_OP). The emitter layer (EML) can include organic and / or inorganic materials. The emitter layer (EML) can produce any of the following: red, green, and blue light.

[0092] The electronic control layer (ECL) can be located on the emitter layer (EML) and the hole control layer (HCL). The ECL can be shared between the emitter region (PA) and the non-emitter region (NPA). The ECL may include an electron transport layer and an electron injection layer.

[0093] The second electrode CE can be located on the electronic control layer ECL. The second electrode CE can be commonly located in the emitting region PA and the non-emitting region NPA. The layer from the buffer layer BFL to the light-emitting element OLED can be defined as a pixel layer.

[0094] The thin-film sealing layer TFE can be located on the light-emitting element OLED. The thin-film sealing layer TFE can also be located on the second electrode CE to cover the pixel PX.

[0095] A first voltage can be applied to the first electrode AE ​​via transistor TR, and a second voltage having a lower level than the first voltage can be applied to the second electrode CE. Holes and electrons injected into the emitter layer EML combine to form excitons, and when the excitons transition to the ground state, the light-emitting element OLED can emit light.

[0096] Figure 9 yes Figure 5 The diagram shows a plan view of the input sensing unit.

[0097] Reference Figure 9The input sensing unit ISP may include multiple sensing electrodes SE1 and SE2, multiple wirings SNL1 and SNL2, and multiple second pads PD2 and third pads PD3. The sensing electrodes SE1 and SE2, wirings SNL1 and SNL2, and second pads PD2 and third pads PD3 may be located on the thin-film sealing layer TFE.

[0098] The planar region of the input sensing unit (ISP) may include an active region AA and an inactive region NAA surrounding the active region AA. The active region AA may be superimposed on the display region DA, and the inactive region NAA may be superimposed on the non-display region NDA. Sensing electrodes SE1 and SE2 may be located within the active region AA, and second pad PD2 and third pad PD3 may be located within the inactive region NAA. When viewed from a planar perspective, the first pad PD1 may include the second pad PD2 and the third pad PD3.

[0099] Wiring SNL1 and SNL2 can be connected to one end of sensing electrodes SE1 and SE2, and can extend to the inactive region NAA to connect to the second pad PD2 and the third pad PD3. The second pad PD2 and the third pad PD3 can be connected to the printed circuit board described above. According to some example embodiments, a sensing control unit for controlling the input sensing unit ISP can be connected to the second pad PD2 and the third pad PD3 via the printed circuit board.

[0100] The sensing electrodes SE1 and SE2 may include a plurality of first sensing electrodes SE1 extending in a first direction DR1 and arranged in a second direction DR2, and a plurality of second sensing electrodes SE2 extending in the second direction DR2 and arranged in the first direction DR1. The second sensing electrodes SE2 may be insulated from the first sensing electrodes SE1 and extend to intersect with the first sensing electrodes SE1.

[0101] The wiring SNL1 and SNL2 may include multiple first signal wirings SNL1 connected to the first sensing electrode SE1 and multiple second signal wirings SNL2 connected to the second sensing electrode SE2. The first signal wirings SNL1 may be connected to the second pad PD2, and the second signal wirings SNL2 may be connected to the third pad PD3.

[0102] Each of the first sensing electrodes SE1 may include a plurality of first sensing portions SP1 arranged on a first direction DR1 and a plurality of connection patterns CP connecting the first sensing portions SP1. Each of the connection patterns CP may be located between two first sensing portions SP1 that are adjacent to each other on the first direction DR1 to connect the two first sensing portions SP1.

[0103] Each of the second sensing electrodes SE2 may include a plurality of second sensing portions SP2 arranged in the second direction DR2 and a plurality of extension patterns EP extending from the second sensing portions SP2. Each of the extension patterns EP may be located between two adjacent second sensing portions SP2 in the second direction DR2 to extend from the two second sensing portions SP2.

[0104] The first sensing portion SP1 and the second sensing portion SP2 can have a grid shape. The first sensing portion SP1 and the second sensing portion SP2 are not superimposed on each other but spaced apart from each other, and can be arranged alternately. The electrostatic capacitance can be formed by the first sensing portion SP1 and the second sensing portion SP2. The extension pattern EP may not be superimposed on the connecting pattern CP.

[0105] Figure 10 yes Figure 9 An enlarged view of the first region AA1 shown.

[0106] Reference Figure 10 In order to have a grid shape, each of the first sensing portion SP1 and the second sensing portion SP2 may include a plurality of first branch portions BP1 extending in the first diagonal direction DDR1 and a plurality of second branch portions BP2 extending in the second diagonal direction DDR2.

[0107] The first diagonal direction DDR1 can be defined as a direction that intersects the first direction DR1 and the second direction DR2 on a plane defined by the first direction DR1 and the second direction DR2. The second diagonal direction DDR2 can be defined as a direction that intersects the first diagonal direction DDR1 on a plane defined by the first direction DR1 and the second direction DR2.

[0108] The first branch portion BP1 and the second branch portion BP2 of each of the first sensing portion SP1 and the second sensing portion SP2 can intersect each other and be integrally formed. The touch opening portion TOP with a diamond shape can be defined by the first branch portion BP1 and the second branch portion BP2.

[0109] The connecting pattern CP can extend without overlapping with the extended pattern EP and connect to the first sensing portion SP1. The connecting pattern CP can be connected to the first sensing portion SP1 through multiple contact holes TC-CH. The connecting pattern CP can extend toward the first sensing portion SP1 through the area overlapping with the second sensing portion SP2. The connecting pattern CP can be defined as a first conductive layer.

[0110] An extended pattern EP can be located between first sensing portions SP1 and can extend from a second sensing portion SP2. The second sensing portion SP2 and the extended pattern EP can be integrally formed. The extended pattern EP can have a grid shape. The extended pattern EP, the first sensing portion SP1, and the second sensing portion SP2 can be patterned simultaneously using the same material, and the extended pattern EP, the first sensing portion SP1, and the second sensing portion SP2 are formed on the same layer. The extended pattern EP, the first sensing portion SP1, and the second sensing portion SP2 are located on a different layer than the connecting pattern CP and can be defined as a second conductive layer.

[0111] The input sensing unit (ISP) may include multiple reflective patterns (RPTs) located on the touch opening portion (TOP). The reflective patterns (RPTs) may extend from the first sensing portion (SP1), the second sensing portion (SP2), and the extension pattern (EP). The reflective patterns (RPTs) can reflect light supplied from the emitting region (PA). A more detailed description of the construction of the reflective patterns (RPTs) will follow.

[0112] The connecting pattern CP may include a first extension EX1 and a second extension EX2 having a shape symmetrical to the first extension EX1. The extension pattern EP may be located between the first extension EX1 and the second extension EX2. The first extension EX1 extends through a region overlapping with one of the second sensing portions SP2 and may be connected to the first sensing portion SP1. The second extension EX2 extends through a region overlapping with the other of the second sensing portions SP2 and may be connected to the first sensing portion SP1.

[0113] In the following text, depending on the relative placement position, the first sensing portion SP1 is defined as either the upper first sensing portion SP1 or the lower first sensing portion SP1. Furthermore, depending on the relative placement position, the second sensing portion SP2 is defined as either the left second sensing portion SP2 or the right second sensing portion SP2.

[0114] The portions of the first extension portion EX1 and the second extension portion EX2 adjacent to one side of the first extension portion EX1 and the second extension portion EX2 (e.g., setting or predetermined portions) can be connected to the lower first sensing portion SP1 through multiple contact holes TC-CH. The portions of the first extension portion EX1 and the second extension portion EX2 adjacent to the other side of the first extension portion EX1 and the second extension portion EX2 (e.g., setting or predetermined portions) can be connected to the upper first sensing portion SP1 through multiple contact holes TC-CH.

[0115] The first extension EX1 may include a first sub-extension EX1_1 and a second sub-extension EX1_2 extending in the first diagonal direction DDR1, a third sub-extension EX1_3 and a fourth sub-extension EX1_4 extending in the second diagonal direction DDR2, a first sub-conductive pattern SCP1 extending in the second diagonal direction DDR2, and a second sub-conductive pattern SCP2 extending in the first diagonal direction DDR1.

[0116] The portions of the first sub-extension EX1_1 and the second sub-extension EX1_2 adjacent to one side of the first sub-extension EX1_1 and the second sub-extension EX1_2 (e.g., setting or predetermined portions) can be connected to the lower first sensing portion SP1 through multiple contact holes TC-CH. The portions of the third sub-extension EX1_3 and the fourth sub-extension EX1_4 adjacent to one side of the third sub-extension EX1_3 and the fourth sub-extension EX1_4 (e.g., setting or predetermined portions) can be connected to the upper first sensing portion SP1 through multiple contact holes TC-CH.

[0117] The other side of the first sub-extension EX1_1 can extend from the other side of the third sub-extension EX1_3, and the other side of the second sub-extension EX1_2 can extend from the other side of the fourth sub-extension EX1_4. The first sub-conductive pattern SCP1 can extend from the other side of the fourth sub-extension EX1_4 along the second diagonal direction DDR2, and can extend to the first sub-extension EX1_1. The second sub-conductive pattern SCP2 can extend from the other side of the second sub-extension EX1_2 along the first diagonal direction DDR1, and can extend to the third sub-extension EX1_3.

[0118] The first sub-extension EX1_1, the second sub-extension EX1_2, the third sub-extension EX1_3, the fourth sub-extension EX1_4, the first sub-conductive pattern SCP1, and the second sub-conductive pattern SCP2 can be formed as a single unit.

[0119] The first sub-extension EX1_1 and the second sub-extension EX1_2 may extend to intersect a certain number (e.g., a set or predetermined number) of second branch portions BP2 adjacent to the same lower first sensing portion SP1 in the second branch portion BP2 of the right second sensing portion SP2. The first branch portion BP1 of the right second sensing portion SP2 may not be located in some areas superimposed with the first sub-extension EX1_1, the second sub-extension EX1_2, and the second sub-conductive pattern SCP2.

[0120] The third sub-extension EX1_3 and the fourth sub-extension EX1_4 may extend to intersect with a certain number (e.g., a set or predetermined number) of first branch portions BP1 adjacent to the same first sensing portion SP1 in the first branch portion BP1 of the right second sensing portion SP2. The second branch portion BP2 of the right second sensing portion SP2 may not be located in some areas superimposed with the third sub-extension EX1_3, the fourth sub-extension EX1_4, and the first sub-conductive pattern SCP1.

[0121] The second extension EX2 may include a fifth sub-extension EX2_1 and a sixth sub-extension EX2_2 extending in the second diagonal direction DDR2, a seventh sub-extension EX2_3 and an eighth sub-extension EX2_4 extending in the first diagonal direction DDR1, a third sub-conductive pattern SCP3 extending in the first diagonal direction DDR1, and a fourth sub-conductive pattern SCP4 extending in the second diagonal direction DDR2.

[0122] The left second sensing portion SP2 may have a structure symmetrical to the right second sensing portion SP2, and the second extension portion EX2 may have a structure symmetrical to the first extension portion EX1. Therefore, the description of the fifth sub-extension portion EX2_1 to the eighth sub-extension portion EX2_4, as well as the third sub-conductive pattern SCP3 and the fourth sub-conductive pattern SCP4, will be omitted.

[0123] The input sensing unit (ISP) may include multiple reflective patterns (RPTs). The reflective patterns (RPTs) may be spaced apart from the first branch portion (BP1) and the second branch portion (BP2) and located on the touch opening portion (TOP). For example, the reflective pattern (RPT) may have a single closed curve shape with a diamond shape, but the shape of the reflective pattern (RPT) is not limited to this. A more detailed description of the construction of the reflective pattern (RPT) will follow.

[0124] Figure 11 It is along Figure 10 The sectional view shown is taken by line I-I'.

[0125] Reference Figure 11 The insulating layer IOL can be located on the thin-film sealing layer TFE. The insulating layer IOL can be an inorganic layer. The first conductive layer CTL1 can be located on the insulating layer IOL. The first conductive layer CTL1 can include a connection pattern CP. According to some exemplary embodiments of the inventive concept, the first conductive layer CTL1 can be located directly on the upper surface of the insulating layer IOL.

[0126] The first insulating layer TC-IL1 may be located on the first conductive layer CTL1 and the insulating layer IOL. The first insulating layer TC-IL1 may be located at the non-emitting region NPA to cover the first conductive layer CTL1.

[0127] The second conductive layer CTL2 may be located on the first insulating layer TC-IL1. The second conductive layer CTL2 may include a first sensing portion SP1 and a second sensing portion SP2. In addition, the second conductive layer CTL2 may include an extended pattern EP integrally formed with the second sensing portion SP2.

[0128] The connection pattern CP can be connected to the first sensing portion SP1 through a plurality of contact holes TC-CH defined in the first insulating layer TC-IL1. The second insulating layer TC-IL2 can be located on the first insulating layer TC-IL1 to cover the first sensing portion SP1 and the second sensing portion SP2.

[0129] The first insulating layer TC-IL1 and the second insulating layer TC-IL2 can be organic layers including organic materials.

[0130] Figure 12 yes Figure 9 An enlarged view of the second region AA2 shown in the image.

[0131] For example, in Figure 12 In the diagram, the emission regions PA1, PA2, and PA3 are shown together with the first sensing portion SP1 and the second sensing portion SP2.

[0132] Reference Figure 12 The emitting region PA can be arranged along the first diagonal direction DDR1 and the second diagonal direction DDR2. The first branch portion BP1 and the second branch portion BP2 can be superimposed on the non-emitting region NPA between the emitting regions PA. That is, the first sensing portion SP1 and the second sensing portion SP2 can be located in the non-emitting region NPA. Because the first sensing portion SP1 and the second sensing portion SP2 are located in the non-emitting region NPA, the light generated in the emitting regions PA1, PA2, and PA3 can be emitted normally without being affected by the first sensing portion SP1 and the second sensing portion SP2.

[0133] The emission area PA may include a plurality of first emission areas PA1 displaying red, a plurality of second emission areas PA2 displaying green, and a plurality of third emission areas PA3 displaying blue. When viewed from a plane, the second emission areas PA2 have a smaller area than the first emission areas PA1, and the third emission areas PA3 may have a larger area than the first emission areas PA1.

[0134] The emitting areas PA1, PA2, and PA3 can have a rhombus shape. The touch opening portion TOP can be superimposed on the emitting areas PA1, PA2, and PA3. The touch opening portion TOP can have a rhombus shape corresponding to the shape of the emitting areas PA1, PA2, and PA3.

[0135] When viewed from a flat surface, the reflective pattern RPT can be spaced apart from the second conductive layer CTL2, which includes a first branch portion BP1 and a second branch portion BP2, and located on the touch opening portion TOP. When viewed from a flat surface, the reflective pattern RPT can be superimposed on the non-emitting region NPA and can be adjacent to the emitting region PA. The reflective pattern RPT can be located between the emitting region PA and the second conductive layer CTL2.

[0136] The reflective pattern RPT can be positioned adjacent to the edge of the emitting region PA, extending along the edge of the emitting region PA. The reflective pattern RPT can also surround the emitting region PA individually.

[0137] The reflective pattern RPT may include a plurality of first reflective patterns RPT1 adjacent to the first emission region PA1, a plurality of second reflective patterns RPT2 adjacent to the second emission region PA2, and a plurality of third reflective patterns RPT3 adjacent to the third emission region PA3. The first reflective patterns RPT1 may surround the first emission region PA1, the second reflective patterns RPT2 may surround the second emission region PA2, and the third reflective patterns RPT3 may surround the third emission region PA3.

[0138] Figure 13 yes Figure 12 An enlarged view of the emission area and the reflection pattern around the emission area shown. Figure 14 It is along Figure 13 The sectional view shown is taken from line II-II'.

[0139] For example, in Figure 14 The diagram also shows an external reflective pattern RPT instead of a reflective pattern RPT surrounding a single emission region PA. Additionally, the circuit element layer DP-CL is shown as a single layer. In the following sections, in... Figure 13 and Figure 14 The construction of a reflection pattern RPT surrounding a emission region PA will be described in the following section.

[0140] Reference Figure 13 and Figure 14 The display element layer of DP-OLED may include an emitting region PA and a non-emitting region NPA surrounding the emitting region PA. Figure 13 and Figure 14 The emission region PA shown can be any one of the first emission region PA1, the second emission region PA2, and the third emission region PA3.

[0141] When viewed from a planar surface, an opening portion IL-OP, superimposed on the emitting region PA, can be defined in the first insulating layer TC-IL1. When viewed from a planar surface, the area of ​​the opening portion IL-OP can be larger than the area of ​​the opening portion PX_OP defined in the emitting region PA. Therefore, when viewed from a planar surface, the area of ​​the opening portion IL-OP can be larger than the area of ​​the emitting region PA, and can also be larger than the area of ​​the light-emitting element OLED located in the emitting region PA.

[0142] The second conductive layer CTL2 and the reflective pattern RPT can be located on the first insulating layer TC-IL1. Figure 13 and Figure 14 The reflection pattern RPT shown can be any one of the first reflection pattern RPT1, the second reflection pattern RPT2, and the third reflection pattern RPT3.

[0143] The first insulating layer TC-IL1 may include a flat upper surface US, a side surface SS defining an opening portion IL-OP, and a flat lower surface LS located below the upper surface US. The side surface SS may connect the ends of the upper surface US and the lower surface LS. The lower surface LS may be defined as a surface opposite to the upper surface US.

[0144] The upper surface US and the lower surface LS may have a plane defined by a first direction DR1 and a second direction DR2. The side surface SS may have an inclined surface. For example, the side surface SS may have an inclination angle θs of 40° to 80° relative to the lower surface LS, and for example, an inclination angle θs of 70° relative to the lower surface LS.

[0145] The second conductive layer CTL2 can be located on the upper surface US. The reflective pattern RPT can be located on the side surface SS. The reflective pattern RPT can be formed simultaneously with the second conductive layer CTL2 by patterning with the same material. This structure will be described in detail below in the method of manufacturing the display device DD.

[0146] The reflective pattern RPT can also be located on the portion of the upper surface US adjacent to the side surface SS. The reflective pattern RPT can also be located on the portion of the insulating layer IOL adjacent to the first insulating layer TC-IL1. The reflective pattern RPT may not be located within the emitting region PA.

[0147] The reflective pattern RPT can be spaced at a certain distance (e.g., a set or predetermined distance) from the boundary between the emitting region PA and the non-emitting region NPA. However, embodiments according to the inventive concept are not limited to this, and the reflective pattern RPT can also be located at the boundary between the emitting region PA and the non-emitting region NPA.

[0148] The second insulating layer TC-IL2 can be located on the first insulating layer TC-IL1 and the insulating layer IOL to cover the reflective pattern RPT and the second conductive layer CTL2. The second insulating layer TC-IL2 can be located in the opening portion IL-OP to fill the opening portion IL-OP. The reflective pattern RPT can be insulated from the second conductive layer CTL2 through the second insulating layer TC-IL2 and can be electrically separated.

[0149] Light L1 generated by the OLED located in the emitting region PA can travel in the upward direction (e.g., the third direction DR3). Light L2 generated by the OLED can travel towards the non-emitting region NPA. Light L2 can travel towards the side surface SS and can be provided to the reflective pattern RPT.

[0150] The reflective pattern RPT can reflect light L2. The reflective pattern RPT can include a metallic material that can reflect light. Light L2 can be reflected at the reflective pattern RPT and travel upwards. Therefore, the front brightness of the display device DD can be improved.

[0151] After the first insulating layer TC-IL1, without using the reflective pattern RPT and with the undefined opening portion IL-OP completely located on the insulating layer IOL, a separate refractive pattern for reflecting light L2 can be located on the first insulating layer TC-IL1. The second insulating layer TC-IL2 can be located on the separate refractive pattern. In this case, because a separate refractive pattern is used or formed, the manufacturing process steps for adding the separate refractive pattern to the display device DD may increase. Furthermore, because a separate refractive pattern is added, the thickness of the display device DD may increase.

[0152] However, according to some exemplary embodiments of the inventive concept, because a separate refractive pattern is not used, the manufacturing process steps of the display device DD can be reduced, and the thickness of the display device DD can be reduced.

[0153] Figures 15 to 19 This is a diagram illustrating a method of manufacturing a display device according to some example embodiments of an inventive concept.

[0154] As an example, Figures 15 to 19 To correspond to Figure 14 The cross-section is shown.

[0155] Reference Figure 15 Prepare a display element layer DP-OLED including an emitting region PA and a non-emitting region NPA, and set a thin film sealing layer TFE and an insulating layer IOL on the display element layer DP-OLED.

[0156] A first insulating layer TC-IL1 can be formed on the insulating layer IOL. According to some example embodiments, it can be formed on the insulating layer IOL in the non-emitting region NPA. Figure 11 The first conductive layer CTL1 is shown, and a first insulating layer TC-IL1 can be disposed on the insulating layer IOL to cover the first conductive layer CTL1.

[0157] When viewed from a planar perspective, a removed portion RMP can be defined within the first insulating layer TC-IL1, which is superimposed on the portion of the emitting region PA and the non-emitting region NPA adjacent to the emitting region PA. A photomask PMK is located within the non-emitting region NPA, and the removed portion RMP is exposed by the photomask PMK, allowing the removed portion RMP to be exposed. Essentially, the removed portion RMP can be the portion of the first insulating layer TC-IL1 superimposed on the opening portion IL-OP.

[0158] Reference Figure 16 The exposed portion of RMP can be removed by a developing process. Because the exposed portion of RMP is removed, the opening portion IL-OP can be confined within the first insulating layer TC-IL1. The exposed portion of RMP is removed to form the upper surface US, the lower surface LS, and the side surface SS with an inclined surface of the first insulating layer TC-IL1.

[0159] According to some example embodiments, after the partial RMP is removed, a temporary hardening process for the first insulating layer TC-IL1 with the opening portion IL-OP can be further performed. For example, after the partial RMP is removed, the side surface SS can be vertical, and then heat with a certain temperature (e.g., a set or predetermined temperature) can be applied to the first insulating layer TC-IL1. In this case, the side surface of the first insulating layer TC-IL1 flows downward due to heat, and as a result, the side surface SS can have an inclined surface forming an angle θs relative to the lower surface LS.

[0160] Reference Figure 17 A conductive layer CTL can be formed on the first insulating layer TC-IL1 and the insulating layer IOL. The conductive layer CTL includes a conductive material, and a second conductive layer CTL2 and a reflective pattern RPT can be formed from the conductive layer CTL.

[0161] Specifically, the photomask FM can be located on the central portion of the upper surface US, the portion of the conductive layer CTL overlapping with the side surface SS, the portion of the upper surface US adjacent to the side surface SS, and the portion of the insulating layer IOL adjacent to the side surface SS. According to some example embodiments, a photoresist (photosensitive resin) is placed on the conductive layer CTL, and the portion of the photoresist except for the portion that will form the second conductive layer CTL2 and the reflective pattern RPT is removed, so that the photomask FM can be formed.

[0162] By using a photomask FM as a mask, the portion of the conductive layer CTL excluding the area where the photomask FM is located can be removed. This removal can be achieved using either dry etching or wet etching methods.

[0163] Reference Figure 18 A portion of the conductive layer CTL is removed, allowing a second conductive layer CTL2 and a reflective pattern RPT spaced apart from the second conductive layer CTL2 to be formed on the first insulating layer TC-IL1. As described above, the reflective pattern RPT can be located on the side surface SS, the portion of the upper surface US adjacent to the side surface SS, and the portion of the insulating layer IOL adjacent to the side surface SS.

[0164] Reference Figure 19 A second insulating layer TC-IL2 is disposed on the first insulating layer TC-IL1 and the insulating layer IOL to cover the reflective pattern RPT and the second conductive layer CTL2. The second insulating layer TC-IL2 can be disposed on the insulating layer IOL to fill the opening portion IL-OP. The reflective pattern RPT and the second conductive layer CTL2 can be insulated from each other through the second insulating layer TC-IL2.

[0165] According to some example embodiments of the inventive concept, the manufacturing process steps of the display device DD can be reduced because the separate refractive pattern described above is not used.

[0166] According to some example embodiments of the inventive concept, a reflective pattern capable of reflecting light is arranged between the input sensing unit and the emitting area, and the reflective pattern reflects light provided from the emitting area and allows the reflected light to travel upward, thereby improving the front brightness of the display device.

[0167] Furthermore, according to some exemplary embodiments of the inventive concept, the thickness of the display device can be reduced because a separate refractive pattern for reflecting light is not used.

[0168] Although some exemplary embodiments of the inventive concept have been described, it is understood that the inventive concept should not be limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the claims and their equivalents.

Claims

1. A display device, the display device comprising: The display element layer includes an emitting region and a non-emitting region surrounding the emitting region; A first conductive layer is located in the non-emissive region; A first insulating layer is located in the non-emitting region to cover the first conductive layer. The first insulating layer has an opening portion that overlaps with the emitting region in a plan view, and includes a pair of opposing side surfaces and an upper surface located between the pair of opposing side surfaces. A second conductive layer is located on the upper surface of the first insulating layer; as well as The reflective pattern is located on the pair of opposite side surfaces of the first insulating layer. The reflective pattern and the second conductive layer are spaced apart from each other on the upper surface of the first insulating layer.

2. The display device according to claim 1, wherein, The first insulating layer comprises organic materials.

3. The display device according to claim 1, wherein, The reflective pattern is insulated from the second conductive layer.

4. The display device according to claim 1, further comprising: A second insulating layer is located on the first insulating layer to cover the reflective pattern and the second conductive layer, wherein the second insulating layer fills the opening portion.

5. The display device according to claim 4, wherein, The second insulating layer comprises organic materials.

6. The display device according to claim 1, wherein, The first insulating layer further includes: The lower surface, below the upper surface, The pair of opposing side surfaces connect the ends of the upper surface and the lower surface, and define the opening portion.

7. The display device according to claim 6, wherein, Each of the pair of opposite side surfaces has an inclined surface.

8. The display device according to claim 7, wherein, Each of the pair of opposing side surfaces forms an angle of inclination of 40 to 80 degrees relative to the lower surface.

9. The display device according to claim 1, wherein, The reflective pattern is also located on the portion of the upper surface adjacent to the pair of opposite side surfaces.

10. The display device according to claim 6, further comprising: A thin-film sealing layer is located on the display element layer; as well as An insulating layer is located on the thin film sealing layer. The first conductive layer is located directly on the insulating layer.

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