Frequency Doubling Circuit with Controllable Duty Cycle and Its Method

Abstract

The present application relates to a frequency multiplication circuit and method capable of controlling a duty cycle. The frequency multiplication circuit includes a multiplexer, a digitally controlled delay circuit, a one-to-two frequency divider circuit, a duty cycle detector, and a controller. The multiplexer receives a first clock and outputs a second clock based on a third clock, wherein the first clock has a fifty percent duty cycle and is a two-phase clock comprising a first phase and a second phase. The digitally controlled delay circuit receives the second clock and outputs a fourth clock based on a digital word. The one-to-two frequency divider circuit receives the fourth clock and outputs a third clock. The duty cycle detector receives the second clock and outputs a logic signal based on a comparison of the duty cycle of the second clock with a target duty cycle value. The controller outputs a digital word based on the logic signal.

Description

Technical Field

[0001] The present disclosure relates to a frequency multiplier, and more particularly to a frequency multiplier circuit and method with power-saving duty cycle control. Background Art

[0002] Many modern electronic circuits require a precise clock for proper operation. A clock is a voltage signal that periodically switches between a low and a high level. The percentage of time the voltage signal remains at a high level is called the duty cycle. Many circuits require a specific clock duty cycle for optimal performance. For example, in a multi-phase clock system where both the rising and falling edges of the clock are used, a duty cycle of 50% is often desirable.

[0003] Conventional frequency multiplication circuits (also referred to herein as frequency multipliers) receive an input clock and output an output clock whose frequency is twice that of the input clock. However, the duty cycle of the output clock may not be desirable. Schwartz discloses a frequency multiplier with a 50% duty cycle output in U.S. Patent 6,348,821. This frequency multiplier has analog circuit characteristics that require a current generator to periodically charge a capacitor, so it does not conserve power. Furthermore, this frequency multiplier is designed to generate a 50% duty cycle output, which is beneficial for many applications, but may not be ideal for all.

[0004] Therefore, a duty cycle controllable frequency multiplier is needed, which not only has digital circuit characteristics and better power efficiency, but is also not limited to generating a 50% duty cycle output. Summary of the Invention

[0005] One embodiment of the present disclosure provides a frequency multiplication circuit. The frequency multiplication circuit includes: a multiplexer, a digitally controlled delay circuit, a one-to-two frequency divider circuit, a duty cycle detector, and a controller. The multiplexer receives a first clock and outputs a second clock based on a third clock, wherein the first clock has a duty cycle of 50% and is a two-phase clock including a first phase and a second phase. The digitally controlled delay circuit receives the second clock and outputs a fourth clock based on a digital word. The one-to-two frequency divider circuit receives the fourth clock and outputs the third clock. The duty cycle detector receives the second clock and outputs a logic signal based on a comparison of a duty cycle of the second clock with a target duty cycle value. The controller outputs the digital word based on the logic signal.

[0006] An embodiment of the present disclosure provides a frequency multiplication method, comprising the following steps: receiving a first clock having a duty cycle of 50% and being a two-phase clock including a first phase and a second phase; selecting one of the first phase and the second phase of the first clock using a multiplexer according to a third clock to output a second clock; delaying the second clock to a fourth clock using a digitally controlled delay circuit according to a digital word; outputting the third clock according to the fourth clock using a one-to-two frequency divider circuit; generating a logic signal using a duty cycle detector based on a comparison of a duty cycle of the second clock with a target duty cycle value; and updating the digital word according to the logic signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A A circuit diagram showing a frequency multiplier according to an embodiment of the present disclosure;

[0008] Figure 1B show Figure 1A The timing diagram of the frequency multiplier;

[0009] Figure 2A Showing the circuit diagram of the duty cycle detector;

[0010] Figure 2B A circuit diagram showing another type of duty cycle detector;

[0011] Figure 3 a circuit diagram showing a digitally controlled delay circuit; and

[0012] Figure 4 A flow chart of a frequency doubling method according to an embodiment of the present disclosure is shown.

[0013] Explanation of symbols

[0014] 100: Frequency Multiplier

[0015] 110: Multiplexer

[0016] 120: Digital Control Delay Circuit (DCDC)

[0017] 130: One to two frequency division circuit

[0018] 140: Duty cycle detector

[0019] 150: Controller

[0020] 200A: Duty cycle detection circuit

[0021] 210: Low-pass filter

[0022] 211, 221, 222, 241, 251: Resistors

[0023] 212, 242, 252, CL: capacitors

[0024] 220: Resistor voltage divider

[0025] 230, 260: Comparator

[0026] 200B: Duty Cycle Detector

[0027] 240: First low-pass filter

[0028] 250: Second low-pass filter

[0029] 270, INV1, INV2: Inverter

[0030] 300: Digitally controlled delay circuit

[0031] 310: Encoder

[0032] 311, 312, 313, 314, 315, 316, 317: Programmable Delay Circuit (PDC)

[0033] COB314: Detail Box

[0034] PC314: Adjustable capacitor

[0035] N314: Internal Nodes

[0036] MN1, MN2, MN3: NMOS transistors

[0037] MP1, MP2: PMOS transistors

[0038] 410-460: Steps DETAILED DESCRIPTION

[0039] The present disclosure relates to frequency multipliers and methods thereof. While the specification describes several exemplary embodiments of the present disclosure, it should be understood that the present disclosure can be implemented in many ways and is not limited to the specific examples described below or to the specific manner in which any features of the examples are implemented. In other instances, well-known details are not shown or described in order to focus on various aspects of the present disclosure.

[0040] Those skilled in the art understand the terms and basic concepts related to microelectronics used in this disclosure, such as "voltage", "current", "signal", "power supply", "ground", "complementary metal oxide semiconductor (CMOS)", "n-channel metal oxide semiconductor (NMOS)", "p-channel metal oxide semiconductor (PMOS)", "resistor", "capacitor", "comparator", "inverter", "logic signal", "multiplexer", "switch", "data flip flop", "low-pass filter" and "duty cycle". Such terms are used in the field of microelectronics, and the related concepts are obvious to those skilled in the art, so they will not be explained in detail here.

[0041] A person skilled in the art recognizes the symbols for resistors and metal-oxide semiconductor (MOS) transistors (including PMOS and NMOS transistors) and can identify their terminals such as "source," "gate," and "drain." A person skilled in the art can read a schematic diagram of a circuit including resistors, NMOS transistors, and PMOS transistors without requiring a detailed description of how one transistor or resistor is connected to another transistor or resistor in the schematic diagram.

[0042] This disclosure uses engineering concepts for description. For example, regarding two variables X and Y, when we say "X equals Y," we mean "X is approximately equal to Y," that is, "the difference between X and Y is less than a specified engineering tolerance." When we say "X is zero," we mean "X is approximately zero," that is, "X is less than a specified engineering tolerance." When we say "X is significantly less than Y," we mean "X is negligible relative to Y," that is, "the ratio of X to Y is less than the engineering tolerance, and therefore, X is negligible compared to Y."

[0043] Throughout this disclosure, “V DD ” represents a power supply node. Please note that a power supply node is a node at which the voltage level is substantially fixed. In this disclosure, sometimes V DD Refers to the power supply node V DD For example, it is obvious that when we say “V DD When it is 1.05V", it refers to the power supply node V DDThe voltage level on the ground node is 1.05 V. The ground node is a node whose voltage level is substantially zero.

[0044] In this disclosure, a signal is a voltage with a variable level that can change over time, or a number with a value that can change over time. When a signal is a voltage, it is called a voltage signal, and the level of the signal at a given moment represents the state of the signal at that moment. When a signal is a number, it is called a numerical signal, and the value of the signal at a given moment represents the state of the signal at that moment.

[0045] A logic signal is a voltage signal with two states: a low-level state and a high-level state. The low-level state is also called the "0" state, and the high-level state is also called the "1" state. Regarding the logic signal Q, when we say "Q is high" or "Q is low," it means "Q is in a high-level state" or "Q is in a low-level state." Similarly, when we say "Q is 1" or "Q is 0," it means "Q is in a 1 state" or "Q is in a 0 state."

[0046] When a logic signal switches from a low level to a high level, it undergoes a low-to-high level transition with a rising edge. When a logic signal switches from a high level to a low level, it undergoes a high-to-low level transition with a falling edge.

[0047] When a MOS transistor is used to implement a switch, it is controlled by a control signal, which is a logic signal applied to the gate of the MOS transistor. When the control signal is high, the switch implemented by the NMOS transistor is in the "on" state, and when the control signal is low, it is in the "off" state.

[0048] If a first logic signal and a second logic signal are always in opposite states, we say the first logic signal is the inverse or inverted logic of the second logic signal. That is, when the first logic signal is low, the second logic signal is high; and when the first logic signal is high, the second logic signal is low. When we say the first logic signal is the inverse logic of the second logic signal, we mean that the first and second logic signals are complementary to each other.

[0049] A two-phase clock is a clock having two phases (including a first phase and a second phase), wherein the second phase is the inverse logic of the first phase (i.e., the second phase is complementary to the first phase); when both the first phase and the second phase have a 50% duty cycle, the two-phase clock is considered to have a 50% duty cycle.

[0050] A digital word is an integer-valued digital signal. A digital signal can be a set of multiple logical signals according to a certain coding scheme.

[0051] A circuit is a collection of transistors, resistors, and / or other electronic devices that are interconnected in some way to perform a function.

[0052] Figure 1A A schematic diagram of a frequency multiplier 100 according to an embodiment of the present disclosure is shown. The frequency multiplier 100 includes a multiplexer 110, a digitally controlled delay circuit (DCDC) 120, a divide-by-two circuit 130, a duty cycle detector 140, and a controller 150. The multiplexer 110 is used to receive a first clock S1. The first clock S1 has a duty cycle of 50% and is a two-phase clock including a first phase S1[0] and a second phase S1[1]. The multiplexer 110 also outputs a second clock S2 according to a third clock S3. The digitally controlled delay circuit 120 is used to receive the second clock S2 and output the second clock S2 according to the digital word W. ctl Output the fourth clock S4. The one-to-two frequency dividing circuit 130 is used to receive the fourth clock S4 and output the third clock S3. The duty cycle detector 140 is used to receive the second clock S2 and output the logic signal E dc The controller 150 is used to receive the logic signal E dc And output digital word W ctl For the sake of brevity, the first clock S1 is referred to as S1, the first phase S1[0] of the first clock S1 is referred to as S1[0], the second phase S1[1] of the first clock S1 is referred to as S1[1], the second clock S2 is referred to as S2, the third clock S3 is referred to as S3, the fourth clock S4 is referred to as S4, and the logic signal E is referred to as dc Abbreviated as E dc , and the digital word W ctl Abbreviated as W ctl .

[0053] The multiplexer 110 selects S1[0] or S1[1] as the output (i.e., S2) according to S3. Its function can be described as follows:

[0054]

[0055] This can be achieved according to equation (1) Figure 1A The multiplexer 110 is well known in the art and thus will not be described in detail here.

[0056] DCDC 120 implements a programmable delay function, so that S4 is a delay of S2, wherein the rising edge of S2 is transmitted backward and eventually becomes the rising edge of S4, and the transmission delay is determined by W ctl Control. The one-to-two frequency divider circuit 130 implements a one-to-two frequency divider function, so that the rising edge of S4 triggers S3 to switch states, resulting in a rising edge or falling edge of S3. If each rising edge of S4 is assigned a sequence number, then even-numbered rising edges of S4 trigger S3 to switch from a low level to a high level (i.e., a rising edge of S3), while odd-numbered rising edges of S4 trigger S3 to switch from a high level to a low level (i.e., a falling edge of S3). Every two rising edges of S4 trigger only one rising edge of S3, so S3 is called a one-to-two frequency divider clock of S4.

[0057] S1 is a two-phase clock with a 50% duty cycle. Let S1's period be T. The purpose of frequency multiplier 100 is to multiply S2 to a clock with the target duty cycle. That is, S2's period is equal to T / 2, because multiplication cuts the period in half. S4 is a delayed version of S2 and therefore has the same period, T / 2. S3 is a 1:2 divided clock of S4, so its period is twice that of S4, meaning its period is equal to T.

[0058] DCDC 120 receives S2 and outputs S4 so that the rising edge of S2 can be transmitted and become the rising edge of S4 with a transmission delay. Let the transmission delay of DCDC 120 be T D . Figure 1B The timing diagram of the frequency multiplier 100 is shown, where S1[0], S1[1], S2, S4 and S3 are all clocks, and the clock is a logic signal - not a high level (V DD ) is a low level (0V). As shown in the figure, S1[0] and S1[1] are complementary. The period of S1[0] is T. For example, the rising edge 190a (at time point t a ) and the next rising edge 190e (at time point t e ) is shown as the time difference T between the rising edge 190a and the next falling edge 190c (at time point t c ), indicating that S1[0] remains at a high level for 50% of the time in one clock cycle. It is obvious to those skilled in the art that the period of S1[1] is T and the duty cycle of S1[1] is 50%. Initially, S3 is at a low level (i.e., 0), so the multiplexer 110 selects S1[0] as S2. At time point t a, the rising edge 190a of S1[0] leads to the rising edge 192a of S2, which, after being transmitted in DCDC 120, leads to S4 at time point t b The rising edge 194b, where time point t b At time t a The time difference between them is T D , i.e., the transmission delay of DCDC 120. The rising edge 194b of S4 triggers S3 to switch to a high level (i.e., 1), and causes S3 to switch to a high level (i.e., 1) at time t b The rising edge 193b causes the multiplexer 110 to select S1[1] as S2 and causes S2 to be at time t b Afterwards, at time t c (Time point t c and time point t b The time difference between them is T / 2-T D ), since the multiplexer 110 selects S1[1] as S2, the rising edge 191c of S1[1] causes the rising edge 192c of S2. The rising edge 192c of S2 is transmitted in the DCDC 120 and causes S4 to be switched at time point t d The rising edge 194d triggers S3 to switch to a low level (ie, 0), and causes S3 to be at time point t d The falling edge 193d causes the multiplexer 110 to select S1[0] as S2, and causes S2 to d The falling edge 192d, where the time point t d and time point t c The time difference between them is T D , which is the transfer delay of DCDC 120. Then, at time point t e (Time point t e and time point t d The time difference between them is T / 2-T D ), because the multiplexer 110 selects S1[0] as S2, the rising edge 190e of S1[0] leads to the rising edge 192e of S2. The duty cycle of S2 is equal to T D Divide by T / 2, as shown below:

[0059]

[0060] Among them, D o Represents the duty cycle of S2.

[0061] The purpose of the duty cycle detector 140 and the controller 150 is to ctl Establish appropriate values so that D o Equal to the target duty cycle value Dt .

[0062] The duty cycle detector 140 outputs E according to the following formula: dc :

[0063]

[0064] When E dc When it is 1, it means that the duty cycle of S2 is greater than the target duty cycle value D t , so it is necessary to reduce the duty cycle of S2. dc When it is 0, it means that the duty cycle of S2 is less than the target duty cycle value D t , so the duty cycle of S2 needs to be increased.

[0065] In one embodiment, W ctl is an integer, and W ctl The larger the value of DCDC 120, the greater the transfer delay T D In one embodiment, the controller 150 periodically updates W according to the following formula: ctl Value:

[0066]

[0067] in, Represents W ctl The old value before the update, and Represents W ctl The new value after updating. When the duty cycle of S2 is too large (ie, D o >D t ) when E dc is 1, the controller 150 reduces W ctl The value of makes the transmission delay of DCDC 120 smaller, thereby reducing the duty cycle of S2. When the duty cycle of S2 is too small (i.e., D o <D t ) when E dc is 0, the controller 150 increases W ctl The value of increases the transmission delay of DCDC 120, thereby increasing the duty cycle of S2.

[0068] Figure 2A A schematic diagram of a duty cycle detection circuit 200A that can be used to implement the duty cycle detector 140 is shown. The duty cycle detection circuit 200A includes a low-pass filter 210 including a resistor 211 and a capacitor 212; a resistor divider 220 including a resistor 221 and a resistor 222; and a comparator 230. The low-pass filter 210 receives S2 and outputs an average voltage V a , average voltage V a About Do V DD For example, if the duty cycle of S2 is 40%, then V a About 0.4V DD , because S2 remains high for 40% of the time. DD The output of the resistor divider 220 represents D t The target voltage V t , D t is the target duty cycle value of S2. Let the resistance of resistor 221 and resistor 222 be R 221 and R 222 , then R 221 It can be determined according to the following formula:

[0069]

[0070] Target voltage V t According to V DD The voltage divided by resistors 221 and 222 is determined by:

[0071]

[0072] Equation (5) is applied. Comparator 230 converts V a With V t Compare and output E dc , E dc Indicates V a Is it higher than V t When V a Higher (lower) than V t When E dc is 1(0), which means D o V DD Greater than (less than) D t V DD , so D o Greater than (less than) D t When D o Greater than (less than) D t When E dc =1(0), the controller 150 decreases (increases) W ctl value, resulting in a transmission delay T D and the duty cycle of S2 decreases (increases). Therefore, the duty cycle of S2 is adjusted in a closed loop manner and gradually becomes equal to D t .

[0073] At the target duty cycle value D t For the special case of 50%, Figure 2B Another duty cycle detector 200B shown in FIG can be used to implement Figure 1AThe duty cycle detector 140. The duty cycle detector 200B includes: a first low-pass filter 240, which includes a resistor 241 and a capacitor 242; an inverter 270; a second low-pass filter 250, which includes a resistor 251 and a capacitor 252; and a comparator 260. The inverter 270 receives S2 and outputs a complementary signal S'2, which is the inverted logic of S2. Since the duty cycle of S2 is D o , so the working period of S′2 is 1-D o (Because S′2 is complementary to S2). The first low-pass filter 240 receives S2 and outputs a first average voltage V p (approximately equal to D o V DD For example, if the duty cycle of S2 is 40%, then V p About 0.4V DD , because S2 remains high for 40% of the time. DD The second low-pass filter 250 receives S′2 and outputs a second average voltage V n (approximately equal to (1-D o )V DD For example, if the duty cycle of S2 is 40%, since S′2 remains at a high level V for 60% of the time, DD (Because S′2 is complementary to S2), so V n About 0.6V DD The comparator 260 converts V p With V n Compare and output E dc , E dc Indicates V p Is it higher than V n When V p Above / below V n When E dc is 1(0), indicating D o V DD Greater than / less than (1-D o )V DD , so D o Greater than / less than (1-D o ), and that means D o Greater / less than 50%. Therefore, if the target duty cycle value D t If the duty cycle is 50%, the duty cycle detector 200B can perform duty cycle detection on S2.

[0074] Comparator (e.g. Figure 2A The comparator 230 or Figure 2BComparator 260 is a circuit that receives two voltages and outputs a logic signal indicating which of the two voltages is higher. This circuit can be implemented using any circuit known in the art at the discretion of the circuit designer. Inverters (such as inverter 270) perform logical inversion and are well known in the art, so they will not be described in detail here.

[0075] Figure 3 Describing the implementation Figure 1A Schematic diagram of the digital control delay circuit 300 of the DCDC 120. The digital control delay circuit 300 includes: an encoder 310, the encoder 310 is configured to ctl Encoded into a plurality of logic control signals C1, C2, C3, ..., etc.; and a plurality of programmable delay circuits (PDC) 311, 312, 313, ..., etc., which are respectively controlled by the plurality of logic signals C1, C2, C3, ..., etc., and are cascaded to form a delay chain, which is configured to receive S2 and output S4, wherein the rising edge of S2 will be transmitted along the delay chain and become the rising edge of S4 at the end of the delay chain. Figure 3 As shown (as an example and not to limit the present invention), seven logic control signals C1, C2, C3, C4, C3, C6 and C7 are shown, as well as seven programmable delay circuits 311, 312, 313, 314, 315, 316 and 317. The seven programmable delay circuits 311, 312, 313, 314, 315, 316 and 317 are cascaded and controlled by C1, C2, C3, C4, C3, C6 and C7 respectively. In one embodiment, the programmable delay circuits 311, 312, 313, ..., etc. are all the same circuits, but are independently controlled by C1, C2, C3, ..., etc. Each programmable delay circuit introduces a delay determined by its respective logic control signal. Programmable delay circuits 311 (312, 313, 314, 315, 316, 317) introduce a delay controlled by C1 (C2, C3, C4, C5, C6, C7). When C1 (C2, C3, C4, C5, C6, C7) is 0, programmable delay circuits 311 (312, 313, 314, 315, 316, 317) have a small delay Δ0. When C1 (C2, C3, C4, C5, C6, C7) is 1, programmable delay circuits 311 (312, 313, 314, 315, 316, 317) have a large delay Δ1, where Δ1 is greater than Δ0. Here, "large delay" and "small delay" are relative terms. Therefore, when the DCDC 120 is implemented by the digitally controlled delay circuit 300 , the propagation delay of the DCDC 120 is:

[0076] T D =∑ i＝1,2,3 ,…(C i Δ1+(1-C i )Δ0) (7)

[0077] In one embodiment, the encoder 310 encodes W according to a “thermometer code” encoding method. ctl The encoding is C1, C2, C3, etc. The encoding method can be described by the following formula:

[0078]

[0079] Where i is an index, and its value is 1, 2, 3, ... For this example including seven programmable delay circuits, the encoding table is as follows:

[0080] <![CDATA[W ctl ]]> 0 1 2 3 4 5 6 7 <![CDATA[C1]]> 0 1 1 1 1 1 1 1 <![CDATA[C2]]> 0 0 1 1 1 1 1 1 <![CDATA[C3]]> 0 0 0 1 1 1 1 1 <![CDATA[C4]]> 0 0 0 0 1 1 1 1 <![CDATA[C5]]> 0 0 0 0 0 1 1 1 <![CDATA[C6]]> 0 0 0 0 0 0 1 1 <![CDATA[C7]]> 0 0 0 0 0 0 0 1

[0081] With W ctl As the value increases, more of the logic control signals C1, C2, C3, etc. are set to 1, so that more of the PDCs 311, 312, 313, etc. are controlled to have larger delays. As a result, the transmission delay of the digitally controlled delay circuit 300 increases.

[0082] A schematic diagram of an embodiment of a PDC 314 is shown within detail block COB314. PDC 314 receives input from PDC 313 and outputs output to PDC 315 based on logic control signal C4. PDC 314 includes a cascaded first inverter INV1 (including a first NMOS transistor MN1 and a first PMOS transistor MP1) and a second inverter INV2 (including a second NMOS transistor MN2 and a second PMOS transistor MP2), as well as an adjustable capacitor PC314 (including a capacitor CL and a switch implemented as a third NMOS transistor MN3 controlled by logic control signal C4). Adjustable capacitor PC314 implements an adjustable capacitive load at internal node N314 between first inverter INV1 and second inverter INV2; a higher capacitive load on internal node N314 results in a greater delay in signal transmission from PDC 313 to PDC 315. When C4 is 1, the third NMOS transistor MN3 is turned on, and the capacitance of the adjustable PC 314 is approximately equal to the capacitance of the capacitor CL. When C4 is 0, the third NMOS transistor MN3 is turned off, and the capacitance of the adjustable PC 314 is approximately zero. As a result, when C4 is 0, the PDC 314 has a small delay, and when C4 is 1, the PDC 314 has a large delay.

[0083] The same circuitry inside the detail box COB314 is used for all other programmable delay cells, only the input, output and logic control signals are different.

[0084] The one-to-two frequency divider circuit 130 includes a data flip flop (DFF) 131 having a data pin "D", an output pin "Q", a complementary output pin "QB", and an edge-triggered pin represented by a wedge. The DFF 131 is triggered by the rising edge of S4 and outputs S3 through its output pin "Q". At the same time, negative feedback is formed by connecting the complementary output pin "QB" to the data pin "D". In the prior art, the data flip flop 131 itself is well known, and when the data flip flop 131 is used as shown in FIG. Figure 1A The negative feedback topology shown can be used to implement a one-to-two frequency division function, which is also well known and will not be described in detail here.

[0085] like Figure 4 As shown in the flowchart of , the frequency multiplication method according to an embodiment of the present disclosure includes: (step 410) receiving a first clock, the first clock having a fifty percent duty cycle and being a two-phase clock including a first phase and a second phase; (step 420) selecting one of the first phase and the second phase of the first clock through a multiplexer according to a third clock to output a second clock; (step 430) using a digitally controlled delay circuit to delay the second clock to a fourth clock according to a digital word; (step 440) using a one-to-two frequency division circuit to output a third clock according to the fourth clock; (step 450) using a duty cycle detector to generate a logic signal according to a comparison between the duty cycle of the second clock and a target duty cycle value; (step 460) updating the digital word according to the logic signal.

[0086] Those skilled in the art will readily observe that various modifications and variations can be made to the apparatus and method while maintaining the teachings of the present disclosure. Therefore, the above disclosure should not be interpreted as being limited only by the limits of the claims.

Claims

1. A frequency multiplication circuit, comprising: A multiplexer is used to receive a first clock and output a second clock according to a third clock, wherein The first clock has a 50% duty cycle and is a two-phase clock including a first phase and a second phase; a digitally controlled delay circuit, configured to receive the second clock and output a fourth clock according to a digital word; a one-to-two frequency dividing circuit, configured to receive the fourth clock and output the third clock; a duty cycle detector for receiving the second clock and outputting a logic signal according to a comparison between a duty cycle of the second clock and a target duty cycle value; as well as A controller is used for outputting the digital word according to the logic signal.

2. The frequency multiplication circuit according to claim 1, wherein: When the value of the digital word is larger, the propagation delay of the digital controlled delay circuit is larger.

3. The frequency multiplication circuit according to claim 2, wherein: The controller increases the value of the digital word when the logic signal indicates that the duty cycle of the second clock is less than the target duty cycle value, and decreases the value of the digital word when the logic signal indicates that the duty cycle of the second clock is greater than the target duty cycle value.

4. The frequency multiplication circuit according to claim 3, wherein: The digital controlled delay circuit includes: an encoder for encoding the digital word into a plurality of logic control signals; and a plurality of programmable delay circuits, each of which is controlled by the plurality of logic control signals. The plurality of programmable delay circuits are cascaded and used to form a delay chain to allow the second clock to pass and generate the fourth clock.

5. The frequency multiplication circuit according to claim 4, wherein: The encoder is based on thermometer code.

6. The frequency multiplying circuit according to claim 5, wherein: Each of the plurality of programmable delay circuits has a large delay when the logic control signal thereof is at a high level, and has a small delay when the logic control signal thereof is at a low level.

7. The frequency multiplying circuit according to claim 1, wherein: The duty cycle detector includes: a low-pass filter for receiving the second clock and outputting an average voltage; a voltage divider for receiving a power supply voltage and outputting a target voltage; and a comparator for outputting the logic signal according to the comparison between the average voltage and the target voltage.

8. The frequency multiplying circuit according to claim 7, wherein: The target voltage is equal to the power supply voltage multiplied by the target duty cycle value.

9. The frequency multiplying circuit according to claim 1, wherein: The duty cycle detector includes: a first low-pass filter for receiving the second clock and outputting a first average voltage; an inverter for receiving the second clock and outputting a complementary clock; a second low-pass filter for receiving the complementary clock and outputting a second average voltage; and a comparator for outputting the logic signal based on the comparison between the first average voltage and the second average voltage.

10. A frequency doubling method, comprising: receiving a first clock having a fifty percent duty cycle and being a two-phase clock including a first phase and a second phase; Selecting one of the first phase and the second phase of the first clock using a multiplexer according to a third clock to output a second clock; Delaying the second clock to a fourth clock according to a digital word using a digitally controlled delay circuit; Using a one-to-two frequency dividing circuit to output the third clock according to the fourth clock; using a duty cycle detector to generate a logic signal based on a comparison of a duty cycle of the second clock with a target duty cycle value; and The digital word is updated according to the logic signal.

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