Asymmetric input-output structure

Abstract

The application discloses an asymmetric input / output structure, which comprises a first power supply node and a second power supply node; a pull-up unit and a pull-down unit, which are sequentially connected between the first power supply node and the second power supply node, and a node between the pull-up unit and the pull-down unit is connected with an input / output node. The pull-up unit comprises one or more pull-up transistors, the pull-down unit comprises one or more pull-down transistors, and the number of the pull-up transistors is different from that of the pull-down transistors. The asymmetric input / output structure can improve the performance of a circuit while meeting the reliability requirement.

Description

Technical Field

[0001] This invention generally relates to the field of integrated circuit technology, and in particular to an asymmetric input / output structure. Background Technology

[0002] With current technology, integrated circuits (ICs) can perform multiple different types of tasks simultaneously. Furthermore, packaging many circuits within a single chip or integrating circuits for different purposes into a single component increases the overall capabilities of the integrated circuit. An integrated circuit typically includes one or more input / output (I / O) units, which are the interface circuits through which signals are exchanged between the internal circuitry of the integrated circuit and external device circuitry.

[0003] Current input / output architectures are all symmetrical. When the operating voltage of a single transistor is not lower than the supply voltage, a single-transistor design is generally used, meaning both NMOS and PMOS transistors are single-transistor symmetrical structures. When the operating voltage of a single transistor is lower than the supply voltage, a stacked design is used, meaning both NMOS and PMOS transistors are dual-transistor symmetrical structures, or multiple-transistor (including series and parallel) symmetrical structures. Current design schemes, especially stacked designs, are often not optimal, and this problem becomes more pronounced as chip manufacturing processes advance to more advanced nodes.

[0004] On the one hand, as the linewidth of manufacturing processes continues to decrease, the operating voltage of devices also decreases. In some applications, such as high-speed interfaces, the nominal withstand voltage of the fastest devices may be lower than the supply voltage. Stacked designs often become a choice to meet withstand voltage and reliability requirements, but this comes at the cost of some performance degradation. On the other hand, the manufacturing processes for NMOS and PMOS are becoming increasingly separate, such as gate dielectric, work function matching materials, and strain gauge processes. This can lead to significant differences in the reliability indicators of NMOS and PMOS, manifested in time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and bias temperature instability (BTI). Based on these characteristics and specific design and application considerations, including voltage range, duty cycle, data switching rate, area, and biasing method, the lifespan of NMOS and PMOS can vary considerably. Therefore, this application proposes a high-performance asymmetric input / output structure. Summary of the Invention

[0005] The purpose of this invention is to provide an asymmetric input / output structure that uses a single transistor and stacked design to reduce power consumption and improve circuit performance while meeting the requirements for service life and reliability.

[0006] One aspect of this application discloses an asymmetric input / output structure, including:

[0007] The first power node and the second power node are respectively connected to the first voltage and the second voltage;

[0008] Pull-up unit and pull-down unit, the pull-up unit and the pull-down unit are connected between the first power node and the second power node, and the node between the pull-up unit and the pull-down unit is connected to the input / output node;

[0009] The pull-up unit includes one or more pull-up transistors, the pull-down unit includes one or more pull-down transistors, and the number of pull-up transistors and pull-down transistors are different, and the first voltage is higher than the second voltage.

[0010] In a preferred embodiment, the pull-up unit includes a first pull-up transistor, and the pull-down unit includes a first pull-down transistor and a second pull-down transistor, wherein the pull-up transistor is a PMOS transistor and the pull-down transistor is an NMOS transistor.

[0011] In a preferred embodiment, the source of the first pull-up transistor is connected to the first power supply node, and the drain is connected to the input / output node. When the first pull-up transistor is turned on, its gate is connected to ground voltage, and when it is turned off, its gate is connected to the first voltage.

[0012] The source of the first pull-down transistor is connected to the second power supply node, and the drain is connected to the source of the second pull-down transistor. When the first pull-down transistor is turned on, its gate is connected to the maximum operating voltage, and when it is turned off, its gate is connected to the ground voltage.

[0013] The drain of the second pull-down transistor is connected to the input / output node, and the gate is connected to the maximum operating voltage, or: when the second pull-down transistor is turned on, its gate is connected to the first voltage, and when it is turned off, its gate is connected to the voltage difference between the first voltage and the maximum operating voltage.

[0014] In a preferred embodiment, the first voltage is greater than the maximum operating voltage.

[0015] In a preferred embodiment, the first pull-up transistor, the first pull-down transistor, and the second pull-down transistor are each formed by one or more transistors connected in parallel.

[0016] In a preferred embodiment, the pull-up unit includes a first pull-up transistor and a second pull-up transistor, and the pull-down unit includes a first pull-down transistor. The pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor.

[0017] In a preferred embodiment, the source of the first pull-up transistor is connected to the first power supply node, and the drain is connected to the source of the second pull-up transistor. When the first pull-up transistor is turned on, its gate is connected to the voltage difference between the first voltage and the maximum operating voltage, and when it is turned off, its gate is connected to the first voltage.

[0018] The drain of the second pull-up transistor is connected to the input / output node, and the gate is connected to the voltage difference between the first voltage and the maximum operating voltage; or: when the second pull-up transistor is turned on, its gate is connected to the voltage difference between the first voltage and the maximum operating voltage, and when it is turned off, its gate is connected to the first voltage.

[0019] The source of the first pull-down transistor is connected to the second power supply node, and the drain is connected to the input / output node. When the first pull-down transistor is turned on, its gate is connected to the first voltage, and when it is turned off, its gate is connected to the ground voltage.

[0020] In a preferred embodiment, the first voltage is greater than the maximum operating voltage.

[0021] In a preferred embodiment, the first pull-up transistor, the second pull-up transistor, and the first pull-down transistor are each formed by one or more transistors connected in parallel.

[0022] In a preferred embodiment, the node between the pull-up unit and the pull-down unit is connected to the input / output node via a resistor.

[0023] In the asymmetric input / output structure disclosed in this application, the pull-up and pull-down units adopt single-transistor or stacked structures, respectively. This reduces the device size for the same output impedance, thereby reducing device capacitance and parasitic capacitance, and lowering dynamic power consumption. Furthermore, it reduces the sensitivity of output impedance to output voltage changes, improves the linearity of output impedance, avoids inter-symbol interference, and improves the signal integrity of the output signal. Attached Figure Description

[0024] Non-limiting and non-exhaustive embodiments of this application are described with reference to the following figures, wherein, unless otherwise stated, the same reference numerals refer to the same parts in the various figures.

[0025] Figure 1 A schematic diagram of an asymmetric input / output structure employing a single PMOS transistor and two NMOS transistors according to an embodiment of this application is shown.

[0026] Figure 2 A schematic diagram of an asymmetric input / output structure employing a single PMOS transistor and two NMOS transistors according to another embodiment of this application is shown.

[0027] Figure 3 A schematic diagram of an asymmetric input / output structure employing two PMOS transistors and a single NMOS transistor according to an embodiment of this application is shown.

[0028] Figure 4 A schematic diagram of an asymmetric input / output structure employing two PMOS transistors and a single NMOS transistor, according to another embodiment of this application, is shown.

[0029] Figure 5 A schematic diagram of an asymmetric input / output structure employing two PMOS transistors is shown for a pull-up unit according to another embodiment of this application.

[0030] Figure 6 A schematic diagram of an asymmetric input / output structure employing three PMOS transistors is shown for a pull-up unit according to another embodiment of this application. Detailed Implementation

[0031] Various aspects and examples of this application will now be described. The following description provides specific details for a thorough understanding and implementation of these examples. However, those skilled in the art will understand that this application can be practiced without many of these details.

[0032] Additionally, some well-known structures or functions may not be shown or described in detail in order to be concise and avoid unnecessarily obscuring the relevant descriptions.

[0033] The terminology used in the description given below is intended to be interpreted in its broadest and most reasonable manner, even when used in conjunction with the detailed description of certain specific examples of this application. Some terms may even be emphasized below; however, any term intended to be interpreted in any restrictive manner will be explicitly and specifically defined in this detailed description section.

[0034] The first embodiment of this application discloses an asymmetric input / output structure, which includes: a first power node and a second power node, a pull-up unit and a pull-down unit connected between the first power node and the second power node, and an input / output node connected between the pull-up unit and the pull-down unit. The pull-up unit includes one or more pull-up transistors, and the pull-down unit includes one or more pull-down transistors, with the number of pull-up transistors and pull-down transistors being different. The pull-up transistors can be of a first type, and the pull-down transistors can be of a second type. The input / output node can be connected to external circuitry to enable signal interaction between the internal circuitry of the chip and the circuitry of external devices.

[0035] In one embodiment, the pull-up unit may include one, two, three or more pull-up transistors, and the pull-down unit may include one, two, three or more pull-down transistors, wherein the number of pull-up transistors and pull-down transistors are different. In one embodiment, the pull-up unit is a single-transistor design, and the pull-down unit is a stacked design; for example, the pull-up unit includes one pull-up transistor, and the pull-down unit includes two pull-down transistors.

[0036] It should be understood that signal input and output are achieved by controlling the on and off states of the pull-up and pull-down units, i.e., controlling the on and off states of the pull-up and pull-down transistors. When a pull-up or pull-down unit comprises two or more transistors, the on and off states must simultaneously turn on and off the two or more transistors of the pull-up or pull-down unit.

[0037] Figure 1 A schematic diagram of an embodiment of an asymmetric input / output structure is shown. This asymmetric input / output structure includes a first power node S1, a second power node S2, a pull-up unit 10 and a pull-down unit 20 connected between the first power node S1 and the second power node S2, and a node S0 between the pull-up unit 10 and the pull-down unit 20 connected to an input / output node 30. The input / output node 30 can be a pad or a pin. The pull-up unit 10 includes a first pull-up transistor P1, and the pull-down unit 20 includes a first pull-down transistor N1 and a second pull-down transistor N2, wherein the pull-up transistor P1 is a PMOS transistor, and the pull-down transistors N1 and N2 are NMOS transistors; the voltage of the first power node S1 is a first voltage VDD, and the voltage of the second power node S2 is a second voltage VSS. Typically, the first voltage VDD is higher than the second voltage VSS.

[0038] In one embodiment, the source of the first pull-up transistor P1 is connected to the first power supply node S1, and the drain is connected to the input / output node 30. The first pull-up transistor P1 is ON when its gate is connected to ground, and OFF when its gate is connected to a first voltage VDD. Preferably, the first voltage VDD can be the power supply voltage. The source of the first pull-down transistor N1 is connected to the second power supply node S2, and the drain is connected to the source of the second pull-down transistor N2. The first pull-down transistor N1 is ON when its gate is connected to the maximum operating voltage Vmax, and OFF when its gate is connected to ground GND. The maximum operating voltage is the maximum withstand voltage for the transistor. In one embodiment, the first voltage VDD is greater than the maximum operating voltage Vmax. In one embodiment, the second voltage VSS is less than the maximum operating voltage Vmax. Preferably, the second voltage VSS is ground. The drain of the second pull-down transistor N2 is connected to the input / output node 30, and its gate is connected to the maximum operating voltage Vmax, regardless of whether the second pull-down transistor is ON or OFF.

[0039] Typically, the first voltage VDD can be greater than the transistor's maximum operating voltage Vmax. However, those skilled in the art should understand that the first voltage VDD can be less than or equal to the transistor's maximum operating voltage Vmax. This is a setting made according to the actual operating needs of the circuit, and the present invention is not limited thereto.

[0040] Figure 2 A schematic diagram of another embodiment of an asymmetric input / output structure is shown. The circuit structure in this embodiment is similar to... Figure 1 The same as shown, and the gate voltages of the first pull-up transistor P1 and the first pull-down transistor N1 when they are turned on and off are the same as those shown. Figure 1 The bias conditions are the same. When the gate of the second pull-down transistor N2 is connected to the first voltage VDD, the second pull-down transistor N2 is turned on; when the gate of the second pull-down transistor N2 is connected to the voltage difference (VDD-Vmax) between the first voltage VDD and the maximum operating voltage Vmax, the second pull-down transistor N2 is turned off. In this embodiment, since the gate voltage VDD-Vmax applied when the second pull-down transistor N2 is turned off is less than the maximum operating voltage Vmax, the gate-source voltage at the time of turn-off is smaller, thereby reducing the channel leakage current and lowering the static power consumption.

[0041] In one embodiment, node S0 between the pull-up unit 10 and the pull-down unit 20 can be connected to the input / output node 30 via a resistor (not shown in the figure).

[0042] Figure 3A schematic diagram of another embodiment of an asymmetric input / output structure is shown. This asymmetric input / output structure includes a first power node S1, a second power node S2, a pull-up unit 10 and a pull-down unit 30 connected between the first power node S1 and the second power node S2, and a node S0 between the pull-up unit 10 and the pull-down unit 30 connected to the input / output node 30. The pull-up unit 10 includes a first pull-up transistor P1 and a second pull-up transistor P2, and the pull-down unit 30 includes a first pull-down transistor N1. The pull-up transistors P1 and P2 are PMOS transistors, and the pull-down transistor N1 is an NMOS transistor. The voltage of the first power node S1 is a first voltage VDD, and the voltage of the second power node S2 is a second voltage VSS. Typically, the first voltage VDD is higher than the second voltage VSS.

[0043] In one embodiment, the source of the first pull-up transistor P1 is connected to the first power supply node S1, and its drain is connected to the source of the second pull-up transistor P2. The first pull-up transistor P1 is ON when its gate is connected to the voltage difference (VDD-Vmax) between the first voltage VDD and the maximum operating voltage Vmax; and OFF when its gate is connected to the first voltage VDD. The maximum operating voltage is the maximum voltage the transistor can withstand. In one embodiment, the first voltage VDD is greater than the maximum operating voltage Vmax. In another embodiment, the second voltage VSS is less than the maximum operating voltage Vmax; preferably, VSS is ground. The drain of the second pull-up transistor P2 is connected to the input / output node 30, and its gate is connected to the voltage difference (VDD-Vmax) between the first voltage VDD and the maximum operating voltage Vmax, regardless of whether the second pull-up transistor P2 is ON or OFF. The source of the first pull-down transistor N1 is connected to the second power supply node S2, the drain is connected to the input / output node 30, and the first pull-down transistor N1 is turned on when the gate is connected to the first voltage VDD and turned off when the gate is connected to the ground voltage GND.

[0044] Figure 4 A schematic diagram of another embodiment of an asymmetric input / output structure is shown. The circuit structure in this embodiment is similar to... Figure 3 The structures are the same, and the gate voltages of the first pull-up transistor P1 and the first pull-down transistor N1 are the same when they are turned on and off. Figure 3The biasing is the same. The second pull-up transistor P2 is turned on when its gate is connected to the voltage difference (VDD-Vmax) between the first voltage VDD and the maximum operating voltage Vmax, and turned off when its gate is connected to the first voltage VDD. In this embodiment, the gate voltage VDD-Vmax when the second pull-up transistor P2 is turned off is less than the voltage Vmax, which makes the gate-source voltage smaller when it is turned off, thereby reducing the channel leakage current and reducing the static power consumption.

[0045] In one embodiment, node S0 between the pull-up unit 10 and the pull-down unit 30 is connected to the input / output node 30 via a resistor (not shown in the figure).

[0046] It should be noted that the one, two, three, or more transistors in this application are defined by electrical connections, not by layout or subjective understanding. Taking a pull-up cell as an example, such as... Figure 5 As shown, the pull-up unit 10 may include two pull-up transistors P11 and P12 connected in parallel, such as... Figure 6 As shown, the pull-up unit 10 includes three pull-up transistors P11, P12, and P13 connected in parallel. Although a PMOS or NMOS can be composed of two or more devices connected in parallel, from an electrical connection perspective, all the ports connected to the gate, source, and drain are exactly the same as those in the case of a single transistor. Therefore, these cases should all be considered as "one" transistor, and thus fall within the scope of protection of this application.

[0047] The asymmetric input / output structure disclosed in this application employs single-transistor or stacked structures for the pull-up and pull-down units, respectively. This reduces device size for the same output impedance, thereby decreasing device capacitance and parasitic capacitance, and lowering dynamic power consumption. Furthermore, it reduces the sensitivity of output impedance to output voltage variations, improves output impedance linearity, avoids inter-symbol interference, and enhances signal integrity. It should be noted that for more general cases of asymmetric input / output structures (not limited to single-transistor at one end and stacked dual-transistor at the other), such as single-transistor at one end and three-transistor at the other; or three-transistor at one end and stacked dual-transistor at the other, the aforementioned advantages still apply and are therefore within the scope of this application.

[0048] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0049] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

[0050] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. An asymmetric input / output structure, characterized in that, include: The first power node and the second power node are respectively connected to the first voltage and the second voltage; Pull-up unit and pull-down unit, the pull-up unit and the pull-down unit are connected between the first power node and the second power node, and the node between the pull-up unit and the pull-down unit is connected to the input / output node; The pull-up unit includes M series-connected pull-up transistors, and the pull-down unit includes N series-connected pull-down transistors, where M and N are both integers greater than or equal to 1, and M and N are not equal; the first voltage is higher than the second voltage; Among them, the M series-connected pull-up transistors are all PMOS transistors, and the N series-connected pull-down transistors are all NMOS transistors.

2. The asymmetric input / output structure as described in claim 1, characterized in that, Each of the M series-connected pull-up transistors and the N series-connected pull-down transistors is composed of a single transistor or multiple parallel transistors, and the multiple parallel transistors are electrically equivalent to a single transistor.

3. The asymmetric input / output structure as described in claim 1, characterized in that, The pull-up unit includes a first pull-up transistor, and the pull-down unit includes a first pull-down transistor and a second pull-down transistor connected in series.

4. The asymmetric input / output structure as described in claim 3, characterized in that, The source of the first pull-up transistor is connected to the first power supply node, and the drain is connected to the input / output node. When the first pull-up transistor is turned on, its gate is connected to the ground voltage, and when it is turned off, its gate is connected to the first voltage. The source of the first pull-down transistor is connected to the second power supply node, and the drain is connected to the source of the second pull-down transistor. When the first pull-down transistor is turned on, its gate is connected to the maximum operating voltage, and when it is turned off, its gate is connected to the ground voltage. The drain of the second pull-down transistor is connected to the input / output node, and the gate is connected to the maximum operating voltage, or: when the second pull-down transistor is turned on, its gate is connected to the first voltage, and when it is turned off, its gate is connected to the voltage difference between the first voltage and the maximum operating voltage.

5. The asymmetric input / output structure as described in claim 4, characterized in that, The first voltage is greater than the maximum operating voltage.

6. The asymmetric input / output structure as described in claim 1, characterized in that, The pull-up unit includes a first pull-up transistor and a second pull-up transistor connected in series, and the pull-down unit includes a first pull-down transistor.

7. The asymmetric input / output structure as described in claim 6, characterized in that, The source of the first pull-up transistor is connected to the first power supply node, and the drain is connected to the source of the second pull-up transistor. When the first pull-up transistor is turned on, its gate is connected to the voltage difference between the first voltage and the maximum operating voltage. When it is turned off, its gate is connected to the first voltage. The drain of the second pull-up transistor is connected to the input / output node, and the gate is connected to the voltage difference between the first voltage and the maximum operating voltage; or: when the second pull-up transistor is turned on, its gate is connected to the voltage difference between the first voltage and the maximum operating voltage, and when it is turned off, its gate is connected to the first voltage. The source of the first pull-down transistor is connected to the second power supply node, and the drain is connected to the input / output node. When the first pull-down transistor is turned on, its gate is connected to the first voltage, and when it is turned off, its gate is connected to the ground voltage.

8. The asymmetric input / output structure as described in claim 7, characterized in that, The first voltage is greater than the maximum operating voltage.

9. The asymmetric input / output structure as described in claim 1, characterized in that, The node between the pull-up unit and the pull-down unit is connected to the input / output node via a resistor.

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