Method and apparatus for testing non-linearity of high-speed serial interface chip

Abstract

The application discloses a method and device for testing non-linearity of a high-speed serial interface chip, which hardly needs any testing equipment and has extremely low testing cost. The method comprises the following steps: providing a first local oscillation clock to a data source and a second local oscillation clock to a chip to be tested, wherein the first local oscillation clock and the second local oscillation clock have different frequencies; outputting a data signal from the data source to the chip to be tested, wherein the chip to be tested comprises a clock and data recovery circuit; sampling a control code generated by the chip to be tested after the clock and data recovery circuit is locked; calculating a statistical value of the control code and calculating differential non-linearity and integral non-linearity according to the statistical value.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit, and particularly relates to a method for testing non-linearity of a high-speed serial interface chip and a device thereof. BACKGROUND

[0002] A digitally controlled phase interpolator is usually used in the clock and data recovery circuit of the receiving end of a high-speed serial interface chip. The input of the phase interpolator is usually a quadrature clock signal, and according to different control codes, the phase interpolator can generate a plurality of phase clocks through interpolation. Referring to Figure 1 The basic principle of the phase interpolator can be explained by the following formula:

[0003]

[0004]

[0005] Wherein, α and β represent the control codes of two quadrature clock signals respectively, and sinθ and cosθ represent the two quadrature clock signals. By adjusting the values of different α and β through a digital circuit, various phases between 0° and 360° can be generated. In actual circuit design, the number of bits of the control code is limited, so the number of phases that can be generated in name is also limited. Assuming that the number of bits of the control code is M, the number of phases of the corresponding phase interpolator is N=2 M .

[0006] The phase interpolator is usually an important part of the clock and data recovery circuit, and its performance directly determines the overall performance of the entire serial chip, so the evaluation of its performance is an important part of the test of the serial chip. An important parameter for measuring the performance of a phase interpolator is its linearity, that is, the consistency of the interval between each generated phase. The linearity is usually divided into differential non-linearity (DNL) and integral non-linearity (INL). The differential non-linearity is used to measure the deviation between the interval of two adjacent phases and the ideal interval. The integral non-linearity is used to measure the deviation between the absolute position of the phase and its ideal position

[0007] In the current high-speed interface chip, since the interpolator usually works at several GHz, even tens of GHz, and each phase interval is usually only a few hundred femtoseconds (fs, 10 -15) magnitude. It is very difficult to actually measure the linearity of such a circuit through instruments. On one hand, the high-speed clock signal outputted by the phase interpolator needs to be sent to the output port of the chip, and the design of such a high-speed chip output port is very difficult, and the requirements for packaging, test board and even test cable are very high, which requires huge cost to complete the output of the signal. Even so, the signal will be disturbed by many non-ideal factors in the transmission process, such as circuit noise, reflection introduced by packaging and test board, crosstalk and the like. These will affect the accuracy of the test results. On the other hand, testing such a small phase interval usually requires a very expensive real-time sampling oscilloscope. However, for a 56G or even 112G high-speed serial interface chip, even the most advanced sampling oscilloscope is difficult to guarantee sufficient resolution to accurately measure the femtosecond-level phase deviation.

[0008] In order to avoid the above problems, some circuit design engineers will specially design some auxiliary circuits in the interface chip for measuring the performance of the phase interpolator. However, these circuits will increase the area overhead of the chip, and some will become an additional load of the phase integrator, which will reduce its dynamic performance, and it is not worth the cost. SUMMARY

[0009] The purpose of the present application is to provide a non-linearity test method and device for a high-speed serial interface chip, which almost does not need any test equipment and has very low test cost.

[0010] One aspect of the present application discloses a non-linearity test method for a high-speed serial interface chip, comprising:

[0011] providing a first local oscillator clock to a data source and providing a second local oscillator clock to a chip to be tested, the frequencies of the first local oscillator clock and the second local oscillator clock being different;

[0012] outputting a data signal from the data source to the chip to be tested, the chip to be tested comprising a clock and data recovery circuit;

[0013] sampling the control code generated by the chip to be tested after the clock and data recovery circuit is locked, calculating the statistical value of the control code and calculating the differential non-linearity and integral non-linearity according to the statistical value.

[0014] In a preferred embodiment, the differential non-linearity is calculated according to the statistical value by the following formula

[0015] DNL i = -(B i+1 -B i ) / LSB

[0016] The integral non-linearity is calculated according to the statistical value by the following formula

[0017]

[0018] wherein, LSB is the average value of the control code, N is the number of steps of the phase interpolator, B i is the statistical value of the control code corresponding to the i-th step.

[0019] In a preferred embodiment, the frequency deviation of the first local clock and the second local clock is less than 100ppm.

[0020] In a preferred embodiment, the sampling is random sampling.

[0021] In a preferred embodiment, the sampling is realized by a logic analyzer.

[0022] In a preferred embodiment, the chip to be tested writes the control code into a register, and the sampling is realized by reading the register by a computer.

[0023] In a preferred embodiment, the chip to be tested has one or more of the following register read-write interfaces: SPI, I2C, MDIO, GPIO, JTAG, UART.

[0024] In a preferred embodiment, the clock and data recovery circuit comprises a phase detector, a differential path, an integral path, an integrator, an encoder and a phase interpolator, the data signal is input to the phase detector, the phase detector passes through the differential path and the integral path in parallel and is connected to the integrator, the integrator is connected to the encoder, the encoder outputs the control code to the phase interpolator, the second local clock is input to the phase interpolator, the phase interpolator recovers a clock signal and outputs it to the phase detector.

[0025] In a preferred embodiment, the data source is a high-speed serial interface chip or a bit error instrument.

[0026] Another aspect of the present application also discloses a non-linearity testing device for a high-speed serial interface chip, comprising:

[0027] a data source connected to a chip to be tested, for outputting a data signal to the chip to be tested, the chip to be tested comprising a clock and data recovery circuit;

[0028] a first crystal oscillator for providing a first local clock to the data source;

[0029] a second crystal oscillator for providing a second local clock to the chip to be tested, wherein the first local clock and the second local clock have different frequencies.

[0030] A sampling module is configured to sample the control code generated by the chip under test after the clock and data recovery circuit is locked.

[0031] A calculating module is configured to calculate a statistical value of the control code and calculate the differential nonlinearity and the integral nonlinearity according to the statistical value.

[0032] The embodiment of the present application is simple and easy to implement, and does not need to design any other auxiliary circuit in the chip, so that the test is realized, the test environment is simple to build, and the cost is low. The high-speed and high-precision circuit test problem is converted into a statistical problem of the control code, and the update speed of the control code is usually low, so it is easier to measure. In the case of long-term and large amount of data statistics, the test precision is high, and is not affected by circuit noise and jitter. BRIEF DESCRIPTION OF DRAWINGS

[0033] Non-limiting and non-exhaustive embodiments of the present application will be described with reference to the following drawings, in which the same reference notations are used to represent the same elements in each of the several views.

[0034] Figure 1 The basic principle of the phase interpolator in an embodiment of the present application is shown.

[0035] Figure 2 The schematic diagram of the clock and data recovery circuit in an embodiment of the present application is shown.

[0036] Figure 3 The statistical law diagram of the control data in an ideal case with frequency offset in an embodiment of the present application is shown.

[0037] Figure 4 The statistical law diagram of the control data in a non-ideal case with frequency offset in an embodiment of the present application is shown.

[0038] Figure 5 The schematic diagram of the nonlinearity test device in an embodiment of the present application is shown.

[0039] Figure 6 The schematic diagram of the nonlinearity test device in another embodiment of the present application is shown.

[0040] Figure 7 The flowchart of the nonlinearity test method in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0041] Various aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding of, and enabling disclosure of, these examples. One skilled in the art will understand, however, that the application can be practiced without many of these details.

[0042] Also, some of the disclosed implementations can be used in conjunction with one another in any combination. Various aspects will be appreciated, regardless of the particular

[0043] The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even if it is being used in a specific example. Certain terms can even be emphasized, below, but any terminology should be interpreted as the broadest possible way consistent

[0044] High speed serial interface chips do not transmit clock signal at the same time when transmitting data. This requires the use of clock and data recovery circuit in high speed serial interface chips, which is responsible for recovering the sampling clock from the input data, ensuring that the sampling clock can always sample data at the optimal phase. The basic block diagram of clock and data recovery circuit is shown in Figure 2 The clock and data recovery circuit is usually composed of a phase detector, a differential path, an integral path, an integrator, an encoder and a phase interpolator. The integral path can include an integrator. The phase detector is used to monitor the phase deviation between the input data and the recovered clock in real time. This phase deviation is adjusted through the integral and differential paths to adjust the phase of the phase interpolator and in turn adjust the phase of the recovered clock to compensate for the phase deviation between the recovered clock and the input data.

[0045] Usually, there is a frequency deviation between the input data and the local clock, and the phase interpolator can only adjust the phase. In order to compensate for the frequency deviation, the control code of the phase integrator will start to accumulate under the control of the integral path. In this case, the phase integrator will rotate continuously. As shown in Figure 3 The control code usually varies between the maximum and minimum values in the form of a sawtooth wave under the condition of frequency deviation.

[0046] If the linearity of the phase interpolator is ideal, that is, the phase interval obtained by any two adjacent control codes is fixed, then the statistical law of each control code under the condition of frequency deviation should be exactly the same, as shown in Figure 3 That is, the control code should conform to the average distribution after a long-term and large number of counts (statistical values). It is emphasized here that a long-term and large number of counts because in actual situations, the clock and data are subject to various noises and jitter, which will cause the count of a single control code to deviate from the average distribution. These noises and jitter are usually independent random events, and their mean value is 0 when a large amount of data is counted in the long term. Therefore, as the number of statistics increases, the influence of noise and jitter will decrease to be negligible, and the control code will not deviate from the average distribution.

[0047] In practice, due to the existence of semiconductor manufacturing process deviation, the phase interpolator has more or less a linearity error. The existence of this error will cause the phase interval introduced by each control code to be uneven, and further, with the conduction of the clock and data recovery circuit loop, the statistical law of the control code will deviate from uniform distribution. Specifically, if the phase deviation introduced by a control code is small, the phase detector will detect the phase deviation earlier due to the existence of frequency deviation, the loop will jump to the next control code in advance, and the statistical value B i of this code will be small. Conversely, if the phase deviation is larger than the ideal value, the loop will wait longer before jumping to the next control code, and the statistical value B i of this code will be large. As shown in FIG. 8, assuming that due to the existence of process deviation, the phase deviation controlled by control code B3 is large, and the phase deviation controlled by control code B4 is small, it can be clearly seen from the statistical results that this linearity error exists. Figure 4

[0048] Specifically, differential non-linearity (DNL) and integral non-linearity (INL) can be calculated by the following formulas:

[0049]

[0050] DNL i =-(B i+1 -B i ) / LSB

[0051]

[0052] wherein LSB is the mean value of the statistical values of all control codes, which is used as the number of control codes in the ideal case, N is the number of steps of the phase interpolator, B i is the statistical value of the control code corresponding to the i-th step. In this application, the original high-speed high-precision circuit test problem is converted into a statistical problem of control codes, and the update speed of the control code is usually low, which is easier to measure. In the case of long-term large amount of data statistics, the test precision is high and is not affected by circuit noise and jitter.

[0053] ​One embodiment of this application discloses a nonlinearity testing device for a high-speed serial interface chip, comprising: a data source connected to the chip under test (DUT), the data source being used to output a data signal, such as a high-speed signal, to the DUT; a first crystal oscillator for providing a first local oscillator clock to the data source; a second crystal oscillator for providing a second local oscillator clock to the DUT; a sampling module for sampling control codes generated by the DUT after the clock and data recovery circuit is locked; and a calculation module for calculating statistical values ​​of the control codes and calculating differential nonlinearity and integral nonlinearity based on the statistical values. The DUT is a high-speed serial interface chip and includes a clock and data recovery circuit, such as... Figure 2 The clock and data recovery circuit shown is illustrated. The first local oscillator clock and the second local oscillator clock have different frequencies.

[0054] Figure 5 This is a schematic diagram of a nonlinearity testing device in one embodiment of the present invention, including: a data source 10A, a chip under test (DUT) 20A, a logic analyzer 30A, and a computer 40A. The data source 10A can be the same high-speed serial interface chip, or it can be a bit error rate tester or other signal data source device. Crystal oscillators 1A and 2A represent the reference clocks of the data source 10A and the DUT 20A, respectively. The test requires different reference clocks for both, with a slight frequency deviation between them, typically less than 100 ppm. Data signals generated by the data source 10A are sent to the DUT 20A. The clock and data recovery circuit of the DUT 20A are locked to the frequency of the input data. After locking, due to the frequency deviation, the control digits will begin to cycle between maximum and minimum values. If the control digits are routed to the output pins of the DUT, the logic analyzer 30A can sample these outputs to directly obtain the control digits, which are then sent to the computer 40A. The differential nonlinearity INL and integral nonlinearity DNL are calculated using the formulas described above. In this embodiment, no additional auxiliary circuits are required on the chip, making the test environment simple to set up and cost-effective.

[0055] Since statistical control numbers do not actually need to sample all numbers, randomly sampling a certain number of control numbers can also meet the statistical requirements, as long as the sampling is completely random and the sampling period is not an integer multiple of the change in control numbers, the testing requirements can still be met.

[0056] In a typical chip under test, there is usually a serial interface for reading and writing registers, such as one or more of SPI, I2C, MDIO, GPIO, JTAG, UART, etc. These ports are simple and easy to configure. Figure 6is a schematic diagram of a non-linearity testing device in one embodiment of the present application, including a data source 10B, a chip under test 20B, and a computer 40B. The main difference between the embodiment of the present application and the prior art is that the sampling can be performed repeatedly through the register serial bus port to control the digital code and read it out, and then stored in the computer 40B for calculation, using the sampling method of the present application, almost no testing equipment is needed, and the testing cost is extremely low. Figure 5 Figure 6

[0057] In another embodiment of the present application, a method for testing the non-linearity of a high-speed serial interface chip is disclosed, Figure 7 is a flowchart of a method for testing the non-linearity of a high-speed serial interface chip. The method comprises the following steps:

[0058] Step 701, providing a first local oscillator clock to a data source and a second local oscillator clock to a chip under test, the frequencies of the first and second local oscillator clocks being different. Wherein the frequency deviation between the first and second local oscillator clocks is less than 100ppm

[0059] Step 702, the data source outputs a data signal to the chip under test, and the chip under test includes a clock and data recovery circuit.

[0060] Step 703, after the clock and data recovery circuit is locked, the control code generated by the chip under test is sampled, the statistical value of the control code is calculated, and the differential non-linearity and integral non-linearity are calculated according to the statistical value. Wherein the sampling is random sampling.

[0061] In one embodiment, the differential non-linearity is calculated according to the statistical value using the following formula

[0062] DNL i =-(B i+1 -B i ) / LSB

[0063] The integral non-linearity is calculated according to the statistical value using the following formula

[0064]

[0065] Wherein, LSB is the average value of the control code, N is the number of phase interpolators, and B i is the statistical value of the control code corresponding to the i-th step number.

[0066] ​​The first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can be applied to the first embodiment.

[0067] It should be noted that the relationship terms such as first and second, and the like, are used only to differentiate one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. In addition, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or apparatus including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus including the element. In the application file of the present patent, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, including two cases: the action is performed only according to the element, and the action is performed according to the element and other elements. The expressions of multiple, multiple times, multiple kinds, etc. include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0068] All the documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so as to be used as a modification if necessary. In addition, it should be understood that the above description is only the preferred embodiment of the present specification, and is not intended to limit the protection scope of the present specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of one or more embodiments of the present specification should be included in the protection scope of one or more embodiments of the present specification.

[0069] In some cases, the actions or steps recited in the claims can be performed in a different order than the order described in the embodiments and still achieve the desired results. In addition, the processes depicted in the figures do not necessarily require the particular order shown or sequential order to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or advantageous.

Claims

1. A method for testing the nonlinearity of a high-speed serial interface chip, characterized in that, include: A first local oscillator clock is provided to the data source, and a second local oscillator clock is provided to the chip under test. The frequencies of the first local oscillator clock and the second local oscillator clock are different. The data source outputs a data signal to the chip under test (DUT). The DUT includes a clock and data recovery circuit, which comprises a phase detector, a differentiating path, an integrating path, an integrator, an encoder, and a phase interpolator. The data signal is input to the phase detector, which passes in parallel through the differentiating path and the integrating path and is connected to the integrator. The integrator is connected to the encoder, and the encoder outputs control digital signals to the phase interpolator. The second local oscillator clock is input to the phase interpolator, which recovers the clock signal and outputs it to the phase detector. The frequency of the data signal received by the clock and data recovery circuit deviates from its own reference clock. After the clock and data recovery circuit is locked, the control code generated by the chip under test is sampled, the statistical value of the control code is calculated, and the differential nonlinearity and integral nonlinearity are calculated based on the statistical value.

2. The nonlinearity testing method for a high-speed serial interface chip according to claim 1, characterized in that, The difference nonlinearity is calculated using the following formula based on the statistical values. DNL i =-(B i+1 -B i ) / LSB The integral nonlinearity is calculated using the following formula based on the statistical values. in, LSB is the average value of the control digital code, N is the number of steps in the phase interpolator, and B... i This is the statistical value of the control code corresponding to the i-th step.

3. The nonlinearity testing method for a high-speed serial interface chip according to claim 1, characterized in that, The frequency deviation between the first local oscillator clock and the second local oscillator clock is less than 100ppm.

4. The nonlinearity testing method for a high-speed serial interface chip according to claim 1, characterized in that, The sampling is random sampling.

5. The nonlinearity testing method for a high-speed serial interface chip according to claim 1, characterized in that, The sampling is performed using a logic analyzer.

6. The nonlinearity testing method for a high-speed serial interface chip according to claim 1, characterized in that, The chip under test writes the control code into a register, and the sampling is achieved by reading the register through a computer.

7. The nonlinearity testing method for a high-speed serial interface chip according to claim 1, characterized in that, The chip under test has one or more of the following interfaces: SPI, I2C, MDIO, GPIO, JTAG, and UART register read / write interface.

8. The nonlinearity testing method for a high-speed serial interface chip according to claim 1, characterized in that, The data source is a high-speed serial interface chip or a bit error rate tester.

9. A nonlinearity testing device for a high-speed serial interface chip, characterized in that, include: A data source, connected to the chip under test (DUT), is used to output data signals to the DUT. The DUT includes a clock and data recovery circuit, which includes a phase detector, a differentiating path, an integrating path, an integrator, an encoder, and a phase interpolator. The data signal is input to the phase detector, which passes in parallel through the differentiating path and the integrating path and is connected to the integrator. The integrator is connected to the encoder, and the encoder outputs control digital signals to the phase interpolator. A second local oscillator clock is input to the phase interpolator, which recovers the clock signal and outputs it to the phase detector. The frequency of the data signal received by the clock and data recovery circuit is offset from its own reference clock. The first crystal oscillator is used to provide the first local oscillator clock to the data source; A second crystal oscillator is used to provide a second local oscillator clock to the chip under test, wherein the first local oscillator clock and the second local oscillator clock have different frequencies; The sampling module is used to sample the control digital data generated by the chip under test after the clock and data recovery circuit is locked. The calculation module is used to calculate the statistical value of the control code and calculate the differential nonlinearity and integral nonlinearity based on the statistical value.

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