measuring device

Abstract

A measurement device includes a first terminal to receive an input signal of a circuit under test; a second terminal to receive an output signal of the circuit under test. A first and a second phase splitter are configured to generate a first phase signal I1 and a second phase signal I2 and a first quadrature signal Q1 and a second quadrature signal Q2. A first and a second multiplexer are each coupled to the first and second terminals and configured to alternately pass the input and output signals of the circuit under test to inputs of the first and second phase splitters. A double quadrature mixer has four inputs configured to receive I1, Q1, I2, and Q2, and an output. A computing unit determines one or both of a phase shift of the circuit under test and / or a gain of the circuit under test based on the output of the double quadrature mixer.

Description

Technical Field

[0001] This disclosure relates to a measurement device. The measurement device can be used in the field of testing RF signal processing circuits. Specifically, this disclosure relates to a measurement device for determining the phase shift and / or gain introduced by the circuit under test. Background Technology

[0002] In RF signal processing, circuits can be configured to change the amplitude of a signal; such circuits are called "amplifiers." Furthermore, circuits can be configured to change the phase of a signal; such circuits are called "phase rotators," "phase shifters," or "delay circuits." These circuits can be formed into integrated circuits commonly known as radio frequency integrated circuits (RFICs).

[0003] Due to the variability in the manufacturing process of these circuits (e.g., in RFICs), manufacturing tolerances may exist for such amplifiers and phase rotators. Therefore, the exact gain and / or phase of these blocks cannot be known. Summary of the Invention

[0004] According to a first aspect of this disclosure, a measuring device is provided, comprising:

[0005] A first terminal is used to couple to the circuit under test to receive a first signal representing an input signal to the circuit under test;

[0006] The second terminal is used to couple to the circuit under test to receive a second signal representing the output from the circuit under test;

[0007] A first phase splitter is configured to generate a first phase signal I1 and a first quadrature signal Q1 based on a signal provided at the input of the first phase splitter, the first quadrature signal being orthogonal to the first phase signal;

[0008] A second phase splitter is configured to generate a second phase signal I2 and a second quadrature signal Q2 based on a signal provided at the input of the second phase splitter, the second quadrature signal being orthogonal to the second phase signal;

[0009] A first multiplexer, coupled to the first terminal and the second terminal, and configured to transmit the first signal to the input of the first phase splitter in a first mode of the first multiplexer, and to transmit the second signal to the input of the first phase splitter in a second mode of the first multiplexer;

[0010] A second multiplexer, coupled to the first terminal and the second terminal, and configured to transmit the second signal to the input of the second phase splitter in a first mode of the second multiplexer, and to transmit the first signal to the input of the second phase splitter in a second mode of the second multiplexer;

[0011] A biorthogonal mixer having four inputs configured to receive a first phase signal I1, a first quadrature signal Q1, a second phase signal I2, and a second quadrature signal Q2, and an output; and

[0012] A computing unit configured to receive the output of the bi-quadrature mixer, the output comprising a pair of signals, and the computing unit determining one or both of the following:

[0013] a) Determine the phase shift of the circuit under test based on the pair of signals at the output of the bi-quadrature mixer when the first multiplexer is in the first mode and the second multiplexer is in the first mode, and based on the pair of signals at the output of the first multiplexer in the second mode and the second multiplexer in the second mode.

[0014] b) Determine the gain of the circuit under test based on the output of the bi-orthogonal mixer when the first multiplexer is in the first mode and the second multiplexer is in the second mode, and the output of the bi-orthogonal mixer when the first multiplexer is in the second mode and the second multiplexer is in the first mode, wherein the gain includes the ratio of the amplitude B of the second signal to the amplitude A of the first signal.

[0015] In one or more examples, the pair of signals includes:

[0016] (i)I1.I2+Q1.Q2; and

[0017] (ii)I1.Q2-I2.Q1.

[0018] In one or more examples, the measuring device includes one or both of the following: an averaging element configured to average each of the pair of signals before each signal is received by the computing unit; and the computing unit configured to determine the average value of each of the pair of signals provided at the output of the quadrature mixer; and wherein the phase shift and / or the gain are determined based on the average value.

[0019] In one or more examples, the biorthogonal mixer is configured to output the pair of signals at different times and can be configured to output the pair of signals continuously.

[0020] In one or more embodiments, the measuring device is configured to determine the phase shift of the circuit under test, wherein the computing unit is configured to determine the following based on a pair of signals at the output of the measuring device when the first multiplexer is in the first mode and the second multiplexer is in the first mode:

[0021] The first average value M1 of I1.I2+Q1.Q2; and

[0022] The second average value M2 of I1.Q2-I2.Q1; and

[0023] The computing unit is configured to determine the following based on the pair of signals at the output of the measuring device when the first multiplexer is in the second mode and when the second multiplexer is in the second mode:

[0024] The third average value M3 of I1.I2+Q1.Q2;

[0025] The fourth average value M4 of I1.Q2-I2.Q1;

[0026] The phase shift of the circuit under test is given by the following formula:

[0027]

[0028] In one or more embodiments, the measuring device is configured to determine the phase shift of the circuit under test, and the computing unit is configured to determine the following:

[0029] A reference average value M0 is determined based on the output of the quadrature mixer, wherein the measuring device is configured such that one of the following occurs: the input to the quadrature mixer is disconnected from the first phase splitter and the second phase splitter, or the first signal and the second signal are set to zero; and

[0030] The phase shift of the circuit under test includes:

[0031]

[0032] It should be understood that the reference average value M0 is intended to determine the effect of the measuring device on the signal transmitted through it, particularly the effect of the bi-quadrature mixer. Therefore, this can be achieved by interrupting the first and second signals at any point before the bi-quadrature mixer.

[0033] In one or more embodiments, the computing unit is configured to determine the following average value to determine the gain of the circuit under test:

[0034] The fifth average value M5 of one of the pairs of signals provided at the output of the bi-orthogonal mixer includes I1.I2+Q1.Q2, wherein the first multiplexer is in the first mode and the second multiplexer is in the second mode;

[0035] The pair of signals provided at the output of the bi-quadrature mixer includes a sixth average value M6 of one of the signals I1.I2 + Q1.Q2, wherein the first multiplexer is in the second mode and the second multiplexer is in the first mode; and

[0036] The gain mentioned above includes:

[0037]

[0038] In one or more embodiments, the computing unit is configured to determine the gain of the circuit under test by determining an additional average value, the additional average value including:

[0039] A reference average value M0 is determined based on the output of the quadrature mixer, wherein the measuring device is configured such that one of the following occurs: the input to the quadrature mixer is disconnected from the first phase splitter and the second phase splitter, or the first signal and the second signal are set to zero; and

[0040] The gain mentioned above includes:

[0041]

[0042] In one or more embodiments, the computing unit is configured to determine the gain of the circuit under test by determining an additional average value, the additional average value including:

[0043] A reference average value M0 is determined based on the output of the quadrature mixer, wherein the measuring device is configured such that one of the following occurs: the input to the quadrature mixer is disconnected from the first phase splitter and the second phase splitter, or the first signal and the second signal are set to zero; and

[0044] The gain mentioned above includes:

[0045]

[0046] In one or more embodiments, the computing unit is configured to determine the following average value to determine the signal power of the first signal provided to the circuit under test:

[0047] The fifth average value M5 of one of the pairs of signals provided at the output of the bi-orthogonal mixer includes I1.I2+Q1.Q2, wherein the first multiplexer is in the first mode and the second multiplexer is in the second mode;

[0048] A reference average value M0 is determined based on the output of the quadrature mixer, wherein the device is configured such that one of the following occurs: the input to the quadrature mixer is disconnected from the first phase splitter and the second phase splitter, or the first signal and the second signal are set to zero; and

[0049] The signal power of the first signal includes:

[0050] =fc(M5-M0)

[0051] Where f C This includes a function based on predetermined calibration data that takes into account the signal power introduced by the measuring device.

[0052] In one or more embodiments, the computing unit is configured to determine the following average value to determine the signal power of the second signal provided to the circuit under test:

[0053] The sixth average value M6 of the outputs including I1.I2+Q1.Q2, wherein the first multiplexer is in the second mode and the second multiplexer is in the first mode; and

[0054] Referring to an average value M0, the device is configured such that one of the following occurs: the input to the bi-quadrature mixer is disconnected from the first phase splitter and the second phase splitter, or the first signal and the second signal are set to zero; and

[0055] The signal power of the first signal includes:

[0056] =fc(M6-M0)

[0057] Where f C This includes a function based on predetermined calibration data that takes into account the signal power introduced by the measuring device.

[0058] In one or more embodiments, the calibration data is determined based on signals with known signal power at both the first and second multiplexers, and wherein the calibration data is determined based on one or both of the following values:

[0059] The pair of signals provided at the output of the bi-orthogonal mixer includes the value M5 of one of the signals I1.I2+Q1.Q2, wherein the first multiplexer is in the first mode and the second multiplexer is in the second mode;

[0060] The pair of signals provided at the output of the bi-quadrature mixer includes the value M6 of one of the signals I1.I2+Q1.Q2, wherein the first multiplexer is in the second mode and the second multiplexer is in the first mode.

[0061] In one or more embodiments, an AC coupler is provided at one or more of the inputs of the first multiplexer, the second multiplexer, the first phase splitter, the second phase splitter, the output of the first phase splitter, and the output of the second phase splitter.

[0062] In one or more embodiments, the bi-quadrature mixer includes:

[0063] A first mixer, configured to receive I1 from the first phase splitter and the output of the first multiplexer;

[0064] A second mixer is configured to receive Q1 from the first phase splitter and the output of the second multiplexer;

[0065] The outputs of the first mixer and the second mixer are coupled to a summing element configured to determine the sum of the outputs of the first mixer and the second mixer and provide the sum to the output of the quadrature mixer; and

[0066] The first multiplexer is configured to select I2 in a first mode and Q2 in a second mode to provide to the first mixer; and

[0067] The second multiplexer is configured to select Q2 in a first mode and -I2 in a second mode to provide to the second mixer.

[0068] In one or more embodiments, the mixer of the biorthogonal mixer includes a Gilbert multiplier.

[0069] In one or more embodiments, the first phase splitter and / or the second phase splitter are based on a multiphase filter.

[0070] In one or more embodiments, one or both of the following:

[0071] To determine the phase shift of the circuit under test, the computing unit includes an analog-to-digital converter for converting the output of the bi-quadrature mixer into a digital signal for processing by the computing unit; and

[0072] To determine the gain of the circuit under test, the calculation unit includes a voltmeter for determining the voltage at the output of the quadrature mixer for processing by the calculation unit.

[0073] In one or more embodiments, the computing unit may include a switch that toggles between the ADC and the voltmeter.

[0074] In one or more embodiments, the first phase splitter and the second phase splitter are formed on the same integrated circuit.

[0075] In one or more embodiments, the measuring device includes a built-in self-test circuit for the circuit under test.

[0076] In one or more examples, one or both of the following:

[0077] The phase shift of the circuit under test is provided to the calibration unit, which is configured to calibrate the circuit under test based on the phase shift.

[0078] The gain of the circuit under test is provided to a calibration unit, which is configured to calibrate the circuit under test based on the phase shift.

[0079] According to a second aspect of this disclosure, an electronic device is provided, the electronic device including a measurement circuit according to any of the preceding claims, the electronic device including a 5G new radio transceiver, wherein the circuit under test includes a portion of either a transmission path or a reception path of the transceiver.

[0080] While this disclosure allows for various modifications and alternatives, their details have been illustrated by way of example in the drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described may also exist. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0081] The above discussion is not intended to present every exemplary embodiment or implementation within the scope of the present or future claims. The accompanying drawings and detailed description further illustrate various exemplary embodiments. A more comprehensive understanding of these exemplary embodiments can be achieved by considering the following detailed description in conjunction with the drawings. Attached Figure Description

[0082] One or more embodiments will now be described with reference to the accompanying drawings, by way of example only, in which:

[0083] Figure 1 An example circuit is shown, which may include a built-in self-test circuit for determining the phase change of the output of the circuit under test, which in this example includes a signal processing chain, relative to the input to the circuit under test.

[0084] Figure 2 An alternative example circuit is shown that utilizes only a single mixer component;

[0085] Figure 3 The example diagram shown illustrates the phase of a pair of quadrature signals output from a phase splitter relative to the frequency;

[0086] Figure 4 An example circuit is shown for determining the phase change of the output of a circuit under test (DUT) that includes a signal processing chain in this example, using two phase splitters, a single mixer assembly, and a multiplexer feeding the single mixer assembly.

[0087] Figure 5 An example circuit is shown for determining the phase change of the output of a circuit under test (DUT) that includes a signal processing chain in this example, using an arrangement of two phase splitters and a bi-quadrature mixer.

[0088] Figure 6 An example circuit for forming a bi-quadrature mixer arrangement is shown;

[0089] Figure 7 An example embodiment of a measuring device is shown, the measuring device having two multiplexers feeding two phase splitters, the multiplexers being coupled to a circuit under test including a signal processing chain, which in this example is the signal processing chain;

[0090] Figure 8 An example configuration of a bi-quadrature mixer embodied as a Gilbert multiplier is shown;

[0091] Figure 9 This illustrates the effect of the additional phase delay introduced by the mixer components in a quadrature mixer;

[0092] Figure 10 Another example embodiment of the measuring device is shown, along with an example controller for controlling the multiplexer of the measuring device;

[0093] Figure 11 Another example embodiment of the measuring device is shown; and

[0094] Figure 12 An electronic device including measurement circuitry is shown, wherein the electronic device may include a new 5G radio transceiver. Detailed Implementation

[0095] Measurement devices can be developed to measure the effect of a circuit under test (DUT) on a signal. Therefore, the DUT can receive an input signal and output an output signal. Due to the functionality of the DUT, the output signal may differ from the input signal in one or two amplitudes or phases by the gain or phase rotation applied by the DUT. In other examples, the DUT may be configured not to apply gain and / or phase rotation to the input signal, and defects in the manufacturing process can cause such gain and / or phase rotation to occur in practice. The measurement device can be implemented as a built-in self-test (BIST) on the same integrated circuit (IC) as the DUT. This "built-in self-test" (BIST) measurement device is helpful for testing the main circuit (i.e., the DUT) of an IC or RFIC where the input signals are alternating.

[0096] Measuring devices can also be used to modify the gain of the circuit under test (DUT) and / or the insertion phase of the DUT's input signal during the circuit's production or service life. Therefore, in one or more examples, the measuring device can be configured to provide a feedback signal that modifies one or both gains of the DUT, a phase shift implemented by the DUT (which may or may not be intentional), or provides a modification to the input signal to compensate for the phase shift and / or gain provided by the DUT to the input signal.

[0097] BIST measurement equipment can be affected by manufacturing tolerances, much like the manufacturing tolerances of amplifier and phase rotator components that BIST measurement equipment can be configured to test. As a result, measurements performed by the measurement equipment are not perfect and may contain some measurement errors. The entire BIST methodology relies on the fundamental assumption that the tolerances of these measurements are smaller than the original tolerances of the circuit under test. In one or more instances, it may be important to accurately determine the phase and gain measurements of the circuit under test by the BIST hardware and to do so in a manner that eliminates any influence from the manufacturing tolerances of the BIST hardware.

[0098] We will now describe a series of circuits that can be used as test circuits, such as BIST circuits, and then describe several embodiments of a measurement device that includes embodiments of the present disclosure.

[0099] Figure 1 A combination 100 of the circuit under test and a coupled test circuit (which may include a BIST circuit) is shown. The circuit under test includes a signal processing chain 101. This signal processing chain may include linear circuits commonly used in RFICs, such as amplifiers, phase rotators, filters, attenuators, couplers, etc.

[0100] The signals present at the corresponding input and output terminals of the signal processing chain will be referred to as the input signal at input terminal 102 and the output signal at output terminal 103, respectively. The input and output signals will be referred to as having amplitudes denoted by "A" and "B," respectively, and as described below by... This represents the relative phase difference.

[0101] The gain of the signal processing chain 101 can be measured by the ratio of the amplitudes of the output signal to the amplitude of the input signal, i.e., B / A. The phase difference between the input and output signals of the signal processing chain 101 can also be measured. The phase change introduced by the signal processing chain is measured. Therefore, the gain and phase introduced by the signal processing chain can be measured by observing the input signal at input terminal 102 and the output signal at output terminal 103.

[0102] Figure 1 The test circuit also includes a phase splitter 104 for obtaining two quadrature signal components from the output signal. These quadrature signals consist of a signal "I" represented by output 105 and a signal "Q" represented by output 106, and these two quadrature signals have phases relative to the input signal. and As is well known to those skilled in the art, such a phase splitter can have a multiphase filter built in.

[0103] also, Figure 1 The test circuit includes two mixers, 107 and 108. Each mixer is a circuit component that generates a mixer output signal at mixer output terminals 109 and 110, said signal being proportional to the product of the signals received at each of the two input terminals of the mixer. Regarding... Figure 1 :

[0104] - The mixer output signal at output 109 is the product of the input signal at 102 and one of the quadrature signals from the output 105 of the phase splitter.

[0105] - The mixer output signal 110 is the product of the input signal at 102 and one of the quadrature signals from the output 106 of the phase splitter.

[0106] The average value of the output signals of these two mixers can be calculated using the following formula:

[0107] - Mixer output terminal 109

[0108] - Mixer output terminal 110

[0109] Therefore, the phase can be derived from the measurement of the average value of the mixer output signal at mixer output terminals 109 and 110.

[0110]

[0111]

[0112] Considering The sign of the signal, i.e. the sign of the average signal value at the mixer output terminal 110, can convert the modulus-180° result generated by the arctangent function into the modulus-360° result.

[0113] The advantage of this measurement principle is that it does not depend on the amplitudes of the input and output signals, A and B, respectively. In fact, both the numerator and denominator of the ratio within the parentheses in Equation 2 are proportional to A and B. Therefore, A and B cancel each other out. Similarly, as long as the two gain factors are equal, the measurement result is independent of the gain factors of the two mixer components.

[0114] However, Figure 1 Test circuits may encounter various problems that affect the accuracy of their outputs by introducing measurement errors. These errors may be caused by one or more of the following reasons:

[0115] a) The gain of each mixer may be different.

[0116] (b) The phase splitter 104 may introduce an additional phase into the signal path. This phase can be difficult to control. This additional phase will be added to the measurement results.

[0117] c) Due to a circuit defect in the phase splitter 104, the two output signals 105 and 106 may have different amplitudes. This incomplete amplitude cancellation will lead to measurement errors.

[0118] d) Due to a circuit defect in phase splitter 104, the phase difference between the quadrature signals at terminals 105 and 106 may not be exactly 90°. This can also lead to measurement errors.

[0119] e) Mixers 107 and 108 may introduce additional phase in the signal paths from their two inputs to their outputs. When the additional phase in the signal path from one input to one output differs from the additional phase from the other input to the same output, this will affect the measurement results, resulting in measurement errors.

[0120] f) Figure 1 All circuits in the circuit will generate a DC offset voltage that causes measurement errors.

[0121] We will now describe modifications to the circuit under test 100 that, in one or more examples, address the aforementioned potential measurement problems. It should be noted that corresponding features in the following figures use equivalent reference numerals with different first numerals corresponding to the figures they refer to.

[0122] a) The gains of the two mixers may be different.

[0123] Figure 1 Each mixer 107 and 108 in the equation can have a different signal gain. For example, the gain of mixer 107 might be too large, exceeding the factor 1+δ, where δ represents the mixer gain imbalance. Ideally, δ equals zero. As a result, Equation 1 becomes:

[0124]

[0125] Therefore, when using Equation 2 to calculate When, it becomes:

[0126]

[0127] As can be seen from the above formula, the calculated measurement result may differ from the ideal result. Different. The measurement error is approximately equal to For example, for a gain error of 5% δ, the measurement error can reach 0.025 radians, which is equal to 1.5°.

[0128] This problem can be solved by Figure 2 The example test circuit 200 (bounded by the dashed box) is used to solve this problem. This setup contains only one mixer 207. Test circuit 200 also includes a signal multiplexer 211. This multiplexer can be configured in two configurations:

[0129] - In the first configuration, the first output 205 of the phase splitter 204 is connected to the input of the mixer 207, thereby providing the mixer 207 with the first of two quadrature signals.

[0130] - In the second configuration, the second output 206 of the phase splitter 204 is connected to the input of the mixer 207, thereby providing the mixer 207 with the second of two quadrature signals.

[0131] Two measurements were taken, one after the other, at two different times:

[0132] - At one moment, the first of the quadrature signals from output 205 is connected to mixer 207, and the average value of the product between the input signal from input 202 and the first of the quadrature signals from output 205 is measured. This measurement result is equivalent to... Figure 1 The average value of the signal output at 109 points.

[0133] - At another moment, the second of the quadrature signals from output 206 is connected to mixer 207, and the average value of the product between the input signal from input 202 and the second of the quadrature signals from output 206 is measured. This measurement result is equivalent to... Figure 1 The average value of the medium signal 110.

[0134] The average values ​​of the mixer output signals 109 and 110 may include the arithmetic mean.

[0135] Then, the phase can be calculated according to Equations 1 and 2. However, since both measurements were performed by the same mixer 207, the gain error δ in Equation 3 is zero.

[0136] b) Phase splitter 204 can introduce additional phase into the signal path.

[0137] In the example described herein, the output of phase splitter 204 from output terminal 205 will be referred to as signal I, and the output of phase splitter 204 from output terminal 206 will be referred to as signal Q. I and Q each have a phase relative to the phase of the input signal at input terminal 202. and However, when the phase splitter 204 is configured as a multiphase filter, the actual phase is as follows: Figure 3 As depicted in Figure 300, the phase difference between I and Q remains 90°, but each signal has an error phase. And 303. Therefore, the phases of I and Q are respectively and Error phase It is difficult to control and is frequency-dependent.

[0138] In these cases, see Figure 2 :

[0139] - When the multiplexer 211 is in the first configuration, the mixer output at the mixer output terminal 221 is...

[0140] - When the multiplexer 211 is in the second configuration, the mixer output at mixer output terminal 221

[0141] Therefore, when calculating the phase according to Equation 2 At that time, the result was Therefore, this error phase This can cause errors in the final calculation results.

[0142] Figure 4Another circuit under test 400 is shown. A second phase splitter 412 is introduced here. Therefore, in this example, the phase splitter coupled to input 402 will be referred to as the first phase splitter 412. The phase splitter coupled to output 403 will be referred to as the second phase splitter 404. Similar to... Figure 2 The phase splitter 204, the first phase splitter, and the second phase splitter can be configured to provide two quadrature signals. The pair of quadrature signals output by the first phase splitter 412 will be referred to as I1 and Q1, and will be output at terminals 413 and 414, respectively. The pair of quadrature signals output by the second phase splitter 404 will be referred to as I2 and Q2, and will be output at terminals 405 and 406, respectively. Therefore:

[0143] -The phase of signal I1 is

[0144] -The phase of signal I2 is

[0145] - The phase of signal Q2 is

[0146] In these cases, we can obtain two average signals, including:

[0147] - First average signal: When multiplexer selection I2 is passed to mixer 407, it is output at mixer output 421.

[0148] - Second average signal: When multiplexer selector Q2 passes to mixer 407, it is output at mixer output 421.

[0149] Then the phase can be The measurement is as follows:

[0150]

[0151] As long as the two phase splitters are substantially equal in terms of the phase changes they cause in quadrature signals, the result will be consistent with the error phase. Irrelevant.

[0152] c) Due to a circuit defect in the phase splitter 404, the two signals I2 and Q2 provided at output terminals 405 and 406 may... They can have different amplitudes.

[0153] consider Figure 4 In the test circuit 400, the amplitude of signal Q2 is too large, exceeding the factor 1+δ, where δ represents the amplitude imbalance between signals I2 and Q2. Ideally, δ should be zero. As a result, the phase is calculated using Equation 4. It becomes:

[0154]

[0155] Similarly, a non-zero amplitude imbalance δ can cause errors in the final calculation results. For example, for an amplitude imbalance δ of 5%, the measurement error can reach 0.025 radians, equivalent to 1.5°.

[0156] Figure 5 An additional test circuit 500 is depicted. This test circuit includes a "bi-quadrature mixer" 515, well known to those skilled in the art. This mixer component has four signal inputs. It allows for the performance of two measurements:

[0157] -M1 = Average value (I1.I2 + Q1.Q2)

[0158] -M2 = Average value (11.Q2 - I2.Q1)

[0159] Signals I1 provided at output 513, Q1 provided at output 514, I2 provided at output 505, and Q2 provided at output 506 are obtained from two phase splitters 504 and 512.

[0160] The phases of these four signals relative to the input signal at input terminal (502) are as follows:

[0161] The phase of -I1 is 45°.

[0162] The phase of -Q1 is -45°.

[0163] -

[0164] -

[0165] The phase can then be calculated as:

[0166]

[0167] Figure 6 An example embodiment of a "bi-quadrature mixer" 600 is depicted. This includes two mixers 616 and 617 and two multiplexers 618 and 619. Multiplexer 618 connects a signal I2 or Q2 to one input of the first mixer 616, while multiplexer 619 connects a signal Q2 or -I2 to one input of the second mixer 617.

[0168] The example bi-quadrature mixer circuit further includes a summing element 620 configured to provide an output signal 621, which is the sum of the output signals of the first mixer 616 and the second mixer 617. The summing element 620 may include a resistive load that sums the input currents of the preceding components, such as... Figure 8 The dashed box marked 620 is shown in the middle.

[0169] result, Figure 6 The circuit can be configured in two ways:

[0170] - In one configuration, the output of the summing element at position 621 = I2 * I1 + Q2.Q1

[0171] - In another configuration, the output of the summing element at position 621 is Q2*I1+(-I2).Q1.

[0172] It can be understood that these correspond to the measured values ​​M1 and M2 described above, respectively.

[0173] To study the effect of signal amplitude reduction, we reconsider the case where the Q2 amplitude is too large, increasing it by a factor of 1+δ. Equation 5 now becomes:

[0174]

[0175] As can be seen, signal Q2 appears in both the numerator and denominator of this expression. The amplitude reduction δ will not introduce errors into the calculation results.

[0176] Essentially similar calculations show that amplitude reduction of signals I1, I2, or Q1 does not introduce measurement error.

[0177] In summary, by using a bi-quadrature mixer, the final calculated result becomes insensitive to the amplitude reduction of the signals I1 provided at output 513, Q1 provided at output 514, I2 provided at output 505, and Q2 provided at output 506 by the first order.

[0178] d) Due to circuit defects in phase splitters 504 or 512, the phase difference between signals I2 and Q2, or between I1 and Q1, may... It might not be exactly 90 degrees.

[0179] consider Figure 5 The test circuit 500. Due to manufacturing tolerances, phase splitters 504 and 512 are not exactly the same. Therefore, the phase of one or more of the following signals may deviate from the expected value: signal I1 provided at output 513, signal Q1 provided at output 514, signal I2 provided at output 505, and signal Q2 provided at output 506. Consider, for example, the phase of signal Q2 to indicate a phase error. That is the situation. Ideally, The phases of the four signals I1, Q1, I2, and Q2 relative to the input signal (502) become zero.

[0180] The phase of -I1 is 45°.

[0181] The phase of -Q1 is -45°.

[0182] -

[0183] -

[0184] Phase calculation using Equation 5 Now it becomes:

[0185]

[0186] Therefore, phase error The error in the final calculation result is approximately equal to 50%. For example, when At a 5° angle, the resulting measurement error is approximately 2.5%°. Similar calculations reveal phase errors on signals I1, I2, or Q2. The error that causes the final calculation result is the original phase error. ±50%.

[0187] Figure 7 A measuring device 700, including an example embodiment of the present disclosure, is depicted. Figure 5 In contrast, two multiplexers 722 and 723 are provided. A first multiplexer 723 is provided, coupled to a first terminal 702 for receiving an input signal and coupled to a second terminal 703 for receiving an output signal. A second multiplexer 722 is provided, coupled to a second terminal 703 for receiving an output signal and coupled to a first terminal 702 for receiving an input signal. These multiplexers can be configured to operate in two different configurations:

[0188] - In one configuration, the output signal of the circuit under test is connected to the second phase splitter 704, while the input signal of the circuit under test is connected to the first phase splitter 712.

[0189] - In another configuration, the multiplexer is configured to pass another signal at its input, thereby routing the input signal of the circuit under test to the second phase splitter 704, while at 703 the output signal of the circuit under test is connected to the first phase splitter 712.

[0190] This means that, under ideal conditions, the phases of signal I1 provided at output 713, signal Q1 provided at output 714, signal I2 provided at output 705, and signal Q2 provided at output 706 are all ideal.

[0191] In the first configuration:

[0192] - The phase of I1 is 45° relative to the phase of the input signal.

[0193] - The phase of Q1 is -45° relative to the phase of the input signal.

[0194] - Phase relative to the input signal,

[0195] - Phase relative to the input signal,

[0196] In the second configuration:

[0197] - Phase relative to the input signal,

[0198] - Phase relative to the input signal,

[0199] - The phase of I2 is 45° relative to the phase of the input signal.

[0200] - The phase of Q2 is -45° relative to the phase of the input signal.

[0201] Now, four measurements can be performed: the first and second multiplexers for two measurements are in the aforementioned first configuration (M1 and M2), and the first and second multiplexers for two measurements are in the aforementioned second configuration (M3 and M4):

[0202] - In the first configuration, M1 = average value (I1.I2 + Q1.Q2)

[0203] - In the first configuration, M2 = average value (I1.Q2 - I2.Q1)

[0204] - In the second configuration, M3 = average value (I1.I2 + Q1.Q2)

[0205] - In the second configuration, M4 = average value (I1.Q2 - I2.Q1)

[0206] It should be noted that averaging can be performed while measuring using passive averaging elements, or alternatively, once the measurement has been performed, averaging can be achieved by a separate unit, such as a computation unit that performs the following calculations. Therefore, averaging can be performed in either the analog or digital domain.

[0207] The average value of the signal at 721 can include the arithmetic mean.

[0208] Therefore, the measurement device 700 may include one or both of an averaging element, such as an integrator or an ADC with a low cutoff frequency, and a computing unit coupled to the output 721 of a bi-quadrature mixer.

[0209] Therefore, in some examples, the calculation unit may be configured to sample the output of the quadrature mixer 715 a predetermined number of times or for a predetermined time period, and determine the arithmetic mean based on these samples. In other examples, the calculation unit may not actively take the average of the output of the quadrature mixer. In one or more examples, the output of the quadrature mixer may be received by an analog-to-digital converter (ADC) (e.g., relative to...). Figure 10 As described, the cutoff frequency of the ADC is inherently set to average the outputs of the bi-quadrature mixers 715 and 1015. In other examples, averaging elements based on filters or integrators at the outputs of the bi-quadrature mixers can be provided.

[0210] In summary Figure 7 In one or more embodiments, a measuring device 700 is provided for measuring one or both of the phase difference and amplitude ratio (i.e., gain) provided by the circuit under test 701 to the input signal input at the input terminal 702 relative to the output signal at the output terminal 703.

[0211] The measuring device 700 includes a first terminal 742, which in this example couples an input terminal 702 of a circuit under test 701 to the measuring device 700 to receive a first signal representing an input signal to the circuit under test. It should be understood that in this example, the input to the measuring device 700 at the first terminal is the same as the input to the circuit under test 701. However, in other examples, terminal 742 may be coupled to input terminal 702 via one or more other components.

[0212] The measuring device 700 further includes a second terminal 743, which in this example couples the output terminal 703 of the circuit under test 701 to the measuring device 700 to receive a second signal representing the output from the circuit under test. It should be understood that in this example, the input to the measuring device 700 at the second terminal is the same as the output from the circuit under test 701. However, in other examples, terminal 743 may be coupled to the output terminal 703 via one or more other components.

[0213] It should be understood that the circuit under test 701 can be any signal processing component or component chain, which may include linear circuits commonly used in RFICs, such as amplifiers, phase rotators, filters, attenuators and couplers.

[0214] The measuring device 700 further includes a first phase splitter 712, which is configured to generate a first phase signal I1 at output 713 and a first quadrature signal Q1 at output 714, wherein the first phase signal I1 is phase-shifted by +45° relative to the input to the phase splitter, and the first quadrature signal Q1 is phase-shifted by -45° relative to the input to the phase splitter. It will be readily understood that these two signals will be orthogonal to each other (i.e., there will be a 90° phase difference between them).

[0215] The second phase splitter 704 is configured to generate a second phase signal I2 at output 705 and a second quadrature signal Q2 at output 706, wherein the second phase signal I2 is phase-shifted by +45° relative to the input to the second phase splitter 712, and the second quadrature signal Q2 is phase-shifted by -45° relative to the input to the second phase splitter 712. It will be readily understood that these two signals will be orthogonal to each other (i.e., there will be a 90° phase difference between them).

[0216] It should be understood that the first phase splitter 704 and the second phase splitter 712 can be any type of distributor that provides two orthogonal signal components from the signal supplied to their inputs. In one or more other examples, phase splitters 704, 712 can be configured to provide one output with a 90° phase shift relative to the input signal and another output with no phase shift. However, as mentioned above, the two outputs of the phase splitter can also be shifted by ±45° relative to the signal supplied to the phase splitter at its input. In one or more examples, such a phase splitter can be based on a polyphase filter.

[0217] The first multiplexer 723 is coupled to a first terminal 702 and a second terminal 703 of the circuit under test and is configured to operate in two modes. In the first mode, the first multiplexer transmits a first signal (i.e., the input signal to the circuit under test) to the input of the first phase splitter 712, while in the second mode, the first multiplexer transmits a second signal (i.e., the output signal from the circuit under test) to the input of the first phase splitter.

[0218] The second multiplexer 722 is coupled to the first terminal 702 and the second terminal 703 of the circuit under test and is configured to operate in two modes. In the first mode, the second multiplexer transmits a second signal to the input of the second phase splitter 704, while in the second mode, the second multiplexer 722 transmits a first signal to the input of the second phase splitter.

[0219] In one or more instances, the first and second multiplexers can be controlled based on control signals to employ their respective first and second modes. In one or more instances, the control signals can be common, causing the first and second multiplexers to employ their respective first mode in one instance and their respective second mode in another instance. In other instances, the multiplexers can operate independently without needing to synchronize their mode-switching operations. The measuring device can be configured such that the first and second multiplexers can be operated such that they are both in their respective first mode, both in their respective second mode, or can be in different modes from each other, or can be configured not to pass either of their input signals to their respective phase splitters. In one or more instances, the computing unit can control the modes of the first and second multiplexers. In other instances, the multiplexers can, for example, automatically switch between their modes periodically so that calculations described later can be performed.

[0220] The measuring device 700 further includes a biorthogonal mixer 715, which is configured to receive a first phase signal I1, a first quadrature signal Q1, a second phase signal I2, and a second quadrature signal Q2 from a first multiplexer and a second multiplexer. The biorthogonal mixer also includes an output 721, providing a similar output to the example provided. Figure 5 The signal pair described.

[0221] The bi-quadrature mixer 721 can be configured to provide the following signal pairs:

[0222] (i)I1.I2+Q1.Q2; and

[0223] (ii)I1.Q2-I2.Q1.

[0224] It should be understood that when the first multiplexer 723 is in the first mode and the second multiplexer 722 is in the first mode, I1 and Q1 are quadrature signals based on the input signals to the circuit under test, and I2 and Q2 are quadrature signals based on the output signals from the circuit under test 701. Similarly, it should be understood that when the first multiplexer 723 is in the second mode and the second multiplexer 722 is in the second mode, I1 and Q1 are quadrature signals based on the output signals from the circuit under test, and I2 and Q2 are quadrature signals based on the input signals to the circuit under test 701.

[0225] A computing unit is provided to receive the output of a bi-quadrature mixer 721 (not shown in this example). The computing unit is configured to determine one or both of the following:

[0226] (a) The phase shift of the circuit under test based on two pairs of signals at the output of the quadrature mixer 721. Specifically, signal pairs M1 and M2 are determined when the first multiplexer 723 is in a first mode and the second multiplexer 722 is in a first mode (i.e., in a first configuration). Signal pairs M3 and M4 are determined when the first multiplexer is in a second mode and the second multiplexer is in a second mode (i.e., in a second configuration). The phase can be determined using the average of the measured values ​​M1 to M4. It should be understood that this averaging can be performed by the calculation unit itself, for example, in the digital domain, or by any passive averaging component, such as an integrator, placed between the output of the quadrature mixer and the calculation unit. In other examples, the calculation unit can sample the output of the quadrature mixer 715 over a time period, thereby inherently averaging. The phase can then be determined using the average of each of the measured values ​​M1 to M4 based on Equations 6 or 7 outlined above.

[0227] (b) The gain of the circuit under test, including the ratio of the amplitude B of the signal at the output 703 of the circuit under test to the amplitude A of the signal at the input 702 of the circuit under test. The gain is determined based on the measured values ​​M5 and M6. The measured value M5 is determined when the first multiplexer 723 is in the first mode and the second multiplexer 722 is in the second mode (i.e., in the third configuration), and the measured value M6 is determined when the first multiplexer 723 is in the second mode and the second multiplexer 722 is in the first mode (i.e., in the fourth configuration). The gain can be determined using the average of the measured values ​​M5 to M6. It should be understood that this averaging can be performed by the calculation unit 730 itself, for example, in the digital domain, or by any passive averaging component, such as an integrator, placed between the output of the quadrature mixer and the calculation unit. In other examples, the calculation unit can sample the output of the quadrature mixer 715 over a time period, thereby inherently averaging. The gain can be determined by averaging the measurements M5 and M6 based on Equations 8 through 10 outlined above.

[0228] The computing unit may include a microprocessor, computer, ASIC, FPGA, or another form of digital circuitry used to perform the required calculations.

[0229] The 715 bi-quadrature mixer can be characterized as Figure 6 The circuit includes two mixers, 616 and 617. In one or more examples, according to the example... Figure 8 Based on this principle, the mixer can be implemented as a Gilbert multiplier. Furthermore, the biorthogonal mixer 715 may also include a summing circuit 620 for summing the two output signals of mixers 616 and 617. The biorthogonal mixer 715 also includes two additional multiplexers 618 and 619. These additional multiplexers control the input signals to mixers 616 and 617 and can operate in two configurations:

[0230] In one configuration, signal I1 provided at output 713 and signal I2 provided at output 705 are connected to mixer 616. Furthermore, signal Q1 provided at output 714 and signal Q2 provided at output 706 are connected to multiplier 617 to generate measurement values ​​M1 or M3, depending on the configuration of the first multiplexer 722 and the second multiplexer 723 feeding the inputs of the first phase splitter 704 and the second phase distributor 712.

[0231] - In an alternative configuration, signal I1 provided at output 713 and signal Q2 provided at output 706 are connected to mixer 616. Furthermore, signal Q1 provided at output 1014 and signal I2 provided at output 705 are connected to mixer 617 to generate measurement values ​​M2 or M4 depending on the configuration of the first multiplexer and the second multiplexer that feed the inputs to the first phase splitter 704 and the second phase distributor 712.

[0232] Therefore, in one or more examples, in order to determine the phase shift of the circuit under test, the computing unit is configured to determine the following based on a pair of signals at output 721 when the first multiplexer is in the first mode and the second multiplexer is in the first mode:

[0233] The first average value (M1) of I1.I2+Q1.Q2; and

[0234] The second average value (M2) of I1.Q2-I2.Q1; and

[0235] The computing unit is configured to determine the following based on a pair of signals at output 721 when the first multiplexer is in the second mode and when the second multiplexer is in the second mode:

[0236] The third average value (M3) of I1.I2+Q1.Q2;

[0237] The fourth average value (M4) of I1.Q2-I2.Q1.

[0238] The phase can then be measured using the following calculations.

[0239]

[0240] However, now we need to reconsider that the signal Q2 at output 706 has a phase error. This means:

[0241] In the first configuration:

[0242] - The phase of I1 is 45° relative to the phase of the input signal.

[0243] - The phase of Q1 is -45° relative to the phase of the input signal.

[0244] - Phase relative to the input signal,

[0245] - Phase relative to the input signal,

[0246] In the second configuration:

[0247] - Phase relative to the input signal,

[0248] - Phase relative to the input signal,

[0249] - The phase of I2 is 45° relative to the phase of the input signal.

[0250] - Phase relative to the input signal,

[0251] Phase is measured according to Equation 6. Therefore, we can conclude that:

[0252]

[0253] Since signal exchange occurs through the operation of the first multiplexer 722 and the second multiplexer 723, the measurement error caused by the phase error on Q2 is canceled out. In the first order, the calculation result calculated by Equation 6 is unaffected by... Impact. Similar calculations show that phase errors on signals I1, I2, or Q1 are also canceled out in first order.

[0254] e) It is possible that the mixer may introduce different phases in the signal path from its input to its output.

[0255] like Figure 1 The mixer 107 or 108 shown, or as... Figure 2 The mixer 207 shown, or as Figure 6 The mixers shown, such as mixers 616 or 617 (i.e., part of biquadrature mixer 715), can be constructed according to a principle known in the art as a "Gilbert multiplier." Such a Gilbert multiplier 800, as... Figure 8 As shown.

[0256] Typically, the signal path from one mixer input 824 to the mixer output 826 is fundamentally different from the signal path from the other mixer input 825 to the output 826. Therefore, the mixer introduces unequal phase in these two signal paths. This phase difference can be difficult to control during manufacturing. Phase errors may be added to the final calculation results.

[0257] The effect of this phase difference can be used Figure 9 The equivalent circuit is analyzed. This diagram is related to... Figure 6 Similarly, and for the sake of understanding, the phase error is shown as a phase change component, to add two additional phase errors, namely the phase error introduced by block 927. and the phase error introduced by block 928 As will be understood, these phase errors are introduced in practice by mixers 916 and 917 in one of their signal paths, respectively.

[0258] Still using Figure 7 700 measuring device for phase measurement The bi-quadrature mixer 715 is exemplified by... Figure 9 The circuit 900. The phase is still calculated using Equation 6. However, the error phase needs to be considered. and Make:

[0259]

[0260]

[0261]

[0262]

[0263] Then, equation 6 yields:

[0264]

[0265] In summary, without signal switching provided by multiplexers 722 and 723, the non-zero phase imbalance... and / or This may result in an error in the final calculation result of approximately equal to 50%.

[0266] Due to the swapping of the input signals of multiplexers 722 and 723, the phase error... 927 and The value of 928 ensures that the final calculation result is error-free.

[0267] Therefore, phase calculations use four measurements: M1, M2, M3, and M4. It should be understood that measurements M1, M2, M3, and M4 can be performed consecutively, one after another. Alternatively, M1, M2, M3, and M4 can be determined at time intervals.

[0268] In other embodiments of this disclosure, the presence of a DC offset voltage may be considered.

[0269] f) Figure 7 The circuitry in the embodiments may generate a DC offset voltage that can lead to measurement errors.

[0270] In one or more examples, due to inaccurate components, Figure 7 The DC voltage at all circuit nodes in the circuit may be affected by manufacturing tolerances. These may affect the results of the four measurements M1 to M4 described above. Therefore, they may affect the results calculated by equation (6).

[0271] When the signals at input terminal 702 and output terminal 703 of the circuit under test are AC signals, meaning the signal information is not represented as a DC component, AC coupling can be applied to all signal paths from input terminal 702 and output terminal 703 of the circuit under test to the inputs I1, Q1, I2, and Q2 of the quadrature mixer 715. In this way, the DC offset voltage generated in these signal paths is canceled out.

[0272] Therefore, in one or more examples, an AC coupler is provided at one or more of the inputs of the first multiplexer, the second multiplexer, the first phase splitter, the second phase splitter, the output of the first phase splitter, and the output of the second phase splitter to pass only the AC signal to subsequent components.

[0273] However, mixers 916 and 917 of the quadrature mixer 715 themselves perform frequency conversion. Therefore, useful information from each of the four measurements M1 to M4 can be included in the average of the output signal at the output of the quadrature mixer 921, and thus in the DC component. AC coupling cannot be placed in the signal path at the outputs 621 or 921 of the quadrature mixers 715 or 900. Any offset voltage generated by mixers 916 or 917 or by the summing circuit 920 is added to the measurements M1 to M4, and may therefore affect the results calculated by Equation 6.

[0274] To compensate for the DC offset voltage, a fifth measurement, referred to herein as the reference average and designated by the symbol "M0," can be performed, thereby setting the amplitudes of the input signal at input 702 and the output signal at output 703 of the circuit under test to zero. Alternatively, the fifth measurement can be performed using multiplexers 722 and 723, configured such that none of the signals at input 702 and output 703 of the circuit under test are routed to the output of multiplexers 722 or 723. This can be considered a fifth configuration of the measuring device or multiplexers 722 and 723. Measurements M1 through M4 can then be corrected using this reference average measurement M0.

[0275] Therefore, the measuring device 700 can be configured to determine a reference average value (M0) based on the output of the bi-quadrature mixer 715, wherein the measuring device is configured such that one of the following is true: the input to the bi-quadrature mixer is disconnected from the first phase splitter and the second phase splitter, or the first signal and the second signal are set to zero.

[0276] This means that equation 6 becomes:

[0277]

[0278] As described above, the measuring device 700 is alternatively or additionally configured to measure the gain of the circuit under test. Calculation unit ( Figure 7 (Not shown in the image) can be configured as follows.

[0279] In the third configuration, the first multiplexer 722 and the second multiplexer 723 are configured such that the first signal (in this example, the input signal at input 702 of the circuit under test 701) is passed to the phase splitter by the first multiplexer 722 and the second multiplexer 723. The quadrature mixer 715 provides one of a pair of signals at its output 721, the signals comprising I1.I2 + Q1.Q2. Their average value can be determined in any of the ways described above. Therefore, in this third configuration, measurement “M5” can be performed, where:

[0280] M5 = Average value in the third configuration (I1.I2 + Q1.Q2)

[0281] =A.Acos((45°)-(45°))+A.Acos((-45°)-(-45°))=2.AA

[0282] In the fourth configuration, the first multiplexer 722 and the second multiplexer 723 are configured such that the second signal (in this example, the output signal at output 703 of the circuit under test 701) is passed to the phase splitter by the first and second multiplexers. The quadrature mixer 715 provides one of a pair of signals at its output 721, the signal comprising I1.I2 + Q1*Q2. Their average value can be determined in any of the ways described above. Therefore, in this fourth configuration, measurement “M6” can be performed:

[0283]

[0284] Therefore, in summary, the measuring device 700 is configured to determine a fifth average value (M5), the fifth average value including a signal comprising I1.I2+Q1.Q2 in one of the pair of signals provided at the output of the quadrature mixer, wherein the first multiplexer is in a first mode and the second multiplexer is in a second mode; and the measuring device 700 is configured to determine a sixth average value (M6), the sixth average value including a signal comprising I1.I2+Q1.Q2 in one of the pair of signals provided at the output of the quadrature mixer, wherein the first multiplexer is in a second mode and the second multiplexer is in a first mode.

[0285] Then, the signal gain equal to the ratio B / A can be calculated as:

[0286]

[0287] It should be understood that in one or more examples where only the gain is determined (i.e., the phase shift is uncertain), given a pair of signals output by the bi-quadrature mixer 715, only one signal is needed to determine the gain. In this case, the bi-quadrature mixer 715 can be embodied as a first mixer for determining I1.I2 and a second mixer for determining Q1.Q2, and a summing element for determining I1.I2 + Q1.Q2 based on the outputs of the first and second mixers.

[0288] As mentioned above, Figure 7 The circuitry in the embodiments may generate a DC offset voltage that could lead to measurement errors. Therefore, M0 can be used to remove any DC offset value, and this is determined by placing multiplexers 722 and 723 in the fifth configuration as previously outlined. Therefore, in one or more examples, the gain is determined using the following calculation to compensate for the DC offset voltage:

[0289]

[0290] therefore, Figure 7 The circuit allows for the measurement of the signal gain of the circuit under test 701.

[0291] In an alternative embodiment, the gain can also be calculated as:

[0292]

[0293] In one or more examples, calculations using Equation 10 can be performed efficiently. In fact, based on the definitions of M0, M1, M2, and M6 described above, this can be verified to correspond to:

[0294]

[0295] Now, the ratio between M1 and M6 or between M2 and M6 only changes with the ratio Instead Increasing this number might make it easier to determine.

[0296] The measuring device 700 can also be configured to estimate the signal power of the signals at the input terminal 702 and the output terminal 703 of the circuit under test.

[0297] As described above, M5-M0 is calculated to be proportional to AA, that is, proportional to the signal power of the signal at input 702 of the circuit under test 701. The absolute value of M5-M0 also depends on the gain of the measuring device 700 between input 702 and the output of the quadrature mixer 721. This means it depends on the mixer conversion gain, the insertion gain of multiplexers 722 and 723, and the gain of phase splitters 704 and 712. Furthermore, the phase errors in phase splitters 704 and 712 affect the measurement result M5-M0. If necessary, all these errors can be compensated for by performing a one-time calibration. During such calibration, a known signal is applied to input 702 of the circuit under test 701, and a measurement result corresponding to the measured value M5 is obtained and stored as a calibration function (fc). This calibration function information can be used later to compensate for these errors when the result M5-M0 is used to estimate the signal power at input 702. The calibration function can include values ​​added to or subtracted from, for example, the result M5-M0+fc. In other examples, the calibration function includes a function of the result, namely fc(M5-M0).

[0298] Similarly, the signal power at the output terminal 703 of the circuit under test 701 can be estimated using the measurement results M6-M0. Here, the calibration of the gain of the measurement chain used to determine the output terminal 703 of the circuit under test 701 and the output terminal of the quadrature mixer 721 can also be determined, which allows compensation for all gain or phase errors in the measurement device 700.

[0299] In summary, the measurement device 700 can be configured in various ways to determine the phase shift and / or gain, wherein the first multiplexer 723 and the second multiplexer 722 can be configured in different combinations of modes. Table 1 summarizes the various configurations described above for generating one or more of the phase shift, gain, input signal power, and output signal power.

[0300] Configuration First multiplexer Second multiplexer Measured values 1 First Mode First Mode M1, M2 2 Second Mode Second Mode M3, M4 3 First Mode Second Mode M5 4 Second Mode First Mode M6 5 No throughput No throughput MO (Reference Average) 6 Given (a) Given (a) Fc (input branch) 7 Given (b) Given (b) Fc (output branch)

[0301] Table 1

[0302] Example Figure 10 An embodiment of the measuring device 1000 is shown. The measuring device 1000 and... Figure 7 The measuring equipment is basically the same as that of the 700. However, in Figure 10In this example, the calculation unit 1030 is shown in conjunction with the analog-to-digital converter 1029 that converts the signal pairs output from the bi-quadrature mixer 1021 into digital format. Therefore, in this example, the calculation unit can be configured to determine the average values ​​of M1 to M6 and M0 as needed. As described above, the calculation unit 1030 is configured to perform calculations according to equations 7, 9, and / or 10. Figure 10 The embodiment further includes a control unit 1031. The control unit 1031 controls the first multiplexer 1022, the second multiplexer 1023, and those multiplexers of the bi-quadrature mixers 618, 619. The control unit can be configured to control the multiplexers to allow the required measurements (from M0 to M6) to be performed sequentially or at spaced intervals. The control unit can also be configured to control the calculation unit 1030 to perform all calculations at the correct time based on the current signal output from the bi-quadrature mixer 1015.

[0303] In one or more examples, the computation unit 1030 may not perform averaging. Averaging can be achieved by using an ADC 1029 with a low cutoff frequency. Therefore, a single sample of the output of such an ADC 1029 can provide an average value.

[0304] As a practical example, the operating frequency of the circuit under test 1001 can be in the 5 GHz band, including frequencies around the 28 GHz band. In this example, the cutoff frequency of the ADC can be set to 1 MHz. It should be understood that the ADC cutoff frequency can be lower than the operating frequency of the circuit under test to provide an average value. In the example above, the ADC cutoff frequency is approximately four orders of magnitude lower than the operating frequency of the circuit under test operating in the 5 GHz band. In other examples, the ADC cutoff frequency can be one-tenth, one-hundredth, or one-thousandth of the operating frequency of the circuit under test. However, as long as the ADC cutoff frequency is lower than the frequency of the circuit under test, a single sample taken by the ADC will experience multiple cycles of the circuit under test, thus inherently outputting an average value.

[0305] Figure 11 Another example embodiment is shown below. Here, the bi-quadrature mixer output signal 1121 is received by voltmeter 1132. Calculation unit 1130 can be configured to determine phase shift and / or gain as described above.

[0306] In other examples, computing units 1030, 1130 may be configured to provide average values ​​for determining phase shift and / or gain by different entities.

[0307] Therefore, in order to summarize Figure 10 and 11The measuring devices 700, 1000, and 1100 may include a calculation unit for determining the phase shift of the circuit under test. The calculation unit includes an analog-to-digital converter 1029 for converting the output of the bi-quadrature mixer into a digital signal for processing by the calculation unit.

[0308] In addition, the measuring devices 700, 1000, and 1100 may include a calculation unit for determining the gain of the circuit under test, the calculation unit including a voltmeter 1132 for determining the voltage at the output of the bi-quadrature mixer for processing by the calculation unit 1130.

[0309] exist Figure 11 In such cases, a separate averaging component as discussed above may exist, or alternatively, the calculation unit 1130 may be configured to determine the average value based on the output of the voltmeter.

[0310] In one or more embodiments, the measuring devices 700, 1000, and 1100 can... Figure 10 and 11 The example can be switched between. Therefore, the computing unit 1030 may include a switch for switching between ADC 1029 and voltmeter 1132, both of which are coupled to the output of bi-quadrature mixers 715, 1015, 1115.

[0311] In one or more examples, the measuring devices 700, 1000, and 1100 may be formed on the same integrated circuit as the circuit under test. In one or more embodiments, at least the first and second phase splitters 704, 1004, 1104, 712, 1012, and 1112 are formed on the same integrated circuit.

[0312] In one or more embodiments, the measuring device includes a built-in self-test circuit. Figure 12 The arrangement 1200 is shown, in which measuring devices 700, 1000, and 1100 and circuits under test 701, 1001, and 1101 are located on the same integrated circuit. Measuring devices 700, 1000, and 1100 can be considered as BIST circuits.

[0313] In one or more examples, the phase shift of the circuit under test (DUT), determined by a measuring device, is provided to a calibration unit 1201, which can be configured to calibrate the DUT based on the phase shift. Therefore, when a desired phase shift is required from the DUT, the measuring device can be configured to measure the phase shift and provide feedback to the calibration unit, which can be configured to adjust the DUT to achieve the desired phase shift.

[0314] In one or more examples, the gain of the circuit under test (DUT), determined by a measuring device, is provided to a calibration unit 1201, which is configured to calibrate the DUT based on the gain. Therefore, when a desired gain is required from the DUT, the measuring device can be configured to measure the gain and provide feedback to the calibration unit, which can be configured to adjust the DUT to achieve the desired gain.

[0315] Arrangement 1200 may include electronic devices including a 5G new radio transceiver, wherein the circuit under test 701, 1001, 1101 includes a portion of one of the transmission path or reception path of the transceiver, and the measuring devices 700, 1000, 1100 are configured to determine one or both of the phase shift and gain of the transmission / reception path.

[0316] In one or more examples, the measuring device is configured to track circuit aging, thereby allowing the measurement of the gain and / or phase shift of the circuit under test during its lifetime to determine the effects associated with circuit aging.

[0317] In one or more examples, the measuring device is configured to measure the gain and / or phase of the circuit under test (DUT) and can be used as a self-test. In one or more examples, the DUT can be considered defective when the phase shift and / or gain measurements fall outside a predetermined range. This provides the possibility of low-cost production testing or the possibility of automatically generating warnings during operation.

[0318] Implementing extensive self-calibration and self-testing of RFICs can significantly reduce costs, especially for low-cost components such as RFICs in wireless communication systems.

[0319] Unless a specific order is explicitly specified, the instructions and / or flowchart steps in the above diagram can be executed in any order. Furthermore, those skilled in the art will recognize that while an example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to produce other examples, and should be understood within the context provided in this detailed description.

[0320] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0321] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any single or multiple manufactured components. One or more non-transitory machine- or computer-usable media as defined herein exclude signals, but such media are capable of receiving and processing information from signals and / or other transient media.

[0322] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via networks, computers, or data-based devices and / or services. These may include cloud, Internet, intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0323] In one example, one or more instructions or steps discussed in this article are automated. The terms automated or automatic (and similar variations) mean using computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0324] It should be understood that any components that are to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, another component may be placed between the two components that are said to be coupled.

[0325] In this specification, exemplary embodiments have been presented according to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of details, can be practiced. The appended claims are intended to cover all possible exemplary embodiments.

Claims

1. A measuring device, characterized in that comprises: a first end for coupling to a circuit under test to receive a first signal representative of an input to the circuit under test; a second end for coupling to the circuit under test to receive a second signal representative of an output from the circuit under test; a first phase splitter configured to generate a first phase signal I1 and a first quadrature signal Q1 based on a signal provided at an input of the first phase splitter, the first quadrature signal being orthogonal to the first phase signal; a second phase splitter configured to generate a second phase signal I2 and a second quadrature signal Q2 based on a signal provided at an input of the second phase splitter, the second quadrature signal being orthogonal to the second phase signal; a first multiplexer coupled to the first end and the second end and configured to pass the first signal to the input of the first phase splitter in a first mode of the first multiplexer and to pass the second signal to the input of the first phase splitter in a second mode of the first multiplexer; a second multiplexer coupled to the first end and the second end and configured to pass the second signal to the input of the second phase splitter in a first mode of the second multiplexer and to pass the first signal to the input of the second phase splitter in a second mode of the second multiplexer; a double quadrature mixer having four inputs configured to receive the first phase signal I1, the first quadrature signal Q1, the second phase signal I2 and the second quadrature signal Q2, and an output; and a computing unit configured to receive the output of the double quadrature mixer, the output comprising a pair of signals, and to determine one or both of: a) a phase shift of the circuit under test based on the pair of signals at the output of the double quadrature mixer when the first multiplexer is in the first mode and the second multiplexer is in the first mode, and based on the pair of signals at the output when the first multiplexer is in the second mode and the second multiplexer is in the second mode; b) a gain of the circuit under test comprising a ratio of an amplitude B of the second signal to an amplitude A of the first signal based on the output of the double quadrature mixer when the first multiplexer is in the first mode and the second multiplexer is in the second mode and the output of the double quadrature mixer when the first multiplexer is in the second mode and the second multiplexer is in the first mode, wherein, to determine the phase shift of the circuit under test, the computing unit is configured to determine, based on the pair of signals at the output when the first multiplexer is in the first mode and the second multiplexer is in the first mode: a first average M1 of I1.I2 + Q1.Q2; and a second average M2 of I1.Q2 - I2.Q1; and The computing unit is configured to determine, based on the pair of signals at the output when the first multiplexer is in the second mode and the second multiplexer is in the second mode: a third average M3 of I1.I2 + Q1.Q2; a fourth average M4 of I1.Q2 - I2.Q1; wherein the phase shift of the circuit under test is given by: wherein the computing unit is configured to determine the following averages to determine the gain of the circuit under test: a fifth average M5 of one of the pair of signals provided at the output of the double quadrature mixer comprising I1.I2 + Q1.Q2, wherein the first multiplexer is in the first mode and the second multiplexer is in the second mode; a sixth average M6 of one of the pair of signals provided at the output of the double quadrature mixer comprising I1.I2 + Q1.Q2, wherein the first multiplexer is in the second mode and the second multiplexer is in the first mode; and wherein the gain comprises:

2. The measuring device of claim 1, wherein, To determine the phase shift of the circuit under test, the computing unit is configured to determine: a reference average M0 based on the output of the double quadrature mixer, wherein the measurement device is configured such that one of the following is true: the input to the double quadrature mixer is disconnected from the first and second phase splitters, or the first and second signals are set to zero; and wherein the phase shift of the circuit under test comprises:

3. The measuring device of claim 1, wherein, The computing unit is configured to determine the gain of the circuit under test by determining further averages, the further averages comprising: a reference average M0 based on the output of the double quadrature mixer, wherein the measurement device is configured such that one of the following is true: the input to the double quadrature mixer is disconnected from the first and second phase splitters, or the first and second signals are set to zero; and wherein the gain comprises:

4. The measuring device of claim 1, wherein, The computing unit is configured to determine the gain of the circuit under test by determining further averages, the further averages comprising: a reference average M0 based on the output of the double quadrature mixer, wherein the measurement device is configured such that one of the following is true: the input to the double quadrature mixer is disconnected from the first and second phase splitters, or the first and second signals are set to zero; and wherein the gain comprises:

5. The measuring device of claim 1, wherein, The computing unit is configured to determine the following average to determine a signal power of the first signal provided to the circuit under test: a fifth average M5 of one of the pair of signals provided at the output of the double quadrature mixer comprising I1.I2 + Q1.Q2, wherein the first multiplexer is in the first mode and the second multiplexer is in the second mode; a sixth average M6 of one of the pair of signals provided at the output of the double quadrature mixer comprising I1.I2 + Q1.Q2, wherein the first multiplexer is in the second mode and the second multiplexer is in the first mode; and wherein the gain comprises: determining a reference average value M0 based on the output of the double quadrature mixer, wherein the measurement device is configured such that one of the following: the input to the double quadrature mixer is disconnected from the first and second phase dividers, or the first and second signals are set to zero; and wherein the signal power of the first signal comprises: = fc(M5 - M0) wherein f C comprises a function based on predetermined calibration data taking into account the signal power introduced by the measuring device.

6. The measuring device of claim 1, wherein, the calculation unit is configured to determine the following averages to determine the signal power of the second signal provided to the circuit under test: a sixth average value M6 of the output comprising I1.I2 + Q1.Q2, wherein the first multiplexer is in the second mode and the second multiplexer is in the first mode; and a reference average value M0, wherein the measurement device is configured such that one of the following: the input to the double quadrature mixer is disconnected from the first and second phase dividers, or the first and second signals are set to zero; and wherein the signal power of the first signal comprises: = fc(M6 - M0) wherein f C comprises a function based on predetermined calibration data taking into account the signal power introduced by the measuring device.

7. The measuring device according to claim 5 or claim 6, characterized in that, The calibration data is determined based on the measurement device being equipped with signals of known signal power at both the first and second multiplexers, and wherein the calibration data is determined based on one or both of the following values: a value M5 of one of the pair of signals provided at the output of the double quadrature mixer comprising I1.I2 + Q1.Q2, wherein the first multiplexer is in the first mode and the second multiplexer is in the second mode; a value M6 of one of the pair of signals provided at the output of the double quadrature mixer comprising I1.I2 + Q1.Q2, wherein the first multiplexer is in the second mode and the second multiplexer is in the first mode.

8. An electronic device, comprising: The measurement device according to any one of the preceding claims, the electronic device comprising a 5G New Radio transceiver, wherein the circuit under test comprises a part of one of a transmit path or a receive path of the transceiver.

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