Display panel, manufacturing method thereof and display device

Abstract

A display panel, a manufacturing method thereof and a display device. The display panel comprises a plurality of sub-pixel regions, and a reset signal line pattern (905), an initialization signal line pattern (904) and a conductive connection part pattern (909) in each sub-pixel region; the initialization signal line pattern (904) comprises a first main body part (9041) and a first protruding part (9042) coupled with each other, the orthographic projection of the first main body part (9041) on a substrate is located between the orthographic projection of the first protruding part (9042) on the substrate and the orthographic projection of the reset signal line pattern (905) on the substrate; the orthographic projection of a first end part (9091) of the conductive connection part pattern (909) on the substrate has a first overlapping area (F1) with the orthographic projection of the first protruding part (9042) on the substrate, in the first overlapping area (F1), the first end part (9091) is coupled with the first protruding part (9042); a second end part (9092) of the conductive connection part pattern (909) is coupled with a target coupling part; the orthographic projection of the reset signal line pattern (905) on the substrate is located between the orthographic projection of the target coupling part on the substrate and the orthographic projection of the initialization signal line pattern (904) on the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] With the rapid development of Organic Light-Emitting Diode (OLED) display technology, consumers have increasingly higher demands for the screen-to-body ratio and resolution of OLED display devices. The screen-to-body ratio of an OLED display device refers to the proportion of the active display area (AA area) on the front panel of the device, while the resolution of an OLED display device refers to the number of pixels included in the AA area. A larger screen-to-body ratio results in a better user experience. Higher resolution OLED displays produce clearer images. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display panel, a method for manufacturing the same, and a display device.

[0004] The first aspect of this disclosure provides a display panel, comprising: a substrate, a functional film layer disposed on the substrate; and a plurality of sub-pixel regions arranged in an array;

[0005] The functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;

[0006] The reset signal line layer includes: a reset signal line pattern disposed in each of the sub-pixel regions, the reset signal line pattern extending along a first direction;

[0007] The initialization signal line layer includes: an initialization signal line pattern disposed in each of the sub-pixel regions. The initialization signal line pattern includes a first main body portion and a first protruding portion coupled together. The first main body portion extends along the first direction. In the same sub-pixel region, the orthographic projection of the first main body portion on the substrate is located between the orthographic projection of the first protruding portion on the substrate and the orthographic projection of the reset signal line pattern on the substrate.

[0008] The conductive connection layer includes: conductive connection patterns disposed in each of the sub-pixel areas; in the same sub-pixel area, the orthographic projection of the first end of the conductive connection pattern on the substrate has a first overlapping area with the orthographic projection of the first protruding portion on the substrate; in the first overlapping area, the first end is coupled to the first protruding portion; the second end of the conductive connection pattern is coupled to a target coupling portion in its sub-pixel area; and the orthographic projection of the reset signal line pattern on the substrate is located between the orthographic projection of the target coupling portion on the substrate and the orthographic projection of the initialization signal line pattern on the substrate.

[0009] Optionally, the display panel further includes:

[0010] A plurality of light-emitting elements corresponding one-to-one with the plurality of sub-pixel regions, wherein the plurality of light-emitting elements are located on the side of the functional film layer facing away from the substrate;

[0011] A plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel regions, each of the sub-pixel driving circuits including a seventh transistor, the gate of the seventh transistor being coupled to the corresponding reset signal line pattern, the first electrode of the seventh transistor serving as the target coupling portion, and the second electrode of the seventh transistor extending along the second direction and being coupled to the anode of the corresponding light-emitting element;

[0012] The conductive connection pattern further includes a second main body portion connected between the first end and the second end, the second main body portion extending along a second direction; in the same sub-pixel region, along the first direction, the first end of the conductive connection pattern protrudes from the second main body portion in a direction away from the second pole of the seventh transistor.

[0013] Optionally, the functional film layer further includes a data line pattern located in each sub-pixel region, the data line pattern including a portion extending along the second direction;

[0014] The orthographic projection of the initialization signal line pattern on the substrate and the orthographic projection of the conductive connection part pattern on the substrate have a third overlapping area;

[0015] The orthographic projection of the initialization signal line pattern on the substrate and the orthographic projection of the data line pattern on the substrate have a fourth overlapping region;

[0016] The width of the initialization signal line pattern along the second direction in the fourth overlapping region is smaller than the width of the initialization signal line pattern along the second direction in the third overlapping region.

[0017] Optionally, within the same sub-pixel region, the orthographic projection of the second main body portion onto the substrate and the orthographic projection of the second electrode of the seventh transistor onto the substrate have a first gap, the first gap being greater than a threshold.

[0018] The optional display panel also includes:

[0019] A plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel regions, each of the sub-pixel driving circuits including a driving transistor and a second transistor;

[0020] The gate of the second transistor is pattern-coupled with the reset signal line in the adjacent previous sub-pixel region along the second direction, the first electrode of the second transistor serves as the target coupling portion in the previous sub-pixel region, and the second electrode of the second transistor is coupled with the gate of the driving transistor.

[0021] The second transistor includes two semiconductor portions spaced apart along the first direction, and a first conductor portion connecting the two semiconductor portions respectively. The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first protrusion in the previous sub-pixel region on the substrate.

[0022] Optionally, the orthographic projection of the first conductor portion on the substrate overlaps with the orthographic projection of the first end of the conductive connection portion pattern in the previous sub-pixel region on the substrate.

[0023] Optionally, each of the initialization signal line patterns further includes a second protrusion coupled to the first body portion. In the same sub-pixel region, the orthographic projection of the second protrusion onto the substrate is located between the orthographic projection of the first body portion onto the substrate and the orthographic projection of the reset signal line pattern onto the substrate, and the orthographic projection of the first conductor portion onto the substrate overlaps with the orthographic projection of the second protrusion onto the substrate.

[0024] Optionally, the conductive connection pattern further includes a second main body portion connected between the first end and the second end, the second main body portion extending along a second direction;

[0025] One end of the conductive connection pattern in the first conductor portion, near the previous sub-pixel region, extends along the second direction. The orthographic projection of this end on the substrate and the orthographic projection of the second main body portion of the conductive connection pattern on the substrate have a second gap, which is greater than a threshold.

[0026] Optionally, within the same sub-pixel region, the orthographic projection of the first end of the conductive connection pattern onto the substrate also forms a second overlapping region with the orthographic projection of the first main body portion of the initialization signal line pattern onto the substrate.

[0027] The functional film layer also includes a first connection hole located in each of the sub-pixel regions. In the same sub-pixel region, the orthographic projection of the first connection hole on the substrate overlaps with the first overlapping region and the second overlapping region, respectively. The first end of the conductive connection part pattern is coupled to the initialization signal line pattern through the first connection hole.

[0028] Optionally, the orthographic projection of the first conductor portion of the second transistor onto the substrate does not overlap with the orthographic projection of the first connection hole in the previous sub-pixel region onto the substrate.

[0029] Optionally, the functional film layer further includes a power signal line layer, the power signal line layer including a power signal line pattern disposed in each of the sub-pixel regions, at least a portion of the power signal line pattern extending along a second direction;

[0030] One end of the first conductor portion, away from the conductive connection pattern in the previous sub-pixel region, extends along the second direction, and the orthographic projection of this end on the substrate is completely covered by the orthographic projection of the power signal line pattern located in the same sub-pixel region on the substrate.

[0031] Optionally, the display panel further includes:

[0032] A plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel regions, each of the sub-pixel driving circuits including a driving transistor and a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate being multiplexed as the gate of the driving transistor, and the second electrode plate being located on the side of the first substrate facing away from the substrate;

[0033] The functional film layer further includes a power signal line layer, the power signal line layer including a power signal line pattern disposed in each of the sub-pixel regions, at least a portion of the power signal line pattern extending along a second direction, the power signal line pattern including a first power part and a second power part;

[0034] The orthographic projection of the first power supply unit on the substrate overlaps with the orthographic projection of each reset signal line pattern located in the same sub-pixel region on the substrate, and also overlaps with the orthographic projection of each gate line pattern located in the same sub-pixel region on the substrate; the orthographic projection of the second power supply unit on the substrate overlaps with the orthographic projection of the second plate of the corresponding storage capacitor on the substrate; the width of the first power supply unit along the first direction is smaller than the width of the second power supply unit.

[0035] Optionally, the functional film layer further includes a power signal line layer, the power signal line layer including a power signal line pattern disposed in each of the sub-pixel regions, at least a portion of the power signal line pattern extending along a second direction;

[0036] The functional film layer further includes an auxiliary power layer, which includes an auxiliary power pattern disposed in each of the sub-pixel regions. The orthographic projection of the auxiliary power pattern on the substrate and the orthographic projection of the power signal line pattern located in the same sub-pixel region on the substrate have an overlapping area, and the auxiliary power pattern and the power signal line pattern are coupled in the overlapping area.

[0037] Optionally, the display panel further includes: a plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel areas, each of the sub-pixel driving circuits including a driving transistor and a second transistor;

[0038] The gate of the second transistor is pattern-coupled with the reset signal line in the adjacent previous sub-pixel region along the second direction. The first electrode of the second transistor serves as the target coupling portion in the previous sub-pixel region. The second electrode of the second transistor includes a coupled first electrode portion and a second electrode portion. The first electrode portion extends along the second direction, and the second electrode portion extends along a third direction. The third direction intersects both the first direction and the second direction. The first electrode portion is located between the semiconductor portion of the second transistor and the second electrode portion. The second electrode portion is coupled with the gate of the driving transistor.

[0039] The orthographic projections of the first electrode portion and the second electrode portion on the substrate are both covered by the orthographic projections of the corresponding auxiliary power supply pattern on the substrate.

[0040] Optionally, the auxiliary power supply pattern includes a first auxiliary sub-pattern and a second auxiliary sub-pattern coupled together, wherein the first auxiliary sub-pattern extends along a second direction and at least a portion of the second auxiliary sub-pattern extends along the first direction;

[0041] The orthographic projection of the first auxiliary sub-pattern onto the substrate covers the orthographic projection of the first electrode portion onto the substrate and the orthographic projection of the second electrode portion onto the substrate.

[0042] Optionally, along the first direction, the width of the first auxiliary sub-pattern is greater than the width of the corresponding power signal line pattern.

[0043] Optionally, the orthographic projections of the first electrode portion and the second electrode portion on the substrate are both covered by the orthographic projections of the corresponding power signal line pattern on the substrate.

[0044] Optionally, the functional film layer includes: a gate line pattern and a light emission control signal line pattern located in each sub-pixel region; in the same sub-pixel region, along the second direction, the gate line pattern, the light emission control signal line pattern, the reset signal line pattern, and the initialization signal line pattern are arranged sequentially.

[0045] The functional film layer also includes power signal line patterns and data line patterns located in each sub-pixel region, and both the power signal line patterns and the data line patterns include portions extending along the second direction.

[0046] The display panel also includes:

[0047] Light-emitting elements that correspond one-to-one with the plurality of sub-pixel regions;

[0048] Each sub-pixel driving circuit corresponds one-to-one with the plurality of sub-pixel regions, and each sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0049] In the same sub-pixel region, the gate of the driving transistor is coupled to the second terminal of the first transistor, the first terminal of the driving transistor is coupled to the second terminal of the fifth transistor, and the second terminal of the driving transistor is coupled to the first terminal of the first transistor;

[0050] The gate of the first transistor is coupled to the gate line pattern;

[0051] The gate of the second transistor is pattern-coupled with the reset signal line in the adjacent previous sub-pixel region along the second direction, the first electrode of the second transistor serves as the target coupling portion in the previous sub-pixel region, and the second electrode of the second transistor is coupled with the gate of the driving transistor.

[0052] The gate of the fourth transistor is coupled to the gate line pattern, the first terminal of the fourth transistor is coupled to the data line pattern, and the second terminal of the fourth transistor is coupled to the first terminal of the driving transistor.

[0053] The gate of the fifth transistor is coupled to the light-emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power supply signal line pattern.

[0054] The gate of the sixth transistor is pattern-coupled with the light-emitting control signal line, the first terminal of the sixth transistor is coupled with the second terminal of the driving transistor, and the second terminal of the sixth transistor is coupled with the corresponding light-emitting element.

[0055] The second terminal of the seventh transistor is coupled to the light-emitting element, the gate of the seventh transistor is coupled to the reset signal line pattern, and the first terminal of the seventh transistor is coupled to the second initialization signal line pattern.

[0056] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel.

[0057] Based on the above-described technical solution for the display panel, a third aspect of this disclosure provides a method for manufacturing a display panel, comprising:

[0058] A functional film layer is fabricated on the substrate, forming multiple sub-pixel regions arranged in an array;

[0059] The functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;

[0060] The reset signal line layer includes: a reset signal line pattern disposed in each of the sub-pixel regions, the reset signal line pattern extending along a first direction;

[0061] The initialization signal line layer includes: an initialization signal line pattern disposed in each of the sub-pixel regions. The initialization signal line pattern includes a first main body portion and a first protruding portion coupled together. The first main body portion extends along the first direction. In the same sub-pixel region, the orthographic projection of the first main body portion on the substrate is located between the orthographic projection of the first protruding portion on the substrate and the orthographic projection of the reset signal line pattern on the substrate.

[0062] The conductive connection layer includes: conductive connection patterns disposed in each of the sub-pixel areas; in the same sub-pixel area, the orthographic projection of the first end of the conductive connection pattern on the substrate has a first overlapping area with the orthographic projection of the first protruding portion on the substrate; in the first overlapping area, the first end is coupled to the first protruding portion; the second end of the conductive connection pattern is coupled to a target coupling portion in its sub-pixel area; and the orthographic projection of the reset signal line pattern on the substrate is located between the orthographic projection of the target coupling portion on the substrate and the orthographic projection of the initialization signal line pattern on the substrate. Attached Figure Description

[0063] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0064] Figure 1 This is a schematic diagram of sub-pixel layout in the prior art;

[0065] Figure 2 for Figure 1 A schematic diagram of the layout of the active layer;

[0066] Figure 3 for Figure 1 A schematic diagram of the layout of the first gate metal layer;

[0067] Figure 4 for Figure 1 Schematic diagram of the layout of the second gate metal layer;

[0068] Figure 5 for Figure 1 Schematic diagram of the layout of the central source drain metal layer;

[0069] Figure 6 A circuit diagram of a sub-pixel driving circuit provided in an embodiment of this disclosure;

[0070] Figure 7 A timing diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0071] Figure 8 This is a first layout schematic diagram of the sub-pixel region provided in an embodiment of the present disclosure;

[0072] Figure 9 This is a schematic diagram of the second layout of the sub-pixel region provided in an embodiment of the present disclosure;

[0073] Figure 10 for Figure 8 A schematic diagram of the layout of the active layer;

[0074] Figure 11 for Figure 8 A schematic diagram of the layout of the first gate metal layer;

[0075] Figure 12 for Figure 8 Schematic diagram of the layout of the second gate metal layer;

[0076] Figure 13 for Figure 8 Schematic diagram of the layout of the central source drain metal layer;

[0077] Figure 14 for Figure 8A schematic diagram of the cross-section along the A1A2 direction;

[0078] Figure 15 This is a schematic diagram of the third layout of the sub-pixel region provided in an embodiment of this disclosure;

[0079] Figure 16 for Figure 15 First enlarged schematic diagram of section X1;

[0080] Figure 17 for Figure 15 A second enlarged schematic diagram of section X1 in the middle;

[0081] Figure 18 for Figure 17 A schematic diagram of the cross-section along the B1B2 direction;

[0082] Figure 19 for Figure 15 A schematic diagram of the layout of the active layer;

[0083] Figure 20 for Figure 15 A schematic diagram of the layout of the first gate metal layer;

[0084] Figure 21 for Figure 15 Schematic diagram of the layout of the second gate metal layer;

[0085] Figure 22 for Figure 15 Schematic diagram of the layout of the central source drain metal layer;

[0086] Figure 23 This is a fourth layout diagram of the sub-pixel region provided in an embodiment of the present disclosure;

[0087] Figure 24 This is a schematic diagram of the structure of the power signal line pattern provided in the embodiments of this disclosure;

[0088] Figure 25 This is a fifth layout schematic diagram of the sub-pixel region provided in an embodiment of the present disclosure;

[0089] Figure 26 for Figure 25 A schematic diagram of the layout of the active layer;

[0090] Figure 27 for Figure 25 A schematic diagram of the layout of the first gate metal layer;

[0091] Figure 28 for Figure 25 Schematic diagram of the layout of the second gate metal layer;

[0092] Figure 29 for Figure 25 Schematic diagram of the layout of the central source drain metal layer;

[0093] Figure 30 This is a schematic diagram of the layout of the second source / drain metal layer provided in an embodiment of this disclosure;

[0094] Figure 31 This is a schematic diagram of the layout of the second source / drain metal layer and the anode layer provided in an embodiment of this disclosure;

[0095] Figure 32 This is a schematic diagram of the sixth and fifth layout of the sub-pixel region provided in an embodiment of the present disclosure;

[0096] Figure 33 for Figure 32 A schematic diagram of the layout of the second gate metal layer and the second source / drain metal layer in the diagram;

[0097] Figure 34 for Figure 32 A schematic diagram of the cross-section along the C1C2 direction. Detailed Implementation

[0098] To further illustrate the display panel, its manufacturing method, and the display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0099] The structure of an AMOLED display panel includes: a substrate, multiple sub-pixel driving circuits disposed on the substrate, and multiple light-emitting elements disposed on the side of the sub-pixel driving circuits facing away from the substrate. Each light-emitting element corresponds to a sub-pixel driving circuit, and the sub-pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function of the display panel.

[0100] In related technologies, the sub-pixel driving circuit generally includes multiple thin-film transistors, such as... Figure 1 As shown, Figure 1 The diagram illustrates the specific layout of the seven thin-film transistors (TFTs) M1 to M7 in the sub-pixel driving circuit. When arranged in this manner, the sub-pixel driving circuit includes... Figure 2 The active layer shown is as follows: Figure 3 The first metal layer shown, such as Figure 4 The second metal layer shown, and as shown Figure 5 The third metal layer shown; the active layer includes active patterns (such as those for forming the channel regions of each thin-film transistor) for forming the channel regions of each thin-film transistor. Figure 2 The portion within the dashed box in the image), and the doped active pattern coupled to the active pattern and possessing conductive properties (such as...). Figure 2The first metal layer includes the gate of each thin-film transistor, the scan signal line GATE coupled to the gate, one electrode CE1 of the storage capacitor in the sub-pixel driving circuit, the reset signal line RST, and the light emission control signal line EM; the second metal layer includes the initialization signal line VINT, and the other electrode CE2 of the storage capacitor in the sub-pixel driving circuit; the third metal layer includes the data line DATA, the power signal line VDD, and some conductive connections (such as those marked 341 to 343).

[0101] It is worth noting that, for example Figure 1 As shown, in order to achieve coupling between functional graphics set in different layers when laying out the sub-pixel driving circuit, some vias (such as those marked: 381~388) can also be set.

[0102] like Figure 6 , Figure 8 and Figure 14 As shown, this disclosure provides a display panel including multiple sub-pixel driving circuits, and further including a power signal line pattern 901, a data line pattern 908, a gate line pattern 902, a light emission control signal line pattern 903, a reset signal line pattern 905, and an initialization signal line pattern 904; at least a portion of the power signal line pattern 901 and the data line pattern 908 extend along a second direction; the gate line pattern 902, the light emission control signal line pattern 903, the reset signal line pattern 905, and the initialization signal line pattern 904 all extend along a first direction, which intersects with the second direction. For example, the first direction includes the X direction, and the second direction includes the Y direction.

[0103] like Figure 9 As shown, the plurality of sub-pixel driving circuits can be divided into multiple rows of sub-pixel driving circuits arranged sequentially along the second direction, and multiple columns of sub-pixel driving circuits arranged sequentially along the first direction. The initialization signal line pattern 904 corresponding to the sub-pixel driving circuits in the same row are electrically connected in sequence to form an integral structure; the gate line pattern 902 corresponding to the sub-pixel driving circuits in the same row are electrically connected in sequence to form an integral structure; the light emission control signal line pattern 903 corresponding to the sub-pixel driving circuits in the same row are electrically connected in sequence to form an integral structure; the reset signal line pattern 905 corresponding to the sub-pixel driving circuits in the same row are electrically connected in sequence to form an integral structure; the data line pattern 908 corresponding to the sub-pixel driving circuits in the same column are electrically connected in sequence to form an integral structure; and the power signal line pattern 901 corresponding to the sub-pixel driving circuits in the same column are electrically connected in sequence to form an integral structure.

[0104] For example, each row of sub-pixel driving circuits includes multiple sub-pixel driving circuits arranged sequentially along the X direction. The initialization signal line pattern 904, gate line pattern 902, light emission control signal line pattern 903, and reset signal line pattern 905 all extend along the X direction. The multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits can be coupled to the corresponding initialization signal line pattern 904, gate line pattern 902, light emission control signal line pattern 903, and reset signal line pattern 905, respectively. Each column of sub-pixel driving circuits includes multiple sub-pixel driving circuits arranged sequentially along the Y direction. The data line pattern 908 and power signal line pattern 901 both extend along the Y direction. The multiple sub-pixel driving circuits included in each column of sub-pixel driving circuits can be coupled to the corresponding data line pattern 908 and power signal line pattern 901, respectively.

[0105] It is worth noting that there are various physical division methods for sub-pixel areas in the display panel. Two specific division methods are given below as examples.

[0106] The first method of division, such as Figure 8 As shown, the first transistor T1, located at... Figure 8 The top transistors T2, T3, T4, T5, and T6, and located at... Figure 8 The seventh transistor T7 at the top, along with gate pattern 902, light-emitting control signal line pattern 903, and located at... Figure 8 The reset signal line at the top is pattern 905' and located at... Figure 8 The initialization signal line at the top, pattern 904', is divided into a sub-pixel region (i.e., the current sub-pixel region). For Figure 8 The second transistor T2 at the bottom of the middle, Figure 8 The seventh transistor T7 at the bottom center is located Figure 8 The reset signal line pattern 905 at the bottom, and located at... Figure 8 The initialization signal line pattern 904 at the bottom is divided into the next sub-pixel area adjacent to the current sub-pixel area along the Y direction.

[0107] The second classification method, such as Figure 8 As shown, the first transistor T1, located at... Figure 8 The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 at the bottom and located at Figure 8 The seventh transistor T7 at the bottom, along with the gate pattern 902, the light-emitting control signal line pattern 903, and located at... Figure 8 The reset signal line at the bottom is pattern 905 and located at... Figure 8 The initialization signal line pattern 904 at the bottom is divided into a sub-pixel area (i.e., the current sub-pixel area). ForFigure 8 The second transistor T2 at the top of the middle, Figure 8 The seventh transistor T7 at the top center is located Figure 8 The reset signal line at the top is pattern 905', and located at... Figure 8 The initialization signal line pattern 904' at the top is divided into the previous sub-pixel area that is adjacent to the current sub-pixel area along the Y direction.

[0108] It should be noted that the sub-pixel region division method described in this disclosure adopts the second division method mentioned above. For the second division method, in the sub-pixel driving circuit corresponding to the current sub-pixel region (i.e., the corresponding...) Figure 8 In the sub-pixel driving circuit of the structure, it includes: a first transistor T1, located in Figure 6 The top transistors T2, T3, T4, T5, and T6, and located at... Figure 8 The seventh transistor T7 at the bottom; this is located Figure 8 The gate 202g of the top second transistor T2 is coupled to the reset signal line pattern 905' in the adjacent previous sub-pixel region along the second direction, the source S2 of the second transistor T2 is coupled to the initialization signal line pattern 904' in the previous sub-pixel region, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0109] like Figure 8 and Figure 6 As shown, taking a sub-pixel driving circuit as an example, the sub-pixel driving circuit includes 7 thin-film transistors and 1 capacitor. Each transistor in the sub-pixel driving circuit is a P-type transistor. The first transistor T1 has a dual-gate structure. The gate 201g of the first transistor T1 is coupled to the gate line pattern 902. The source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor). The drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0110] The second transistor T2 has a dual-gate structure. The gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the adjacent previous sub-pixel region along the second direction. The source S2 of the second transistor T2 is coupled to the initialization signal line pattern 904' in the previous sub-pixel region. The drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0111] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0112] The gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power supply signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0113] The gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light-emitting element EL.

[0114] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905, the drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL, and the source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904.

[0115] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.

[0116] like Figure 8 As shown, when the display sub-pixel driving circuit with the above structure is working, each working cycle includes a reset period P1, a write compensation period P2, and a light emission period P3. Figure 7 In this context, E1 represents the light emission control signal transmitted on the light emission control signal line pattern 903 in the current sub-pixel area, R1 represents the reset signal transmitted on the reset signal line pattern 905 in the current sub-pixel area, D1 represents the data signal transmitted on the data line pattern 908 in the current sub-pixel area, G1 represents the gate scan signal transmitted on the gate line pattern 902 in the current sub-pixel area, and R1' represents the reset signal transmitted on the reset signal line pattern 905' in the previous sub-pixel adjacent to the current sub-pixel along the second direction.

[0117] During the first reset period P1, the reset signal input by the reset signal line pattern 905' is at an active level, the second transistor T2 is turned on, and the initialization signal transmitted by the initialization signal line pattern 904' is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0118] During the write compensation period P2, the reset signal input to the reset signal line pattern 905' is at an inactive level, the second transistor T2 is turned off, and the gate scan signal input to the gate line pattern 902 is at an active level, controlling the first transistor T1 and the fourth transistor T4 to turn on. The data line pattern 908 writes the data signal, which is transmitted to the source S3 of the third transistor T3 via the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, making the third transistor T3 form a diode structure. Therefore, by working together, the first transistor T1, the third transistor T3, and the fourth transistor T4 can achieve threshold voltage compensation for the third transistor T3. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to eventually reach Vdata + Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0119] During the write compensation period P2, the reset signal input to the reset signal line pattern 905 is at an active level, controlling the seventh transistor T7 to turn on. The initialization signal transmitted by the initialization signal line pattern 904 is input to the anode of the light-emitting element EL, controlling the light-emitting element EL not to emit light.

[0120] During the light-emitting period P3, the light-emitting control signal written in the light-emitting control signal line pattern 903 is at an effective level, controlling the fifth transistor T5 and the sixth transistor T6 to conduct, so that the power signal transmitted by the power signal line pattern 901 is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on. The gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power signal. The leakage current generated based on this gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.

[0121] like Figure 7 As shown, the layout of each film layer corresponding to the display sub-pixel driving circuit is as follows when fabricating the above-mentioned display sub-pixel driving circuit:

[0122] An active film layer, a gate insulating layer, a first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer, a first source / drain metal layer, and a third interlayer insulating layer are sequentially stacked along a direction away from the substrate.

[0123] like Figures 10-13As shown, the active film layer is used to form the channel region (e.g., 101pg~107pg), source formation region (e.g., 101ps~107ps), and drain formation region (e.g., 101pd~107pd) of each transistor in the display sub-pixel driving circuit. Due to doping, the conductivity of the active film layer corresponding to the source and drain formation regions is better than that of the active film layer corresponding to the channel region. The active film layer can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0124] In addition, it is worth noting that the active film layers corresponding to the source forming region and the drain forming region can be directly used as the corresponding source or drain. Alternatively, a metal material can be used to make the source that contacts the source forming region and the drain that contacts the drain forming region.

[0125] like Figure 10 As shown, the first gate metal layer is used to form the gates of each transistor in the display sub-pixel driving circuit (e.g., 201g to 207g), as well as the gate line pattern 902, light emission control signal line pattern 903, reset signal line pattern 905 and other structures included in the display substrate. The gate 203g of the third transistor T3 in each display sub-pixel driving circuit is multiplexed as the first plate Cst1 of the second storage capacitor Cst in the display sub-pixel driving circuit.

[0126] like Figure 11 As shown, the second gate metal layer is used to form the second electrode Cst2 of the second storage capacitor Cst, and the initialization signal line pattern 904 included in the display substrate.

[0127] like Figure 12 , Figure 6 and 13 As shown, the first source-drain metal layer is used to form the source (e.g., S1 to S7) and drain (e.g., D1 to D7) of each transistor in the display sub-pixel driving circuit, as well as the data line pattern 908, power signal line pattern 901 and some conductive connection portions included in the display substrate.

[0128] For more details, please continue reading. Figure 8 The gate 201g of the first transistor T1 covers the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.

[0129] The gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.

[0130] The gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.

[0131] The gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation region 104pd.

[0132] The gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.

[0133] The gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.

[0134] The gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.

[0135] The gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.

[0136] In addition, such as Figures 10-13As shown, in the display panel provided in this disclosure, in the second direction (e.g., the Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gates of the seventh transistor T7, the sixth transistor T6, and the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first and second sides of the gate of the driving transistor are opposite sides along the second direction. Further, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor. The lower side, for example, is the side of the display substrate used for bonding the IC, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor further away from the IC.

[0137] In the first direction (e.g., the X direction), the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor. For example, the third and fourth sides of the gate of the driving transistor are opposite sides along the first direction; further, the third side of the gate of the driving transistor can be the right side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor can be the left side of the gate of the driving transistor. The left and right sides, for example, in the same sub-pixel region, may have the data line pattern 908 located to the right of the power signal line pattern 901, and the power signal line pattern 901 located to the right of the data line pattern 908.

[0138] While the aforementioned display panel can improve resolution, the improvement is limited. Furthermore, from... Figure 8 As can be seen, when the second transistor T2 and the seventh transistor T7 are coupled to the initialization signal line pattern 904 (904') through the conductive part 909 via vias, for high-resolution display panels, due to the small layout space, the space that can be punched is small. During the punching process, it is easy to deviate the vias onto the nearby reset signal line pattern 905 when there are process fluctuations, resulting in signal interference.

[0139] Therefore, for high-resolution display panels, the pixel structure in the aforementioned display panels needs further optimization to solve the above problems.

[0140] Please see Figure 8 and Figure 15This disclosure provides a display panel, including: a substrate, a functional film layer disposed on the substrate; and a plurality of sub-pixel regions arranged in an array;

[0141] The functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;

[0142] The reset signal line layer includes: a reset signal line pattern 905 disposed in each of the sub-pixel areas, the reset signal line pattern 905 extending along a first direction;

[0143] The initialization signal line layer includes: an initialization signal line pattern 904 disposed in each of the sub-pixel areas. The initialization signal line pattern 904 includes a first main body portion 9041 and a first protruding portion 9042 coupled together. The first main body portion 9041 extends along the first direction. In the same sub-pixel area, the orthographic projection of the first main body portion 9041 on the substrate is located between the orthographic projection of the first protruding portion 9042 on the substrate and the orthographic projection of the reset signal line pattern 905 on the substrate.

[0144] The conductive connection layer includes: a conductive connection pattern 909 disposed in each of the sub-pixel areas; in the same sub-pixel area, the orthographic projection of the first end portion 9091 of the conductive connection pattern 909 on the substrate has a first overlapping area F1 with the orthographic projection of the first protrusion 9042 on the substrate; in the first overlapping area F1, the first end portion 9091 is coupled to the first protrusion 9042; the second end portion 9092 of the conductive connection pattern 909 is coupled to a target coupling portion in its sub-pixel area; and the orthographic projection of the reset signal line pattern 905 on the substrate is located between the orthographic projection of the target coupling portion on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.

[0145] Specifically, the array of multiple sub-pixel regions can be divided into multiple rows of sub-pixel regions arranged sequentially along a second direction, and multiple columns of sub-pixel regions arranged sequentially along a first direction. Each row of sub-pixel regions includes multiple sub-pixel regions spaced apart along the first direction, and each column of sub-pixel regions includes multiple sub-pixel regions spaced apart along the second direction. The first direction intersects the second direction; for example, the first direction includes the X direction, and the second direction includes the Y direction.

[0146] The reset signal line layer includes reset signal line patterns 905 disposed in each of the sub-pixel areas, and the reset signal line patterns 905 extend along the first direction. Each reset signal line pattern 905 corresponds to one of the sub-pixel areas, and the reset signal line patterns 905 located in the corresponding sub-pixel areas are electrically connected sequentially to form an integral structure.

[0147] The initialization signal line layer includes: initialization signal line patterns 904 disposed in each of the sub-pixel areas, each initialization signal line pattern 904 corresponding to a sub-pixel area, each initialization signal line pattern 904 located in the corresponding sub-pixel area, and each initialization signal line pattern 904 corresponding to a sub-pixel area in the same row being electrically connected in sequence to form an integral structure.

[0148] like Figure 16 As shown, each initialization signal line pattern 904 includes a first main body portion 9041 and a first protruding portion 9042 coupled together. The first main body portion 9041 extends along the first direction. The first main body portions 9041 of each initialization signal line pattern 904 located in the same row of sub-pixel areas are electrically connected in sequence to form an integral structure. It is worth noting that, considering manufacturing process errors, the first main body portion is not necessarily a straight line extending along the first direction.

[0149] The specific shape of the first protruding portion 9042 can vary, as long as it satisfies the requirement that the first protruding portion 9042 protrudes beyond the coupled first main body portion 9041 in the second direction. By setting it in the same sub-pixel area, the orthographic projection of the first main body portion 9041 on the substrate is located between the orthographic projection of the first protruding portion 9042 on the substrate and the orthographic projection of the reset signal line pattern 905 on the substrate, so that the first protruding portion 9042 can be positioned away from the reset signal line pattern 905, thereby allowing the first protruding portion 9042 to have a greater distance from the reset signal line pattern 905.

[0150] It should be noted that in an initialization signal line pattern 904, the first main body portion 9041 and the first protruding portion 9042 can be formed as an integral structure, but are not limited to this.

[0151] The conductive connection layer includes: a conductive connection pattern 909 disposed in each of the sub-pixel areas, wherein the conductive connection pattern 909 corresponds one-to-one with the sub-pixel areas and is located in the corresponding sub-pixel area.

[0152] The orthographic projection of the first end portion 9091 of the conductive connection pattern 909 onto the substrate has a first overlapping region F1 with the orthographic projection of the first protrusion 9042 onto the substrate. The first end portion 9091 and the first protrusion 9042 can be coupled by drilling a hole (such as a first connection hole 70) in the first overlapping region F1. The second end portion 9092 of the conductive connection pattern 909 is coupled to a target coupling portion in its sub-pixel region. The target coupling portion may include the first electrode of the seventh transistor corresponding to the current sub-pixel region and the first electrode of the second transistor corresponding to the next sub-pixel region adjacent to the current sub-pixel region along the second direction.

[0153] The target coupling portion can be positioned in various ways. For example, it can be positioned in the same sub-pixel area, with the orthographic projection of the reset signal line pattern 905 on the substrate located between the orthographic projection of the target coupling portion on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.

[0154] It should be noted that the display panel further includes an interlayer dielectric layer (i.e., the previously mentioned second interlayer insulating layer ILD). This interlayer dielectric layer is located between the second gate metal layer and the first source / drain metal layer in the display panel. The initialization signal line pattern 904 can be disposed on the same layer as the second gate metal layer and can be formed in the same patterning process. The conductive connection pattern 909 can be disposed on the same layer as the first source / drain metal layer and can be formed in the same patterning process. The aforementioned via is drilled in the first overlapping region F1 to couple the first end 9091 of the conductive connection pattern 909 with the first protruding portion 9042. The via is a through-hole that penetrates the ILD layer, and the distance between this via and the reset signal line pattern 905 is greater.

[0155] As can be seen from the specific structure of the display panel described above, in the display panel provided in this embodiment, the initialization signal line pattern 904 is provided with a first protruding portion 9042 on the side facing away from the reset signal line pattern 905, and the first end 9091 of the conductive connection portion pattern 909 is provided with a projection on the substrate, which has a first overlapping area F1 with the projection of the first protruding portion 9042 on the substrate. The first end 9091 and the first protruding portion 9042 can be coupled by drilling holes in the first overlapping area F1. This arrangement makes the vias used to couple the conductive connection portion and the initialization signal line pattern 904 have a greater distance from the reset signal line pattern 905, thereby avoiding the problem that the vias are easily deflected onto the nearby reset signal line pattern 905 during the drilling process due to process fluctuations, resulting in signal interference, and thus better ensuring the yield of the display panel.

[0156] Furthermore, since the initialization signal line pattern 904 includes a first protrusion 9042 on the side facing away from the reset signal line pattern 905, and a via for coupling the conductive connection portion and the initialization signal line pattern 904 is formed on the first protrusion 9042, the orthographic projection of the via on the substrate can be wrapped by the orthographic projection of the initialization signal line pattern 904 on the substrate. This greatly improves the reliability of the coupling between the initialization signal line pattern 904 and the conductive connection portion pattern 909, and better ensures the stability of the display panel during operation.

[0157] like Figure 16 and Figure 15 As shown, in some embodiments, the display panel further includes:

[0158] A plurality of light-emitting elements corresponding one-to-one with the plurality of sub-pixel regions, wherein the plurality of light-emitting elements are located on the side of the functional film layer facing away from the substrate;

[0159] A plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel regions, each of the sub-pixel driving circuits including a seventh transistor T7, the gate 207g of the seventh transistor T7 being coupled to the corresponding reset signal line pattern 905, the first electrode of the seventh transistor T7 serving as the target coupling portion, and the second electrode of the seventh transistor T7 (formed in the 107pd region) extending along the second direction and coupled to the anode of the corresponding light-emitting element;

[0160] The conductive connection pattern 909 further includes a second main body portion 9093 connected between the first end portion 9091 and the second end portion 9092, the second main body portion 9093 extending along a second direction; in the same sub-pixel region, along the first direction, the first end portion 9091 of the conductive connection pattern 909 protrudes from the second main body portion 9093 in a direction away from the second pole of the seventh transistor.

[0161] Specifically, the display panel further includes a plurality of light-emitting elements located on the side of the functional film layer facing away from the substrate, and the plurality of light-emitting elements correspond one-to-one with the plurality of sub-pixel areas. Each light-emitting element includes: an anode, a light-emitting pattern, and a cathode, which are sequentially stacked along a direction away from the substrate; when the display panel is in operation, a driving signal is provided to the anode and a common signal is provided to the cathode, so that an electric field is generated between the anode and the cathode, thereby controlling the light-emitting pattern to emit light of a corresponding color; for example, the light-emitting elements include red light-emitting elements that can emit red light, green light-emitting elements that can emit green light, and blue light-emitting elements that can emit blue light, etc.

[0162] The display panel further includes a plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel areas. Each sub-pixel driving circuit is used to provide a driving signal to the anode of its corresponding light-emitting element. For example, each sub-pixel driving circuit includes a seventh transistor. The gate of the seventh transistor is coupled to the corresponding reset signal line pattern 905. The first electrode of the seventh transistor serves as the target coupling portion and can be coupled to the corresponding initialization signal line pattern 904 through the corresponding conductive connection portion pattern 909. The second electrode of the seventh transistor T7 extends along the second direction and is coupled to the anode of the corresponding light-emitting element.

[0163] like Figure 16 As shown, the seventh transistor is mainly used to reset the N2 node before pixel charging. The detailed reset process is as follows: the seventh transistor provides an initialization signal through the initialization signal line pattern 904 coupled to the conductive connection pattern 909. The seventh transistor transmits the initialization signal to the N2 node, thereby resetting the N2 node. It is worth noting that the conductive connection pattern 909 acts as an intermediate layer to implement jumpers. The coupling of the conductive connection pattern 909 to the seventh transistor, as well as its coupling to the initialization signal line pattern 904, can both be achieved through vias.

[0164] The specific structure of the conductive connection part pattern 909 varies, for example, such as Figure 6 As shown, the conductive connection pattern 909 also includes a second main body portion 9093 connected between the first end portion 9091 and the second end portion 9092. The second main body portion 9093 can extend along the second direction. In the same sub-pixel area, along the first direction, the first end portion 9091 of the conductive connection pattern 909 protrudes from the second main body portion 9093 in a direction away from the second pole of the seventh transistor. This structure of the conductive connection pattern 909 allows for a greater distance between its first end portion 9091 and the second pole of the seventh transistor. Thus, when forming vias on the ILD to couple the first end portion 9091 of the conductive connection pattern 909 and the initialization signal line pattern 904, the vias are formed further away from the second pole of the seventh transistor. This helps to avoid the problem of the vias being misaligned onto the second pole of the seventh transistor during the manufacturing process due to process fluctuations, leading to signal interference. This, in turn, better ensures the yield of the display panel.

[0165] More specifically, such as Figure 16As shown, the second electrode of the seventh transistor is made using a poly layer (i.e., an active layer). By forming the conductive connection pattern 909 into the above structure, it is possible to better avoid the problem of the via being misaligned onto the poly layer corresponding to the second electrode of the seventh transistor during the via fabrication process due to process fluctuations, which would lead to signal interference. This, in turn, better ensures the yield of the display panel.

[0166] like Figure 15 As shown, in some embodiments, the functional film layer further includes a data line pattern 908 located in each sub-pixel region, the data line pattern 908 including a portion extending along the second direction;

[0167] The orthographic projection of the initialization signal line pattern 904 on the substrate and the orthographic projection of the conductive connection pattern 909 on the substrate have a third overlapping region F3;

[0168] The orthographic projection of the initialization signal line pattern 904 on the substrate and the orthographic projection of the data line pattern 908 on the substrate have a fourth overlapping region F4;

[0169] The width L5 of the initialization signal line pattern 904 along the second direction in the fourth overlapping region F4 is smaller than the width L6 of the initialization signal line pattern 904 along the second direction in the third overlapping region F3.

[0170] Specifically, the data line pattern 908 corresponds one-to-one with the sub-pixel area, the data line pattern 908 is located in the corresponding sub-pixel area, the data line pattern 908 includes a portion extending along the second direction, and the data line patterns 908 corresponding to the sub-pixel areas in the same column are electrically connected in sequence to form an integral structure.

[0171] Since the data line pattern 908 extends along the second direction, and the first main body portion 9041 of the initialization signal line pattern 904 extends along the first direction, and the first direction intersects with the second direction, the initialization signal line pattern 904 must overlap with the data line pattern 908 at least partially in the direction perpendicular to the base.

[0172] The above-described configuration includes a third overlapping region F3 between the orthographic projection of the initialization signal line pattern 904 on the substrate and the orthographic projection of the conductive connection pattern 909 on the substrate; a fourth overlapping region F4 between the orthographic projection of the initialization signal line pattern 904 on the substrate and the orthographic projection of the data line pattern 908 on the substrate; and a width of the initialization signal line pattern 904 along the second direction in the fourth overlapping region F4 being smaller than the width of the initialization signal line pattern 904 along the second direction in the third overlapping region F3. This allows the width of the initialization signal line pattern 904 to be narrowed along the second direction in some regions (specifically, the third overlapping region F3). This not only helps to reduce the overlap area between the initialization signal line pattern 904 and the data line pattern 908, reducing the value of parasitic capacitance, but also effectively reduces the layout space of the initialization signal line pattern 904, thereby saving pixel space and promoting the development of high resolution in the display panel.

[0173] like Figure 15 As shown, in some embodiments, in the same sub-pixel region, the orthographic projection of the second main body portion 9093 on the substrate and the orthographic projection of the second electrode of the seventh transistor T7 on the substrate have a first gap L1, the first gap being greater than a threshold.

[0174] Specifically, the above-mentioned arrangement of the orthographic projection of the second main body portion 9093 on the substrate and the orthographic projection of the second electrode of the seventh transistor T7 on the substrate has a first gap L1, which avoids the overlap between the second main body portion 9093 and the second electrode of the seventh transistor T7 in the direction perpendicular to the substrate.

[0175] Furthermore, by setting the first gap L1 to be greater than a threshold, a large distance is maintained between the orthographic projection of the second main body portion 9093 on the substrate and the orthographic projection of the second electrode of the seventh transistor on the substrate. This effectively avoids damage to the second electrode of the seventh transistor during the fabrication of the second main body portion 9093. It should be noted that the threshold can be set according to actual needs; for example, the threshold is between 8 μm and 35 μm and may include endpoint values.

[0176] like Figures 15-17 and Figure 15 As shown, in some embodiments, the display panel further includes:

[0177] A plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel regions, each of the sub-pixel driving circuits including a driving transistor and a second transistor T2;

[0178] The gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the previous sub-pixel region adjacent along the second direction. The first electrode of the second transistor T2 serves as the target coupling portion in the previous sub-pixel region. The second electrode of the second transistor T2 is coupled to the gate of the driving transistor (i.e., the third transistor T3).

[0179] The second transistor T2 includes two semiconductor portions (e.g., spaced apart along the first direction) Figure 16 As shown, located in the marked 102pg region, and a first conductor portion 80 connecting the two semiconductor portions respectively, the orthographic projection of the first conductor portion 80 on the substrate does not overlap with the orthographic projection of the first protrusion 9042 in the previous sub-pixel region on the substrate.

[0180] Specifically, each sub-pixel driving circuit includes a driving transistor and a second transistor. The driving transistor generates a driving signal to drive the light-emitting element to emit light. The gate of the second transistor is coupled to the reset signal line pattern 905 in the adjacent previous sub-pixel region along the second direction. The first electrode of the second transistor serves as the target coupling portion in the previous sub-pixel region, and the second electrode of the second transistor is coupled to the gate of the driving transistor. The second transistor is used to transmit the initialization signal provided by its coupled initialization signal line pattern 904 to node N1 (coupled to the gate of the driving transistor) before pixel charging, thereby resetting node N1.

[0181] For example, the second transistor may be a dual-gate structure. Specifically, the second transistor includes two semiconductor portions spaced apart along the first direction, and a first conductor portion 80 connecting the two semiconductor portions. The two semiconductor portions correspond to the channel region of the second transistor. The two semiconductor portions and the first conductor portion 80 can be formed as a single unit. During fabrication, the two semiconductor portions and a third semiconductor portion corresponding to the first conductor portion 80 can be formed first, and then the third semiconductor portion can be doped to form the first conductor portion 80.

[0182] The above-mentioned arrangement ensures that the orthographic projection of the first conductor portion 80 on the substrate does not overlap with the orthographic projection of the first protruding portion 9042 in the previous sub-pixel area on the substrate. This prevents the vias from being misaligned onto the first conductor portion 80 during process fluctuations, thus avoiding signal interference and better guaranteeing the yield of the display panel.

[0183] like Figure 19 and Figure 15 As shown, in some embodiments, the orthographic projection of the first conductor portion 80 on the substrate overlaps with the orthographic projection of the first end portion 9091 of the conductive connection pattern 909 in the previous sub-pixel region on the substrate.

[0184] Specifically, the above-mentioned arrangement of the orthographic projection of the first conductor portion 80 on the substrate overlapping the orthographic projection of the first end portion 9091 of the conductive connection portion pattern 909 in the previous sub-pixel area on the substrate not only allows the first end portion 9091 of the conductive connection portion pattern 909 to have a larger area to cover the connection via between it and the initialization signal line pattern 904, but also makes the layout of the first end portion 9091 of the conductive connection portion pattern 909 and the first conductor portion 80 more compact, thereby saving pixel space and facilitating the development of high resolution display panels.

[0185] like Figure 16 and Figure 15 As shown, in some embodiments, each of the initialization signal line patterns 904 further includes a second protrusion 9043 coupled to the first body portion 9041. In the same sub-pixel region, the orthographic projection of the second protrusion 9043 on the substrate is located between the orthographic projection of the first body portion 9041 on the substrate and the orthographic projection of the reset signal line pattern 905 on the substrate. The orthographic projection of the first conductor portion 80 on the substrate overlaps with the orthographic projection of the second protrusion 9043 and / or the first body portion 9041 on the substrate.

[0186] Specifically, each of the initialization signal line patterns 904 may further include a second protrusion 9043, which may be located between the first main body portion 9041 and the reset signal line pattern 905. For example, the second protrusion 9043, the first protrusion 9042, and the first main body portion 9041 may be formed as a single integral structure.

[0187] The above-described configuration allows the orthographic projection of the first conductor portion 80 on the substrate to overlap with the orthographic projection of the second protruding portion 9043 / or the first main body portion 9041 on the substrate. This enables the initialization signal line pattern 904 to block the first conductor portion 80. Since the initialization signals transmitted on the initialization signal line pattern 904 are stable signals, this blocking ensures signal stability on the first conductor portion 80 when external data signals change. This avoids the signal instability of the first conductor portion 80 due to capacitive coupling caused by the floating connection of the first conductor portion 80 when external data signals change.

[0188] like Figure 16 As shown, in some embodiments, the conductive connection pattern 909 further includes a second body portion 9093 connected between the first end portion 9091 and the second end portion 9092, the second body portion 9093 extending along a second direction;

[0189] One end 801 of the conductive connection pattern 909 in the first conductor portion 80, near the previous sub-pixel region, extends along the second direction. The orthographic projection of this end 801 on the substrate and the orthographic projection of the second main body portion 9093 of the conductive connection pattern 909 on the substrate have a second gap L2, which is greater than a threshold.

[0190] Specifically, the shape of the first conductor portion 80 can vary. For example, the first conductor portion 80 has a "gate-shaped" structure, that is, one end 801 of the first conductor portion 80 near the conductive connection pattern 909 in the previous sub-pixel area extends along the second direction, one end 802 of the first conductor portion 80 near the power signal line pattern 901 extends along the second direction, and the portion of the first conductor portion 80 located between these two ends extends along the first direction.

[0191] The above-described configuration provides a second gap L2 between the orthographic projection of one end 801 of the conductive connection pattern 909 in the first conductor portion 80 near the previous sub-pixel region on the substrate and the orthographic projection of the second main body portion 9093 of the conductive connection pattern 909 on the substrate, thereby preventing overlap between the second main body portion 9093 and the first conductor portion 80 in a direction perpendicular to the substrate.

[0192] Furthermore, by setting the second gap L2 to be greater than a threshold, a large distance is maintained between the orthographic projection of the second main body portion 9093 on the substrate and the orthographic projection of the first conductor portion 80 on the substrate. This effectively avoids damage to the first conductor portion 80 during the fabrication of the second main body portion 9093. It should be noted that the threshold can be set according to actual needs; for example, the threshold is between 8 μm and 35 μm and may include endpoint values.

[0193] like Figures 15-17 and Figure 15 As shown, in some embodiments, in the same sub-pixel area, the orthographic projection of the first end portion 9091 of the conductive connection pattern 909 onto the substrate also forms a second overlapping region F2 with the orthographic projection of the first main body portion 9041 of the initialization signal line pattern 904 onto the substrate.

[0194] The functional film layer also includes a first connection hole 70 located in each of the sub-pixel regions. In the same sub-pixel region, the orthographic projection of the first connection hole 70 on the substrate overlaps with the first overlapping region F1 and the second overlapping region F2, respectively. The first end 9091 of the conductive connection part pattern 909 is coupled to the initialization signal line pattern 904 through the first connection hole 70.

[0195] Specifically, the orthographic projection of the first end 9091 of the conductive connection pattern 909 onto the substrate can have a first overlapping region F1 with the orthographic projection of the first protruding portion 9042 of the initialization signal line pattern 904 onto the substrate, and can also have a second overlapping region F2 with the orthographic projection of the first main body portion 9041 of the initialization signal line pattern 904 onto the substrate.

[0196] When the first end 9091 of the conductive connection portion is coupled to the initialization signal line pattern 904 through the first connection hole 70, the orthographic projection of the first connection hole 70 on the substrate can be set to overlap with the first overlapping area F1 and the second overlapping area F2 respectively. In this way, the layout space of the first connection hole 70 is large, which can ensure good connection performance between the conductive connection portion pattern 909 and the initialization pattern.

[0197] like Figure 16 As shown, in some embodiments, the orthographic projection of the first conductor portion 80 of the second transistor T2 onto the substrate 40 does not overlap with the orthographic projection of the first connection hole 70 in the previous sub-pixel region onto the substrate 40.

[0198] Specifically, the orthographic projection of the first conductor portion 80 of the second transistor on the substrate 40 does not overlap with the orthographic projection of the first connection hole 70 in the previous sub-pixel area on the substrate 40. This can better avoid the problem that the via is easily misaligned onto the first conductor portion 80 during the manufacturing process of the first connection hole due to process fluctuations, which would cause signal interference. This, in turn, better ensures the yield of the display panel.

[0199] like Figure 18 and Figure 15 As shown, in some embodiments, the functional film layer further includes a power signal line layer, the power signal line layer including a power signal line pattern 901 disposed in each of the sub-pixel regions, at least a portion of the power signal line pattern 901 extending along a second direction;

[0200] One end 802 of the first conductor portion 80, away from the conductive connection pattern 909 in the previous sub-pixel region, extends along the second direction. The orthographic projection of this end 802 on the substrate is completely covered by the orthographic projection of the power signal line pattern 901 located in the same sub-pixel region on the substrate.

[0201] Specifically, each power signal line pattern 901 corresponds one-to-one with a sub-pixel region, and the power signal line pattern 901 is located in the corresponding sub-pixel region. The power signal line patterns 901 arranged in each column of sub-pixel regions are sequentially coupled along the second direction and can form a single integrated structure.

[0202] In the above-described configuration, one end 802 of the first conductor portion 80, which is away from the conductive connection pattern 909 in the previous sub-pixel region, extends along the second direction. The orthographic projection of this end 802 on the substrate is completely covered by the orthographic projection of the power signal line pattern 901 located in the same sub-pixel region on the substrate. This allows the power signal line pattern 901 to block the end of the first conductor portion 80 that is away from the conductive connection pattern 909 in the previous sub-pixel region. Since the power signals transmitted on the power signal line pattern 901 are stable signals, this blocking ensures the signal stability on the first conductor portion 80 when the external data signal changes. This avoids the signal instability of the first conductor portion 80 due to capacitive coupling caused by the floating connection of the first conductor portion 80 when the external data signal changes.

[0203] In addition, the above-mentioned arrangement effectively reduces the layout space occupied by the first conductive part and the power signal line pattern 901, greatly reduces the pixel structure, and is more conducive to the development of high resolution of the display panel.

[0204] The structure of the power signal line pattern 901 varies, such as... Figure 16 As shown. In some embodiments, the power signal line pattern 901 may be configured to extend along the second direction, and the width of the power signal line pattern 901 perpendicular to the second direction may be substantially uniform.

[0205] like Figure 22 and Figure 23 As shown, in some other embodiments, the display panel further includes:

[0206] A plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel regions, each of the sub-pixel driving circuits including a driving transistor and a storage capacitor, the storage capacitor including a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate being multiplexed as the gate of the driving transistor, and the second electrode plate being located on the side of the first substrate facing away from the substrate;

[0207] The functional film layer further includes a power signal line layer, the power signal line layer including a power signal line pattern 901 disposed in each of the sub-pixel regions, at least a portion of the power signal line pattern 901 extending along a second direction, the power signal line pattern 901 including a first power part 9011 and a second power part 9012.

[0208] The orthographic projection of the first power supply unit 9011 on the substrate overlaps with the orthographic projection of each reset signal line pattern 905 located in the same sub-pixel region on the substrate, and overlaps with the orthographic projection of each gate line pattern 902 located in the same sub-pixel region on the substrate; the orthographic projection of the second power supply unit 9012 on the substrate overlaps with the orthographic projection of the second plate Cts2 of the corresponding storage capacitor Cts on the substrate; the width L3 of the first power supply unit 9011 along the first direction is smaller than the width L4 of the second power supply unit 9012.

[0209] Specifically, each of the sub-pixel driving circuits may include a driving transistor and a storage capacitor Cts. The first plate Cts1 of the storage capacitor Cts is multiplexed as the gate of the driving transistor coupled to it. The second plate Cts2 of the storage capacitor is located on the side of the first plate Cts1 facing away from the substrate and can form a face-to-face area with the first plate.

[0210] The power signal line pattern 901 may specifically include a first power supply section 9011 and a second power supply section 9012. For example, the first power supply section 9011 and the second power supply section 9012 are arranged alternately along the second direction, and adjacent first and second portions are coupled together. For example, the first power supply section 9011 and the second power supply section 9012 are formed as a single structure.

[0211] The specific layout positions of the first power supply unit 9011 and the second power supply unit 9012 are varied. For example, the orthographic projection of the first power supply unit 9011 on the substrate overlaps with the orthographic projections of the reset signal line patterns 905 located in the same sub-pixel region on the substrate, and also overlaps with the orthographic projections of the gate line patterns 902 located in the same sub-pixel region on the substrate; the orthographic projection of the second power supply unit 9012 on the substrate overlaps with the orthographic projection of the second electrode plate of the corresponding storage capacitor on the substrate. By setting the width of the first power supply unit 9011 along the first direction to be smaller than the width of the second power supply unit 9012, the width of the first power supply unit 9011 along the first direction is effectively narrowed, reducing the overlap area between the first power supply unit 9011 and the reset signal line patterns 905, and also reducing the overlap area with the gate line patterns 902, thereby effectively reducing the coupling capacitance generated between the power signal line patterns 901 and the reset signal lines.

[0212] It should be noted that the width of the first power supply unit 9011 along the first direction refers to the maximum or minimum distance between two opposite boundaries of the first power supply unit 9011 along the first direction; similarly, the width of the second power supply unit 9012 along the first direction refers to the maximum or minimum distance between two opposite boundaries of the second power supply unit 9012 along the first direction.

[0213] It is worth noting that Figure 24 The diagram shows a schematic of eight sub-pixel areas when the power signal line pattern 901 adopts the structure of the first power supply section 9011 and the second power supply section 9012. Figure 25 The first connecting hole 70 shown is only an indication of its approximate location; the actual diameter of the first connecting hole may be larger than that shown. Figure 25 The aperture shown in the diagram should be large. The specific location of the first connecting hole can be the overlapping area of ​​the orthographic projection of the first end 9091 of the conductive connection part pattern 909 on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.

[0214] also, Figure 25 for Figure 26 A schematic diagram of the active layer. Figure 25 for Figure 27 A schematic diagram of the first gate metal layer; Figure 25 for Figure 28 A schematic diagram of the second gate metal layer; Figure 25 for Figure 29 A schematic diagram of the first source / drain metal layer; Figure 25This is a schematic diagram showing the eight sub-pixel regions corresponding to the second source / drain metal layer when the display panel includes the second source / drain metal layer.

[0215] It needs to be explained, such as Figure 30 and Figure 30 As shown, the second source / drain metal layer may specifically include: a power compensation pattern 300 and a transition pattern 310; the power compensation pattern 300 includes a horizontal connecting portion 3001 and a vertical connecting portion 3002, and the power compensation pattern 300 is coupled to the power signal line pattern included in the display panel to reduce IR drop on the power signal line pattern; the transition pattern 310 corresponds one-to-one with the anodes included in the display panel, and the transition pattern 310 is used to connect the corresponding anode 320 and the sub-pixel driving circuit for providing a driving signal to the anode 320.

[0216] In a specific embodiment, refer to Figure 31 A second transition pattern 906 may also be provided between the transition pattern 310 and the anode included in the display panel, and the second transition pattern 906 is located in the first source / drain metal layer.

[0217] It should be noted that a passivation layer may also be provided on the first source / drain metal layer and / or the second source / drain metal layer, such as inorganic materials such as silicon nitride and silicon oxide. This embodiment does not limit this.

[0218] See also Figure 34 The display panel further includes a pixel defining layer, which forms pixel openings 330. Each pixel opening 330 corresponds to one of the anodes 320. Each pixel opening 330 is used to expose at least a portion of the corresponding anode 320. An organic light-emitting material layer included in the display panel is formed in each of the corresponding pixel openings 330.

[0219] It is worth noting that the display panel may include sub-pixels of multiple colors, and the light emitted by the light-emitting elements corresponding to the sub-pixels of different colors are different. For example, each pixel unit of the display panel includes one red sub-pixel R, two green sub-pixels G, and one blue sub-pixel B. Figures 30-32 and Figure 31 The diagram shows the layout of sub-pixel units of various colors within a single pixel unit, i.e., the GGRB pixel arrangement.

[0220] Of course, the pixel unit in the display panel can also include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. This type of pixel unit can specifically adopt a strip RGB arrangement, meaning the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B are arranged sequentially along the same direction (e.g., the X direction). Alternatively, this type of pixel unit can also specifically adopt a triangular RGB arrangement, such as the red sub-pixel R and the blue sub-pixel B being located in the same row along the X direction, and the green sub-pixel G being located in another row along the X direction.

[0221] like Figure 32 As shown, Figure 33 The corresponding Figure 33 The second gate metal layer and the second source / drain metal layer are included. In some embodiments, sub-pixels corresponding to different colors can be provided, and the overlapping area of ​​the orthographic projection of the transition pattern 310 on the substrate and the orthographic projection of the second plate Cst2 of the corresponding storage capacitor on the substrate are different.

[0222] For more details, see Figure 32 and Figure 32 For the red sub-pixel R, the orthographic projection of the transition pattern 310 onto the substrate and the orthographic projection of the second plate Cst2 of the corresponding storage capacitor onto the substrate form a first overlapping area J1. For the green sub-pixel G, the orthographic projection of the transition pattern 310 onto the substrate and the orthographic projection of the second plate Cst2 of the corresponding storage capacitor onto the substrate form a second overlapping area J2. For the blue sub-pixel B, the orthographic projection of the transition pattern 310 onto the substrate and the orthographic projection of the second plate Cst2 of the corresponding storage capacitor onto the substrate form a third overlapping area J3. The second overlapping area J2 is smaller than the first overlapping area J1, and the first overlapping area J1 is smaller than the third overlapping area J3.

[0223] The above configuration can better balance the RC loading on the power signal line pattern 901 corresponding to pixel units of different colors.

[0224] Please see Figure 33 , Figure 34 for Figure 34 Cross-sectional view along the C1C2 direction. Figure 32 Between the intermediate substrate 40 and the sixth drain formation region 106pd (i.e., the active layer in this region used to form the drain of the sixth transistor T6), there are also other film layers such as a buffer layer. Figure 34 Not shown in the image. Figure 34 The diagram also shows a first gate insulating layer 41, a second gate insulating layer 42, an interlayer insulating layer 43, a first planarization layer 44, and a second planarization layer 45.

[0225] like Figure 34 and Figure 15 As shown, in some embodiments, the functional film layer further includes a power signal line layer, the power signal line layer including a power signal line pattern 901 disposed in each of the sub-pixel regions, at least a portion of the power signal line pattern 901 extending along a second direction;

[0226] The functional film layer further includes an auxiliary power layer, which includes an auxiliary power pattern 60 disposed in each of the sub-pixel regions. The orthographic projection of the auxiliary power pattern 60 on the substrate overlaps with the orthographic projection of the power signal line pattern 901 located in the same sub-pixel region on the substrate. The auxiliary power pattern 60 and the power signal line pattern 901 are coupled in the overlapping region.

[0227] Specifically, the auxiliary power pattern 60 corresponds one-to-one with the sub-pixel area, and the auxiliary power pattern 60 is located in the corresponding sub-pixel area. For example, the auxiliary power pattern 60 can be disposed on the same layer and made of the same material as the second electrode plate of the storage capacitor, that is, it can be formed in the same patterning process.

[0228] When laying out the auxiliary power pattern 60, the orthographic projection of the auxiliary power pattern 60 on the substrate and the orthographic projection of the power signal line pattern 901 located in the same sub-pixel area on the substrate may overlap. The auxiliary power pattern 60 and the power signal line pattern 901 can be coupled through a via provided in the overlapping area.

[0229] By coupling the auxiliary power supply pattern 60 with the power signal line pattern 901, the RC (resistive-capacitive) loading on the power signal line pattern 901 is effectively reduced, as is the IR drop on the power signal line pattern 901, thereby better ensuring the stability of the display panel operation.

[0230] like Figure 21 and Figure 15 As shown, in some embodiments, the display panel further includes: a plurality of sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel areas, each of the sub-pixel driving circuits including a driving transistor and a second transistor;

[0231] The gate of the second transistor is coupled to the reset signal line pattern 905 in the adjacent previous sub-pixel region along the second direction. The first electrode of the second transistor serves as the target coupling portion in the previous sub-pixel region. The second electrode of the second transistor includes a coupled first electrode portion 51 and a second electrode portion 52. The first electrode portion 51 extends along the second direction, and the second electrode portion 52 extends along a third direction. The third direction intersects both the first direction and the second direction. The first electrode portion 51 is located between the semiconductor portion of the second transistor and the second electrode portion 52. The second electrode portion 52 is coupled to the gate of the driving transistor.

[0232] The orthographic projections of the first electrode portion 51 and the second electrode portion 52 on the substrate are both covered by the orthographic projections of the corresponding auxiliary power supply pattern 60 on the substrate.

[0233] Specifically, the second electrode of the second transistor is used to be coupled to the gate of the driving transistor. For example, the second electrode may specifically include: a first electrode portion 51 and a second electrode portion 52 coupled together. The first electrode portion 51 is located between the semiconductor portion of the second transistor and the second electrode portion 52, and the second electrode portion 52 is coupled to the gate of the driving transistor.

[0234] The specific layout of the first electrode portion 51 and the second electrode portion 52 can vary. For example, the first electrode portion 51 extends along a second direction, and the second electrode portion 52 extends along a third direction, which intersects both the first and second directions. By setting the orthographic projections of the first electrode portion 51 and the second electrode portion 52 on the substrate to be covered by the orthographic projection of the corresponding auxiliary power supply pattern 60 on the substrate, the potential stability of the N1 node is well guaranteed, and the layout space required by the second electrode of the second transistor and the power signal line pattern 901 is effectively reduced, thereby significantly reducing the pixel structure and making it more conducive to the development of high resolution of the display panel.

[0235] like Figure 19 and Figure 15 As shown, in some embodiments, the auxiliary power supply pattern 60 includes a first auxiliary sub-pattern 601 and a second auxiliary sub-pattern 602 coupled together, the first auxiliary sub-pattern 601 extending along a second direction, and at least a portion of the second auxiliary sub-pattern 602 extending along the first direction; the orthographic projection of the first auxiliary sub-pattern 601 on the substrate covers the orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate.

[0236] Specifically, the auxiliary power supply pattern 60 has various specific structures. For example, the auxiliary power supply pattern 60 includes a first auxiliary sub-pattern 601 and a second auxiliary sub-pattern 602 coupled to each other, and the first auxiliary sub-pattern 601 and the second auxiliary sub-pattern 602 can be formed into an integral structure.

[0237] For example, the first auxiliary sub-pattern 601 extends along a second direction, and at least a portion of the second auxiliary sub-pattern 602 extends along the first direction, such that the auxiliary power supply pattern 60 is formed in an L-shaped manner.

[0238] Since the auxiliary power pattern 60 is coupled to the power signal line pattern 901, the auxiliary power pattern 60 has a stable potential. The above-mentioned arrangement, where the orthographic projection of the first auxiliary sub-pattern 601 on the substrate covers the orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate, not only ensures the potential stability of the N1 node, but also effectively reduces the layout space required by the second electrode of the second transistor, the power signal line pattern 901, and the auxiliary power pattern 60, thereby greatly reducing the pixel structure and making it more conducive to the development of high resolution of the display panel.

[0239] In some embodiments, along the first direction, the width of the first auxiliary sub-pattern 601 is greater than the width of the corresponding power signal line pattern 901.

[0240] The width of the first auxiliary sub-pattern 601 is greater than the width of the corresponding power signal line pattern 901, so that the auxiliary power pattern 60 has a larger area. This not only helps to reduce the IR drop of the power signal line pattern 901, but also makes it easier to achieve the coupling between the auxiliary power pattern 60 and the power signal line pattern 901.

[0241] like Figure 21 , Figure 15 and Figure 19 As shown, in some embodiments, the orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate are both covered by the orthographic projection of the corresponding power signal line pattern 901 on the substrate.

[0242] The above-mentioned arrangement ensures that the orthographic projections of the first electrode portion 51 and the second electrode portion 52 on the substrate are both covered by the orthographic projections of the corresponding power signal line pattern 901 on the substrate. This not only effectively ensures the potential stability of the N1 node, but also effectively reduces the layout space required by the second electrode of the second transistor and the power signal line pattern 901, thereby significantly reducing the pixel structure and making it more conducive to the high-resolution development of the display panel.

[0243] In some embodiments, the functional film layer includes: a gate line pattern 902 and a light emission control signal line pattern 903 located in each sub-pixel region; in the same sub-pixel region, along a second direction, the gate line pattern 902, the light emission control signal line pattern 903, the reset signal line pattern 905, and the initialization signal line pattern 904 are arranged sequentially; the functional film layer also includes a power signal line pattern 901 and a data line pattern 908 located in each sub-pixel region, wherein both the power signal line pattern 901 and the data line pattern 908 include a portion extending along the second direction.

[0244] The display panel further includes: light-emitting elements corresponding one-to-one with the plurality of sub-pixel areas; and sub-pixel driving circuits corresponding one-to-one with the plurality of sub-pixel areas, each sub-pixel driving circuit including: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor.

[0245] In the same sub-pixel region, the gate of the driving transistor is coupled to the second terminal of the first transistor, the first terminal of the driving transistor is coupled to the second terminal of the fifth transistor, and the second terminal of the driving transistor is coupled to the first terminal of the first transistor; the gate of the first transistor is coupled to the gate line pattern 902.

[0246] The gate of the second transistor is coupled to the reset signal line pattern 905 in the previous sub-pixel region adjacent to the second direction, the first electrode of the second transistor serves as the target coupling portion in the previous sub-pixel region, and the second electrode of the second transistor is coupled to the gate of the driving transistor.

[0247] The gate of the fourth transistor is coupled to the gate line pattern 902, the first terminal of the fourth transistor is coupled to the data line pattern 908, and the second terminal of the fourth transistor is coupled to the first terminal of the driving transistor.

[0248] The gate of the fifth transistor is coupled to the light-emitting control signal line pattern 903, and the first terminal of the fifth transistor is coupled to the power signal line pattern 901.

[0249] The gate of the sixth transistor is coupled to the light-emitting control signal line pattern 903, the first terminal of the sixth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth transistor is coupled to the corresponding light-emitting element.

[0250] The second terminal of the seventh transistor is coupled to the light-emitting element, the gate of the seventh transistor is coupled to the reset signal line pattern 905, and the first terminal of the seventh transistor is coupled to the second initialization signal line pattern 904.

[0251] For example, each of the sub-pixel driving circuits includes seven thin-film transistors and one capacitor. Each transistor in the sub-pixel driving circuit is a P-type transistor. The driving transistor is the third transistor. The first electrode of each transistor is the source, and the second electrode of each transistor is the drain.

[0252] like Figure 22 , Figure 6 , Figure 15 Figures 19-22 As shown, the first transistor T1 has a dual-gate structure. The gate 201g of the first transistor T1 is coupled to the gate line pattern 902. The source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3 (i.e., the driving transistor). The drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0253] The second transistor T2 has a dual-gate structure. The gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the adjacent previous sub-pixel region along the second direction. The source S2 of the second transistor T2 serves as the target coupling portion in the previous sub-pixel region and is coupled to the initialization signal line pattern 904' in the previous sub-pixel region. The drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0254] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0255] The gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power supply signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0256] The gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the corresponding light-emitting element EL.

[0257] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905, the drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element EL, and the source S7 of the seventh transistor T7 is coupled to the initialization signal line pattern 904.

[0258] The pixel driving circuit also includes a storage capacitor Cst, the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.

[0259] The sub-pixel driving circuit provided in the above embodiments not only avoids the problem of the via being misaligned onto the nearby reset signal line pattern 905 during the drilling process due to process fluctuations, thus causing signal interference, but also better ensures the yield of the display panel; moreover, the pixel structure size using this sub-pixel driving circuit is smaller, which is more conducive to the display panel achieving high resolution.

[0260] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0261] In the display panel provided by the above-disclosed embodiments, the initialization signal line pattern 904 is provided with a first protruding portion 9042 on the side facing away from the reset signal line pattern 905, and the first end portion 9091 of the conductive connection portion pattern 909 is provided with a projection on the substrate, which has a first overlapping area F1 with the projection of the first protruding portion 9042 on the substrate. The first end portion 9091 and the first protruding portion 9042 can be coupled by drilling holes in the first overlapping area F1. This arrangement makes the vias used to couple the conductive connection portion and the initialization signal line pattern 904 have a greater distance from the reset signal line pattern 905, thereby avoiding the problem that the vias are easily misaligned onto the nearby reset signal line pattern 905 during the drilling process due to process fluctuations, resulting in signal interference. This better ensures the yield of the display panel.

[0262] Furthermore, since the initialization signal line pattern 904 includes a first protrusion 9042 on the side facing away from the reset signal line pattern 905, and a via for coupling the conductive connection portion and the initialization signal line pattern 904 is formed on the first protrusion 9042, the orthographic projection of the via on the substrate can be wrapped by the orthographic projection of the initialization signal line pattern 904 on the substrate. This greatly improves the reliability of the coupling between the initialization signal line pattern 904 and the conductive connection portion pattern 909, and better ensures the stability of the display panel during operation.

[0263] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0264] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer.

[0265] This disclosure also provides a method for manufacturing a display panel, used to manufacture the display panel provided in the above embodiments, the method comprising:

[0266] A functional film layer is fabricated on the substrate, forming multiple sub-pixel regions arranged in an array;

[0267] The functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;

[0268] The reset signal line layer includes: a reset signal line pattern 905 disposed in each of the sub-pixel areas, the reset signal line pattern 905 extending along a first direction;

[0269] The initialization signal line layer includes: an initialization signal line pattern 904 disposed in each of the sub-pixel areas. The initialization signal line pattern 904 includes a first main body portion 9041 and a first protruding portion 9042 coupled together. The first main body portion 9041 extends along the first direction. In the same sub-pixel area, the orthographic projection of the first main body portion 9041 on the substrate is located between the orthographic projection of the first protruding portion 9042 on the substrate and the orthographic projection of the reset signal line pattern 905 on the substrate.

[0270] The conductive connection layer includes: a conductive connection pattern 909 disposed in each of the sub-pixel areas; in the same sub-pixel area, the orthographic projection of the first end portion 9091 of the conductive connection pattern 909 on the substrate has a first overlapping area F1 with the orthographic projection of the first protrusion 9042 on the substrate; in the first overlapping area F1, the first end portion 9091 is coupled to the first protrusion 9042; the second end portion 9092 of the conductive connection pattern 909 is coupled to a target coupling portion in its sub-pixel area; and the orthographic projection of the reset signal line pattern 905 on the substrate is located between the orthographic projection of the target coupling portion on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.

[0271] Specifically, the array of multiple sub-pixel regions can be divided into multiple rows of sub-pixel regions arranged sequentially along a second direction, and multiple columns of sub-pixel regions arranged sequentially along a first direction. Each row of sub-pixel regions includes multiple sub-pixel regions spaced apart along the first direction, and each column of sub-pixel regions includes multiple sub-pixel regions spaced apart along the second direction. The first direction intersects the second direction; for example, the first direction includes the X direction, and the second direction includes the Y direction.

[0272] The reset signal line layer includes reset signal line patterns 905 disposed in each of the sub-pixel areas, and the reset signal line patterns 905 extend along the first direction. Each reset signal line pattern 905 corresponds to one of the sub-pixel areas, and the reset signal line patterns 905 located in the corresponding sub-pixel areas are electrically connected sequentially to form an integral structure.

[0273] The initialization signal line layer includes: initialization signal line patterns 904 disposed in each of the sub-pixel areas, each initialization signal line pattern 904 corresponding to a sub-pixel area, each initialization signal line pattern 904 located in the corresponding sub-pixel area, and each initialization signal line pattern 904 corresponding to a sub-pixel area in the same row being electrically connected in sequence to form an integral structure.

[0274] Each initialization signal line pattern 904 includes a first main body portion 9041 and a first protruding portion 9042 coupled together. The first main body portion 9041 extends along the first direction. The first main body portions 9041 of each initialization signal line pattern 904 located in the same row of sub-pixel areas are electrically connected in sequence to form an integral structure. It is worth noting that, considering manufacturing process errors, the first main body portion is not necessarily a straight line extending along the first direction.

[0275] The specific shape of the first protruding portion 9042 can vary, as long as it satisfies the requirement that the first protruding portion 9042 protrudes beyond the coupled first main body portion 9041 in the second direction. By setting it in the same sub-pixel area, the orthographic projection of the first main body portion 9041 on the substrate is located between the orthographic projection of the first protruding portion 9042 on the substrate and the orthographic projection of the reset signal line pattern 905 on the substrate, so that the first protruding portion 9042 can be positioned away from the reset signal line pattern 905, thereby allowing the first protruding portion 9042 to have a greater distance from the reset signal line pattern 905.

[0276] It should be noted that in an initialization signal line pattern 904, the first main body portion 9041 and the first protruding portion 9042 can be formed as an integral structure, but are not limited to this.

[0277] The conductive connection layer includes: a conductive connection pattern 909 disposed in each of the sub-pixel areas, wherein the conductive connection pattern 909 corresponds one-to-one with the sub-pixel areas and is located in the corresponding sub-pixel area.

[0278] The orthographic projection of the first end portion 9091 of the conductive connection pattern 909 onto the substrate has a first overlapping region F1 with the orthographic projection of the first protrusion 9042 onto the substrate. The first end portion 9091 and the first protrusion 9042 can be coupled by drilling a hole in the first overlapping region F1. The second end portion 9092 of the conductive connection pattern 909 is coupled to a target coupling portion in its sub-pixel region. The target coupling portion may include the first electrode of the seventh transistor corresponding to the current sub-pixel region and the first electrode of the second transistor corresponding to the next sub-pixel region adjacent to the current sub-pixel region along the second direction.

[0279] The target coupling portion can be positioned in various ways. For example, it can be positioned in the same sub-pixel area, with the orthographic projection of the reset signal line pattern 905 on the substrate located between the orthographic projection of the target coupling portion on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.

[0280] It should be noted that the display panel further includes an interlayer dielectric layer (i.e., the previously mentioned second interlayer insulating layer ILD). This interlayer dielectric layer is located between the second gate metal layer and the first source / drain metal layer in the display panel. The initialization signal line pattern 904 can be disposed on the same layer as the second gate metal layer and can be formed in the same patterning process. The conductive connection pattern 909 can be disposed on the same layer as the first source / drain metal layer and can be formed in the same patterning process. The aforementioned via is drilled in the first overlapping region F1 to couple the first end 9091 of the conductive connection pattern 909 with the first protruding portion 9042. The via is a through-hole that penetrates the ILD layer, and the distance between this via and the reset signal line pattern 905 is greater.

[0281] In the display panel manufactured using the method provided in this embodiment, the initialization signal line pattern 904 includes a first protruding portion 9042 on the side facing away from the reset signal line pattern 905, and the first end portion 9091 of the conductive connection portion pattern 909 has a first overlapping area F1 with the first protruding portion 9042 on the substrate. The first end portion 9091 and the first protruding portion 9042 can be coupled by drilling holes in the first overlapping area F1. This arrangement ensures that the vias used to couple the conductive connection portion and the initialization signal line pattern 904 are far apart from the reset signal line pattern 905, thereby avoiding the problem that the vias are easily misaligned onto the nearby reset signal line pattern 905 during the drilling process due to process fluctuations, leading to signal interference. This better ensures the yield of the display panel.

[0282] Furthermore, since the initialization signal line pattern 904 includes a first protrusion 9042 on the side facing away from the reset signal line pattern 905, and a via for coupling the conductive connection portion and the initialization signal line pattern 904 is formed on the first protrusion 9042, the orthographic projection of the via on the substrate can be wrapped by the orthographic projection of the initialization signal line pattern 904 on the substrate. This greatly improves the reliability of the coupling between the initialization signal line pattern 904 and the conductive connection portion pattern 909, and better ensures the stability of the display panel during operation.

[0283] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0284] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0285] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0286] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0287] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: A substrate, a functional film layer disposed on the substrate; Further comprising a plurality of sub-pixel regions arranged in an array; The functional film layer comprises: a reset signal line layer, an initialization signal line layer, and a conductive connection portion layer; The reset signal line layer comprises: a reset signal line pattern disposed in each of the sub-pixel regions, the reset signal line pattern extending along a first direction; The initialization signal line layer comprises: an initialization signal line pattern disposed in each of the sub-pixel regions, the initialization signal line pattern comprising a first main body portion and a first protruding portion coupled to each other, the first main body portion extending along the first direction, and in the same sub-pixel region, a projection of the first main body portion on the substrate is located between a projection of the first protruding portion on the substrate and a projection of the reset signal line pattern on the substrate; The conductive connection portion layer comprises: a conductive connection portion pattern disposed in each of the sub-pixel regions, and in the same sub-pixel region, a projection of a first end portion of the conductive connection portion pattern on the substrate has a first overlapping area with a projection of the first protruding portion on the substrate, the first end portion is coupled to the first protruding portion in the first overlapping area, a second end portion of the conductive connection portion pattern is coupled to a target coupling portion in the sub-pixel region, and a projection of the reset signal line pattern on the substrate is located between a projection of the target coupling portion on the substrate and a projection of the initialization signal line pattern on the substrate; The display panel further comprises: a plurality of sub-pixel drive circuits corresponding to the plurality of sub-pixel regions one by one, each of the sub-pixel drive circuits comprising a second transistor; The second transistor comprises two semiconductor portions arranged at intervals along the first direction, and a first conductor portion connected to the two semiconductor portions respectively, and a projection of the first conductor portion on the substrate does not overlap with a projection of the first protruding portion on the substrate in a previous sub-pixel region adjacent along a second direction; Each of the initialization signal line patterns further comprises a second protruding portion coupled to the first main body portion, and in the same sub-pixel region, a projection of the second protruding portion on the substrate is located between a projection of the first main body portion on the substrate and a projection of the reset signal line pattern on the substrate, and a projection of the first conductor portion on the substrate overlaps with a projection of the second protruding portion on the substrate; In the same sub-pixel region, a projection of the first end portion of the conductive connection portion pattern on the substrate further forms a second overlapping area with a projection of the first main body portion of the initialization signal line pattern on the substrate; The functional film layer further comprises a first connection hole in each of the sub-pixel regions, and in the same sub-pixel region, a projection of the first connection hole on the substrate overlaps with the first overlapping area and the second overlapping area respectively, and the first end portion of the conductive connection portion pattern is coupled to the initialization signal line pattern through the first connection hole. In the first direction, the length of the second protruding portion is greater than the length of the first protruding portion; the orthographic projection of the first connecting hole on the substrate does not overlap with the orthographic projection of the second protruding portion on the substrate.

2. The display panel of claim 1, wherein, The display panel further comprises: a plurality of light emitting elements corresponding to the plurality of sub-pixel regions, the plurality of light emitting elements being located on a side of the functional film layer away from the substrate; a plurality of sub-pixel drive circuits corresponding to the plurality of sub-pixel regions, each of the sub-pixel drive circuits comprising a seventh transistor, a gate of the seventh transistor being coupled to the reset signal line pattern corresponding thereto, a first electrode of the seventh transistor serving as the target coupling portion, a second electrode of the seventh transistor extending in a second direction and being coupled to an anode of the light emitting element corresponding thereto; the conductive connection portion pattern further comprises a second main portion connected between the first end portion and the second end portion, the second main portion extending in the second direction; in the same sub-pixel region, in the first direction, the first end portion of the conductive connection portion pattern protrudes from the second main portion in a direction away from the second electrode of the seventh transistor.

3. The display panel of claim 2, wherein, the functional film layer further comprises a data line pattern in each sub-pixel region, the data line pattern comprising a portion extending in the second direction; the orthographic projection of the initialization signal line pattern on the substrate and the orthographic projection of the conductive connection portion pattern on the substrate have a third overlapping region; the orthographic projection of the initialization signal line pattern on the substrate and the orthographic projection of the data line pattern on the substrate have a fourth overlapping region; in the fourth overlapping region, the width of the initialization signal line pattern in the second direction is less than the width of the initialization signal line pattern in the second direction in the third overlapping region.

4. The display panel of claim 2, wherein, in the same sub-pixel region, the orthographic projection of the second main portion on the substrate and the orthographic projection of the second electrode of the seventh transistor on the substrate have a first gap, the first gap being greater than a threshold value.

5. The display panel of claim 1, wherein, each of the sub-pixel drive circuits comprises a drive transistor; a gate of the second transistor is coupled to the reset signal line pattern in the last sub-pixel region adjacent in the second direction, a first electrode of the second transistor serving as the target coupling portion in the last sub-pixel region, a second electrode of the second transistor being coupled to a gate of the drive transistor.

6. The display panel of claim 5, wherein, the orthographic projection of the first conductor portion on the substrate overlaps with the orthographic projection of the first end portion of the conductive connection portion pattern in the last sub-pixel region on the substrate.

7. The display panel of claim 5, wherein, the conductive connection portion pattern further comprises a second main portion connected between the first end portion and the second end portion, the second main portion extending in the second direction; one end of the first conductor portion close to the conductive connection portion pattern in the last sub-pixel region extends in the second direction, the orthographic projection of the one end on the substrate and the orthographic projection of the second main portion of the conductive connection portion pattern on the substrate have a second gap, the second gap being greater than a threshold value.

8. The display panel of claim 1, wherein, A projection of the first conductor portion of the second transistor on the substrate does not overlap with a projection of the first connection hole in the last sub-pixel region on the substrate.

9. The display panel of claim 5, wherein, The functional film layer further includes a power signal line layer, the power signal line layer includes a power signal line pattern arranged in each of the sub-pixel regions, at least part of the power signal line pattern extends along a second direction; An end of the first conductor portion away from the conductive connection part pattern in the last sub-pixel region extends along the second direction, a projection of the end on the substrate is completely covered by a projection of the power signal line pattern in the same sub-pixel region on the substrate.

10. The display panel of claim 1, wherein, The display panel further includes: A plurality of sub-pixel drive circuits corresponding to the plurality of sub-pixel regions, each of the sub-pixel drive circuits includes a drive transistor and a storage capacitor, the storage capacitor includes a first plate and a second plate arranged oppositely, the first plate is multiplexed as a gate electrode of the drive transistor, and the second plate is located on a side of the first plate away from the substrate; The functional film layer further includes a power signal line layer, the power signal line layer includes a power signal line pattern arranged in each of the sub-pixel regions, at least part of the power signal line pattern extends along a second direction, the power signal line pattern includes a first power supply part and a second power supply part; A projection of the first power supply part on the substrate overlaps with a projection of each of the reset signal line patterns in the same sub-pixel region on the substrate, and overlaps with a projection of each of the gate line patterns in the same sub-pixel region on the substrate; a projection of the second power supply part on the substrate overlaps with a projection of the second plate of the corresponding storage capacitor on the substrate; the width of the first power supply part along the first direction is less than the width of the second power supply part.

11. The display panel of claim 1, wherein, The functional film layer further includes a power signal line layer, the power signal line layer includes a power signal line pattern arranged in each of the sub-pixel regions, at least part of the power signal line pattern extends along a second direction; The functional film layer further includes an auxiliary power supply layer, the auxiliary power supply layer includes an auxiliary power supply pattern arranged in each of the sub-pixel regions, a projection of the auxiliary power supply pattern on the substrate overlaps with a projection of a power signal line pattern in the same sub-pixel region on the substrate, and the auxiliary power supply pattern and the power signal line pattern are coupled in the overlapping area.

12. The display panel of claim 11, wherein, The display panel further includes: a plurality of sub-pixel drive circuits corresponding to the plurality of sub-pixel regions, each of the sub-pixel drive circuits includes a drive transistor and a second transistor; The gate of the second transistor is coupled with the reset signal line pattern in the previous sub-pixel area adjacent to the second direction, the first electrode of the second transistor is the target coupling part in the previous sub-pixel area, the second electrode of the second transistor includes a first electrode part and a second electrode part coupled with each other, the first electrode part extends along the second direction, the second electrode part extends along a third direction intersecting with the first direction and the second direction, the first electrode part is between the semiconductor part of the second transistor and the second electrode part, and the second electrode part is coupled with the gate of the driving transistor; The orthographic projection of the first electrode part on the substrate and the orthographic projection of the second electrode part on the substrate are covered by the orthographic projection of the corresponding auxiliary power supply pattern on the substrate.

13. The display panel of claim 12, wherein, The auxiliary power supply pattern includes a first auxiliary sub-pattern and a second auxiliary sub-pattern coupled with each other, the first auxiliary sub-pattern extends along the second direction, and at least part of the second auxiliary sub-pattern extends along the first direction; The orthographic projection of the first auxiliary sub-pattern on the substrate covers the orthographic projection of the first electrode part on the substrate and the orthographic projection of the second electrode part on the substrate.

14. The display panel of claim 13, wherein, Along the first direction, the width of the first auxiliary sub-pattern is greater than the width of the corresponding power supply signal line pattern.

15. The display panel of claim 12, wherein, The orthographic projection of the first electrode part on the substrate and the orthographic projection of the second electrode part on the substrate are covered by the orthographic projection of the corresponding power supply signal line pattern on the substrate.

16. The display panel of claim 1, wherein, The functional film layer includes: a gate line pattern located in each sub-pixel area, a light-emitting control signal line pattern; in the same sub-pixel area, the gate line pattern, the light-emitting control signal line pattern, the initialization signal line pattern and the reset signal line pattern are arranged in sequence along the second direction; The functional film layer further includes a power supply signal line pattern and a data line pattern located in each sub-pixel area, and the power supply signal line pattern and the data line pattern each include a part extending along the second direction; The display panel further includes: A light-emitting element corresponding to each of the plurality of sub-pixel areas; A sub-pixel drive circuit corresponding to each of the plurality of sub-pixel areas, each sub-pixel drive circuit including: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; In the same sub-pixel area, the gate of the driving transistor is coupled with the second electrode of the first transistor, the first electrode of the driving transistor is coupled with the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled with the first electrode of the first transistor; The gate of the first transistor is coupled with the gate line pattern; The gate of the second transistor is coupled with the reset signal line pattern in the previous sub-pixel area adjacent to the second direction, the first electrode of the second transistor is the target coupling part in the previous sub-pixel area, and the second electrode of the second transistor is coupled with the gate of the driving transistor; a gate of the fourth transistor is coupled with the gate line pattern, a first electrode of the fourth transistor is coupled with the data line pattern, and a second electrode of the fourth transistor is coupled with the first electrode of the driving transistor; a gate of the fifth transistor is coupled with the light-emitting control signal line pattern, and a first electrode of the fifth transistor is coupled with the power signal line pattern; a gate of the sixth transistor is coupled with the light-emitting control signal line pattern, a first electrode of the sixth transistor is coupled with the second electrode of the driving transistor, and a second electrode of the sixth transistor is coupled with the light-emitting element; a second electrode of the seventh transistor is coupled with the light-emitting element, a gate of the seventh transistor is coupled with the reset signal line pattern, and a first electrode of the seventh transistor is coupled with the second initialization signal line pattern.

17. A display device, comprising the display panel according to any one of claims 1-16.

18. A manufacturing method of a display panel, comprising: manufacturing a functional film layer on a substrate, and forming a plurality of sub-pixel regions arranged in an array; the functional film layer comprises a reset signal line layer, an initialization signal line layer, and a conductive connection portion layer; the reset signal line layer comprises a reset signal line pattern arranged in each of the sub-pixel regions, and the reset signal line pattern extends along a first direction; the initialization signal line layer comprises an initialization signal line pattern arranged in each of the sub-pixel regions, and the initialization signal line pattern comprises a first main body portion and a first protruding portion coupled with each other, the first main body portion extends along the first direction, and in the same sub-pixel region, a projection of the first main body portion on the substrate is located between a projection of the first protruding portion on the substrate and a projection of the reset signal line pattern on the substrate; the conductive connection portion layer comprises a conductive connection portion pattern arranged in each of the sub-pixel regions, and in the same sub-pixel region, a first end portion of the conductive connection portion pattern has a first overlapping area with a projection of the first protruding portion on the substrate, the first end portion is coupled with the first protruding portion in the first overlapping area, a second end portion of the conductive connection portion pattern is coupled with a target coupling portion in the sub-pixel region, and a projection of the reset signal line pattern on the substrate is located between a projection of the target coupling portion on the substrate and a projection of the initialization signal line pattern on the substrate; the display panel further comprises a plurality of sub-pixel driving circuits corresponding to the plurality of sub-pixel regions one by one, and each of the sub-pixel driving circuits comprises a second transistor; the second transistor comprises two semiconductor portions arranged at intervals along the first direction, and a first conductor portion connected with the two semiconductor portions respectively, and a projection of the first conductor portion on the substrate does not overlap with a projection of the first protruding portion on the substrate in a previous sub-pixel region adjacent along a second direction. Each of the initialization signal line patterns further comprises a second protruding portion coupled with the first body portion, in the same sub-pixel region, a projection of the second protruding portion on the substrate is located between a projection of the first body portion on the substrate and a projection of the reset signal line pattern on the substrate, and a projection of the first conductor portion on the substrate overlaps with a projection of the second protruding portion on the substrate; In the same sub-pixel region, a projection of the first end portion of the conductive connection portion pattern on the substrate further forms a second overlapping area with a projection of the first body portion of the initialization signal line pattern on the substrate; The functional film layer further comprises a first connection hole in each of the sub-pixel regions, in the same sub-pixel region, a projection of the first connection hole on the substrate respectively overlaps with the first overlapping area and the second overlapping area, and the first end portion of the conductive connection portion pattern is coupled with the initialization signal line pattern through the first connection hole; In the first direction, a length of the second protruding portion is greater than a length of the first protruding portion, and a projection of the first connection hole on the substrate does not overlap with a projection of the second protruding portion on the substrate.

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