Display substrate and display device

Abstract

The display substrate and display device provided by the embodiments of the present disclosure include: a base substrate, multiple sub-pixels, multiple data lines, multiple power lines, multiple data signal input lines, multiple selection switches, a first power bus located in the peripheral area and on the side of the multiple selection switches away from the display area; multiple power connection lines located in the peripheral area and between the first power bus and the multiple power lines; wherein the multiple power connection lines electrically connect the first power bus and the multiple power lines.

Description

Technical Field

[0001] The present disclosure relates to the field of display, and in particular to a display substrate and a display device. Background Art

[0002] With the advancement of smart display technology, organic light emitting diode (OLED) displays have become one of the hot topics in the field of display research. More and more active matrix organic light emitting diode (AMOLED) display substrates have entered the market. Compared with traditional thin film transistor liquid crystal display (TFT-LCD) substrates, AMOLED displays have faster response speed and higher contrast. Summary of the Invention

[0003] The display substrate provided in the embodiment of the present disclosure includes:

[0004] A base substrate, comprising a display area and a peripheral area located on at least one side of the display area;

[0005] A plurality of sub-pixels are located in the display area;

[0006] a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels;

[0007] a plurality of power lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of power lines being configured to provide power signals to the plurality of sub-pixels;

[0008] a plurality of data signal input lines, located in the peripheral area;

[0009] a plurality of selection switches located in the peripheral area and between the plurality of data lines and the plurality of data signal input lines; wherein at least one selection switch among the plurality of selection switches is electrically connected to at least two of the plurality of data lines and one of the plurality of data signal input lines;

[0010] a first power bus located in the peripheral area and on a side of the plurality of selection switches away from the display area;

[0011] A plurality of power connection lines are located in the peripheral area and between the first power bus and the plurality of power lines; wherein the plurality of power connection lines electrically connect the first power bus and the plurality of power lines.

[0012] Optionally, in an embodiment of the present invention, an orthographic projection of at least one of the plurality of power connection lines on the base substrate at least partially overlaps with an orthographic projection of at least one of the plurality of selection switches on the base substrate.

[0013] Optionally, in an embodiment of the present invention, the plurality of power connection lines correspond one-to-one to the plurality of selection switches, and an orthographic projection of each power line on the base substrate at least partially overlaps with an orthographic projection of a corresponding selection switch on the base substrate.

[0014] Optionally, in an embodiment of the present invention, at least one selection switch among the plurality of selection switches includes at least two thin film transistors; the at least two thin film transistors include: a gate, and at least one source and at least two drains located on a side of the gate facing away from the substrate;

[0015] An orthographic projection of the power connection line on the base substrate at least partially overlaps with an orthographic projection of one of the source electrode and the drain electrode on the base substrate.

[0016] Optionally, in an embodiment of the present invention, an orthographic projection of the power connection line on the base substrate does not overlap with an orthographic projection of the gate on the base substrate.

[0017] Optionally, in an embodiment of the present invention, each of the selection switches includes two thin film transistors;

[0018] The two thin film transistors include:

[0019] a first active layer located on the substrate;

[0020] A first gate and a second gate located on a side of the first active layer away from the base substrate; wherein the first gate and the second gate are located in the same layer and do not overlap;

[0021] a first source electrode, a first drain electrode, and a second drain electrode located on a side of the first gate electrode and the second gate electrode away from the substrate; wherein the first source electrode, the first drain electrode, and the second drain electrode are located on the same layer and do not overlap, and the first source electrode is located between the first drain electrode and the second drain electrode;

[0022] The first source is electrically connected to one of the plurality of data signal input lines, and the first drain and the second drain are electrically connected to two of the plurality of data lines;

[0023] The orthographic projection of the power connection line on the base substrate covers the orthographic projection of the first source electrode on the base substrate;

[0024] The orthographic projection of the power connection line on the base substrate does not overlap with the orthographic projection of the first gate and the second gate on the base substrate.

[0025] Optionally, in an embodiment of the present invention, the power connection line has a first width in a direction perpendicular to the extension direction of the data line, the first source electrode has a second width in a direction perpendicular to the extension direction of the data line, and the first width is substantially the same as the second width.

[0026] Optionally, in an embodiment of the present invention, the orthographic projections of the plurality of power connection lines on the base substrate are located within gaps between the plurality of selection switches.

[0027] Optionally, in an embodiment of the present invention, the power connection line has a third width in a direction perpendicular to an extension direction of the data line, the gap has a fourth width in a direction perpendicular to an extension direction of the data line, and the third width is smaller than the fourth width.

[0028] Optionally, in an embodiment of the present invention, the device further comprises: a second power bus located between the plurality of selection switches and the plurality of power lines; the second power bus is electrically connected to the plurality of power lines;

[0029] The plurality of power connection lines electrically connect the first power bus and the second power bus.

[0030] Optionally, in the embodiment of the present invention, the device further comprises: a third power bus located in the peripheral area;

[0031] The orthographic projection of the third power bus on the base substrate at least partially overlaps with the orthographic projection of the first power bus on the base substrate, and the third power bus is electrically connected to the first power bus.

[0032] Optionally, in an embodiment of the present invention, at least one of the plurality of sub-pixels includes a driving thin film transistor, a connecting electrode, and a storage capacitor;

[0033] The driving thin film transistor includes a driving active layer located on the base substrate, a driving gate located on a side of the driving active layer away from the base substrate, a gate insulating layer located on a side of the driving gate away from the base substrate, an interlayer dielectric layer located on a side of the gate insulating layer away from the base substrate, and a driving source electrode and a driving drain electrode located on a side of the interlayer dielectric layer away from the base substrate;

[0034] The connecting electrode is located on a side of the driving source electrode and the driving drain electrode away from the base substrate;

[0035] The storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the driving gate are located in the same layer, and the second capacitor electrode is located between the gate insulation layer and the interlayer dielectric layer;

[0036] At least one of the power connection line, the first power bus, and the data line is located in the same layer as the connection electrode.

[0037] Optionally, in an embodiment of the present invention, at least one of the power line, the second power bus, and the third power bus is located on the same layer as the driving source and the driving drain;

[0038] The data signal input line and the second capacitor electrode are located in the same layer.

[0039] Optionally, in an embodiment of the present invention, the driving active layer and the first active layer are located in the same layer;

[0040] The first gate, the second gate and the driving gate are located on the same layer;

[0041] The first source electrode, the first drain electrode, the second drain electrode, and the driving source electrode and the driving drain electrode are located in the same layer.

[0042] Optionally, in an embodiment of the present invention, an orthographic projection of the first power bus on the base substrate and an orthographic projection of the data signal input line on the base substrate at least partially overlap.

[0043] Optionally, in an embodiment of the present invention, the first power bus includes a plurality of openings arranged at intervals; the orthographic projections of the openings on the base substrate overlap with the orthographic projections of the data signal input lines on the base substrate.

[0044] Optionally, in an embodiment of the present invention, the plurality of openings are divided into a plurality of opening groups arranged along the second direction; wherein each of the opening groups includes a plurality of openings arranged along the first direction, and the first direction and the second direction intersect;

[0045] The openings in at least two adjacent opening groups are arranged in a staggered manner.

[0046] Optionally, in an embodiment of the present invention, the plurality of data signal input lines include a first data signal input line and a second data signal input line;

[0047] The first data signal input lines and the second data signal input lines are alternately arranged along a first direction;

[0048] The first data signal input line and the driving gate are located on the same layer;

[0049] The second data signal input line and the second capacitor electrode are located in the same layer.

[0050] Optionally, in an embodiment of the present invention, at least one of the plurality of sub-pixels further includes: a light emitting diode located on a side of the connecting electrode away from the base substrate, and the driving drain, the connecting electrode and the light emitting diode are electrically connected in sequence.

[0051] The display device in the embodiment of the present disclosure includes the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1a Schematic diagrams of the structures of some display substrates in related technologies;

[0053] Figure 1b Schematic diagrams of the structures of some display substrates in related technologies;

[0054] Figure 2 Schematic diagrams of the structures of other display substrates in related technologies;

[0055] Figure 3 Schematic diagrams of the structures of some display substrates in the embodiments of the present disclosure;

[0056] Figure 4a Schematic diagram of the structure of some selection switches in some display substrates in the embodiments of the present disclosure;

[0057] Figure 4b Schematic diagrams of the structures of some selection switches in some display substrates in the embodiments of the present disclosure;

[0058] Figure 5a for Figure 3 The cross-sectional structure diagram of the display substrate shown along the AA' direction;

[0059] Figure 5b for Figure 3 The cross-sectional structural diagram of the display substrate shown along the BB' direction;

[0060] Figure 5c for Figure 3 The cross-sectional structure diagram of the display substrate along the CC' direction is shown;

[0061] Figure 5d is a schematic cross-sectional structural diagram of a sub-pixel in an embodiment of the present disclosure;

[0062] Figure 6a Schematic diagrams of the structures of other display substrates in the embodiments of the present disclosure;

[0063] Figure 6b for Figure 6aThe cross-sectional structure diagram of the display substrate shown along the AA' direction;

[0064] Figure 7 Schematic diagrams of the structures of some further display substrates in the embodiments of the present disclosure;

[0065] Figure 8 Schematic diagrams of the structures of some further display substrates in the embodiments of the present disclosure;

[0066] Figure 9 Schematic diagrams of the structures of some further display substrates in the embodiments of the present disclosure;

[0067] Figure 10 Schematic diagrams of the structures of some further display substrates in the embodiments of the present disclosure;

[0068] Figure 11a Schematic diagrams of the structures of some further display substrates in the embodiments of the present disclosure;

[0069] Figure 11b Schematic diagrams of the structures of some further display substrates in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0071] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0072] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0073] Generally speaking, if Figure 1a and Figure 1b As shown, the display substrate includes a display area 1 and a peripheral area 2 surrounding the display area 1. A pixel array is arranged in the display area 1, and a circuit pattern is arranged in the peripheral area 2. The pixel array includes a plurality of sub-pixels and signal lines for the sub-pixels. These signal lines include, for example, gate lines, data lines, and power lines. Typically, one gate line is provided for each row of sub-pixels, and one or two data lines are provided for each column of sub-pixels. A circuit pattern for providing corresponding signals to the gate and data lines is provided in the peripheral area 2, such as a gate drive circuit (GOA circuit) that provides signals to the gate lines.

[0074] For example, a circuit pattern may be arranged in the lower frame region 3 of the peripheral area. For example, a narrow frame may be achieved by simplifying the design of the circuit pattern arranged in the lower frame region 3, thereby improving the screen ratio.

[0075] For example, multiplexing technology (MUX technology) can be used to simplify circuit layout. Multiplexing technology connects multiple data lines (for example, two) in the peripheral area to a selector switch. The selector switch transmits electrical signals to different data lines at different time periods, thereby reducing the number of wiring in the peripheral area and shrinking the space occupied by the circuit.

[0076] For example, in a display substrate, two data lines can be connected to a selection switch so that the two data lines share the same signal channel, that is, a MUX 1:2 (i.e., a two-to-one selection circuit) setting is adopted. This can reduce the number of some routing lines in the peripheral area 2 to half of the original number, thereby reducing the space occupied by the routing lines and ultimately achieving the purpose of reducing the border.

[0077] In some cases, in order to further improve the display effect of the display area and the overall aesthetics of the display substrate while achieving a narrow bezel, the bezel of the display substrate and the corners of the display area can be rounded. However, such a design will affect the circuit settings in the peripheral area.

[0078] At least one embodiment of the present disclosure provides a display substrate. Figure 2 is a schematic plan view of a display substrate in an embodiment of the present disclosure;

[0079] Figure 3 is a plan view schematically showing a specific structure of a display substrate in an embodiment of the present disclosure; Figure 4a Some structural diagrams of a selection switch 06; Figure 4b Schematic diagram of some structures of a selection switch 06; Figure 5a for Figure 3 A schematic cross-sectional structural diagram of the display substrate along the AA' direction is shown; Figure 5b for Figure 3 A schematic cross-sectional structural diagram of the display substrate along the BB' direction is shown; Figure 5c for Figure 3 FIG. 1 is a schematic cross-sectional structural diagram of a display substrate along the CC′ direction. Figure 5d Schematic diagram of the cross-sectional structure in a sub-pixel.

[0080] like Figures 3 to 5c As shown, the display substrate in the embodiment of the present disclosure may include:

[0081] The base substrate 01 includes a display area AA and a peripheral area BB located on at least one side of the display area AA. This embodiment is described by taking the peripheral area BB located around the display area AA as an example.

[0082] Multiple sub-pixels 02 are located in the display area AA, and the multiple sub-pixels 02 can emit light, thereby realizing a display function;

[0083] A plurality of data lines 03 are located in the display area AA and are electrically connected to the plurality of sub-pixels 02; wherein the plurality of data lines 03 are configured to provide data signals to the plurality of sub-pixels 02;

[0084] A plurality of power lines 04 are located in the display area AA and are electrically connected to the plurality of sub-pixels 02 ; wherein the plurality of power lines 04 are configured to provide power signals to the plurality of sub-pixels 02 ;

[0085] A plurality of data signal input lines 07 are located in the peripheral area BB;

[0086] A plurality of selection switches 06 are located in the peripheral area BB and arranged at intervals. The plurality of selection switches 06 are located between the plurality of data lines 03 and the plurality of data signal input lines 07. At least one selection switch 06 among the plurality of selection switches 06 is electrically connected to at least two data lines 03 among the plurality of data lines and one data signal input line among the plurality of data signal input lines 07. The plurality of selection switches 06 can selectively transmit data signals to the plurality of data lines 03. This embodiment is described by taking an example in which each selection switch 06 is connected to two data lines 03. Furthermore, the plurality of data signal input lines 07 are located on a side of the plurality of selection switches 06 away from the display area AA, and at least one of the plurality of selection switches 06 is electrically connected to one of the plurality of data signal input lines 07. This embodiment is described by taking an example in which each selection switch 06 is connected to one data signal input line.

[0087] The first power bus 08 is located in the peripheral area BB and on a side of the plurality of selection switches 06 away from the display area AA;

[0088] Multiple power connection lines 09 are located in the peripheral area BB and between the first power bus 08 and the multiple power lines 04. The multiple power connection lines 09 are electrically connected to the first power bus 08 and the multiple power lines 04. For example, the first power bus 08 can be connected to the sub-pixels 02 in the display area AA via the multiple power connection lines 09 and the multiple power lines 04 to provide power to the sub-pixels 02.

[0089] For example, Figure 2 As shown, a plurality of power connection lines 09A are located at the lower border CC of the peripheral area BB.

[0090] For example, Figure 3 As shown, multiple power connection lines 09 extend along the column direction F2 of the sub-pixels. Furthermore, in the extending direction of the edge of the display area AA adjacent to the multiple power connection lines 09, i.e., in the direction F1 in the figure, multiple selection switches 06 are arranged at intervals, and the multiple power connection lines 09 are also arranged at intervals.

[0091] In specific implementation, in the embodiment of the present invention, as Figure 3 As shown, the orthographic projection of at least one of the multiple power connection lines on the base substrate at least partially overlaps with the orthographic projection of at least one of the multiple selector switches on the base substrate. This reduces the space occupied by the power connection lines. This also reduces the space occupied by the lower border CC of the peripheral area BB, thereby achieving a narrow border.

[0092] The display substrate provided in the embodiment of the present disclosure can reduce the space occupied by the lower frame CC of the peripheral area BB by designing the circuit pattern of the peripheral area, for example, by designing the circuit pattern in the lower frame CC of the peripheral area BB, thereby achieving a narrow frame design.

[0093] In specific implementation, in the embodiment of the present invention, as Figures 3 to 5c As shown, multiple power connection lines can be aligned one-to-one with multiple selector switches, i.e., one power connection line 09 corresponds to one selector switch 06. This allows the orthographic projection of each of the multiple power connection lines on the substrate to at least partially overlap with the orthographic projection of the corresponding selector switch on the substrate. This reduces the space occupied by the power connection lines, thereby reducing the space occupied by the lower border CC of the peripheral area BB, thereby achieving a narrow border. Furthermore, multiple power connection lines 09 can be provided, which facilitates the transmission stability of the power signal.

[0094] In specific implementation, in the embodiment of the present invention, as Figures 3 to 5cAs shown, at least one of the plurality of selection switches includes at least two thin film transistors; wherein the at least two thin film transistors include: a gate electrode and at least one source electrode and at least two drain electrodes located on a side of the gate electrode facing away from the substrate. For example, Figure 3 As shown, each of the plurality of selection switches includes two thin film transistors. Alternatively, each of the plurality of selection switches includes three thin film transistors. Alternatively, each of the plurality of selection switches includes six thin film transistors, which is not limited here.

[0095] In a specific implementation, in an embodiment of the present invention, the orthographic projection of the power connection line on the substrate at least partially overlaps with the orthographic projection of one of the source and drain on the substrate. Figures 3 to 5c As shown, the orthographic projection of the power connection line 09 on the substrate 01 at least partially overlaps with the orthographic projection of a source electrode (eg 064 ) on the substrate 01 .

[0096] In specific implementation, in the embodiment of the present invention, as Figures 3 to 5c As shown, the orthographic projection of the power connection line 09 on the substrate 01 does not overlap with the orthographic projection of the gate (such as 062, 063) on the substrate 01. Normally, when the gate of the thin film transistor is loaded with a turn-on signal, the thin film transistor can be controlled to be turned on so that the source and drain of the thin film transistor form a signal flow path. The embodiment of the present disclosure makes the orthographic projection of the power connection line on the substrate substrate and the orthographic projection of the gate on the substrate substrate not overlap. In this way, it is possible to avoid the formation of parasitic capacitance between the power connection line and the gate of the thin film transistor, and avoid the adverse effects of the power connection line on the switching of the thin film transistor.

[0097] In specific implementation, in the embodiment of the present invention, as Figures 3 to 5c As shown, the selection switch 06 includes two thin film transistors, that is, the selection switch 06 having two thin film transistors includes:

[0098] A first active layer 061 located on the base substrate 01;

[0099] A first gate electrode 062 and a second gate electrode 063 are located on a side of the first active layer 061 away from the base substrate 01 . The first gate electrode 062 and the second gate electrode 063 are located in the same layer and do not overlap.

[0100] A first source electrode 064, a first drain electrode 065, and a second drain electrode 066 are located on a side of the first gate electrode 062 and the second gate electrode 063 away from the substrate 01. The first source electrode 064, the first drain electrode 065, and the second drain electrode 066 are located on the same layer and do not overlap. The first source electrode 064 is located between the first drain electrode 065 and the second drain electrode 066.

[0101] The first source electrode 064 is connected to one data signal input line 07 among the plurality of data signal input lines 07 , and the first drain electrode 065 and the second drain electrode 066 are electrically connected to two data lines 03 among the plurality of data lines 03 .

[0102] For example, Figure 4a As shown, the first active layer 061 can be an integrated structure. Alternatively, Figure 4b As shown, the first active layer 061 can also be divided into scattered parts to improve the heat dissipation effect.

[0103] Optionally, the orthographic projection of each of the first gate electrode 062 and the second gate electrode 063 on the substrate 01 does not overlap with the orthographic projections of the first source electrode 064, the first drain electrode 065, and the second drain electrode 066 on the substrate 01. For example, the orthographic projection of the first gate electrode 062 on the substrate 01 is located between the orthographic projections of the first drain electrode 065 and the first source electrode 064 on the substrate 01. The orthographic projection of the second gate electrode 063 on the substrate 01 is located between the orthographic projections of the first source electrode 064 and the second drain electrode 066 on the substrate 01.

[0104] In specific implementation, in the embodiment of the present invention, as Figures 3 to 5c As shown, the orthographic projection of the power connection line 09 on the base substrate 01 overlaps the orthographic projection of the first source electrode 064 on the base substrate 01. Furthermore, the orthographic projection of the power connection line 09 on the base substrate 01 does not overlap with the orthographic projections of the first gate electrode 062 and the second gate electrode 063 on the base substrate. Since the first source electrode is used for signal input, its impact on the conduction and cutoff of the thin-film transistor is relatively small. Therefore, while reducing the occupied area, the impact of the power connection line on the conduction and cutoff of the thin-film transistor can also be reduced.

[0105] In specific implementation, in the embodiment of the present invention, as Figure 3 and Figure 5a As shown, for the power connection line 09 and the first source electrode 064 whose orthographic projections overlap, the power connection line 09 has a first width W1 in the F1 direction, and the first source electrode 064 has a second width W2 in the F1 direction, and the first width W1 and the second width W2 are substantially the same. This allows the width of the power connection line to be designed based on the first source electrode, thereby reducing the design difficulty of the power connection line. Of course, the first width can also be smaller than the second width, and this is not limited here.

[0106] In specific implementation, in the embodiment of the present invention, as Figure 3 and 5bAs shown, the display substrate further includes a second power bus 010 located between the plurality of selection switches 06 and the plurality of power lines 04. The second power bus 010 is electrically connected to the plurality of power lines 04. Furthermore, the plurality of power connection lines 09 are electrically connected to the first power bus 08 and the second power bus 010. Therefore, the first power bus 08 can sequentially provide power signals to the plurality of power lines 04 via the plurality of power connection lines 09 and the second power bus 010.

[0107] For example, the orthographic projection of the second power bus 010 on the base substrate does not overlap with the orthographic projection of the multiple select switches 06 on the base substrate 01. The second power bus 010 can be located in the peripheral area, for example, between the multiple select switches 06 and the display area AA. Alternatively, the second power bus 010 can be located in the display area AA.

[0108] In specific implementation, in the embodiment of the present invention, as Figure 6a and Figure 6b As shown, the display substrate also includes a third power bus 012 located in the peripheral area; the orthographic projection of the third power bus 012 on the base substrate 01 at least partially overlaps with the orthographic projection of the first power bus 08 on the base substrate 01, and the third power bus 012 and the first power bus 08 are electrically connected via vias. Therefore, based on the multi-layer routing design, the parallel connection of power buses with the same width can reduce the resistance of the power buses, thereby reducing the voltage drop of the first power bus 08, thereby ensuring long-range uniformity of the display substrate.

[0109] In specific implementation, in the embodiment of the present invention, as Figure 3 As shown, the orthographic projection of the first power bus 08 on the base substrate 01 and the orthographic projection of the data signal input line 07 on the base substrate 01 at least partially overlap. For example, the orthographic projection of the first power bus 07 on the base substrate 01 and the orthographic projection of the data signal input line 07 on the base substrate 01 partially overlap.

[0110] In specific implementation, in the embodiment of the present invention, as Figure 3 and Figure 6a As shown, the signal source end of the display substrate (eg Figure 3Multiple signal input pads (DZ) in the circuit can input data signals to multiple selection switches 06 via multiple data signal input lines 07. When the signal source inputs a data signal to a selection switch 06 via each data signal input line 07, the data signal is input to the first source 064 of the selection switch. By coordinating the control signals provided by the first control line 014 and the second control line 015, the data signal on the first source 064 can be transmitted to two data lines 03 at different time periods. For example, an on signal can be first input to the first control line 014 to conduct the first source 064 and the first drain 065. At this time, the data signal on the first source 064 is transmitted to one data line 03 via the first drain 064. Subsequently, an on signal can be input to the second control line 015 to conduct the first source 064 and the second drain 066. At this time, the data signal on the first source 064 is transmitted to another data line 03 via the second drain 066. After a data signal is input to each data line 03, the sub-pixels connected to each data line 03 also receive the data signal. For example, after each sub-pixel 02 receives a power signal and a data signal, in conjunction with other electrical signals, the display substrate can display an image.

[0111] In specific implementation, in the embodiment of the present invention, as Figure 3 and Figure 6a As shown, at least one sub-pixel 02 (e.g., each sub-pixel 02) among the plurality of sub-pixels 02 may include a pixel driving circuit and a light-emitting diode. The pixel driving circuit includes a transistor and a capacitor, and generates an electrical signal through the interaction between the transistor and the capacitor. The generated electrical signal is input to the first electrode of the light-emitting diode. A corresponding voltage is applied to the second electrode of the light-emitting diode to drive the light-emitting diode to emit light.

[0112] For example, a 7T1C pixel circuit may be used as the pixel driving circuit, or a 2T1C pixel circuit may be used as the pixel driving circuit, which is not limited here.

[0113] In specific implementation, in the embodiment of the present invention, as Figures 3 to 5dAs shown, the pixel driving circuit may include a driving thin film transistor 021 and a connecting electrode 022 (the driving thin film transistor 021 and the connecting electrode 022 are used as examples for description). The driving thin film transistor 021 includes a driving active layer 0211 located on the base substrate 01, a driving gate 0212 located on the side of the driving active layer 0211 away from the base substrate 01, and a driving source 0213 and a driving drain 0214 located on the side of the driving gate 0212 away from the base substrate 01. The connecting electrode 022 is located on the side of the driving source 0213 and the driving drain 0214 away from the base substrate 01. Furthermore, a light-emitting diode 023 (comprising a first electrode 0231, a light-emitting layer 0232, and a second electrode 0233 arranged in sequence away from the base substrate 01) is located on the side of the connecting electrode 022 away from the base substrate 01, and the driving drain 0214, the connecting electrode 022, and the light-emitting diode 023 are connected in sequence. When a voltage is applied between the first electrode 0231 and the second electrode 0233, the light-emitting layer 0232 emits light. For example, the first electrode 0231 of the light-emitting diode 023 is electrically connected to the driving drain electrode 0214 via the connecting electrode 022, so that the driving thin film transistor can control the light-emitting state of the light-emitting diode 023.

[0114] Exemplarily, the material of the driving gate 0212 and the driving drain 0214 can be a conductive material. For example, the material of the conductive layer can include a metal material or alloy material such as aluminum, molybdenum, titanium, etc., or can also include a metal oxide such as indium tin oxide (ITO). The embodiments of the present disclosure do not limit the materials of the functional layers.

[0115] In specific implementation, in the embodiment of the present invention, as Figure 3 and Figure 5d As shown, sub-pixel 02 may further include: a buffer layer 024, a first gate insulating layer 025, a second gate insulating layer 026, an interlayer dielectric layer 027, a passivation layer 028, a first planarization layer 029, a second planarization layer 030, a pixel defining layer 031, a support layer 032, and an encapsulation layer 033, arranged in sequence away from base substrate 01. The aforementioned driving active layer 0211 is located between buffer layer 024 and first gate insulating layer 025; the driving gate 0212 is located between first gate insulating layer 025 and second gate insulating layer 026; the driving source electrode 0213 and the driving drain electrode 0214 are located between interlayer dielectric layer 027 and passivation layer 028; and the connecting electrode 022 is located between first planarization layer 029 and second planarization layer 030. The pixel defining layer 031 is configured to define a pixel region on base substrate 01, within which the aforementioned light-emitting diode 023 is located.

[0116] For example, pixel defining layer 031 includes a plurality of openings corresponding to the plurality of sub-pixels 02, and light-emitting diodes 023 are formed in the plurality of openings. For example, encapsulation layer 033 may include multiple encapsulation sublayers, such as three encapsulation sublayers shown in the figure. For example, the three encapsulation sublayers include a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked to enhance the encapsulation effect of encapsulation layer 033.

[0117] For example, the gate insulating layer (including the first gate insulating layer 025 and the second gate insulating layer 026), the interlayer dielectric layer 027, the buffer layer 024, the flat layer 028, the pixel defining layer 031, the support layer 032 and the encapsulation layer 033 are all formed of insulating materials. According to needs, organic insulating materials such as polyimide, resin materials, etc. can be selected, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. can be selected. The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0118] It should be noted that the buffer layer 024, the first gate insulating layer 025, the second gate insulating layer 026, the interlayer dielectric layer 027, the passivation layer 028, the first planarizing layer 029, and the second planarizing layer 030 in the display area AA can all be extended to the peripheral area BB, and the relative positional relationship of these film layers in the peripheral area BB is the same as that in the display area AA, and the embodiments of the present disclosure are not repeated here.

[0119] It should be noted that if Figure 5c As shown, the power line 04 is directly electrically connected to the second power bus 010. Furthermore, the first source electrode 064 is electrically connected to the first active layer 061 via a plurality of vias penetrating the first gate insulating layer 025, the second gate insulating layer 026, and the interlayer dielectric layer 027. Furthermore, the first source electrode 064 is electrically connected to the data signal input line 07 via a via penetrating the interlayer dielectric layer 027.

[0120] In addition, if Figure 3 and Figure 5d As shown, the sub-pixel 02 may further include: a storage capacitor 034, the storage capacitor 034 includes a first capacitor electrode 0341 and a second capacitor electrode 0342, the first capacitor electrode 0341 and the driving gate 0212 are located in the same layer, and the second capacitor electrode 0342 is located between the second gate insulating layer 026 and the interlayer dielectric layer 027.

[0121] For example, some structures in the display area AA of the display substrate may be located on the same layer as some structures in the peripheral area BB. These structures are explained below. It should be noted that in the embodiments of the present disclosure, multiple structures located on the same layer means that the multiple structures can be formed from the same material layer through a patterning process during the manufacturing process, thereby simplifying the manufacturing process of the display substrate.

[0122] For example, Figures 3 to 5d As shown, at least one of the power connection line 09, the first power bus 08, and the data line 03 can be located on the same layer as the connection electrode 022. For example, the power connection line 09 and the connection electrode 022 are located on the same layer. In this way, when preparing the connection electrode 022 in the display area AA, the power connection line 09 in the peripheral area BB can be prepared at the same time, simplifying the process of preparing the display substrate. Of course, the power connection line 09 and the connection electrode 022 do not need to be located on the same layer, and this embodiment of the present disclosure is not limited to this.

[0123] For example, Figures 3 to 5d As shown, the first power bus 08 and the connecting electrode 022 are located on the same layer. This allows the first power bus 08 in the peripheral area BB to be prepared simultaneously with the connecting electrode 022 in the display area AA, simplifying the process of manufacturing the display substrate. Of course, the first power bus 08 and the connecting electrode 022 may not be located on the same layer, and this is not limited in the present embodiment.

[0124] For example, Figures 3 to 5d As shown, the data line 03 and the connecting electrode 022 are located on the same layer. In this way, when preparing the connecting electrode 022 in the display area AA, the data line 03 can be prepared at the same time, simplifying the process of preparing the display substrate. Of course, the data line 03 and the connecting electrode 022 can also be located on different layers, and this embodiment of the disclosure is not limited to this.

[0125] For example, Figures 3 to 5d As shown, the power connection line 09, the first power bus 08, and the data line 03 are all located on the same layer as the connection electrode 022. In this way, when preparing the connection electrode 022 in the display area AA, the power connection line 09, the first power bus 08, and the data line 03 in the peripheral area BB can be prepared at the same time, simplifying the process of preparing the display substrate.

[0126] When the power connection line 09 and the first power bus 08 are located on the same layer, if the first power bus 08 is also located on the same layer as the connection electrode 022, then the power connection line 09 and the connection electrode 022 are also located on the same layer. However, the selection switch 06 is usually located on a different layer from the connection electrode 022. In this way, the power connection line 09 and the first power bus 08 are both located on a different layer from the selection switch 06, thereby further reducing the risk of short circuits between the power connection line 09, the first power bus 08, and the selection switch 06.

[0127] For example, Figures 3 to 6bAs shown, at least one of the power line 04, the second power bus 010, and the third power bus 012 can be located on the same layer as the driving source electrode 0213 and the driving drain electrode 0214. For example, the power line 04 can be located on the same layer as the driving source electrode 0213 and the driving drain electrode 0214. In this way, when the driving source electrode 0213 and the driving drain electrode 0214 in the display area AA are prepared, the power line 04 can be prepared at the same time, simplifying the process of preparing the display substrate.

[0128] For example, Figures 3 to 6b As shown, the second power bus 010 can be located on the same layer as the driving source electrode 0213 and the driving drain electrode 0214. This allows the second power bus 010 in the peripheral area BB to be prepared simultaneously with the driving source electrode 0213 and the driving drain electrode 0214 in the display area AA, simplifying the process of manufacturing the display substrate. Of course, the second power bus 010 and the driving source electrode 0213 and the driving drain electrode 0214 do not need to be located on the same layer, and this is not limited in the present embodiment.

[0129] For example, Figures 3 to 6b As shown, the third power bus 012 can be located on the same layer as the driving source electrode 0213 and the driving drain electrode 0214. This allows the third power bus 012 in the peripheral area BB to be prepared simultaneously with the driving source electrode 0213 and the driving drain electrode 0214 in the display area AA, simplifying the process of manufacturing the display substrate. Of course, the third power bus 012 and the driving source electrode 0213 and the driving drain electrode 0214 do not need to be located on the same layer, and this is not limited in the present embodiment.

[0130] For example, Figures 3 to 5d As shown, the data signal input line 07 can be located on the same layer as the second capacitor electrode 0342. In this way, when preparing the second capacitor electrode 0342 in the display area AA, the data signal input line 07 of the peripheral area BB can be prepared at the same time, which simplifies the process of preparing the display substrate. Of course, the data signal input line 07 and the second capacitor electrode 0342 may not be located on the same layer. For example, the data signal input line 07 may be partially located on the same layer as the drive gate, and the remaining part may be located on the same layer as the second capacitor electrode, and the two parts may be arranged alternately. This is not limited in the present embodiment.

[0131] By way of example, some structures of the thin-film transistor in the selection switch 06 may also be located on the same layer as some structures of the driving thin-film transistor in the pixel driving circuit. For example, the first active layer 061 and the driving active layer 0211 are located on the same layer, the first gate electrode 062, the second gate electrode 063 and the driving gate electrode 0212 are located on the same layer, and the first source electrode 064, the first drain electrode 065, the second drain electrode 066 and the driving source electrode 0213 are located on the same layer. Of course, the first active layer 061 and the driving active layer 0211 may not be located on the same layer, the first gate electrode 062 and the driving gate electrode 0212 may not be located on the same layer, and the first source electrode 064 and the driving source electrode 0213 may not be located on the same layer, and this is not limited in the present embodiment.

[0132] In specific implementation, in the embodiment of the present invention, the material of the first flat layer 029 can be an organic material. Since organic materials easily absorb water and oxygen, these water and oxygen may have an adverse effect on the remaining film layers. Based on this, in the embodiment of the present disclosure, Figure 6a and Figure 6b As shown, the first power bus 08 includes a plurality of spaced-apart openings KB. The orthographic projections of the openings KB on the base substrate 01 overlap with the orthographic projections of the data signal input lines 07 on the base substrate 01. This allows moisture and oxygen in the first planar layer 029 to be released through the openings KB, improving the reliability of the display substrate.

[0133] In specific implementation, in the embodiment of the present invention, as Figure 7 and Figure 8 As shown, the plurality of openings KB are divided into a plurality of opening groups ZB-k (1≤k≤K, k and K are both integers, K is the total number of opening groups, and Figure 7 Taking K=4 as an example); wherein, each opening group ZB-k (comprises a plurality of openings KB arranged along the first direction F1. In this way, by providing a plurality of dispersed openings KB, water and oxygen in the first flat layer 029 can be further released, thereby further improving the reliability of the display substrate.

[0134] In a specific implementation, in the embodiment of the present invention, the first direction F1 and the second direction F2 intersect. For example, the first direction F1 and the second direction F2 are perpendicular.

[0135] In specific implementation, in the embodiment of the present invention, as Figure 7As shown, the openings in at least two adjacent opening groups are arranged in a staggered manner. Exemplarily, the openings in each two adjacent opening groups can be arranged in a staggered manner. Taking four opening groups as an example, the display substrate has opening groups ZB-1, ZB-2, ZB-3, and ZB-4. Among them, the openings in opening group ZB-1 and opening group ZB-2 are arranged in a staggered manner, for example, the openings in opening group ZB-2 correspond to the gap positions between adjacent openings in opening group ZB-1. The openings in opening group ZB-2 and opening group ZB-3 are arranged in a staggered manner, for example, the openings in opening group ZB-2 correspond to the gap positions between adjacent openings in opening group ZB-3. The openings in opening group ZB-3 and opening group ZB-4 are arranged in a staggered manner, for example, the openings in opening group ZB-2 correspond to the gap positions between adjacent openings in opening group ZB-3.

[0136] In specific implementation, in the embodiment of the present invention, as Figure 8 As shown, multiple openings can also be arranged in an array, which can reduce the difficulty of designing the openings.

[0137] In specific implementation, in the embodiment of the present invention, as Figure 7 and Figure 8 As shown, the gaps between each two adjacent openings in each opening group can be made substantially equal. For example, the gaps between the centers of each two adjacent openings in each opening group can be made substantially equal.

[0138] It should be noted that in actual processes, due to limitations in process conditions or other factors, the equality of the above-mentioned features may not be completely equal and may have some deviations. Therefore, as long as the equality relationship between the above-mentioned features generally meets the above-mentioned conditions, it falls within the scope of protection of the present invention. For example, the above-mentioned equality can be equality that is allowed within the allowable error range.

[0139] The embodiments of the present invention provide some schematic diagrams of the structure of display substrates, such as Figure 9 As shown, the embodiment described above is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0140] In specific implementation, in the embodiment of the present invention, as Figure 9 As shown, the orthographic projections of the multiple power connection lines 09 on the base substrate 01 can be positioned within the gaps between the multiple selection switches 06 and within the orthographic projection of the base substrate 01. This ensures that the orthographic projections of the multiple power connection lines 09 on the base substrate 01 do not overlap with the orthographic projections of the multiple selection switches 06 on the base substrate 01. This reduces the degree of overlap between the first power bus and the selection switches, thereby reducing the parasitic capacitance formed by the first power bus and the selection switches, ensuring that both the first power bus and the selection switches can function normally.

[0141] For example, in an embodiment of the present invention, Figure 9 As shown, one power connection line is set corresponding to one gap.

[0142] In specific implementation, in the embodiment of the present invention, as Figure 10 As shown, for the power connection line and the gap whose orthographic projections overlap, the power connection line has a third width W3 in the F1 direction, and the gap has a fourth width W4 in the F1 direction, and the third width is smaller than the fourth width.

[0143] Furthermore, in the specific implementation, in the embodiment of the present invention, as Figure 10 As shown, the orthographic projections of some of the power connection lines 09 on the base substrate 01 can overlap the orthographic projections of the first source electrode 064 on the base substrate 01. The orthographic projections of the remaining power connection lines 09 on the base substrate 01 can be located in the gaps between the selection switches 06 and within the orthographic projections of the base substrate 01.

[0144] For example, the display substrate may be a self-luminous display substrate such as OLED or QLED (Quantum Dot Light Emitting Diodes) or a non-self-luminous display substrate such as LCD. The embodiments of the present disclosure do not limit the type of display substrate.

[0145] For example, when the display substrate is an OLED or QLED display substrate, the display substrate can be packaged to form a display device.

[0146] For example, when the display substrate is an LCD display substrate, the display substrate also includes an opposing substrate. The display substrate and the opposing substrate are arranged opposite each other, and liquid crystal material is injected between the display substrate and the opposing substrate, thereby forming an LCD display device. For example, the opposing substrate is a color filter substrate, which includes a color filter layer for generating monochromatic light and a black matrix layer for shielding light. The embodiments of the present disclosure do not specifically limit the structure of the display substrate.

[0147] The display substrate provided by the embodiment of the present disclosure may have, for example, special-shaped corners such as curved corners, and may also realize a narrow frame design to help achieve a high screen-to-body ratio, thereby having a better display effect.

[0148] The embodiments of the present invention provide some schematic diagrams of the structure of display substrates, such as Figure 11a and Figure 11b As shown, the embodiment described above is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0149] In specific implementation, in the embodiment of the present invention, as Figure 11a and Figure 11b As shown, the plurality of data signal input lines 07 may include a first data signal input line 071 and a second data signal input line 072, wherein the first data signal input lines 071 and the second data signal input lines 072 are alternately arranged along the first direction F1. This can reduce interference between devices on the same layer.

[0150] In specific implementation, in the embodiment of the present invention, as Figure 11a and Figure 11b As shown, the first data signal input line 071 and the driving gate can be located in the same layer, so that the first data signal input line 071 and the driving gate can be formed using the same patterning process.

[0151] In specific implementation, in the embodiment of the present invention, as Figure 11a and Figure 11b As shown, the second data signal input line 072 and the second capacitor electrode can be located in the same layer, so that the second data signal input line 072 and the second capacitor electrode can be formed using the same patterning process.

[0152] At least one embodiment of the present disclosure further provides a display device comprising the aforementioned display substrate. For example, the display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The embodiments of the present disclosure do not limit the specific form of the display device.

[0153] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0154] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display substrate, wherein: include: A base substrate, comprising a display area and a peripheral area located on at least one side of the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels; a plurality of power lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of power lines being configured to provide power signals to the plurality of sub-pixels; a plurality of data signal input lines, located in the peripheral area; a plurality of selection switches located in the peripheral area and between the plurality of data lines and the plurality of data signal input lines; wherein at least one selection switch among the plurality of selection switches is electrically connected to at least two of the plurality of data lines and one of the plurality of data signal input lines; a first power bus located in the peripheral area and on a side of the plurality of selection switches away from the display area; a plurality of power connection lines located in the peripheral area and between the first power bus and the plurality of power lines; Wherein, the plurality of power connection lines are electrically connected to the first power bus and the plurality of power lines; An orthographic projection of at least one of the plurality of power connection lines on the base substrate at least partially overlaps with an orthographic projection of at least one of the plurality of selection switches on the base substrate.

2. The display substrate according to claim 1, wherein The plurality of power connection lines correspond one-to-one to the plurality of selection switches, and an orthographic projection of each power line on the base substrate at least partially overlaps with an orthographic projection of a corresponding selection switch on the base substrate.

3. The display substrate according to claim 2, wherein: At least one selection switch among the plurality of selection switches includes at least two thin film transistors; The at least two thin film transistors include: a gate electrode, and at least one source electrode and at least two drain electrodes located on a side of the gate electrode facing away from the substrate; An orthographic projection of the power connection line on the base substrate at least partially overlaps with an orthographic projection of one of the source electrode and the drain electrode on the base substrate.

4. The display substrate according to claim 3, wherein: The orthographic projection of the power connection line on the base substrate does not overlap with the orthographic projection of the gate on the base substrate.

5. The display substrate according to claim 4, wherein: Each of the selection switches includes two thin film transistors; The two thin film transistors include: a first active layer located on the base substrate; A first gate and a second gate located on a side of the first active layer away from the base substrate; wherein the first gate and the second gate are located in the same layer and do not overlap; a first source electrode, a first drain electrode, and a second drain electrode located on a side of the first gate electrode and the second gate electrode away from the substrate; wherein the first source electrode, the first drain electrode, and the second drain electrode are located on the same layer and do not overlap, and the first source electrode is located between the first drain electrode and the second drain electrode; The first source is electrically connected to one of the plurality of data signal input lines, and the first drain and the second drain are electrically connected to two of the plurality of data lines; The orthographic projection of the power connection line on the base substrate covers the orthographic projection of the first source electrode on the base substrate; The orthographic projection of the power connection line on the base substrate does not overlap with the orthographic projection of the first gate and the second gate on the base substrate. The display substrate according to claim 5 , wherein: The power connection line has a first width in a direction perpendicular to an extension direction of the data line, the first source electrode has a second width in a direction perpendicular to an extension direction of the data line, and the first width is the same as the second width.

7. The display substrate according to any one of claims 1 to 6, wherein: The orthographic projections of the plurality of power connection lines on the base substrate are located within the gaps between the plurality of selection switches.

8. The display substrate according to claim 7, wherein: The power connection line has a third width in a direction perpendicular to an extension direction of the data line, the gap has a fourth width in a direction perpendicular to an extension direction of the data line, and the third width is smaller than the fourth width.

9. The display substrate according to any one of claims 1 to 6, wherein: Also includes: a second power bus located between the plurality of selector switches and the plurality of power lines; The second power bus is electrically connected to the plurality of power lines; The plurality of power connection lines electrically connect the first power bus and the second power bus.

10. The display substrate according to claim 9, wherein: Also includes: a third power bus located in the peripheral area; The orthographic projection of the third power bus on the base substrate at least partially overlaps with the orthographic projection of the first power bus on the base substrate, and the third power bus is electrically connected to the first power bus.

11. The display substrate according to claim 5, wherein: At least one of the plurality of sub-pixels comprises a driving thin film transistor, a connecting electrode and a storage capacitor; The driving thin film transistor includes a driving active layer located on the base substrate, a driving gate located on a side of the driving active layer away from the base substrate, a gate insulating layer located on a side of the driving gate away from the base substrate, an interlayer dielectric layer located on a side of the gate insulating layer away from the base substrate, and a driving source electrode and a driving drain electrode located on a side of the interlayer dielectric layer away from the base substrate; The connecting electrode is located on a side of the driving source electrode and the driving drain electrode away from the base substrate; The storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the driving gate are located in the same layer, and the second capacitor electrode is located between the gate insulation layer and the interlayer dielectric layer; At least one of the power connection line, the first power bus, and the data line is located in the same layer as the connection electrode.

12. The display substrate according to claim 11, wherein: At least one of the power line, the second power bus, and the third power bus is located on the same layer as the driving source electrode and the driving drain electrode; The data signal input line and the second capacitor electrode are located in the same layer.

13. The display substrate according to claim 12, wherein: The driving active layer and the first active layer are located on the same layer; The first gate, the second gate and the driving gate are located on the same layer; The first source electrode, the first drain electrode, the second drain electrode, and the driving source electrode and the driving drain electrode are located in the same layer.

14. The display substrate according to claim 13, wherein: The orthographic projection of the first power bus on the base substrate and the orthographic projection of the data signal input line on the base substrate at least partially overlap.

15. The display substrate according to claim 14, wherein: The first power bus includes a plurality of openings arranged at intervals; the orthographic projections of the openings on the base substrate overlap with the orthographic projections of the data signal input lines on the base substrate.

16. The display substrate according to claim 15, wherein: The plurality of openings are divided into a plurality of opening groups arranged along a second direction; wherein each of the opening groups includes a plurality of openings arranged along a first direction, and the first direction and the second direction intersect; The openings in at least two adjacent opening groups are arranged in a staggered manner.

17. The display substrate according to claim 11, wherein The plurality of data signal input lines include a first data signal input line and a second data signal input line; The first data signal input lines and the second data signal input lines are alternately arranged along a first direction; The first data signal input line and the driving gate are located in the same layer; The second data signal input line and the second capacitor electrode are located in the same layer.

18. The display substrate according to claim 11, wherein At least one of the plurality of sub-pixels further includes a light emitting diode located on a side of the connecting electrode away from the base substrate, and the driving drain, the connecting electrode and the light emitting diode are electrically connected in sequence.

19. A display device, wherein: The display substrate comprises any one of claims 1 to 18.

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