A memory control method, a control device, and a storage medium

Abstract

The embodiments of the present disclosure disclose a memory control method, a control device and a storage medium. Each memory string in a memory block includes a channel layer with an N-type doped region at the top. In a memory block, a bit line erase voltage is applied to a selected bit line and a forbidden erase voltage is applied to an unselected bit line, while a top select gate voltage lower than the bit line erase voltage is applied to a top select gate. When a word line erase voltage lower than the bit line erase voltage is applied to a corresponding word line connected to a memory string corresponding to the selected bit line and the unselected bit line, an erase operation can be performed on the memory string corresponding to the selected bit line. This way of selecting a memory string for erasing by a bit line eliminates data migration and potential data loss during the erasing process in units of memory blocks, effectively reduces the erasing time, greatly improves the erasing rate, and also reduces the programming and erasing times of the memory cells and the degradation of the memory cells.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to electronic devices, and more particularly, to a memory control method, a control device and a storage medium. BACKGROUND

[0002] With the development of 5G and big data, people have higher and higher requirements for storage capacity and storage speed. As the mainstream non-volatile memory, the current 3D NAND flash memory array mainly uses block as the unit for erasing. With the increasing density of storage units, the erasing speed will gradually slow down, affecting the use speed of NAND.

[0003] When block1 needs to be erased, an empty block needs to be selected as data migration in advance, and then block1 is erased. When the storage units of the block are more and more, this block erasing method with data migration will seriously affect the erasing speed, and the erasing time is long. Moreover, the whole block erasing method will make the erasing frequency of the storage unit very high, which will affect the data retention characteristics of the storage unit, and make the data easy to lose and the function of the storage unit to degrade. SUMMARY

[0004] Embodiments of the present disclosure aim to provide a memory control method, device and storage medium, which can realize data erasing of a storage string on a bit line in the same storage block.

[0005] In one aspect, the present disclosure provides a memory control method, each storage block of the memory comprising a plurality of storage strings, each of the storage strings comprising a channel layer having an N-type doped region at the top, the control method comprising:

[0006] The bit lines connected to the storage strings of the same storage block include selected bit lines and unselected bit lines, the selected bit lines are applied with a bit line erasing voltage, and the unselected bit lines are applied with a forbidden erasing voltage;

[0007] A top selection gate voltage is applied to the top selection gate, so as to form a potential difference between the top selection gate and the selected bit line to generate electron-hole pairs in the N-type doped region, wherein the top selection gate voltage is lower than the bit line erasing voltage, and higher than or equal to the forbidden erasing voltage;

[0008] A word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word lines of the storage strings connected to the selected bit lines and the unselected bit lines, so as to realize erasing of the storage strings connected to the selected bit lines, and not to erase the storage strings connected to the unselected bit lines.

[0009] Further, the memory further comprises a P-type doped region below the plurality of memory strings, the P-type doped region is connected to the channel layer by an epitaxial layer; in the erasing operation, the P-type doped region is floated.

[0010] Further, each of the memory strings is connected to a bit line by the channel layer, the bit line connects two of the memory strings.

[0011] Further, the memory string comprises a plurality of sub-memory strings, the channel layer is divided into a plurality of sub-channel layers, each of the sub-memory strings is connected to a bit line by one of the sub-channel layers, the bit line connects two of the sub-memory strings.

[0012] Further, the memory string has a plurality of convex portions in a direction parallel to a plane of the substrate, the plurality of convex portions extend along the longitudinal direction, each of the sub-channel layers is located in one of the convex portions to form one of the sub-memory strings.

[0013] Further, the step of applying a word line erasing voltage lower than the bit line erasing voltage to the corresponding word lines of the memory strings connected to the selected bit line and the unselected bit line to achieve the erasing of the memory strings connected to the selected bit line and the non-erasing of the memory strings connected to the unselected bit line comprises: applying a word line erasing voltage lower than the bit line erasing voltage to the corresponding word lines of the sub-memory strings connected to the selected bit line and the unselected bit line to achieve the erasing of the sub-memory strings connected to the selected bit line and the non-erasing of the sub-memory strings connected to the unselected bit line.

[0014] Further, the bit line erasing voltage and the top select gate voltage are synchronously raised and synchronously lowered.

[0015] In another aspect, the embodiments of the present disclosure provide a control device of a memory, each memory block of the memory comprises a plurality of memory strings, each of the memory strings comprises a channel layer with an N-type doped region at the top, a bit line connected to the memory strings of the same memory block comprises a selected bit line and an unselected bit line, the control device comprises:

[0016] a first control unit configured to apply a bit line erasing voltage to the selected bit line and apply a forbidden erasing voltage to the unselected bit line;

[0017] a second control unit configured to apply a top select gate voltage to a top select gate to form a potential difference between the top select gate and the selected bit line to generate electron-hole pairs in the N-type doped region, wherein the top select gate voltage is lower than the bit line erasing voltage and higher than or equal to the forbidden erasing voltage.

[0018] The third control unit is configured to apply a word line erase voltage lower than the bit line erase voltage to the corresponding word lines of the memory strings connected to the selected bit line and the unselected bit line, so as to realize erasing the memory string connected to the selected bit line and not erasing the memory string connected to the unselected bit line.

[0019] In still another aspect, the present disclosure provides a memory control device, comprising a processor and a memory for storing executable instructions capable of running on the processor; wherein the processor is configured to run the executable instructions to perform the steps of any of the above methods.

[0020] The present disclosure also provides a storage medium having stored executable instructions, which, when executed by a processor, implement the steps of any of the above methods.

[0021] The present disclosure provides a memory control method, a control device and a storage medium. Each memory string includes a channel layer having an N-type doped region at the top. The bit lines of the memory strings connected to the same memory block include selected bit lines and unselected bit lines. A bit line erase voltage is applied to the selected bit line, and a forbidden erase voltage is applied to the unselected bit line. At the same time, a top selection gate voltage lower than the bit line erase voltage is applied to the top selection gate. At this time, a potential difference is generated between the selected bit line and the top selection gate, and an electric field is formed to generate electron-hole pairs in the N-type doped region. The separated electrons flow to the selected bit line, and the separated holes flow into the channel layer to form a channel voltage in the channel layer. When a word line erase voltage lower than the bit line erase voltage is applied to the corresponding word lines of the memory strings connected to the selected bit line and the unselected bit line, the memory string corresponding to the selected bit line can be erased, and the memory string corresponding to the unselected bit line cannot be erased. This way of selecting memory strings for erasing by bit lines eliminates data migration and potential data loss during the erasing process in units of memory blocks, effectively reduces the erasing time, greatly improves the erasing rate, and also reduces the programming and erasing times of the memory cells, and reduces the degradation of the memory cells. BRIEF DESCRIPTION OF DRAWINGS

[0022] The technical solutions and other beneficial effects of the present disclosure will become apparent from the following detailed description of the embodiments of the present disclosure, taken in conjunction with the accompanying drawings.

[0023] Figure 1 is a schematic diagram of a data erasing process of a memory in the related art;

[0024] Figure 2 is a schematic diagram of a top view structure of a memory provided by the present disclosure;

[0025] Figure 3 is a cross-sectional structure schematic diagram of the memory in the XZ direction according to an embodiment of the present disclosure; Figure 2

[0026] Figure 4 is a flowchart of a control method of the memory according to an embodiment of the present disclosure;

[0027] Figure 5 is a circuit diagram of one memory string in the memory according to an embodiment of the present disclosure;

[0028] Figure 6 is a timing diagram of an erase process of the memory according to an embodiment of the present disclosure;

[0029] Figure 7 is a top view structure schematic diagram of the memory according to an embodiment of the present disclosure;

[0030] Figure 8 is a cross-sectional structure schematic diagram of the memory in the XY direction according to an embodiment of the present disclosure;

[0031] Figure 9 is a cross-sectional structure schematic diagram of the memory in the XY direction according to a variant of the embodiment of the present disclosure;

[0032] Figure 10 is a top view structure schematic diagram of the memory according to an embodiment of the present disclosure;

[0033] Figure 11 is a cross-sectional structure schematic diagram of the memory in the XY direction according to an embodiment of the present disclosure;

[0034] Figure 12 is a structure schematic diagram of a control device of the memory according to an embodiment of the present disclosure;

[0035] Figure 13 is a structure schematic diagram of a control device of the memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the embodiments of the present disclosure.

[0037] ​It should be understood that, although terms hereinafter can be used in a certain sequence or hierarchy, such terms are not necessarily used in that order. One of ordinary skill in the art would recognize that a mechanism in accordance with the present embodiments can function properly in a different sequence or even contemporaneously. For example, embodiments or components of a mechanism could be implemented regardless of order.

[0038] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion.

[0039] As used herein, the term "layer" refers to a portion of a material that has a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a thickness that is less than the thickness of an underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between or between any horizontal pair of planes between or at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereover and / or thereunder. A layer can include multiple layers, for example, an interconnect layer can include one or more conductors and contact layers and one or more dielectric layers.

[0040] As used herein, the term "memory" refers to a semiconductor device having vertically oriented array structures on a laterally oriented substrate, such that the array structures extend in a vertical direction relative to the substrate. As used herein, the term "lateral" refers to a direction perpendicular to the substrate, denoted by "Z"; the direction parallel to the substrate is denoted by "X" in the drawings, and the direction parallel to the substrate and perpendicular to "X" is denoted by "Y".

[0041] It should be noted that the figures provided in the present disclosure are only schematic and are intended to provide the basic understanding of the present embodiments. In the figures, the thickness of layers, regions and / or areas can be exaggerated for clarity. The same reference numerals are used in different figures to denote the same or similar components.

[0042] Please refer to Figure 1 , Figure 1is a schematic diagram of a data erasing process of a memory in the related art. The erasing manner of the memory is to erase in units of memory blocks. When a memory block block1 to be erased is selected, an extra provided memory block over provisioning (OP) block needs to be set as data migration, and then block1 is erased. When the memory cells of block increase, the erasing manner of the memory block requiring data migration will seriously affect the erasing speed. For example, when only "1", "2", "13", "4", "19" in block1 need to be erased, the other data in block1 need to be migrated to OP first, and then the data in block1 is erased.

[0043] Referring to Figure 2 , Figure 2 is a schematic diagram of a top view structure of a memory provided by an embodiment of the present disclosure. The memory 100 includes a plurality of memory blocks G0 (only one memory block is shown in the figure), the plurality of memory blocks G0 are separated by a gate line gap 10, a top selection gate cut line 20 parallel to the gate line gap 10 divides one memory block G0 into two memory areas, and a virtual channel structure 21 is below the top selection gate cut line. Each memory block G0 has a plurality of memory strings 30.

[0044] Referring to Figure 3 , Figure 3 is a schematic diagram of a cross-sectional structure of the memory provided by an embodiment of the present disclosure at A-A1 in Figure 2 . The memory 100 includes a substrate 40 and a stack layer 50 located on the substrate 40, the stack layer 50 is alternately stacked by an interlayer insulating layer 51 and an interlayer gate layer 52, the interlayer gate layer 52 at the top can be used as a top selection gate (TSG) 53, the interlayer gate layer 52 at the bottom can be used as a bottom selection gate (BSG) 54, and the other interlayer gate layers 52 can be used as a word line (WL) 55. The memory 100 further includes a memory string 30 (only one memory string 30 is shown in the figure) penetrating the stack layer 50 in the longitudinal direction (Z), the memory string 30 includes a channel hole penetrating the stack layer 50 and a memory layer 31, a channel layer 32 and an insulating layer 33 sequentially located on the sidewall of the channel hole. The memory layer 31 includes a blocking layer, a charge trapping layer and a tunneling layer, and the top of the channel layer 32 has an N-type doped region 321. In the embodiment of the present disclosure, the substrate 40 is a P-type substrate, i.e., a high voltage P well (HVPW), and the P-type doped region is connected to the channel layer 32 through an epitaxial layer.

[0045] In the embodiments of the present disclosure, the memory 100 further comprises a plurality of bit lines (BL) 60 extending in the Y direction, each memory string 30 is connected with the bit line 60 through the channel layer 32 and the bit line contact 601 above the channel layer 32. In the embodiments of the present disclosure, one bit line 60 is connected with two memory strings 30.

[0046] Please refer to Figure 4 , Figure 4 is a flowchart of a control method of a memory provided by the embodiments of the present disclosure. The control method can be applied to the memory described above, and thus the structure numbers of the memory described above are used. The flowchart shows a data erasing method of the memory, which comprises steps S1-S2.

[0047] In step S1, the bit lines 60 of the memory strings 30 connected to the same memory block G0 comprise selected bit lines and unselected bit lines, the selected bit lines are applied with a bit line erasing voltage, and the unselected bit lines are applied with a forbidden erasing voltage.

[0048] In step S2, a top select gate voltage is applied to the top select gate 53, so that a potential difference is formed between the top select gate 53 and the selected bit lines to generate electron-hole pairs in the N-type doped region 321, wherein the top select gate voltage is lower than the bit line erasing voltage and higher than or equal to the forbidden erasing voltage.

[0049] In step S3, a word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word lines of the memory strings connected with the selected bit lines and the unselected bit lines, so that the memory strings 30 connected with the selected bit lines are erased, and the memory strings 30 connected with the unselected bit lines are not erased.

[0050] In the embodiments of the present disclosure, the "selected bit" is the bit line connected with the memory string 30 to be erased, and the "unselected bit" is the bit line connected with the memory string 30 not to be erased. It can be understood that the erasing states of the two memory strings 30 connected with one bit line 60 are the same. For example, in Figure 2 , the left part of the bit lines 61 can be selected as the selected bit, and the right part of the bit lines 62 can be selected as the unselected bit. It should be understood that each bit line 60 exists independently, and thus each bit line 60 can be a selected bit or an unselected bit. The "corresponding word line" refers to the word line 55 connected with the memory string 30 connected with the selected bit and the unselected bit, that is, the word line 55 connected with the memory string 30 below the selected bit and the unselected bit. For example, in Figure 3In the figure, if the bit line 60 is a selected bit line or an unselected bit line, the word line 55 connected with the lower storage string 30 is the corresponding word line, that is, all the interlayer gate layers 52 except the top selection gate 53 and the bottom selection gate 54 are the corresponding word line.

[0051] Please refer to Figure 5 , Figure 5 is a circuit diagram of one storage string in the memory provided by the embodiment of the present disclosure, Figure 5 The circuit diagram corresponds to Figure 3 the structure of the storage string 30 in the figure. In the figure, the upper end of one storage string is connected to the BL, the lower end is connected to the HVPW, the drain of the TSG is connected to the BL, and the source of the BSG is connected to the HVPW.

[0052] Please refer to Figure 6 , Figure 6 is a timing diagram of the erasing process of the memory provided by the embodiment of the present disclosure. From Figure 6 the timing diagram can be seen, Figure 4 the order of steps S1-S3 in the figure is not limited by the flowchart, and the steps are executed according to time, can be executed at the same time, and can be executed by different control units.

[0053] In the embodiment of the present disclosure, the HVPW is in a floating state, and the voltage of the BSG is 0V. When the bit line erasing voltage (such as 20V) is applied to the selected bit line (Select Bit), and the top selection gate voltage (such as 12V) lower than the bit line erasing voltage is applied to the top selection gate (TSG) 53, a potential difference is formed between the top selection gate (TSG) 53 and the selected bit line (Select Bit), a strong electric field is formed, band2band occurs, and then the N-type doped region 321 generates electron-hole pairs. Please refer to Figure 3 , the separated electrons flow to the selected bit line (BL) end, and the separated holes flow to the channel layer 32. The material of the channel layer 32 is a semiconductor (such as polysilicon), so the voltage of the channel layer 32 gradually rises. When the word line erasing voltage (such as 0V) lower than the bit line erasing voltage is applied to the corresponding word line, due to the pressure difference between the channel layer 32 and the corresponding word line, the electrons in the storage layer 31 flow to the channel layer 32, and then flow to the bit line 60, so that the storage string 30 is erased. When the unselected bit line (Unselect Bit) is applied with the inhibit erasing voltage (such as 0V) less than or equal to the top selection gate voltage, the unselected bit line will not form a strong electric field with the top selection gate (TSG) 53, and will not generate electron-hole pairs, and the channel layer 32 and the corresponding word line will not generate a pressure difference, and then the storage string 30 will not be erased.

[0054] wherein, when the corresponding word line is 0V, the higher the bit line erase voltage applied by the selected bit line, the deeper the storage unit is erased. In other words, when the bit line erase voltage is 20V, the voltage threshold of the storage layer 31 is generally -2V after the erase operation, and if a deeper erase is required, the bit line erase voltage is greater than 20V. Therefore, the bit line erase voltage can be selected according to the depth of the erase.

[0055] In the embodiments of the present disclosure, the top select gate (TSG) 53 is synchronously raised and synchronously lowered with the bit line erase voltage, so as to maintain the pressure difference between the selected bit line and the top select gate (TSG) 53. When the bit line erase voltage is 20V, the voltage of the top select gate (TSG) 53 can be 8-12V. Because experiments show that, in order to make the top select gate (TSG) 53 corresponding top select tube in the on state, and make the pressure difference between the top select gate (TSG) 53 and the selected bit line be able to produce electron-hole pairs, 8-12V is a suitable top select gate voltage range.

[0056] The control method of the memory provided by the embodiments of the present disclosure applies a bit line erase voltage to the selected bit line, applies a top select gate voltage lower than the bit line erase voltage to the top select gate (TSG) 53, and applies a word line erase voltage lower than the bit line erase voltage to the corresponding word line, so as to realize the erase operation of the storage string 30 corresponding to the selected bit line. At the same time, a forbidden erase voltage less than or equal to the top select gate voltage is applied to the unselected bit line, so that the storage string corresponding to the unselected bit line is not erased, thereby realizing the selection of the storage string by the bit line for erase, eliminating the data migration and potential data loss in the erase process by the storage block as a unit, effectively reducing the erase time, greatly improving the erase rate, and also reducing the programming and erasing times of the storage unit, and reducing the degradation degree of the storage unit.

[0057] Please refer to Figure 7 and Figure 8 , Figure 7 is a top view structural schematic diagram of the memory provided by the present disclosure, Figure 8is a cross-sectional structure diagram of a memory in the XY direction provided by an embodiment of the present disclosure. For ease of understanding, in the present embodiment, the same structure as in the above embodiments uses the same reference numerals. The memory 200 includes memory blocks G0 separated by gate line gaps 10. In one memory block G0, one memory string 30 includes two sub-memory strings 301 separated by a slot 302. The memory string 30 includes a memory layer 31, a channel layer 32, and an insulating layer 33, which are all separated into two parts by the slot 302, such as the channel layer 32 being separated into two sub-channel layers. One of the sub-memory strings 301 is connected to one bit line 60 through one of the sub-channel layers, and the one bit line 60 connects the two sub-memory strings 301.

[0058] The control method of the memory provided by the embodiment of the present disclosure can also be applied to the memory 200, except that one selected bit line corresponds to a sub-memory string 301 instead of a memory string 30. Thus, the erase operation can be performed on the sub-memory string corresponding to the selected bit line, and the erase operation is not performed on the sub-memory string corresponding to the unselected bit line.

[0059] Please refer to Figure 9 , Figure 9 is a cross-sectional structure diagram of a memory in the XY direction provided by a variant of the embodiment of the present disclosure. The memory 300 includes a memory string 30, which includes a memory layer 31, a channel layer 32, and an insulating layer 33. The memory layer 31 includes a blocking layer 311, a charge trapping layer 312, and a tunneling layer 313. The memory string 30 includes two sub-memory strings 301, and the channel layer 32 is separated into two sub-channel layers by the insulating layer 33. In the variant, each sub-memory string 301 is connected to one bit line through a sub-channel layer, and the one bit line connects the two sub-memory strings 301. The control method of the memory 300 is the same as that of the above embodiment of the present disclosure.

[0060] Please refer to Figure 10 and Figure 11 , Figure 10 is a top view structure diagram of a memory provided by an embodiment of the present disclosure, Figure 11 is a cross-sectional structure diagram of a memory in the XY direction provided by an embodiment of the present disclosure. The memory string 30 includes four sub-memory strings 301, the channel layer 32 is separated into four sub-channel layers by the insulating layer 33, the memory string 30 has a plurality of outward protrusions (B1, B2, B3, B4) in the plane (XY) direction parallel to the substrate, the plurality of outward protrusions extend along the longitudinal direction (Z), and one of the sub-channel layers is located in one of the outward protrusions to form one of the sub-memory strings 301. In fact, in the above embodiment ( Figure 8 ) and the related variants ( Figure 9In the above embodiment, the storage string 30 can also be said to have two outer convex portions in a direction parallel to the plane (XY) of the substrate.

[0061] The control method of the memory provided by the embodiments of the present disclosure can also be applied to the memory 400, and the operation process is the same as that of the above embodiments, except that the selected bit line is connected to the sub-storage string 301. The beneficial effects of the control method will not be repeated here.

[0062] In order to implement the method of the embodiments of the present disclosure, the embodiments of the present disclosure also provide a memory control device. Figure 12 is a structural schematic diagram of the memory control device provided by the embodiments of the present disclosure. The memory control device 1000 comprises a first control unit 1001, a second control unit 1002 and a third control unit 1003.

[0063] The first control unit 1001 is configured to apply a bit line erase voltage to the selected bit line and apply a forbidden erase voltage to the unselected bit line.

[0064] The second control unit 1002 is configured to apply a top selection gate voltage to the top selection gate to form a potential difference between the top selection gate and the selected bit line to generate electron-hole pairs in the N-type doped region, wherein the top selection gate voltage is lower than the bit line erase voltage and higher than or equal to the forbidden erase voltage.

[0065] The third control unit 1003 is configured to apply a word line erase voltage lower than the bit line erase voltage to the corresponding word line of the storage string connected to the selected bit line and the unselected bit line, so as to realize erasing the storage string connected to the selected bit line and not erasing the storage string connected to the unselected bit line.

[0066] It should be noted that: when the memory control device 1000 provided by the above embodiments performs control processing, only the above division of each program module is exemplified, and in actual application, the above processing can be completed by different program modules according to needs, that is, the internal structure of the device is divided into different program modules to complete all or part of the above processing. In addition, the memory control device and the control method of the memory provided by the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0067] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiments of the present disclosure, the embodiments of the present disclosure also provide a memory control device. Please refer to Figure 13 , Figure 13 is a structural schematic diagram of the memory control device provided by the embodiments of the present disclosure. The memory control device 2000 comprises:

[0068] a memory 2001, configured to store executable instructions;

[0069] a processor 2002, configured to execute the executable instructions stored in the memory to implement the memory control method provided by the embodiments of the present disclosure.

[0070] In actual application, as shown in Figure 13 Each component in the memory control apparatus 1200 is coupled together through a bus system 2003. It can be understood that the bus system 2003 is used to realize the connection and communication between the components. The bus system 2003 includes not only a data bus, but also a power bus, a control bus and a status signal bus. However, for the purpose of clear illustration, all kinds of buses are marked as the bus system 2003 in the Figure 13 .

[0071] The embodiments of the present disclosure further provide a storage medium, which stores executable instructions, and when the executable instructions are executed by at least one processor, the memory control method provided by the embodiments of the present disclosure is implemented.

[0072] In some embodiments, the storage medium can be a ferromagnetic random access memory (FRAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc. It can also be various devices including one or any combination of the above-mentioned memories.

[0073] In some embodiments, the executable instructions can be in the form of programs, software, software modules, scripts or codes, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as a standalone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0074] By way of example, executable instructions can correspond to a file in a file system, but are not necessarily limited thereto. The executable instructions can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub programs, or code portions.

[0075] By way of example, the executable instructions can be deployed to be executed on one computer, or on multiple computers of a system, or on multiple computers distributed among multiple locations and interconnected by a communication network.

[0076] The above description of the embodiments is only used to help understand the technical solutions of the present disclosure and their core ideas; it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A control method of a memory, characterized by, Each memory block of the memory includes a plurality of memory strings, each of the memory strings including a channel layer having an N-type doped region at a top portion, and the control method includes: applying a bit line erase voltage to the selected bit line; applying a top select gate voltage to the top select gate, so that a potential difference is formed between the top select gate and the selected bit line; wherein the top select gate voltage is lower than the bit line erase voltage; and the bit line erase voltage and the top select gate voltage are changed synchronously; applying a word line erase voltage, which is lower than the bit line erase voltage, to corresponding word lines of the memory strings connected to the selected bit line, so as to perform erasing on the memory strings connected to the selected bit line.

2. The control method of memory according to claim 1, wherein, The bit lines of the memory strings connected to the same memory block include the selected bit line and an unselected bit line, and the control method further includes: applying a forbidden erase voltage to the unselected bit line, and not performing erasing on the memory strings connected to the unselected bit line; wherein the top select gate is higher than or equal to the forbidden erase voltage.

3. The control method of memory according to claim 1, wherein, The memory further includes a P-type doped region at a bottom portion of the plurality of memory strings, and the P-type doped region is connected to the channel layer through an epitaxial layer, and the method further includes: floating the P-type doped region.

4. The control method of memory according to claim 1, wherein, Each of the memory strings is connected to one bit line through the channel layer, and one bit line connects two of the memory strings.

5. The control method of memory according to claim 1, wherein, The memory string includes a plurality of sub-memory strings, and the channel layer is divided into a plurality of sub-channel layers, each of the sub-memory strings is connected to one bit line through one of the sub-channel layers, and one bit line connects two of the sub-memory strings.

6. The control method of memory according to claim 5, wherein, The memory string has a plurality of convex portions in a direction parallel to a substrate surface, the plurality of convex portions extend longitudinally, and each of the sub-channel layers is located in one of the convex portions to form one of the sub-memory strings.

7. The control method of memory according to claim 5, wherein, The applying of the word line erase voltage, which is lower than the bit line erase voltage, to corresponding word lines of the memory strings connected to the selected bit line, so as to perform erasing on the memory strings connected to the selected bit line, includes: applying a word line erase voltage, which is lower than the bit line erase voltage, to corresponding word lines of the sub-memory strings connected to the selected bit line, so as to perform erasing on the sub-memory strings connected to the selected bit line.

8. A control method of a memory, characterized by, Each memory block of the memory includes a plurality of memory strings, each of the memory strings including a channel layer having an N-type doped region at a top portion, and a P-type doped region at a bottom portion of the plurality of memory strings is connected to the channel layer through an epitaxial layer, and the control method includes: applying a bit line erase voltage to the selected bit line; applying a top select gate voltage to the top select gate, so that a potential difference is formed between the top select gate and the selected bit line; wherein the top select gate voltage is lower than the bit line erase voltage; and the bit line erase voltage and the top select gate voltage are changed synchronously; applying a word line erase voltage, which is lower than the bit line erase voltage, to corresponding word lines of the memory strings connected to the selected bit line, so as to perform erasing on the memory strings connected to the selected bit line; floating the P-type doped region.

9. The control method of memory according to claim 8, wherein, The bit lines of the memory strings connected to the same memory block include the selected bit line and an unselected bit line, and the control method further includes: A non-erase voltage is applied to the unselected bit line, and the memory strings connected to the unselected bit line are not erased; wherein the top select gate is higher than or equal to the non-erase voltage.

10. The control method of memory according to claim 8, wherein, Each of the memory strings is connected to a bit line through the channel layer, and the bit line connects two of the memory strings.

11. The control method of memory according to claim 8, wherein, The memory string includes a plurality of sub-memory strings, and the channel layer is divided into a plurality of sub-channel layers, each of the sub-memory strings is connected to a bit line through one of the sub-channel layers, and the bit line connects two of the sub-memory strings.

12. The control method of memory according to claim 11, wherein, The memory string has a plurality of convex portions in a direction parallel to the substrate surface, the plurality of convex portions extend longitudinally, and each of the sub-channel layers is located in one of the convex portions to form one of the sub-memory strings.

13. The control method of memory according to claim 11, wherein, The corresponding word lines of the memory strings connected to the selected bit line are applied with a word line erase voltage lower than the bit line erase voltage, so as to realize erasing of the memory strings connected to the selected bit line, including: The corresponding word lines of the sub-memory strings connected to the selected bit line are applied with a word line erase voltage lower than the bit line erase voltage, so as to realize erasing of the sub-memory strings connected to the selected bit line.

14. The control method of memory according to claim 8, wherein, The bit line erase voltage and the top select gate voltage rise and fall synchronously.

15. A memory memory, comprising: Including: A memory array, each memory block of the memory array includes a plurality of memory strings, and each of the memory strings includes a channel layer with an N-type doped region at the top; A peripheral circuit, the peripheral circuit is configured to: Apply a bit line erase voltage to a selected bit line; Apply a top select gate voltage to a top select gate to form a potential difference between the top select gate and the selected bit line; wherein the top select gate voltage is lower than the bit line erase voltage; The bit line erase voltage and the top select gate voltage change synchronously; The corresponding word lines of the memory strings connected to the selected bit line are applied with a word line erase voltage lower than the bit line erase voltage, so as to realize erasing of the memory strings connected to the selected bit line.

16. The memory of claim 15, wherein, The bit lines of the memory strings connected to the same memory block include the selected bit line and an unselected bit line, and the peripheral circuit is further configured to: Apply a non-erase voltage to the unselected bit line, and the memory strings connected to the unselected bit line are not erased; wherein the top select gate is higher than or equal to the non-erase voltage.

17. A memory, comprising: Including: A memory array, each memory block of the memory array includes a plurality of memory strings, and each of the memory strings includes a channel layer with an N-type doped region at the top, and a P-type doped region at the bottom of the plurality of memory strings is connected to the channel layer through an epitaxial layer; A peripheral circuit, the peripheral circuit is configured to: Apply a bit line erase voltage to a selected bit line; Apply a top select gate voltage to a top select gate to form a potential difference between the top select gate and the selected bit line; wherein the top select gate voltage is lower than the bit line erase voltage; The corresponding word lines of the memory strings connected to the selected bit line are applied with a word line erase voltage lower than the bit line erase voltage, so as to realize erasing of the memory strings connected to the selected bit line. floating the p-type doped region.

18. The memory of claim 17, wherein, The bit lines of the memory strings connected to the same memory block include the selected bit line and an unselected bit line, and the peripheral circuit is further configured to: applying a forbidden erase voltage to the unselected bit line, and not erasing the memory string connected to the unselected bit line; wherein the top select gate is higher than or equal to the forbidden erase voltage.

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