A memory device, data processing system, method and storage medium

Abstract

The present invention discloses a memory device, a data processing system, a method, and a storage medium. A controller in the memory system is programmed to perform the following operations: maintain an L2P management table; the L2P management table is configured to include a first-level management subtable and a second-level management subtable; the first-level management subtable includes multiple first elements; each first element corresponds to a second-level management subtable; the first element is configured to include first identification information; each second element included in the second-level management subtable is configured to include second identification information; in response to a request for an L2P pointer sent from a host device, the L2P management table is used to obtain a physical area indicated by a second element of a second flag from multiple physical areas indicated by a first element of a first flag having first identification information; and information associated with the first L2P pointer is stored in the physical area indicated by a second element of the second flag.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory device, a data processing system, a method, and a storage medium. Background Art

[0002] Memory systems are typically provided as internal semiconductor integrated circuits within computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), or Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory can retain stored data when power is off, and includes flash memory (Flash Memory), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static random access memory (SRAM), erasable programmable ROM (EPROM), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM) or 3D XPointTM memory, etc.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory systems typically include one or more groups of single-transistor, floating gate, or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory device architectures include NAND and NOR architectures, named after the logical arrangement of the basic memory cells of each architecture. The memory cells of a memory device are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of a memory device is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of a memory device is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of a memory device is coupled together in series, source-to-drain, between a source line and a bit line. Both NOR and NAND architecture semiconductor memory devices are accessed through a decoder that activates a particular memory cell by selecting the word line coupled to its gate. In a NOR architecture semiconductor memory device, once a selected memory cell is activated, its data value is placed on the bit line, resulting in different current flows depending on the state in which the particular cell is programmed. In a NAND architecture semiconductor memory device, a high bias voltage is applied to the drain-side select gate (SGD) line. The word line coupled to the gates of the unselected memory cells of each group is driven with a specific pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., pass current in a manner that is not limited by the data value stored in them). Current then flows from the source line to the bit line through each series-coupled group, limited only by the selected memory cell of each group, placing the currently encoded data value of the selected memory cell on the bit line.

[0004] Each flash memory cell in a NOR or NAND architecture semiconductor memory device can be programmed individually or collectively to one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), representing one data bit. However, a flash memory cell can also represent one of more than two programming states, thereby allowing the manufacture of higher density memories without increasing the number of memory cells because each cell can represent more than one binary digit (e.g., more than one bit). These cells may be referred to as multi-state memory cells, multi-bit cells, or multi-level cells (MLC). In some instances, an MLC may refer to a memory cell that can store two bits of data per cell (e.g., one of four programming states), a triple-level cell (TLC) may refer to a memory cell that can store three bits of data per cell (e.g., one of eight programming states), and a quad-level cell (QLC) can store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one data bit per cell (i.e., it can represent more than two programming states).

[0005] Such 3D NAND devices typically include a string of memory cells coupled in series (e.g., drain to source) between one or more source-side select gates (SGS) near the source and one or more drain-side select gates (SGD) near the bit line. In an example, the SGS or SGD may include one or more field effect transistors (FETs) or metal oxide semiconductor (MOS) structure devices, etc. In some examples, the string will extend vertically through multiple vertical spacer layers containing corresponding word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent to a string of memory cells to form a channel for the memory cells of the string. In the example of a vertical string, the polysilicon structure may be in the form of a vertically extending column. In some examples, the string may be "folded" and therefore arranged relative to a U-shaped column. In other examples, multiple vertical structures may be stacked on each other to form a stacked array of memory cell strings.

[0006] Memory devices or components can be combined together to form a storage volume of a memory system, such as a solid state drive (SSD), a universal flash storage (UFS™) device, a multimedia card (MMC) solid state storage device, an embedded MMC device (eMMC™), etc. An SSD can be used as a main storage device for a computer and has advantages over traditional hard disk drives with moving parts in terms of, for example, performance, size, weight, durability, operating temperature range, and power consumption. For example, an SSD can have reduced seek time, latency, or other delays associated with a magnetic disk drive (e.g., electromechanical). An SSD uses non-volatile memory cells (such as flash memory cells) to eliminate the need for an internal battery power supply, thereby allowing the drive to be more versatile and compact.

[0007] An SSD may include several memory systems, including several dies or logical units (e.g., logical unit numbers or LUNs), and may include one or more processors or other controllers that perform the logic functions required to operate the memory system or interface with external systems. Such an SSD may include one or more flash memory circuitry dies, wherein the flash memory circuitry die includes several memory devices and peripheral circuitry thereon. The flash memory devices may include several blocks of memory cells organized into several physical pages. In many instances, the SSD will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands associated with memory operations from a host, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory system and the host, or erase operations to erase data from the memory system. Summary of the Invention

[0008] In view of this, the main purpose of the present invention is to provide a memory device, a data processing system, a method and a storage medium, which can reduce the number of searches when searching for free memory and greatly improve the free memory search speed.

[0009] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0010] In a first aspect, an embodiment of the present invention provides a memory device comprising: a memory array of a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein,

[0011] The control circuit is configured to: in response to a first write instruction, determine a selected word line from the plurality of word lines; determine a selected bit line from the plurality of bit lines; determine a selected first physical address based on the selected word line and the selected word line; and write information associated with a first L2P pointer at the first physical address;

[0012] Among them, the first physical address is the physical address corresponding to the first physical area; the first physical area is the physical area indicated by a second element whose second identification information is a second flag, obtained from multiple physical areas indicated by a first element whose first identification information is a first flag, by the controller of the memory system using the L2P management table maintained by itself; the L2P management table is configured to include a first-level management subtable and a second-level management subtable; the first-level management subtable includes multiple first elements; each first element corresponds to a second-level management subtable; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management subtable is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element in the multiple physical areas; the second element is the second element included in the second-level management subtable corresponding to the first element; the first L2P pointer is generated or obtained by the controller based on a request for the L2P pointer; the controller is coupled to the memory device and can communicate with the memory device.

[0013] In a second aspect, the present invention provides a data processing system comprising: a memory system and a host device; the memory system comprises a memory device and a controller coupled to the memory device, wherein:

[0014] The controller is programmed to perform the following operations, including:

[0015] Maintaining an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas;

[0016] After responding to a request for an L2P pointer sent from the host device, using the L2P management table, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, obtain a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element;

[0017] A physical area indicated by a second element of the second flag is used to store information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request.

[0018] In a third aspect, the present invention further provides a data processing method, applied to a data processing system comprising a memory system and a host device, wherein the memory system comprises a memory device and a controller coupled to the memory device, wherein the method comprises:

[0019] The controller maintains an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas;

[0020] The controller, in response to a request for an L2P pointer sent from the host device, uses the L2P management table to obtain, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element;

[0021] The controller uses a second element of the second flag to indicate a physical area for storing information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request.

[0022] In a fourth aspect, an embodiment of the present invention further provides a computer-readable medium, comprising instructions thereon, which, when executed by a processor, cause the processor to perform the following operations, including:

[0023] Maintaining an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in a memory of a controller in a certain memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of a physical area corresponding to the second element among the multiple physical areas;

[0024] In response to a request for an L2P pointer sent from the host device, using the L2P management table, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, obtain a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element;

[0025] A physical area indicated by a second element of the second flag is used to store information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request;

[0026] The host device is capable of communicating with the memory system.

[0027] Embodiments of the present invention provide a memory device, a data processing system, a method, and a storage medium. The controller in the memory system is programmed to perform the following operations, including: maintaining an L2P management table; wherein the L2P management table is configured to include a first-level management subtable and a second-level management subtable; the first-level management subtable includes multiple first elements; each first element corresponds to a second-level management subtable; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management subtable is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element in the multiple physical areas; after responding to a request for an L2P pointer sent from the host device, using the L2P management table to obtain, from the multiple physical areas indicated by a first element whose first identification information is a first flag, a physical area indicated by a second element whose second identification information is a second flag; the second element is a second element included in the second-level management subtable corresponding to the first element; using the physical area indicated by the second element of the second flag to store information associated with the first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request. The data processing system and method provided by the embodiments of the present invention manage physical areas in RAM by configuring the management table of physical areas as a two-level associated management table. When a host requests L2P mapping data and the memory system needs to store information related to the L2P mapping data, the system can quickly locate idle physical areas through the L2P management table, thereby reducing the number of searches and greatly improving the processing speed of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In the accompanying drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0029] Figure 1 An example of an environment including a host device and a memory system is provided for illustrating an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of an exemplary memory device including peripheral circuits for some aspects of embodiments of the present invention;

[0031] Figure 3 A perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array provided in accordance with an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of a structure of an L2P management table for a physical area in a memory device provided by an embodiment of the present invention;

[0033] Figure 5 FIG3 is a flowchart of a processing flow 300 of the controller 1021 of the memory system 102 in the data processing system provided by an embodiment of the present invention, in which the controller 1021 calls the L2P management table to search for a free physical area in the controller memory after responding to a request for an L2P pointer from a host device;

[0034] Figure 6 A schematic diagram of the working principle of the host device according to an embodiment of the present invention interacting with the memory system when searching for an idle physical area for mapping a certain logical address;

[0035] Figure 7 For Figure 4 A schematic diagram of the structure of the array formed by the first-level management sub-table and the second-level management sub-table when writing the search algorithm for the provided management table;

[0036] Figure 8 Based on Figure 7 Schematic diagram of the search code written for the array shown;

[0037] Figure 9 A schematic diagram of the structure of a management table for managing L2P mapping data in the related art;

[0038] Figure 10 A schematic diagram of a processing flow 800 of a memory system 102 responding to a request for an L2P pointer sent by a host device;

[0039] Figure 11 A schematic structural diagram of an application scenario of a memory system 102 and a host device provided by an embodiment of the present invention;

[0040] Figure 12 A block diagram of an example machine 1000 upon which any one or more of the techniques discussed herein may be performed is provided for embodiments of the present invention. DETAILED DESCRIPTION

[0041] The various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. Other embodiments that can be used as variations of any disclosed embodiment can be formed by configuring or arranging the elements and features in the present invention in different ways. Therefore, the present invention is not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the present invention is thorough and complete, and the scope of the present invention is fully conveyed to those skilled in the art to which the present invention belongs. It should be noted that references to "embodiment", "another embodiment" and the like do not necessarily represent only one embodiment, and different references to any such phrases are not necessarily for the same embodiment. It should be understood that although the terms "first", "second", "third" and the like can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish an element from another element with the same or similar name. Therefore, without departing from the spirit and scope of the present invention, the first element in one embodiment may also be referred to as the second or third element in another embodiment.

[0042] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may be present.

[0043] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified or can be clearly understood from the context to be singular, the articles "one" and / or "an" used in the present invention and the appended claims should be collectively interpreted as meaning "one or more". It should be further understood that the terms "include", "comprise", "include" and "include" used in the present invention specify the presence of the elements and do not exclude the presence or addition of one or more other elements. The term "and / or" used in the present invention includes any and all combinations of one or more associated listed items. Unless otherwise defined, all terms including technology and science used in the present invention have the same meaning as those generally understood by those skilled in the art in view of the present invention. It should be further understood that, unless the present invention is clearly defined, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the present invention and related technologies, and should not be interpreted in an idealized or overly formalized manner.

[0044] In the following description, many specific details are set forth to provide a thorough understanding of the present invention, and the present invention can be practiced without some or all of these specific details. In other cases, well-known processing structures and / or processes are not described in detail to avoid unnecessarily obscuring the present invention. It should also be understood that in some cases, unless otherwise specified, it will be apparent to those skilled in the relevant art that features or elements described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Hereinafter, various embodiments of the present invention are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of embodiments of the present invention. Well-known technical details may be omitted to avoid obscuring features and aspects of the present invention.

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Aspects of the present invention may relate to a data processing system in which a host device is capable of securely caching a memory system, wherein the memory system may be configured as a system that maintains logical-to-physical L2P pointers. The L2P pointers associate a physical address at a memory device in the memory system with a logical address used by the host device. The L2P pointers may be stored in the memory system using a common data structure such as an L2P table. Read and write requests made by the host device include a logical address associated with a data unit to be read or written. The memory system generates an L2P pointer using the logical address and / or accesses a previously generated L2P pointer that associates a logical address with one or more physical addresses of the memory device.

[0047] To maintain persistence, the L2P pointer may be stored in a memory device of the memory system. During the use of the memory system, the L2P pointer is read directly from the memory device. It should be understood that reading the L2P pointer from the memory device takes a long time, and the read and write operations have a large latency. In order to reduce latency, the memory system may also include a memory, such as RAM, and some or all of the L2P pointers may be stored at the controller of the memory system during use to shorten latency. It should be noted that the read operation of accessing the L2P pointer at the controller RAM of the memory system is faster than the read operation of accessing the L2P pointer from the memory device. It should be noted that for some embodiments, the controller's RAM is relatively small and cannot load the complete L2P table of the memory device. In addition, the controller of some memory systems does not include RAM.

[0048] Based on this, in some embodiments, the memory system is configured to cache part or all of the L2P table at the host device. That is, the L2P pointer may be stored in the host device's RAM. When a read request is made at a logical address, the host device determines whether an L2P pointer corresponding to the logical address is cached. If so, the cached L2P pointer is used to resolve the physical address corresponding to the logical address in the memory system. The host device uses the read request containing the physical address. The memory system responds with the data stored at the physical address.

[0049] Caching the L2P pointer at the host device has the following advantages: it allows faster retrieval of data because the memory system does not need to perform a separate read operation at the memory device to obtain the L2P pointer; it reduces the need for RAM at the memory system because the memory system does not need to separately cache the L2P pointer already cached at the host device.

[0050] An embodiment of the present invention is directed to a method for quickly searching a two-level management table of physical areas maintained in a memory system when a host device sends a request for an L2P pointer to a memory system, so as to obtain a physical area in an idle state, and use the physical area to store information associated with the L2P pointer requested from the host device.

[0051] Figure 1 An example environment including a host device and a memory system is provided for illustrating embodiments of the present invention. This example environment 100 includes a host device 101 and a memory system 102; the host device 101 communicates with the memory system 102 via a communication interface. The host device 101 and / or the memory system 102 can be included in various products, such as Internet of Things (IoT) devices, such as refrigerators or other devices, sensors, motors, mobile communication devices, automobiles, and autonomous vehicles, to support product processing, communication, or control.

[0052] The memory system 102 includes a controller 1021 and a memory device 1022. Figure 2 As shown, a memory array 1022-1 including a plurality of stacked individual memory dies and a control circuit 1022-2 coupled to the periphery of the memory array 1022-1 is shown, wherein the memory array can be stacked in two dimensions or three dimensions (3D), for example, a stack of two-dimensional or three-dimensional (3D) NAND dies. An illustrative embodiment of the present invention is as follows: Figure 3 shown. Figure 3 A perspective view of a portion of an exemplary solution of a single-block three-dimensional memory array provided by an embodiment of the present invention is shown. It should be noted that the memory array includes multiple memory blocks. Figure 2 Shown is one of the blocks. Figure 3The memory block 30 includes a plurality of layers stacked on a substrate (not shown) and parallel to the substrate surface. Figure 3 Four word lines (WL) on four layers are shown, which may be denoted as WL0 to WL3. The memory block 30 is also arranged with a plurality of through-holes perpendicular to the word lines. The intersection of a word line and a through-hole forms a memory cell, so a through-hole can also be referred to as a memory cell string. It should be understood by those skilled in the art that the number of word lines of the memory block 30 and the number of memory cell strings are not limited to specific values. For example, the memory block 30 may include 64 word lines, and 64 word lines intersect with a memory cell string to form 64 memory cells along the memory cell string. For another example, the number of memory cell strings included in the memory block 30 may be calculated in the order of hundreds of thousands, millions, or even larger. A word line includes millions of memory cells formed by its intersection with, for example, millions of memory cell strings. The memory cells in the memory block 30 may be single-level memory cells or multi-level memory cells, wherein the single-level memory cells may be single-level cells (SLC) capable of storing 1 bit; the multi-level memory cells may be multi-level cells (MLC) capable of storing 2 bits, triple-level cells (TLC) capable of storing 3 bits, quad-level cells (QLC) capable of storing 4 bits, and quintuple-level cells (PLC) capable of storing 5 bits. Figure 2 As shown, the memory block 200 also includes a bit line (BL), a bit line selector (BLS, also known as a top selection gate line SGDL), a source line (SL), and a source selection line (SLS, also known as a bottom selection gate line SGSL). These circuit lines and the word line (WL) together can realize the addressing of any memory cell in the memory block 30.

[0053] In some embodiments, the memory device 1022 further includes a read / write circuit, a row decoder, and a column decoder. In some embodiments, access to the memory array 1022-1 by various peripheral circuits is implemented in a symmetrical manner on opposite sides of the memory array 1022-1, so that the density of access circuits on each side is reduced by half. The read / write circuit includes a plurality of sense blocks SB for reading or programming pages of the memory array 1022-1 in parallel. The memory array 1022-1 can be addressed by word lines via row decoders and bit lines via column decoders. In some embodiments, the memory array 1022-1, the control circuit 1022-2, the read / write circuit, the row decoder, and the column decoder can be manufactured on a chip, wherein Figure 2 The dotted box may also represent a chip, and is transmitted between the controller 1021 and the chip via the signal line 1022-3. Figure 2 It is also shown that a plurality of dummy cells, dummy word lines and dummy bit lines (not shown) are arranged in the dummy storage areas DMX and DMY. Figure 2 The dummy memories DMX1 - DMX2 and DMY1 - DMY2 are arranged along the side of the memory array 1022 - 1 and are used for read / write testing after the memory system is completed.

[0054] Control circuitry 1022-2 is configured to cooperate with the read / write circuitry to perform memory operations on memory array 1022-1. The control circuitry includes a state machine, an on-chip address decoder, and a power control module. The state machine is configured to provide chip-level control of memory operations; the on-chip address decoder is configured to provide an address interface between addresses used by a host or memory system controller and hardware addresses used by a row decoder and a column decoder. The power control module is configured to control the power and voltage supplied to the word lines and bit lines during each memory operation.

[0055] In some embodiments, the memory device 1022 may further include: a memory array of a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein,

[0056] The control circuit may be configured to: determine a selected word line from the plurality of word lines in response to a first write instruction; determine a selected bit line from the plurality of bit lines; determine a selected first physical address based on the selected word line and the selected word line; and write information associated with a first L2P pointer at the first physical address;

[0057] Among them, the first physical address is the physical address corresponding to the first physical area; the first physical area is the physical area indicated by a second element whose second identification information is a second flag, obtained from multiple physical areas indicated by a first element whose first identification information is a first flag, by the controller of the memory system using the L2P management table maintained by itself; the L2P management table is configured to include a first-level management subtable and a second-level management subtable; the first-level management subtable includes multiple first elements; each first element corresponds to a second-level management subtable; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management subtable is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element in the multiple physical areas; the second element is the second element included in the second-level management subtable corresponding to the first element; the first L2P pointer is generated or obtained by the controller based on a request for the L2P pointer; the controller is coupled to the memory device and can communicate with the memory device.

[0058] It should be noted that the first write instruction mentioned here is only for the convenience of describing the write instructions in different processes and is not used to limit the present invention. The same applies to the subsequent second write instruction. It should be understood that the first physical address is based on the word line and bit line through the control circuit to control the addressing, specifically through Figure 2 The row decoder and column decoder shown are addressed.

[0059] In some embodiments, the control circuit may further be controlled to:

[0060] In response to a read instruction or a second write instruction including the first unencrypted physical address, a selected second physical address is obtained from the plurality of word lines and the plurality of bit lines, and data is read from the second physical address or data is written to the second physical address.

[0061] In some embodiments, the memory array is a three-dimensional NAND memory array; and the memory system is a three-dimensional NAND memory device.

[0062] For memory devices, in 3D architecture semiconductor memory technology, vertical structures are stacked to increase the number of layers and physical pages, thereby increasing the density of the memory system. In one embodiment, memory system 102 can be a discrete memory or memory component of the host device. In other embodiments, memory system 102 can also be part of an integrated circuit, such as a system on a chip (SOC). In this case, memory system 102 is stacked or otherwise assembled with one or more components of host device 101.

[0063] exist Figure 1 In the environment example 100, the host device 101 may include a processor 1011 and a host RAM 1012, wherein the host RAM 1012 may include DRAM, SDRAM or any other suitable volatile or non-volatile memory device. One or more communication interfaces may be provided on the memory system 102 to communicate with one or more components in the host device 101. The one or more components in the host device 101 may be a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC TM interface, etc. The host device 101 may also include electronic components, a memory card reader, or one or more other electronic components external to the memory system 102 .

[0064] Figure 1The operating principle of the environment example 100 in FIG. 1 is as follows: the controller 1021 can receive instructions from the host device 101 and communicate with the memory device 1022. For example, the controller 1021 can transfer data to one or more memory cells, planes, sub-blocks, blocks, or pages in the memory device 1022 by executing a write or erase instruction; or the controller 1021 can transfer data to the host device 101 by executing a read instruction. In terms of hardware, the controller 1021 may include one or more controller units, circuits, or components configured to control access across the memory device 1022 and provide a translation layer between the host device 101 and the memory system 102. The controller 1021 may also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory device 1022.

[0065] The controller 1021 may further include a memory management unit 1021 - 1 and an array control unit 1021 - 2 .

[0066] The memory management unit 1021-1 may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions. To describe the technical solutions of the present invention, NAND memory is used as an example to describe the memory operation or management functions. Those skilled in the art will appreciate that other forms of non-volatile memory may have similar memory operation or management functions. NAND memory management functions may include wear leveling, such as garbage collection or recycling, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit 1021-1 may process instructions from the host device 101 into commands recognizable by the memory system 102, such as parsing or formatting instructions received from the host device 101 into commands related to the operation of the memory device 1022. Alternatively, the memory management unit 1021-1 may generate device commands for the array control unit 1021-2 or one or more other components of the memory system 102, such as commands that implement various memory management functions.

[0067] The memory management unit 1021-1 may be configured to include a set of management tables 130 for maintaining various information associated with one or more components of the memory system 102, such as various information related to the memory device 1022 or one or more memory units coupled to the controller 1021. For example, the management table 130 may include information such as the block age, block erase count, error history, or one or more error counts of one or more blocks of the memory units coupled to the controller 1021. Error counts may include operation error counts, read bit error counts, and the like. In some embodiments, if the detected error count is above a certain threshold, the bit error is considered an uncorrectable bit error. In some embodiments, the management table 130 may maintain counts of correctable or uncorrectable bit errors.

[0068] The management table 130 may also include one or more L2P tables, each containing one or more L2P pointers that associate logical addresses with physical addresses in the memory array of the memory device 1022. In some embodiments, the management table 130 may include an unencrypted L2P table and / or an encrypted L2P table. An unencrypted L2P table may include an L2P pointer indicating an unencrypted logical address and an unencrypted physical address; an encrypted L2P table may include an encrypted physical address and an encrypted L2P pointer indicating an unencrypted logical address. In actual implementation, the management table 130 may be stored in the memory management unit 1021-1, meaning that the management table 130 may be stored in the RAM of the controller 1021. In other embodiments, the management table 130 may also be stored in the memory array of the memory device 1022. During use, the memory management unit 1021-1 may read part or all of the cached management table 130 from the RAM of the controller 1021, or may read the management table 130 from the memory array of the memory device 1022.

[0069] In some embodiments, the management table 130 may also include one or more L2P management tables that store information associated with the L2P pointer. The physical area may be a flash memory space in the memory of the controller; the usage status may indicate whether a physical area in the flash memory space is free or occupied. The L2P management table provided in the embodiment of the present invention is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes multiple first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the random access memory RAM of the controller; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element in the multiple physical areas. It should be noted that the memory of the controller may be a storage medium such as RAM that can be used to store data.

[0070] In order to understand the L2P management table provided by the embodiment of the present invention, Figure 4 As shown in FIG, it is a structural diagram of the L2P management table in an embodiment of the present invention. Figure 4 In the example, it is assumed that a total of 8192 physical regions (Subregions) are set in the controller's RAM for storing information associated with L2P pointers. These physical regions are grouped into groups of 32 each, and are managed using 1 bit. In a group, when all 32 physical regions are marked as occupied, the group is marked as occupied. In a group, when at least one of the 32 physical regions is marked as free, the group is marked as free. It should be understood that the bit used for each group management described here corresponds to one of the aforementioned first elements, for example, Figure 4 Bit 0 in the middle level management subtable is the first element, which manages the physical regions numbered from Sub region 0 to Sub region 31. Each bit used for physical region management described here corresponds to a second element mentioned above, for example, Figure 4Bit 0 in the secondary management subtable is the second element, managing the physical region numbered Sub region 0. The first identification information may include a first flag and a third flag. When the first identification information is the first flag, it indicates that one of the 32 physical regions indicated is idle; when the first identification information is the third flag, it indicates that all 32 physical regions indicated are occupied. The first flag may be represented by FALSE, indicating that one of the 32 physical regions it manages is idle; the third flag may be represented by TRUE, indicating that all 32 physical regions it indicates are occupied. The second identification information may include a second flag and a fourth flag. When the second identification information is the second flag, it indicates that the physical region it indicates is idle; when the second identification information is the fourth flag, it indicates that the physical region it indicates is occupied. In some embodiments, the second flag may also be represented by FALSE; the fourth flag may also be represented by TRUE, indicating that the physical region it indicates is occupied; FALSE indicates that the physical region it indicates is idle. It should be noted that the flags used in the first and second identification information may be the same or different. The information associated with the L2P pointer includes status information of the first L2P pointer; wherein the status information indicates whether the physical address indicated by the first L2P pointer in the memory device or the RAM is valid. The associated information may include information related to the L2P pointer, such as dirty information and unmapping messages.

[0071] The array control unit 1021-2 may include circuit systems or components configured to control and perform the following memory operations, such as controlling the writing of data to one or more memory cells in the memory system 102 coupled to the controller 1021, reading data from the one or more memory cells, or erasing the one or more memory cells. The array control unit 1021-2 may receive commands sent by the host device 101 or host commands generated internally by the memory management unit 1021-1. The host commands may be commands associated with wear leveling, error detection or correction, etc.

[0072] The array control unit 1021-2 may also include an error correction code (ECC) component 140, which may include an ECC engine or other circuitry for detecting or correcting errors associated with writing data to or reading data from one or more memory cells in a memory system 102 coupled to the controller 1021. The controller 1021 is configured to effectively detect and recover from error events associated with various operations or data storage, such as bit errors, operational errors, etc., while maintaining the integrity of data transmitted between the host device 101 and the memory system 102, or maintaining the integrity of stored data, such as by using redundant RAID storage, etc., and removing, such as retiring, failed memory resources, such as memory cells, memory devices 1022, pages, blocks, etc., to prevent future errors.

[0073] The memory array of the memory device 1022 may include, for example, a number of memory cells arranged in one or more devices, one or more planes, one or more sub-blocks, one or more blocks, one or more pages, etc. As an example, a 48GB TLC NAND memory system may include 18592 bytes (B) of data per page (16384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory system (storing two bits of data per cell (i.e., 4 programmable states)) may include 18592 bytes (B) of data per page (16384+2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but the required write time is reduced by half and the program / erase (P / E) cycle is increased by two times compared to the corresponding TLC memory system. Other examples may include other numbers or arrangements. In some examples, a memory system or a portion thereof can selectively operate in an SLC mode or in an MLC mode (eg, TLC, QLC, etc.) as desired.

[0074] The memory device 1022 includes physical address locations 150A, 150B, and 150N. A physical address location is a location on the memory device 1022 that is uniquely associated with a physical address. In operation, data is typically written to or read from the memory system 102 in units of pages and erased in units of blocks. For example, the physical address locations 150A, 150B, and 150N may correspond to pages. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. Therefore, in some examples, the physical address locations 150A, 150B, and 150N include more or less than a page. The data transfer size of the memory system 102 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0075] Although a page of data may include several bytes of user data (e.g., a data payload comprising several data sectors) and its corresponding metadata, the size of the page generally refers only to the number of bytes used to store the user data. As an example, a data page with a page size of 4KB may include 4KB of user data (e.g., 8 sectors with a sector size of 512B) and several bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data. The physical address locations used to store metadata, etc. may be referred to as over-provisioned physical address locations.

[0076] Different types of memory cells or the memory devices 1022 may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory system types may have different bit error rates, which may result in different amounts of metadata required to ensure the integrity of a data page (e.g., a memory system with a higher bit error rate may require more bytes of error correction code data than a memory system with a lower bit error rate). For example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Thus, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0077] Based on the aforementioned environment example 100, Figure 5 As shown, it shows a flowchart of a processing flow 300 in which the controller 1021 of the memory system 102 in the data processing system provided by an embodiment of the present invention calls the L2P management table to search for a free physical area in the controller memory after responding to a request for an L2P pointer from a host device.

[0078] That is, the controller is programmed to perform the following operations, specifically including:

[0079] S3001: Maintain an L2P management table; wherein the L2P management table is configured to include a first-level management subtable and a second-level management subtable; the first-level management subtable includes multiple first elements; each first element corresponds to a second-level management subtable; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management subtable is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas.

[0080] In actual application, the controller responds to the request for the L2P pointer sent from the host device, which may include:

[0081] receiving a request for an L2P pointer from the host device; identifying a first logical address included in the request;

[0082] Generate or access the first L2P pointer corresponding to the first logical address; and send the first L2P pointer to the host device.

[0083] In some embodiments, generating or accessing the first L2P pointer corresponding to the first logical address may include:

[0084] determining whether the memory system includes a first L2P pointer indicating the first logical address;

[0085] Upon determining that the memory system includes a first L2P pointer indicating the first logical address, accessing an L2P table in the memory device or the RAM and obtaining the first L2P pointer from the L2P table;

[0086] When it is determined that the memory system does not include a first L2P pointer indicating the first logical address, the first L2P pointer indicating the first logical address is generated; and the first L2P pointer is stored in an L2P table.

[0087] It should be noted that the L2P management table may be multiple physical areas specifically allocated in the controller's memory for storing information associated with L2P pointers in the L2P table; each of these multiple physical areas can store all information associated with an L2P pointer. In some embodiments, all of the associated information may include L2P pointer status information, dirty information, and unmapping information, among other information related to the L2P pointer. The status information indicates whether the physical address indicated by the first L2P pointer in the memory device or the controller is valid; the dirty information may refer to a dirty mapping; and the unmapping message may cancel the mapping relationship between the logical address and the physical address indicated by the L2P pointer.

[0088] The form of the L2P management table has been described in detail above and will not be repeated here. In actual application, the L2P management table in step S3001 may have been previously established and stored in the memory system.

[0089] In actual application, the L2P management table can store the random access memory RAM of the controller for use when needed. After the controller 1021 receives a request for the L2P pointer from the host device 101, it calls the L2P management table to store the status information of the L2P pointer.

[0090] For example, if you are using the Host Performance Boost (HPB ， Host Performance Booster improves the data processing system in host performance mode. When the host requests an L2P pointer, the firmware code of the memory system needs to find an idle sub region in the L2P management table in the memory system after responding to the request. The specific principle is as follows: Figure 6 As shown. Figure 6 In the figure, the host device 101 is another representation of the host Host.

[0091] S3002: After responding to a request for an L2P pointer sent from the host device, using the L2P management table, obtain a physical area indicated by a second element whose second identification information is a second flag from the multiple physical areas indicated by a first element whose first identification information is a first flag; the second element is a second element contained in the secondary management subtable corresponding to the first element.

[0092] In some embodiments, using the L2P management table to obtain, from the multiple physical areas indicated by a first element of a first flag in the first identification information, a physical area indicated by a second element of a second flag in which the second identification information is present, may include:

[0093] Searching in a first-level management subtable in the L2P management table to obtain a first element of a first flag, wherein the first identification information is a first element of a first flag, wherein the first element of the first flag is a physical area in a usage state of idle among the multiple physical areas indicated by the first element;

[0094] Searching in the secondary management subtable corresponding to a first element of the first flag, obtaining a second identification information as a second element of the second flag; the use status of the physical area indicated by the second element of the second flag is idle;

[0095] A physical area indicated by a second element of the second flag is obtained.

[0096] It should be noted that the first flag can be the aforementioned FALSE; the second flag can also be the aforementioned FALSE, but the first flag and the second flag represent different meanings. It can be seen from the above description that the L2P management table provided by the embodiment of the present invention is a two-level management table. When in use, it is necessary to first search in the first-level management subtable to obtain the first element with the first identification information as the first flag, wherein the first identification information as the first flag can mean that the multiple physical areas indicated by the first element found contain physical areas with a usage status of idle, that is, not all occupied; then search in the second-level management subtable corresponding to the first element found to obtain the second element with the second identification information as the second flag; the second identification information as the second flag can mean that the usage status of the physical area indicated by the second element found is idle, that is, not occupied.

[0097] Specifically, during the programming process, the first-level management subtable may be an array consisting of a plurality of first elements, and the second-level management subtable may be an array consisting of a plurality of second elements. Based on this, in some embodiments, searching the first-level management subtable in the L2P management table to obtain a first element whose first identification information is a first flag may include:

[0098] Searching is performed in ascending order according to the subscripts of the first elements, or searching is performed in descending order according to the subscripts of the first elements, and the search is stopped when the first element whose first identification information is the first flag appears for the first time;

[0099] Correspondingly, searching in the secondary management subtable corresponding to a first element of the first flag to obtain a second element of the second flag whose second identification information is a second element may include:

[0100] The search is performed in ascending order according to the subscripts of the second elements, or the search is performed in descending order according to the subscripts of the second elements, and the search is stopped when the second element whose second identification information is the second mark appears for the first time.

[0101] It should be noted that in the aforementioned search algorithm, the physical areas in the controller's memory can be arranged in ascending order of first address. This search algorithm searches from the beginning in the order of the physical area codes, and stops searching when the first physical area that meets the requirements appears. Other search algorithms may also be used in specific applications.

[0102] For example, assuming that the L2P management table manages 8192 physical regions in the memory of the controller, and the codes of the physical regions are Sub region 0, Sub region 1, ..., Sub region 8191 in sequence; according to the aforementioned search idea, the first-level management subtable contains 256 bits, that is, it contains 256 first elements; each first element corresponds to a second-level management subtable, each second-level management subtable corresponds to 32 bits, and each bit corresponds to a physical region. The search algorithm can be as follows: Figure 7 The array representation shown is written, and the specific search code can be as follows Figure 8 As shown. Figure 7 In the example, each element in u32_a[0]-u32_a[7] corresponds to a 32-bit in the first-level management subtable; this 32-bit is managed by the array u8_b[0]-u8_b[3]; and the 8192 physical areas are represented by 256 32-bit u32_c[0]-u32_c

[255] . The search logic is to search in the first-level management subtable based on the arrays u32_a[0]-u32_a[7] and u8_b[0]-u8_b[3], and then search in the second-level management subtable corresponding to the first element obtained, until an idle physical area is found.

[0103] S3003: Use a physical area indicated by a second element of the second flag to store information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request.

[0104] In actual application, the information associated with the first L2P pointer includes status information of the first L2P pointer; wherein the status information is used to indicate whether the physical address indicated by the first L2P pointer in the memory of the storage device or the controller is valid. The memory may be RAM.

[0105] In summary, the free physical area search method provided by the embodiment of the present invention is more efficient than the single-level management table. Figure 9 As shown, it can greatly reduce the overhead of finding free physical areas, for example, Figure 4 and Figure 9 For physical areas with the same number, when the host device needs the memory system to perform memory allocation searches, the number of searches can be reduced from a maximum of 8192 times to 256+32 times, greatly improving the reading and writing speed.

[0106] In actual application, the controller is further programmed to perform the following operations, which may include:

[0107] In response to a request for a set of L2P pointers sent from the host device, calling the L2P management table;

[0108] Determining a physical area in an idle state for each second L2P pointer based on the L2P management table; each second L2P pointer is generated or obtained by accessing each corresponding second logical address included in a request by the controller based on the set of L2P pointers;

[0109] Information associated with the corresponding second L2P pointer is stored in each corresponding physical area in the idle state.

[0110] What is described here is that when a host device sends a request to the memory system for a set of L2P pointers, the memory system, in response to the request, invokes the L2P management table to locate a free physical area in the controller's RAM for each second L2P pointer obtained based on the request, thereby storing the associated information corresponding to the second L2P pointer. For example, when a host device sends a request to the memory system for five L2P pointers, the memory system, in response to the request, invokes the L2P management table to locate a free physical area in the controller's RAM for each of the five second L2P pointers obtained based on the request, thereby storing the associated information corresponding to the second L2P pointer.

[0111] In some embodiments, the memory system may be a three-dimensional non-volatile memory system, and the memory device may be a memory array including a plurality of memory blocks; wherein the memory blocks include a plurality of levels.

[0112] In other embodiments, the memory array may be a three-dimensional NAND memory array; and the three-dimensional non-volatile memory system may be a three-dimensional NAND memory system.

[0113] Based on the above description, Figure 10 , which shows a schematic diagram of a processing flow 800 of a memory system 102 responding to a request for an L2P pointer sent by a host device. Figure 10 8. In FIG. 8, process flow 800 includes two columns 801 and 802. Column 801 includes operations performed by a host device, such as host device 101. Column 802 includes operations performed by a memory system, such as memory system 102.

[0114] In step 8011, host device 101 generates a read / write request for an L2P pointer. The read / write request may be generated by an operating system of host device 101 and / or may be received from an application executing on host device 101. In step 8012, host device 101 receives a first L2P pointer fed back by memory system 102 and caches the first L2P pointer.

[0115] After receiving the request for the L2P pointer sent from the host device, the memory system 102 identifies the first logical address in the request (step 8021); generates or accesses the first L2P pointer corresponding to the first logical address (step 8022); calls the L2P management table (step 8023); initially searches in the first-level management subtable of the management table to obtain the first element in which the first identification information appears as the first flag for the first time (step 8024); searches again in the second-level management subtable corresponding to the first element to obtain the second element in which the second identification information appears as the second flag for the first time (step 8025); and stores information associated with the first L2P pointer in the physical area corresponding to the second element (step 8026).

[0116] Based on the aforementioned various examples of the memory system 102 and the host device 101, Figure 11 FIG. 1 shows a schematic diagram of a structure of an application scenario of the aforementioned memory system 102 and a host device. Figure 11In the application scenario shown, the memory system 102 and host device 101 disclosed herein can be part of one or more devices 930-950. A device includes any device that can include a host device such as host device 101. Host device 101 can be any device that can execute instructions (in sequence or otherwise). For example, the device is a vehicle 930, and the memory system and host device 101 can be part of an infotainment system, a control system, etc.; for another example, the device includes an unmanned aircraft 950, and the memory system and host device 101 disclosed herein can be part of a control system; for another example, if the device is smart furniture or equipment 940, the memory system and host device 101 disclosed herein can be part of a sensor system, an entertainment or infotainment system, etc. In other examples, although not shown, the device may include aviation, marine, Internet of Things (IoT), and other devices.

[0117] Figure 12 A block diagram of an example machine 1000 is shown on which any one or more techniques (e.g., methods) discussed herein may be performed. In alternative embodiments, the machine 1000 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a network deployment, the machine 1000 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 1000 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1000 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any machine capable of executing instructions (in sequence or otherwise) specifying actions to be taken by the machine. Furthermore, although only a single machine is shown, the term "machine" should also be construed to include any collection of machines that, alone or in combination, execute an instruction set (or multiple instruction sets) to perform any one or more of the methods discussed herein, such as cloud computing, software as a service (SaaS), or other computer cluster configurations.

[0118] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by them. A circuit system is a collection of circuits (e.g., a group of circuits) implemented in a tangible entity including hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can change flexibly over time and with potential hardware variability. A circuit system includes members that can perform specific tasks individually or in combination when in operation. In an example, the hardware of the circuit system can be designed to perform specific operations (e.g., hardwired) invariably. In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that are physically modified (e.g., magnetically, electrically, movably placed particles of constant mass, etc.) to encode instructions for specific operations. When the physical components are connected, the basic electrical properties of the hardware components change, such as from an insulator to a conductor, and vice versa. The instructions enable the addition of hardware (e.g., execution units or loading mechanisms) to create members of the circuit system in hardware via variably connected components to perform a portion of a specific task when in operation. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any physical component can be used in more than one member of more than one circuit system. For example, in operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and can be reused by a second circuit in the first circuit system or a third circuit in the second circuit system at a different time.

[0119] A machine (e.g., a computer system) 1000 (e.g., a host device 101, a memory system 102, etc.) may include a hardware processor 10001 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, such as a memory controller 1021, etc.), a main memory 10003, and a static memory 10005, some or all of which may communicate with each other via an interconnect (e.g., a bus) 10011. The machine 1000 may also include a display unit 10012, an alphanumeric input device 10013 (e.g., a keyboard), and a user interface (UI) navigation device 10014 (e.g., a mouse). In an example, the display unit 10012, the input device 10013, and the UI navigation device 10014 may be a touch screen display. The machine 1000 may further include a storage device (e.g., a drive unit) 10018, a signal generating device 10016 (e.g., a speaker), a network interface device 10009, and one or more sensors 10015, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 1000 may include an output controller 10017, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC)), etc.) connection, to communicate with or control one or more peripheral devices (e.g., printers, card readers, etc.).

[0120] The storage device 10018 may include a machine-readable medium 10007 on which one or more sets of data structures or instructions 10004 (e.g., software) are stored that embody or are used by any one or more techniques or functions described herein. During execution of the instructions 10004 by the machine 1000, the instructions may also reside, in whole or in part, within the main memory 10003, the static memory 10005, or the hardware processor 10001. In an example, one or any combination of the hardware processor 10001, the main memory 10003, the static memory 10005, or the storage device 10018 may constitute the machine-readable medium 10007.

[0121] Although the machine-readable medium 10007 is illustrated as a single medium, the term "machine-readable medium" may also include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 10004.

[0122] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions to be executed by the machine 1000 and causing the machine 1000 to perform any one or more techniques of the present invention, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In an example, a mass machine-readable medium comprises a machine-readable medium having a plurality of particles having a constant (e.g., stationary) mass. Thus, a mass machine-readable medium is not a transient propagating signal. Specific examples of mass machine-readable media may include: non-volatile memory, such as semiconductor memory systems (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory systems; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0123] Instructions 10004 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage device 10006 and can be accessed by memory 1004 for use by processor 10001. Memory 1004 (e.g., DRAM) is typically fast but volatile, and therefore a different type of storage than storage device 10006 (e.g., SSD), which is suitable for long-term storage, including when in an "off" state. Instructions 10004 or data being used by a user or machine 1000 are typically loaded into memory 1004 for use by processor 10001. When memory 1004 is full, virtual space from storage device 10006 can be allocated to supplement memory 1004; however, because memory device 10006 is typically slower than memory 1004, with write speeds typically at least twice as slow as read speeds, the use of virtual memory can significantly degrade the user experience (compared to memory 1004, such as DRAM) due to memory device latency. Furthermore, using storage device 10006 for virtual memory may significantly shorten the useful life of storage device 10006 .

[0124] Compared to virtual memory, virtual memory compression (e.g., the kernel feature "ZRAM") uses a portion of memory stored as compressed blocks to avoid paging to storage device 10006. Paging occurs in compressed blocks until it is necessary to write such data to storage device 10006. Virtual memory compression increases the available size of memory 1004 while reducing wear on storage device 10006.

[0125] Memory devices optimized for mobile electronic devices or mobile storage traditionally include MMC solid-state memory devices (e.g., micro secure digital (microSDTM) cards, etc.). MMC devices include several parallel interfaces (e.g., 8-bit parallel interfaces) with host devices, and components that are usually removable and separate from the host device. In contrast, eMMCTM devices are attached to circuit boards and are considered components of host devices, with read speeds comparable to serial ATATM (serial AT (Advanced Technology) Attachment or SATA) based on SSD devices. However, the demand for mobile device performance continues to grow, such as to fully enable virtual devices or augmented reality devices, to utilize growing network speeds, etc. In response to this demand, memory devices have been converted from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including controllers and firmware) communicate with host devices using a low voltage differential signaling (LVDS) serial interface with a dedicated read / write path, thereby further facilitating higher read / write speeds.

[0126] Instructions 10004 may also be transmitted or received over a communication network 10010 using a transmission medium via a network interface device 10009 using any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, the IEEE 802.16 series of standards), the IEEE 802.15.4 series of standards, a peer-to-peer (P2P) network, etc. In an example, the network interface device 10009 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 10010. In an example, the network interface device 10009 may include multiple antennas to enable wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission medium" should be understood to include any intangible medium capable of storing, encoding, or carrying instructions to be executed by the machine 1000, and includes digital or analog communication signals or other intangible media to facilitate communication of such software.

[0127] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show, by way of illustration, specific embodiments in which the present invention may be implemented. These embodiments are also referred to herein as "examples." These examples may include elements other than those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. In addition, the present inventors also contemplate examples using any combination or permutation of those elements (or one or more aspects thereof) shown or described relative to the specific examples (or one or more aspects thereof) shown or described herein, or relative to other examples (or one or more aspects thereof).

[0128] In this document, as commonly used in patent documents, the terms "a" or "an" are used to include one or more than one, independent of any other instances or uses of "at least one" or "one or more." In this document, unless otherwise stated, the term "or" is used to refer to a non-exclusive or, such that "A or B" may include "A but not B," "B but not A," and "A and B." In the following claims, the terms "including" and "among which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Furthermore, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements in addition to those listed after the term in the claim are still considered to fall within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0129] In various examples, the components, controllers, processors, units, engines, or tables described herein may include physical circuitry or firmware stored on a physical device, etc. As used herein, a "processor" refers to any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or a multi-core device.

[0130] As used in this document, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of a substrate, such as the plane beneath a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal direction defined above. Prepositions (such as "on," "over," and "under") are defined with respect to a conventional plane or surface on the top or exposed surface of a substrate, regardless of the orientation of the substrate; and "on" is intended to indicate direct contact of one structure relative to another structure (in the absence of an explicit indication to the contrary) that the structure is "above" the other structure; the terms "on" and "under" are expressly intended to identify the relative arrangement of structures (or layers, features, etc.), which explicitly includes, but is not limited to, direct contact between the identified structures, unless specifically identified as such. Similarly, the terms "on" and "under" are not limited to a horizontal orientation, as a structure may be "on" if, at a certain point in time, it is the outermost portion of the structure in question, even if such a structure extends vertically relative to a reference structure, rather than being horizontally oriented.

[0131] As used herein, the terms "wafer" and "substrate" generally refer to any structure on which an integrated circuit is formed, and also refer to these structures during the various stages of integrated circuit fabrication. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0132] Various embodiments according to the present invention and described herein include memories utilizing a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, orientation adjectives are applied relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure is considered to extend away from the substrate surface, a bottom end of a vertical structure is considered to be the end closest to the substrate surface, and a top end of a vertical structure is considered to be the end farthest from the substrate surface).

[0133] As used herein, orientation adjectives (such as horizontal, vertical, normal, parallel, perpendicular, etc.) may refer to relative orientations and are not intended to require strict adherence to specific geometric properties unless otherwise indicated. For example, as used herein, a vertical structure need not be strictly perpendicular to the surface of the substrate, but may be approximately perpendicular to the surface of the substrate and may form an acute angle (e.g., between 80 and 120 degrees, etc.) with the surface of the substrate.

[0134] In some embodiments described herein, different doping configurations may be applied to a source-side select gate (SGS), a control gate (CG), and a drain-side select gate (SGD), each of which in this example may be formed of or at least include polysilicon. As a result, these layers (e.g., polysilicon, etc.) may have different etch rates when exposed to an etching solution. For example, during the formation of a single pillar in a 3D semiconductor device, the SGS and CG may be recessed, while the SGD may remain less recessed or even not recessed. These doping configurations can thus enable selective etching into different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide, TMCH).

[0135] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a given state is referred to herein as "programming" and can include both writing to the memory cell and erasing from the memory cell (i.e., a memory cell can be programmed to an erased state).

[0136] According to one or more embodiments of the present invention, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory system can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count operations occurring in the memory system, track operations initiated by the memory system, evaluate memory system characteristics corresponding to the wear states, etc.).

[0137] According to one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to a memory system with each memory operation. Memory system control circuitry (e.g., control logic) may be programmed to compensate for changes in memory system performance corresponding to the wear cycle information. The memory system may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0138] It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, directly connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers present. If two elements are shown in the drawings as being connected by a line, then the two elements may be coupled or directly coupled unless otherwise specified.

[0139] The method examples described herein may be implemented at least in part by a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions that are operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to: a hard disk, a removable magnetic disk, a removable optical disk (e.g., a compact disc and a digital video disc), a magnetic cassette, a memory card or stick, a random access memory (RAM), a read-only memory (ROM), a solid-state drive (SSD), a universal flash storage (UFS) device, an embedded MMC (eMMC) device, and the like.

[0140] Examples:

[0141] Example 1 is a memory device comprising: a memory array of a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein,

[0142] The control circuit is configured to: in response to a first write instruction, determine a selected word line from the plurality of word lines; determine a selected bit line from the plurality of bit lines; determine a selected first physical address based on the selected word line and the selected word line; and write information associated with a first L2P pointer at the first physical address;

[0143] Among them, the first physical address is the physical address corresponding to the first physical area; the first physical area is the physical area indicated by a second element whose second identification information is a second flag, obtained from multiple physical areas indicated by a first element whose first identification information is a first flag, by the controller of the memory system using the L2P management table maintained by itself; the L2P management table is configured to include a first-level management subtable and a second-level management subtable; the first-level management subtable includes multiple first elements; each first element corresponds to a second-level management subtable; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management subtable is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element in the multiple physical areas; the second element is the second element included in the second-level management subtable corresponding to the first element; the first L2P pointer is generated or obtained by the controller based on a request for the L2P pointer; the controller is coupled to the memory device and can communicate with the memory device.

[0144] In Example 2, the subject matter of Example 1 optionally, wherein the control circuit is further controlled to:

[0145] In response to a read instruction or a second write instruction including the first unencrypted physical address, a selected second physical address is obtained from the plurality of word lines and the plurality of bit lines, and data is read from the second physical address or data is written to the second physical address.

[0146] In Example 3, the subject matter of any one of Examples 1 to 2 optionally includes the memory array being a three-dimensional NAND memory array; and the memory system being a three-dimensional NAND memory device.

[0147] Example 4 is a data processing system, comprising: a memory system and a host device;

[0148] The memory system includes a memory device and a controller, wherein the memory device stores a logical-to-physical L2P table;

[0149] The controller is programmed to perform the following operations, including:

[0150] Maintaining an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas;

[0151] After responding to a request for an L2P pointer sent from the host device, using the L2P management table, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, obtain a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element;

[0152] A physical area indicated by a second element of the second flag is used to store information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request.

[0153] In Example 5, the subject matter of Example 4 may optionally include: using the L2P management table to obtain, from the plurality of physical areas indicated by a first element of a first flag in the first identification information, a physical area indicated by a second element of a second flag in the second identification information, comprising:

[0154] Searching in a first-level management subtable in the L2P management table to obtain a first element of a first flag, wherein the first identification information is a first element of a first flag, wherein the first element of the first flag is a physical area in a usage state of idle among the multiple physical areas indicated by the first element;

[0155] Searching in the secondary management subtable corresponding to a first element of the first flag, obtaining a second identification information as a second element of the second flag; the use status of the physical area indicated by the second element of the second flag is idle;

[0156] A physical area indicated by a second element of the second flag is obtained.

[0157] In Example 6, optionally, the subject matter of Example 5, wherein the first-level management subtable is an array consisting of a plurality of first elements; the second-level management subtable is an array consisting of a plurality of second elements, and the searching in the first-level management subtable in the L2P management table to obtain a first element whose first identification information is a first flag includes:

[0158] Searching is performed in ascending order according to the subscripts of the first elements, or searching is performed in descending order according to the subscripts of the first elements, and the search is stopped when the first element whose first identification information is the first flag appears for the first time;

[0159] Correspondingly, searching in the secondary management subtable corresponding to a first element of the first flag to obtain a second element of the second flag whose second identification information is a second element includes:

[0160] The search is performed in ascending order according to the subscripts of the second elements, or the search is performed in descending order according to the subscripts of the second elements, and the search is stopped when the second element whose second identification information is the second identifier appears for the first time.

[0161] In Example 7, the subject matter of Example 4 optionally, the information associated with the first L2P pointer includes status information of the first L2P pointer; wherein the status information is used to indicate whether the physical address indicated by the first L2P pointer in the memory of the storage device or the controller is valid.

[0162] In Example 8, the subject matter of Example 4 optionally, wherein the controller, in response to a request for an L2P pointer sent from the host device, comprises:

[0163] receiving a request for an L2P pointer from the host device; identifying a first logical address included in the request;

[0164] Generate or access the first L2P pointer corresponding to the first logical address; and send the first L2P pointer to the host device.

[0165] In Example 9, the subject matter of Example 4, optionally, the controller is further programmed to perform the following operations, including:

[0166] In response to a request for a set of L2P pointers sent from the host device, calling the L2P management table;

[0167] Determining a physical area in an idle state for each second L2P pointer based on the L2P management table; each second L2P pointer is generated or obtained by accessing each corresponding second logical address included in a request by the controller based on the set of L2P pointers;

[0168] Information associated with the corresponding second L2P pointer is stored in each corresponding physical area in the idle state.

[0169] In Example 10, the subject matter of Example 8 optionally, wherein generating or accessing the first L2P pointer corresponding to the first logical address comprises:

[0170] determining whether the memory system includes a first L2P pointer indicating the first logical address;

[0171] Upon determining that the memory system includes a first L2P pointer indicating the first logical address, accessing an L2P table in a memory of the memory device or the controller, and obtaining the first L2P pointer from the L2P table;

[0172] When it is determined that the memory system does not include a first L2P pointer indicating the first logical address, the first L2P pointer indicating the first logical address is generated; and the first L2P pointer is stored in an L2P table.

[0173] In Example 11, the subject matter of any one of Examples 4 to 10 is optionally, wherein the memory system is a three-dimensional non-volatile memory system, the memory device is a memory array including a plurality of memory blocks; wherein the memory blocks include a plurality of levels.

[0174] In Example 12, the subject matter of Example 11 optionally, the memory array is a three-dimensional NAND memory array; and the three-dimensional non-volatile memory system is a three-dimensional NAND memory system.

[0175] Example 13 is a data processing method applied to a data processing system including a memory system and a host device, wherein the memory system includes a memory device and a controller, wherein the memory device stores a logical-to-physical L2P table, the method comprising:

[0176] The controller maintains an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas;

[0177] The controller, in response to a request for an L2P pointer sent from the host device, uses the L2P management table to obtain, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element;

[0178] The controller uses a second element of the second flag to indicate a physical area for storing information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request.

[0179] In Example 14, the subject matter of Example 13 may optionally include: using the L2P management table to obtain, from the plurality of physical areas indicated by a first element of a first flag in the first identification information, a physical area indicated by a second element of a second flag in the second identification information, comprising:

[0180] The controller searches a first-level management subtable in the L2P management table to obtain a first element of a first flag, wherein the first identification information is a first element of a first flag; the first element of the first flag is a physical area in a usage state of idle among the multiple physical areas indicated by the first element;

[0181] The controller searches in the secondary management subtable corresponding to a first element of the first flag to obtain the second identification information as a second element of the second flag; the use status of the physical area indicated by the second element of the second flag is idle;

[0182] The controller obtains a physical area indicated by a second element of the second flag.

[0183] In Example 15, the subject matter of Example 14 is optionally configured such that, when the first-level management subtable is an array consisting of a plurality of first elements and the second-level management subtable is an array consisting of a plurality of second elements, searching the first-level management subtable in the L2P management table to obtain a first element whose first identification information is a first flag includes: searching, by the controller, in ascending order of subscripts of the first elements, or searching in descending order of subscripts of the first elements, and stopping searching when the first element whose first identification information is the first flag first appears;

[0184] Correspondingly, the search is performed in the secondary management subtable corresponding to a first element of the first flag to obtain a second element whose second identification information is a second flag, including: the controller searches in ascending order according to the subscripts of the second elements, or searches in descending order according to the subscripts of the second elements, and stops searching when the second element whose second identification information is a second flag appears for the first time.

[0185] In Example 16, the subject matter of Example 13 is optionally, wherein the information associated with the first L2P pointer includes status information of the first L2P pointer; wherein the status information is used to indicate whether the physical address indicated by the first L2P pointer in the memory of the storage device or the controller is valid.

[0186] In Example 17, the subject matter of Example 13 is optionally, wherein the response to the request for the L2P pointer sent from the host device includes: receiving, by the controller, the request for the L2P pointer sent from the host device; identifying a first logical address included in the request; generating or accessing the first L2P pointer corresponding to the first logical address; and sending the first L2P pointer to the host device.

[0187] In Example 18, the subject matter of Example 13 optionally further includes: after the controller responds to a request for a group of L2P pointers sent from the host device, calling the L2P management table; determining a physical area in an idle state for each second L2P pointer based on the L2P management table; each second L2P pointer is generated or obtained by accessing each corresponding second logical address included in the request of the controller based on the group of L2P pointers; and storing information associated with the corresponding second L2P pointer in each corresponding physical area in an idle state.

[0188] In Example 19, the subject matter of Example 17 is optionally, wherein the generating or accessing the first L2P pointer corresponding to the first logical address includes: determining, by the controller, whether the memory system includes a first L2P pointer indicating the first logical address; upon determining that the memory system includes the first L2P pointer indicating the first logical address, accessing an L2P table in a memory of the memory device or the controller, and obtaining the L2P pointer from the L2P table; upon determining that the memory system does not include the first L2P pointer indicating the first logical address, generating the first L2P pointer indicating the first logical address; and storing the first L2P pointer in the L2P table.

[0189] In Example 20, the subject matter of any one of Examples 13 to 19 is optionally, wherein the memory system is a three-dimensional non-volatile memory system, the memory device is a memory array including a plurality of memory blocks; wherein the memory blocks include a plurality of levels.

[0190] In Example 21, the subject matter of Example 20 is optional, wherein the memory array is a three-dimensional NAND memory array; and the three-dimensional non-volatile memory system is a three-dimensional NAND memory system.

[0191] Example 22 is a computer-readable medium comprising instructions thereon, which, when executed by a processor, cause the processor to perform the following operations:

[0192] Maintaining an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in a memory of a controller in a certain memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of a physical area corresponding to the second element among the multiple physical areas;

[0193] In response to a request for an L2P pointer sent from the host device, using the L2P management table, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, obtain a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element;

[0194] A physical area indicated by a second element of the second flag is used to store information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request;

[0195] The host device is capable of communicating with the memory system.

[0196] In Example 23, the subject matter of Example 22 optionally further includes instructions thereon, which, when executed by a processor, cause the processor to perform the following operations, including:

[0197] The step of using the L2P management table to obtain, from the plurality of physical areas indicated by a first element of a first flag in the first identification information, a physical area indicated by a second element of a second flag in which the second identification information is present, includes:

[0198] Searching in a first-level management subtable in the L2P management table to obtain a first element of a first flag, wherein the first identification information is a first element of a first flag, wherein the first element of the first flag is a physical area in a usage state of idle among the multiple physical areas indicated by the first element;

[0199] Searching in the secondary management subtable corresponding to a first element of the first flag, obtaining a second identification information as a second element of the second flag; the use status of the physical area indicated by the second element of the second flag is idle;

[0200] A physical area indicated by a second element of the second flag is obtained.

[0201] In Example 24, the subject matter of Example 23 optionally further includes instructions thereon, which, when executed by a processor, cause the processor to perform the following operations:

[0202] When the first-level management subtable is an array consisting of a plurality of first elements and the second-level management subtable is an array consisting of a plurality of second elements, searching the first-level management subtable in the L2P management table to obtain a first element whose first identification information is a first flag includes:

[0203] Searching is performed in ascending order of the subscripts of the first elements, or searching is performed in descending order of the subscripts of the first elements, and the search stops when the first element whose first identification information is the first flag appears for the first time;

[0204] Correspondingly, searching in the secondary management subtable corresponding to a first element of the first flag to obtain a second element of the second flag whose second identification information is a second element includes:

[0205] The search is performed in ascending order of the subscripts of the second elements, or the search is performed in descending order of the subscripts of the second elements, and the search is stopped when the second element whose second identification information is the second mark appears for the first time.

[0206] In Example 25, the subject matter of Example 22 is optional, wherein the information associated with the first L2P pointer includes status information of the first L2P pointer; wherein the status information is used to indicate whether the physical address indicated by the first L2P pointer in the memory of the storage device or the controller is valid.

[0207] In Example 26, the subject matter of Example 22 optionally further includes instructions thereon that, when executed by a processor, cause the processor to perform operations, the controller responding to a request for an L2P pointer sent from the host device, comprising:

[0208] receiving a request for an L2P pointer from the host device; identifying a first logical address included in the request;

[0209] Generate or access the first L2P pointer corresponding to the first logical address; and send the first L2P pointer to the host device.

[0210] In Example 27, the subject matter of Example 22 optionally further includes instructions thereon that, when executed by a processor, cause the processor to perform the following operations:

[0211] In response to a request for a set of L2P pointers sent from the host device, calling the L2P management table;

[0212] Determining a physical area in an idle state for each second L2P pointer based on the L2P management table; each second L2P pointer is generated or obtained by accessing each corresponding second logical address included in a request by the controller based on the set of L2P pointers;

[0213] Information associated with the corresponding second L2P pointer is stored in each corresponding physical area in the idle state.

[0214] In Example 28, the subject matter of Example 26 optionally further includes instructions thereon, which, when executed by a processor, cause the processor to perform the following operations, wherein generating or accessing the first L2P pointer corresponding to the first logical address comprises:

[0215] determining whether the memory system includes a first L2P pointer indicating the first logical address;

[0216] Upon determining that the memory system includes a first L2P pointer indicating the first logical address, accessing an L2P table in a memory of the memory device or the controller, and obtaining the first L2P pointer from the L2P table;

[0217] When it is determined that the memory system does not include a first L2P pointer indicating the first logical address, the first L2P pointer indicating the first logical address is generated; and the first L2P pointer is stored in an L2P table.

[0218] In Example 29, optionally according to any one of Examples 22 to 28, the memory system is a three-dimensional non-volatile memory system, the memory device is a memory array including a plurality of memory blocks; wherein the memory blocks include a plurality of levels.

[0219] In Example 30, the subject matter of Example 29 is optional, wherein the memory array is a three-dimensional NAND memory array; and the three-dimensional non-volatile memory system is a three-dimensional NAND memory system.

[0220] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used, such as those available to a person of ordinary skill in the art upon reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present invention. This should not be interpreted as meaning that unclaimed disclosed features are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment, and it is expected that these embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. A memory device comprising: a memory array of a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a control circuit coupled to the plurality of word lines and the plurality of bit lines; wherein The control circuit is configured to: determine a selected word line from the plurality of word lines in response to a first write command; determining a selected bit line from the plurality of bit lines; determining a selected first physical address based on the selected word line and the selected word line; Writing information associated with the first L2P pointer to the first physical address; Among them, the first physical address is the physical address corresponding to the first physical area; the first physical area is the physical area indicated by a second element whose second identification information is a second flag, obtained from multiple physical areas indicated by a first element whose first identification information is a first flag, by the controller of the memory system using the L2P management table maintained by itself; the L2P management table is configured to include a first-level management subtable and a second-level management subtable; the first-level management subtable includes multiple first elements; each first element corresponds to a second-level management subtable; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management subtable is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element in the multiple physical areas; the second element is the second element included in the second-level management subtable corresponding to the first element; the first L2P pointer is generated or obtained by the controller based on a request for the L2P pointer; the controller is coupled to the memory device and can communicate with the memory device.

2. The memory device according to claim 1, wherein The control circuit is further controlled to: In response to a read instruction or a second write instruction including the first unencrypted physical address, a selected second physical address is obtained from the plurality of word lines and the plurality of bit lines, and data is read from the second physical address or data is written to the second physical address.

3. The memory device according to any one of claims 1 to 2, wherein: The memory array is a three-dimensional NAND memory array; and the memory system is a three-dimensional NAND memory device.

4. A data processing system comprising: A memory system and a host device; the memory system comprising a memory device and a controller coupled to the memory device, wherein The controller is programmed to perform the following operations, including: Maintaining an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas; After responding to a request for an L2P pointer sent from the host device, using the L2P management table, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, obtain a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element; A physical area indicated by a second element of the second flag is used to store information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request.

5. The system according to claim 4, wherein: The step of using the L2P management table to obtain, from the plurality of physical areas indicated by a first element of a first flag in the first identification information, a physical area indicated by a second element of a second flag in which the second identification information is present, includes: Searching in a first-level management subtable in the L2P management table to obtain a first element of a first flag, wherein the first identification information is a first element of a first flag, wherein the first element of the first flag is a physical area in a usage state of idle among the multiple physical areas indicated by the first element; Searching in the secondary management subtable corresponding to a first element of the first flag, obtaining a second identification information as a second element of the second flag; the use status of the physical area indicated by the second element of the second flag is idle; A physical area indicated by a second element of the second flag is obtained.

6. The system according to claim 5, wherein the first-level management subtable is an array consisting of a plurality of first elements; the second-level management subtable is an array consisting of a plurality of second elements, and the searching the first-level management subtable in the L2P management table to obtain a first element whose first identification information is a first flag comprises: Searching is performed in ascending order according to the subscripts of the first elements, or searching is performed in descending order according to the subscripts of the first elements, and the search is stopped when the first element whose first identification information is the first flag appears for the first time; Correspondingly, searching in the secondary management subtable corresponding to a first element of the first flag to obtain a second element of the second flag whose second identification information is a second element includes: The search is performed in ascending order according to the subscripts of the second elements, or the search is performed in descending order according to the subscripts of the second elements, and the search is stopped when the second element whose second identification information is the second identifier appears for the first time.

7. The system of claim 4, wherein the information associated with the first L2P pointer comprises state information of the first L2P pointer; The status information is used to indicate whether the physical address indicated by the first L2P pointer in the memory of the memory device or the controller is valid.

8. The system of claim 4 , wherein the controller, in response to a request for an L2P pointer sent from the host device, comprises: receiving a request for an L2P pointer from the host device; identifying a first logical address included in the request; Generate or access the first L2P pointer corresponding to the first logical address; and send the first L2P pointer to the host device.

9. The system of claim 4, wherein the controller is further programmed to perform the following operations: In response to a request for a set of L2P pointers sent from the host device, calling the L2P management table; determining a physical area in an idle state for each second L2P pointer based on the L2P management table; Each of the second L2P pointers is generated or obtained by accessing the controller based on each corresponding second logical address included in the request of the set of L2P pointers; Information associated with the corresponding second L2P pointer is stored in each corresponding physical area in the idle state.

10. The system of claim 8, wherein generating or accessing the first L2P pointer corresponding to the first logical address comprises: determining whether the memory system includes a first L2P pointer indicating the first logical address; Upon determining that the memory system includes a first L2P pointer indicating the first logical address, accessing an L2P table in a memory of the memory device or the controller, and obtaining the first L2P pointer from the L2P table; Upon determining that the memory system does not include a first L2P pointer indicating the first logical address, generating the first L2P pointer indicating the first logical address; The first L2P pointer is stored in the L2P table.

11. The system according to any one of claims 4 to 10, wherein: The memory system is a three-dimensional non-volatile memory system, and the memory device is a memory array including a plurality of memory blocks; The storage block includes multiple levels. 12 . The system according to claim 11 , wherein the storage array is a three-dimensional NAND storage array; and the three-dimensional non-volatile storage system is a three-dimensional NAND memory system.

13. A data processing method, applied to a data processing system comprising a memory system and a host device, wherein the memory system comprises a memory device and a controller coupled to the memory device, wherein: The method comprises: The controller maintains an L2P management table; wherein the L2P management table is configured to include a first-level management sub-table and a second-level management sub-table; the first-level management sub-table includes a plurality of first elements; each first element corresponds to a second-level management sub-table; the first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory system; each second element included in the second-level management sub-table is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas; The controller, in response to a request for an L2P pointer sent from the host device, uses the L2P management table to obtain, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element; The controller uses a second element of the second flag to indicate a physical area for storing information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request.

14. The method according to claim 13, wherein The step of using the L2P management table to obtain, from the plurality of physical areas indicated by a first element of a first flag in the first identification information, a physical area indicated by a second element of a second flag in which the second identification information is present, includes: The controller searches a first-level management subtable in the L2P management table to obtain a first element of a first flag, wherein the first identification information is a first element of a first flag; the first element of the first flag is a physical area in a usage state of idle among the multiple physical areas indicated by the first element; The controller searches in the secondary management subtable corresponding to a first element of the first flag to obtain the second identification information as a second element of the second flag; the use status of the physical area indicated by the second element of the second flag is idle; The controller obtains a physical area indicated by a second element of the second flag.

15. The method according to claim 14, wherein When the first-level management subtable is an array consisting of a plurality of first elements and the second-level management subtable is an array consisting of a plurality of second elements, searching the first-level management subtable in the L2P management table to obtain a first element whose first identification information is a first flag includes: searching, by the controller, in ascending order of subscripts of the first elements, or searching in descending order of subscripts of the first elements and stopping searching when the first element whose first identification information is the first flag first appears; Correspondingly, the search is performed in the secondary management subtable corresponding to a first element of the first flag to obtain a second element whose second identification information is a second flag, including: the controller searches in ascending order according to the subscripts of the second elements, or searches in descending order according to the subscripts of the second elements, and stops searching when the second element whose second identification information is a second flag appears for the first time.

16. The method according to claim 13, wherein: The information associated with the first L2P pointer includes status information of the first L2P pointer; wherein the status information is used to indicate whether the physical address indicated by the first L2P pointer in the memory of the memory device or the controller is valid.

17. The method according to claim 13, wherein: The responding to the request for the L2P pointer sent from the host device includes: receiving, by the controller, the request for the L2P pointer sent from the host device; identifying a first logical address included in the request; generating or accessing the first L2P pointer corresponding to the first logical address; and sending the first L2P pointer to the host device.

18. The method according to claim 13, further comprising: The controller calls the L2P management table in response to a request for a set of L2P pointers sent from the host device; determining a physical area in an idle state for each second L2P pointer based on the L2P management table; Each second L2P pointer is generated or obtained by accessing each corresponding second logical address included in the request of the group of L2P pointers by the controller; and information associated with the corresponding second L2P pointer is stored in each corresponding physical area in an idle state.

19. The method according to claim 17, wherein The generating or accessing the first L2P pointer corresponding to the first logical address includes: the controller determining whether the memory system includes a first L2P pointer indicating the first logical address; if it is determined that the memory system includes the first L2P pointer indicating the first logical address, accessing an L2P table in a memory of the memory device or the controller, and obtaining the L2P pointer from the L2P table; if it is determined that the memory system does not include the first L2P pointer indicating the first logical address, generating the first L2P pointer indicating the first logical address; and storing the first L2P pointer in the L2P table.

20. The method according to any one of claims 13 to 19, wherein The memory system is a three-dimensional non-volatile memory system, and the memory device is a memory array including a plurality of memory blocks; The storage block includes multiple levels.

21. The method according to claim 20, wherein The storage array is a three-dimensional NAND storage array; and the three-dimensional non-volatile storage system is a three-dimensional NAND memory system.

22. A computer-readable medium comprising instructions thereon, which, when executed by a processor, cause the processor to perform the following operations: Maintain the L2P management table; among them, The L2P management table is configured to include a primary management sub-table and a secondary management sub-table; the primary management sub-table includes a plurality of first elements; each of the first elements corresponds to a secondary management sub-table; The first element is configured to include first identification information; the first identification information is used to indicate the usage status of multiple physical areas in the memory of a controller in a certain memory system; Each second element included in the secondary management subtable is configured to include second identification information; the second identification information is used to indicate the usage status of the physical area corresponding to the second element among the multiple physical areas; In response to a request for an L2P pointer sent from the host device, using the L2P management table, from the plurality of physical areas indicated by a first element of the first identification information being a first flag, obtain a physical area indicated by a second element of the second identification information being a second flag; the second element being a second element included in the secondary management subtable corresponding to the first element; A physical area indicated by a second element of the second flag is used to store information associated with a first L2P pointer; the first L2P pointer is generated or obtained by the controller based on the request; The host device is capable of communicating with the memory system.

23. The readable medium of claim 22, further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: The step of using the L2P management table to obtain, from the plurality of physical areas indicated by a first element of a first flag in the first identification information, a physical area indicated by a second element of a second flag in which the second identification information is present, includes: Searching in a first-level management subtable in the L2P management table to obtain a first element of a first flag, wherein the first identification information is a first element of a first flag, wherein the first element of the first flag is a physical area in a usage state of idle among the multiple physical areas indicated by the first element; Searching in the secondary management subtable corresponding to a first element of the first flag, obtaining a second identification information as a second element of the second flag; the use status of the physical area indicated by the second element of the second flag is idle; A physical area indicated by a second element of the second flag is obtained.

24. The readable medium of claim 23, further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: When the first-level management subtable is an array consisting of a plurality of first elements and the second-level management subtable is an array consisting of a plurality of second elements, searching the first-level management subtable in the L2P management table to obtain a first element whose first identification information is a first flag includes: Searching is performed in ascending order of the subscripts of the first elements, or searching is performed in descending order of the subscripts of the first elements, and the search stops when the first element whose first identification information is the first flag appears for the first time; Correspondingly, searching in the secondary management subtable corresponding to a first element of the first flag to obtain a second element of the second flag whose second identification information is a second element includes: The search is performed in ascending order of the subscripts of the second elements, or the search is performed in descending order of the subscripts of the second elements, and the search is stopped when the second element whose second identification information is the second mark appears for the first time.

25. The readable medium according to claim 22, wherein: The information associated with the first L2P pointer includes status information of the first L2P pointer; wherein the status information is used to indicate whether the physical address indicated by the first L2P pointer in the memory device in the memory system or the memory of the controller is valid.

26. The readable medium of claim 22, further comprising instructions thereon that, when executed by a processor, cause the processor to perform operations, the controller responding to a request for an L2P pointer sent from the host device, comprising: receiving a request for an L2P pointer from the host device; identifying a first logical address included in the request; Generate or access the first L2P pointer corresponding to the first logical address; and send the first L2P pointer to the host device.

27. The readable medium of claim 22, further comprising instructions thereon that, when executed by a processor, cause the processor to perform the following operations: In response to a request for a set of L2P pointers sent from the host device, calling the L2P management table; determining a physical area in an idle state for each second L2P pointer based on the L2P management table; Each of the second L2P pointers is generated or obtained by accessing the controller based on each corresponding second logical address included in the request of the set of L2P pointers; Information associated with the corresponding second L2P pointer is stored in each corresponding physical area in the idle state.

28. The readable medium of claim 26, further comprising instructions thereon, which when executed by a processor cause the processor to perform the following operations, wherein generating or accessing the first L2P pointer corresponding to the first logical address comprises: determining whether the memory system includes a first L2P pointer indicating the first logical address; Upon determining that the memory system includes a first L2P pointer indicating the first logical address, accessing an L2P table in a memory device in the memory system or a memory of the controller, and obtaining the first L2P pointer from the L2P table; Upon determining that the memory system does not include a first L2P pointer indicating the first logical address, generating the first L2P pointer indicating the first logical address; The first L2P pointer is stored in the L2P table.

29. The readable medium according to any one of claims 22 to 28, wherein the memory system is a three-dimensional non-volatile memory system, and the memory device in the memory system is a memory array including a plurality of memory blocks; wherein the memory blocks include a plurality of levels. 30 . The readable medium according to claim 29 , wherein the storage array is a three-dimensional NAND storage array; and the three-dimensional non-volatile storage system is a three-dimensional NAND memory system.

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