Semiconductor device and method of forming the same

Abstract

A semiconductor device and a forming method thereof, comprising a substrate; a fin located on the substrate; an isolation structure located on the substrate, covering part of the sidewall of the fin and the top surface is lower than the top surface of the fin; a gate structure located on the substrate and across the fin; a conductive layer located on both sides of the gate structure; an initial first hard mask layer located on the top surface of the end of the gate structure; a second hard mask layer located on the top surface of the conductive layer on both sides of the center of the gate structure; a dielectric layer on the initial first hard mask layer and the second hard mask layer; a first via located in the dielectric layer, the bottom exposes the top surface of the center of the gate structure; a second via located in the dielectric layer, the bottom exposes the top surface of the conductive layer on one side of the end of the gate structure; a first contact layer located in the first via; a second contact layer located in the second via; the semiconductor device of the application has good performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] Over the past few decades, the scaling of feature sizes in integrated circuits has been a driving force behind the booming semiconductor industry. Shrinking to increasingly smaller feature sizes enables greater density of functional units on the limited substrate surface of a semiconductor chip. For example, reducing transistor size allows for a greater number of memory or logic devices to be included on a chip, resulting in products with increased capacity. But this drive for greater capacity is not without its challenges. The need to optimize the performance of each individual device has become increasingly apparent.

[0003] In the manufacture of integrated circuit devices, multi-gate transistors are becoming more common as device dimensions continue to shrink. In traditional processes, multi-gate transistors are typically fabricated on silicon substrates or silicon-on-insulator substrates.

[0004] However, shrinking the size of multi-gate transistors is not without its drawbacks. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints of the photolithography process used to pattern these building blocks become increasingly difficult to overcome. The electrical performance of multi-gate transistors in the present technology still needs improvement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can effectively improve the performance of the final semiconductor device.

[0006] To address the aforementioned problems, the present invention provides a semiconductor device comprising: a substrate; a fin located on the substrate; an isolation structure located on the substrate, covering a portion of the sidewalls of the fin and having its top surface lower than the top surface of the fin; a gate structure located on the substrate and spanning the fin; conductive layers located on both sides of the gate structure; an initial first hard mask layer located on the top surface of an end of the gate structure; a second hard mask layer located on the top surfaces of the conductive layers on both sides of the center of the gate structure; a dielectric layer on the initial first hard mask layer and the second hard mask layer; a first via located within the dielectric layer, exposing the top surface of the center of the gate structure at its bottom; a second via located within the dielectric layer, exposing the top surface of the conductive layer on one side of the end of the gate structure at its bottom; a first contact layer located within the first via; and a second contact layer located within the second via.

[0007] The present invention also provides another semiconductor device, comprising: a substrate; a fin located on the substrate; an isolation structure located on the substrate, covering a portion of the sidewalls of the fin and having its top surface lower than the top surface of the fin; a gate structure located on the substrate and spanning the fin; conductive layers located on both sides of the gate structure; a first hard mask layer located on the top surface of an end of the gate structure; an initial second hard mask layer located on the top surfaces of the conductive layers on both sides of the center of the gate structure and on one side of the conductive layer of an end of the gate structure; a dielectric layer on the first hard mask layer and the initial second hard mask layer; a first via located within the dielectric layer, exposing the top surface of the center of the gate structure at its bottom; a second via located within the dielectric layer, exposing the top surface of the conductive layer on the other side of an end of the gate structure at its bottom; a first contact layer located within the first via; and a second contact layer located within the second via.

[0008] Optionally, the center of the gate structure is located at the center line of the gate structure, or the center of the gate structure is located at a distance of 0 nm to 5 nm from the center line of the gate structure, wherein the center line is a symmetrical center line of the gate structure parallel to the extension direction of the fin.

[0009] Optionally, the dielectric constant of the dielectric layer is less than 2.5.

[0010] Optionally, the top surface of the gate structure is not flush with the top surface of the conductive layer.

[0011] Accordingly, the present invention also provides a method for forming a semiconductor device, comprising: providing a substrate having a gate structure and conductive layers located on both sides of the gate structure; forming a dielectric layer on the gate structure and the conductive layers; etching the dielectric layer to form a first via and a second via within the dielectric layer, wherein the bottom of the first via exposes the central top surface of the gate structure, and the bottom of the second via exposes the top surface of the conductive layer on one end side of the gate structure.

[0012] Optionally, a second contact layer is formed within the second through-hole.

[0013] Optionally, a first contact layer may be formed within the first through-hole.

[0014] Optionally, the dielectric constant of the dielectric layer is less than 2.5.

[0015] Optionally, before forming a dielectric layer on the first gate structure and the conductive layer, the method further includes forming a second hard mask layer on top of the conductive layer on both sides of the center of the gate structure.

[0016] Optionally, it may also include forming a first hard mask layer on top of the end of the gate structure.

[0017] Optionally, the step of forming the first hard mask layer and the second hard mask layer includes: forming an initial first hard mask layer on the gate structure, forming an initial second hard mask layer on the conductive layer; forming a patterned layer on the initial first hard mask layer and the initial second hard mask layer, the patterned layer having an opening that exposes the initial first hard mask layer at the top center of the gate structure and the initial second hard mask layers located on both sides of the center of the gate structure; or the opening exposes the initial second hard mask layer on one end side of the gate structure and the initial first hard mask layer on the end of the gate structure.

[0018] Optionally, when the opening exposes the initial first hard mask layer at the top center of the gate structure and the initial second hard mask layers located on both sides of the center of the gate structure, the method further includes the steps of: etching away the top surface of the opening exposing the initial first hard mask layer to expose the top center surface of the gate structure; forming a first sacrificial layer on the top surface exposing the center, and the first sacrificial layer covering the top surface of the initial second hard mask layers located on both sides of the center of the gate structure.

[0019] Optionally, after forming the first sacrificial layer, the method further includes the steps of: removing the initial second hard mask layer on both sides of the end of the gate structure to expose the top surface of the conductive layer on both sides of the end of the gate structure, forming a second hard mask layer on the conductive layer on both sides of the center of the gate structure; and removing the first sacrificial layer.

[0020] Optionally, when the opening exposes the initial second hard mask layer on one side of the end of the gate structure and the initial first hard mask layer on the end of the gate structure, the method further includes the steps of: etching away the initial second hard mask layer exposed by the opening to expose the top surface of the conductive layer; forming a second sacrificial layer on the exposed top surface of the conductive layer, and the second sacrificial layer covering the initial first hard mask layer located at the top of the end of the gate structure.

[0021] Optionally, after forming the second sacrificial layer, the method further includes the steps of: removing the initial first hard mask layer at the center top of the gate structure to expose the center top surface of the gate structure, forming a first hard mask layer at the top of the end of the gate structure, and removing the second sacrificial layer.

[0022] Optionally, the center of the gate structure is located at the center line of the gate structure, or the center of the gate structure is located at a distance of 0 nm to 5 nm from the center line of the gate structure, wherein the center line is a symmetrical center line of the gate structure parallel to the extension direction of the fin.

[0023] Optionally, the substrate includes a substrate, a fin located on the substrate, and an isolation structure, the isolation structure covering a portion of the sidewalls of the fin and having a top surface lower than the top surface of the fin.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the semiconductor device of the present invention, both the first via and the second via are located in the dielectric layer. The bottom of the first via exposes the top surface of the center of the gate structure, and the bottom of the second via exposes the top surface of the conductive layer on one side of the end of the gate structure. The first contact layer is formed in the first via, i.e., at the center of the gate structure, and the second contact layer is formed in the second via, i.e., at the end of the gate structure. This ensures that the formation of the first and second vias can be achieved using only one photomask layer, avoiding the use of multiple photomask layers, reducing the difficulty of the process formation, and solving the problem of misalignment caused by multiple photomasks. At the same time, the second hard mask layer is only located on the top surface of the conductive layer on both sides of the center of the gate structure, replacing the traditional structure that does not have a second hard mask layer except on the conductive layer where the second contact layer is formed. This reduces the volume of the second hard mask layer, thereby reducing the parasitic capacitance between the subsequently formed metal layer 1 (M1) and the conductive layer, and improving the electrical performance of the formed semiconductor device.

[0026] In the formation method of the present invention, after forming a dielectric layer on the gate structure and the conductive layer, the dielectric layer is etched to form a first via and a second via within the dielectric layer. The bottom of the first via exposes the top surface of the center of the gate structure, and the bottom of the second via exposes the top surface of the conductive layer on one side of the end of the gate structure. Since the first via and the second via are formed in the dielectric layer at one time, the formation of the first via and the second via is achieved using only one photomask, avoiding the need for multiple photomask formations. This reduces the problem of multiple photomask misalignments during the formation of the first via and the second via, solves the problem of photomask overlay, and simplifies the process flow. Attached Figure Description

[0027] Figures 1 to 3 This is a cross-sectional view of a semiconductor structure in one embodiment;

[0028] Figures 4 to 27 This is a schematic diagram of the formation process of a semiconductor device according to the first embodiment of the present invention;

[0029] Figures 28 to 41 This is a schematic diagram of the formation process of a semiconductor device according to the second embodiment of the present invention. Detailed Implementation

[0030] The electrical performance of COAG structure MOSFETs in the current technology still needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0031] Figures 1 to 3 This is a cross-sectional view of a semiconductor structure in one embodiment.

[0032] Figure 1 for Figure 2 Top view; Figure 2 yes Figure 1 In the cross-sectional view along section AA Figure 3 yes Figure 1 A cross-sectional view along the BB line.

[0033] Please refer to Figures 1 to 3 Substrate 100; fin 101, located on the substrate 100; first gate structure, spanning the fin 101, including gate structure 103 and secondary gate structure 102, the secondary gate structure 102 and gate structure 103 are distributed parallel to each other, and the gate structure 103 is located between adjacent secondary gate structures 102; gate structure 103 includes end I and center II, end I is adjacent to center II, and center I is located between adjacent end I; sidewall 104, located on the sidewall of the gate structure; source / drain doped layer 105, located in the fin 101 on both sides of the gate structure 103; conductive layer 106, located on top of the source / drain doped layer 105; first hard mask layer 107, located on the top surface of the gate structure; second A hard mask layer 108 is located on top of the conductive layer 106; a dielectric layer 109 is located on the first hard mask layer 107 and the second hard mask layer 108; a first contact layer 110 is located on top of the center II of the gate structure 103, ensuring that the first contact layer 110 is formed on the gate structure of the source region (active), thereby forming a COAG structure MOSFET, and the first contact layer 110 is used to realize the electrical connection between the gate structure and the subsequently formed metal layer 1 (M1); a second contact layer 111 is located in the second hard mask layer 108 on one side of the end I of the gate structure and on top of the conductive layer 106, and is used to realize the electrical connection between the conductive layer and the subsequently formed metal layer 1 (M1).

[0034] The inventors discovered that, in the above embodiments, before forming the first contact layer 110 and the second contact layer 111, a first via needs to be formed on the top of the center II of the gate structure 103, and a second via needs to be formed on the top of the conductive layer 106 on the end I side of the gate structure, so as to provide space for the formation of the first contact layer 110 and the second contact layer 111. However, multiple photomasks are required to form the first and second vias, which leads to the problem of photomask coverage and the easy occurrence of pattern misalignment, increasing the difficulty of the process. Furthermore, when the metal layer 1 (M1) is subsequently formed, the parasitic capacitance between the conductive layer and the metal layer 1 (M1) and the parasitic capacitance between the gate structure and the metal layer 1 (M1) are too large, affecting the electrical performance and performance of the semiconductor device.

[0035] The inventors discovered that, in order to overcome the above problems, after forming a dielectric layer on the gate structure and the conductive layer, the dielectric layer is etched to form a first via and a second via within the dielectric layer. The bottom of the first via exposes the top surface of the center of the gate structure, and the bottom of the second via exposes the top surface of the conductive layer on one side of the end of the gate structure. Since the first and second vias are formed in the dielectric layer at once, only one photomask is used to form the first and second vias, avoiding the need for multiple photomask formations. This reduces the problem of multiple photomask misalignments during the formation of the first and second vias, solves the photomask overlay problem, and simplifies the process flow.

[0036] The inventors also discovered that by forming a second hard mask layer on top of the conductive layers on both sides of the center of the gate structure, and not forming a second hard mask layer on top of the conductive layers on both sides of the ends of the gate structure, after the metal layer 1 (M1) is subsequently formed, there is no second hard mask layer between the metal layer 1 (M1) and the conductive layer, thereby reducing the parasitic capacitance between the metal layer 1 (M1) and the conductive layer and enhancing the electrical performance of the semiconductor device.

[0037] Similarly, a first hard mask layer is formed at the top of the end of the gate structure, but no first hard mask layer is formed at the top of the center of the gate structure. In this way, after the metal layer 1 (M1) is formed at the center, there is no first hard mask layer between the metal layer 1 (M1) and the gate structure, thereby reducing the parasitic capacitance between the metal layer 1 (M1) and the gate structure and enhancing the electrical performance of the semiconductor device.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] First Embodiment

[0040] Figures 4 to 27 This is a schematic diagram of the formation process of a semiconductor device according to the first embodiment of the present invention.

[0041] Please refer to Figure 4 Provides a base of 200.

[0042] In this embodiment, the substrate 200 includes a substrate 201 and a plurality of discretely arranged fins 202 located on the substrate 201, the fins 202 extending along a second direction X.

[0043] In other embodiments, the fins 202 may not be formed on the substrate 201.

[0044] In this embodiment, the substrate 201 is made of single-crystal silicon.

[0045] In other embodiments, the substrate 201 may also be polycrystalline silicon or amorphous silicon. The material of the substrate 201 may also be semiconductor materials such as germanium, silicon germanide, gallium arsenide, silicon-on-insulator (SOI), and germanium-on-insulator (GOI).

[0046] In this embodiment, the fin 202 is made of silicon; in other embodiments, the fin 202 may also be made of semiconductor materials such as silicon and germanium.

[0047] In this embodiment, the method for forming the fin 202 includes: forming a fin material film (not shown) on the substrate 201; forming a patterned layer (not shown) on the fin material film; and etching the fin material film using the patterned layer as a mask until the surface of the substrate 201 is exposed to form the fin 202.

[0048] In this embodiment, an isolation structure 203 is also formed on the substrate 201, the isolation structure 203 covering part of the sidewall of the fin 202.

[0049] In this embodiment, the material of the isolation structure 203 is silicon nitride.

[0050] In other embodiments, the material of the isolation structure 203 may also include one or more combinations of materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and silicon carbonitride boron (SiCBN).

[0051] In this embodiment, the isolation structure 203 serves to form electrical isolation.

[0052] The method for forming the isolation structure 203 includes: forming an isolation structure film (not shown) covering the fin structure 202 on the substrate 201; and etching back the isolation structure film to form the isolation structure 203.

[0053] The process for forming the isolation structure membrane is a deposition process, such as fluid chemical vapor deposition (CVD). Using CVD to form the isolation structure membrane results in better filling performance.

[0054] The steps of the fluid chemical vapor deposition process used to form the isolation structure film include: forming an isolation fluid layer on a substrate 201; and performing water vapor annealing to form the isolation fluid layer into an isolation structure film.

[0055] The parameters for the vapor annealing include: the gases used include oxygen, ozone and gaseous water, and the annealing temperature is 350 degrees Celsius to 750 degrees Celsius.

[0056] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 Top view, Figure 6 yes Figure 5 In the cross-sectional view along line AA, a pseudo-gate structure is formed on the substrate 200. The pseudo-gate structure includes a pseudo-gate structure 204 and a secondary pseudo-gate structure 205, with the pseudo-gate structure 204 located between adjacent secondary pseudo-gate structures 205.

[0057] In this embodiment, a pseudo-gate structure spanning the fin 202 is formed on the substrate 201.

[0058] In this embodiment, the dummy gate structure includes: a dummy gate dielectric layer 206 located on the fin 202, a dummy gate layer 207 located on the dummy gate dielectric layer 206, and a protective layer 208 located on the dummy gate layer 207.

[0059] In this embodiment, the dummy gate structure 204 includes an end portion I and a center portion II.

[0060] In this embodiment, the material of the pseudo-gate dielectric layer 206 is silicon oxide.

[0061] In this embodiment, the material of the pseudo-gate layer 207 is polycrystalline silicon.

[0062] In this embodiment, the material of the protective layer 208 includes silicon nitride or silicon oxide; in other embodiments, the material of the protective layer 208 may also be one or more combinations of silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon boron carbonitride (SiCBN), etc.

[0063] In this embodiment, the protective layer 208 protects the dummy gate layer 207 during the subsequent formation of the source / drain doped layer, and also serves as a stop layer for the subsequent planarization dielectric layer.

[0064] In this embodiment, sidewalls 209 are also formed on the sidewalls of the pseudo-gate layer 207 and the protective layer 208.

[0065] In this embodiment, the sidewall 209 is made of silicon oxide; in other embodiments, the sidewall 209 may be made of one or more of the following materials: silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon oxycarbonate (SiOCN), and silicon boron carbonitride (SiCBN).

[0066] The sidewall 209 is used to define the position of the source and drain doped layers to be formed subsequently, and the sidewall 209 is used to protect the sidewall of the dummy gate layer 207 to avoid morphological defects in the gate layer to be formed subsequently, which would affect the electrical performance of the semiconductor structure.

[0067] The method for forming the sidewall 209 includes: forming a sidewall material layer (not shown) on the top surface of the pseudo-gate dielectric layer 206, the sidewall of the pseudo-gate layer 207, and the sidewall and top surface of the protective layer 208; and etching the sidewall material layer back until the top surfaces of the protective layer 208 and the fin 202 are exposed, thereby forming the sidewall 209.

[0068] The sidewall material layer is formed by one or more of the following processes: chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0069] The process for etching the sidewall material layer is anisotropic dry etching. The process parameters for dry etching are as follows: using fluorine-containing gas (e.g., CH3F, CH2F2 or CHF3), argon and oxygen, with an etching power of 200W to 400W, an etching chamber pressure of 30mTorr to 200mTorr, and an etching temperature of 40℃ to 60℃.

[0070] Please refer to Figure 5 In this embodiment, the pseudo gate structure is only formed in region i of the substrate. This is because during the subsequent formation of the first contact layer on the gate structure, the first contact layer is formed at the top of the center of the gate structure between the source and drain doped layers, thereby reducing the length of the final gate structure and improving the integration of the semiconductor device, thus preparing for the manufacture of semiconductor devices with higher integration.

[0071] Please refer to Figure 7 , Figure 7 and Figure 6 With the view orientation consistent, the source and drain doped layers 210 are formed in the substrate 200 on both sides of the pseudo gate structure 204.

[0072] In this embodiment, the fins 202 on both sides of the dummy gate structure 204 are etched, and the source / drain doped layer 210 is formed in the fins 202.

[0073] The source / drain doped layer 210 has source / drain doped ions.

[0074] The process of forming the source / drain doped layer 210 includes an epitaxial growth process; the process of doping source / drain dopant ions in the source / drain doped layer 210 is an in-situ doping process.

[0075] When the semiconductor device is a P-type device, the material of the source / drain doped layer 210 includes silicon, germanium, or silicon-germanium; the source / drain doping ions are P-type ions, including boron ions and BF ions. 2- The source / drain doped layer 210 is made of silicon, gallium arsenide, or indium gallium arsenide when the semiconductor device is an N-type device; the source / drain doped ions are N-type ions, including phosphorus ions or arsenic ions.

[0076] In this embodiment, the semiconductor device is a P-type device, the source / drain doped layer 210 is made of silicon, and the source / drain dopant ions are boron ions. In other embodiments, the semiconductor device is an N-type device, the source / drain doped layer 210 is made of silicon, and the source / drain dopant ions are phosphorus ions.

[0077] In this embodiment, the etching process for the fin 202 is an anisotropic dry etching process. The parameters of the dry etching process include: the etching gases used include HBr and Ar, wherein the gas flow rate of HBr is 10 sccm to 1000 sccm, and the gas flow rate of Ar is 10 sccm to 1000 sccm.

[0078] Please refer to Figure 8 An interlayer dielectric layer 211 is formed on the substrate 200 and the source / drain doped layer 210, the interlayer dielectric layer 211 exposing the top surface of the dummy gate structure.

[0079] In this embodiment, the interlayer dielectric layer 211 is formed on the substrate 201 and the source / drain doped layer 210. The interlayer dielectric layer 211 covers the sidewalls of the dummy gate structure and exposes the top surface of the protective layer 208.

[0080] In this embodiment, the method for forming the interlayer dielectric layer 211 includes: forming an interlayer dielectric material layer on the substrate 201 and on the source / drain doped layer 210, the interlayer dielectric material layer covering the top surface of the dummy gate structure, planarizing the interlayer dielectric material layer until the top surface of the protective layer 208 is exposed, thereby forming the interlayer dielectric layer 211.

[0081] In this embodiment, the material of the interlayer dielectric layer 211 is silicon oxide; in other embodiments, the material of the interlayer dielectric layer 211 may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity of less than 2.5).

[0082] In this embodiment, the interlayer dielectric layer 211 is formed by chemical vapor deposition; in other embodiments, the interlayer dielectric layer 211 may be formed by one or more combinations of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0083] Please refer to Figure 9 The pseudo-gate structure is etched away to expose the surface of the substrate 200, forming a gate opening 212.

[0084] In this embodiment, the protective layer 208, the dummy gate layer 207, and the dummy gate dielectric layer 206 are removed, and the gate opening 212 is formed between the sidewalls 209.

[0085] In this embodiment, the process for removing the pseudo-gate structure is a wet etching process, specifically using tetramethylammonium hydroxide (TMAH) as the etching solution.

[0086] In other embodiments, the process for removing the dummy gate structure may also be a dry etching process.

[0087] Please refer to Figure 10 A gate structure is formed within the gate opening 212, and the top surface of the gate structure is lower than the top surface of the interlayer dielectric layer 211.

[0088] In this embodiment, the gate structure includes a gate dielectric layer (not shown in the figure) and a gate layer (not shown in the figure) located on the gate dielectric layer.

[0089] In this embodiment, the material of the gate dielectric layer includes high-k dielectric materials, such as oxides – Al2O3, HfO2, Ta2O5, TiO2, ZrO2, etc.

[0090] In other embodiments, the material of the gate dielectric layer may also include other dielectric materials with a dielectric constant higher than 3.9.

[0091] In this embodiment, the gate layer is made of metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

[0092] In this embodiment, the method for forming the gate structure includes: forming the gate dielectric layer on the sidewall and bottom of the gate opening 212, forming an initial gate material layer on the gate dielectric layer, planarizing the initial gate material layer until the top surface of the gate material layer is lower than the top of the interlayer dielectric layer 211, thereby forming the gate structure.

[0093] In this embodiment, the gate structure fills approximately two-thirds of the gate opening 212, with the remaining space providing room for the subsequent formation of a first hard mask layer on the top surface of the gate structure.

[0094] In this embodiment, after removing the pseudo-gate structure, a gate structure is formed. A gate structure 213 is formed in the region corresponding to the pseudo-gate structure 204, and a secondary gate structure 214 is formed in the region corresponding to the secondary pseudo-gate structure 205. The gate structure 213 includes an end I and a center II.

[0095] The center II of the gate structure 213 is located at the center line of the gate structure 213, or the center II of the gate structure 213 is located at a distance of 0 nm to 5 nm from the center line of the gate structure 213, wherein the center line is a symmetrical center line of the gate structure 213 along the extension direction parallel to the fin 201.

[0096] Please refer to Figure 11 An initial first hard mask layer 215 is formed on the gate structure 213.

[0097] In this embodiment, an initial first hard mask layer 215 is formed on the top surface of the gate structure 213 and the subgate structure 214, and the top surface of the initial first hard mask layer 215 is flush with the top surface of the interlayer dielectric layer 211.

[0098] In this embodiment, the material of the initial first hard mask layer 215 is silicon nitride.

[0099] In other embodiments, the material of the initial first hard mask layer 215 may also be one or more combinations of silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon carbonitride (SiCBN), etc.

[0100] In this embodiment, the step of forming the initial first hard mask layer 215 includes: forming an initial first hard mask layer material on the gate structure and the interlayer dielectric layer 211, planarizing the initial first hard mask layer material to expose the top surface of the interlayer dielectric layer 211, and forming the initial first hard mask layer 215 on the top surface of the gate structure 213.

[0101] In this embodiment, the process for forming the initial first hard mask layer 215 is chemical vapor deposition; in other embodiments, the process for forming the initial first hard mask layer 215 may also be physical vapor deposition or atomic layer deposition.

[0102] Please refer to Figure 12 Remove the interlayer dielectric layer 211 to expose the surface of the source / drain doped layer 210, forming a contact hole 216.

[0103] In this embodiment, the contact hole 216 provides space for the subsequent formation of the conductive layer and the initial second hard mask layer.

[0104] In this embodiment, the contact hole 216 is formed by a wet etching process; in other embodiments, the contact hole 216 may also be formed by a dry etching process.

[0105] Please refer to Figure 13 A conductive layer 217 is formed inside the contact hole 216, and an initial second hard mask layer 218 is formed on the top of the conductive layer 217. The top surface of the initial second hard mask layer 218 is flush with the top surface of the initial first hard mask layer 215.

[0106] In this embodiment, the conductive layer 217 is made of metal, including copper, tungsten, or aluminum.

[0107] In this embodiment, the process for forming the conductive layer 217 includes physical vapor deposition or electroplating.

[0108] In this embodiment, the conductive layer 217 serves to subsequently enable electrical connection between the source / drain doped layer 210 and the outside.

[0109] In this embodiment, the top surface of the gate structure 213 is not flush with the top surface of the conductive layer 217.

[0110] Please refer to Figures 14 to 15 , Figure 15 yes Figure 14 Top view, Figure 14 yes Figure 15In the cross-sectional view along line AA, a patterned layer 219 is formed on the initial first hard mask layer 215 and the initial second hard mask layer 218. The patterned layer 219 has an opening 220 that exposes the initial first hard mask layer 215 at the top of the center II of the gate structure 213 and the initial second hard mask layer 218 located on both sides of the center II of the gate structure 213.

[0111] In this embodiment, the material of the patterning layer 219 is photoresist, specifically krypton fluoride (KrF); in other embodiments, argon fluoride (ArF) may also be used.

[0112] In this embodiment, the size of the opening 220 is about 3nm to 10nm larger than the subsequently formed first via. This ensures that the patterned layer 219 can expose the initial first hard mask layer 218 on the conductive layer 217 on both sides of the subsequently formed first contact layer, thereby ensuring that the subsequently formed first sacrificial layer can cover the exposed initial first hard mask layer.

[0113] Please refer to Figure 16 , Figure 16 View direction and Figure 14 With the view orientation aligned, the opening 220 is etched away to expose the initial first hard mask layer 215, up to the top surface of the center II of the gate structure 213.

[0114] In this embodiment, etching removes the opening 220 to expose the top surface of the initial first hard mask layer 215 until the top surface of the center II of the gate structure 213 is exposed. The purpose is to form a first contact layer on the top surface of the center II of the gate structure 213, ensuring that the first contact layer is formed on the top surface of the active gate structure, thereby increasing the density of the formed gate structure and improving the integration of the semiconductor device.

[0115] In this embodiment, the process of removing the opening 220 to expose the initial first hard mask layer 215 is a dry etching process; in other embodiments, a wet etching process can also be used to remove the opening 220 to expose the initial first hard mask layer 215.

[0116] In this embodiment, the dry etching process is used because dry etching has high etching directionality, and the etching rate in the vertical direction is much greater than the etching rate in the horizontal direction. This ensures that the surrounding initial second hard mask layer 218 will not be damaged during the process of removing the opening 220 to expose the initial first hard mask layer 215.

[0117] Please refer to Figure 17A first sacrificial layer 221 is formed on the top surface of the center II of the gate structure 213, and the first sacrificial layer 221 covers the top surface of the initial second hard mask layer 218 located on both sides of the center II of the gate structure 213.

[0118] In this embodiment, the material of the first sacrificial layer 221 is silicon-germanium; in other embodiments, the material of the first sacrificial layer 221 may also be an organic filler layer such as amorphous silicon, amorphous carbon, amorphous germanium, or photoresist.

[0119] In this embodiment, the first sacrificial layer 221 is used to cover the top surface of the initial second hard mask layer 218 located on both sides of the center II of the gate structure 213, thereby protecting the initial second hard mask layer 218 on both sides of the center II of the gate structure 213 and preventing the initial second hard mask layer 218 on both sides of the center II of the gate structure 213 from being damaged in subsequent processes.

[0120] In this embodiment, after the first sacrificial layer 221 is formed, the patterning layer 219 is removed.

[0121] In this embodiment, the process for removing the patterned layer 219 is a wet etching process; in other embodiments, processes such as ashing can also be used to remove the patterned layer 219.

[0122] Please refer to Figures 18 to 19 , Figure 19 yes Figure 18 Top view, Figure 18 yes Figure 19 In the cross-sectional view along line BB, the initial second hard mask layer 218 on both sides of end I of the gate structure 213 is removed to expose the top surface of the conductive layer 217 on both sides of end I of the gate structure 213.

[0123] In this embodiment, a dry etching process is used to remove the initial second hard mask layer 218 on both sides of the end I of the gate structure 213.

[0124] In other embodiments, a wet etching process can also be used to remove the initial second hard mask layer 218 on both sides of the end I of the gate structure 213.

[0125] In this embodiment, the purpose of removing the initial second hard mask layer 218 on both sides of the end I of the gate structure 213 and retaining only the initial second hard mask layer 218 on both sides of the center II of the gate structure 213 is to reduce the volume of the high dielectric constant material on the conductive layer 217 on both sides of the end I of the gate structure 213. This way, when the metal layer 1 (M1) is subsequently formed, the parasitic capacitance between the conductive layer 217 and the metal layer 1 (M1) can be reduced, thereby improving the electrical performance of the formed semiconductor device.

[0126] Please refer to Figure 20 , Figure 20 and Figure 17 With the view direction consistent, the first sacrificial layer 221 is removed, and a second hard mask layer 222 is formed on the conductive layer on both sides of the center II of the gate structure 213.

[0127] In this embodiment, the initial second hard mask layer 218 on both sides of the end I of the gate structure 213 is removed (see reference). Figure 18 Only the initial second hard mask layer 218 on both sides of the center II of the gate structure 213 is retained. The remaining initial second hard mask layer 218 on both sides of the center II of the gate structure 213 is named the second hard mask layer 222, that is, the second hard mask layer 222 is formed on the conductive layer 217 on both sides of the center II of the gate structure 213.

[0128] In this embodiment, since the second hard mask layer 222 is formed only on the conductive layer 217 on both sides of the center II of the gate structure 213, and not on the conductive layer 217 on both sides of the end I of the gate structure 213, the volume of the second hard mask layer 222 is greatly reduced. This significantly reduces the parasitic capacitance between the metal layer M1 and the conductive layer 217 when the metal layer M1 is subsequently formed, thereby helping to improve the performance of the formed semiconductor device.

[0129] Please refer to Figures 21 to 23 , Figure 23 yes Figure 21 and Figure 22 Top view, Figure 21 yes Figure 23 In the cross-sectional view along section AA, Figure 22 Figure 23 In the cross-sectional view of section BB, a dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217.

[0130] In this embodiment, the dielectric constant of the dielectric layer 223 is less than 2.5.

[0131] In this embodiment, the dielectric layer 223 is formed on the surface of the second hard mask layer 222 on both sides of the center II of the gate structure 213, the surface of the initial first hard mask layer 215 on the sub-gate structure 214, the surface of the initial first hard mask layer 215 on the end I of the gate structure 213, and the top surface of the conductive layer 217 on both sides of the end I of the gate structure 213.

[0132] In this embodiment, the dielectric constant of the dielectric layer 223 is less than that of the second hard mask layer 222. This is to ensure that when the metal layer 1 (M1) is subsequently formed, the dielectric constant of the material between the metal layer 1 (M1) and the conductive layer 217 is reduced, thereby reducing the parasitic capacitance between the metal layer 1 (M1) and the conductive layer 217 and improving the electrical performance of the formed semiconductor device.

[0133] Please refer to Figure 24 and Figure 25 , Figure 24 and Figure 21 The view orientation is consistent. Figure 25 and Figure 22 With the view direction consistent, the dielectric layer 223 is etched to form a first via 224 and a second via 225 in the dielectric layer 223. The bottom of the first via 224 exposes the top surface of the center II of the gate structure 213, and the bottom of the second via 225 exposes the top surface of the conductive layer 217 on one side of the end I of the gate structure 213.

[0134] In this embodiment, the etching process for the dielectric layer 223 is a dry etching process; in other embodiments, a wet etching process may also be used to etch the dielectric layer 223.

[0135] In this embodiment, the first through hole 224 provides space for forming the first contact layer; the second contact hole 225 provides space for forming the second contact layer.

[0136] In this embodiment, the steps of forming the first via 224 and the second via 225 include: forming a photomask layer on the dielectric layer 223, exposing the photomask layer, and forming the first via 224 and the second via 225 within the dielectric layer 223. In the process of forming the first via 224 and the second via 225, only one photomask layer is needed to simultaneously form the first via 224 and the second via 225. This replaces the traditional process of forming multiple photomask layers, avoids the problem of misalignment due to multiple photomasks, solves the problem of photomask overlay, and simplifies the process flow.

[0137] Please refer to Figures 26 to 27 , Figure 26 and Figure 24 The view orientation is consistent. Figure 27 and Figure 25 With the views aligned, a first contact layer 226 is formed in the first through hole 224, and a second contact layer 227 is formed in the second through hole 225.

[0138] In this embodiment, the first contact layer 226 is located on the top surface of the center II of the gate structure 213 and is used to realize the electrical connection between the gate structure 213 and the outside. The material of the first contact layer 226 is a metal material, including tungsten, copper, aluminum, titanium, nickel or cobalt, etc.

[0139] In this embodiment, the second contact layer 227 is located on the top surface of the conductive layer 217 on one side of the end I of the gate structure 213, and is used to realize the electrical connection between the conductive layer 217 and the outside. The material of the second contact layer 227 is a metal material, including tungsten, copper, aluminum, titanium, nickel or cobalt, etc.

[0140] In this embodiment, please refer to Figure 23 The dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217. In this way, only one photomask layer is needed to form the first via 224 and the second via 225 at the same time, avoiding the need to use multiple photomask layers to form the first via 224 and the second via 225. This avoids the problem of misalignment of multiple photomask layers, reduces the process difficulty of forming the first via 224 and the second via 225, and improves the accuracy of forming the first via 224 and the second via 225.

[0141] In this embodiment, the material on the conductive layer 217 on the end I side of the gate structure 213 is the dielectric layer 223, which replaces the traditional high-k dielectric constant material, the initial hard mask layer 218. This reduces the dielectric constant of the material between the metal layer 1 (M1) and the conductive layer 217 after the metal layer 1 (M1) is formed, thereby reducing the parasitic capacitance between the metal layer 1 (M1) and the conductive layer 217 and enhancing the electrical performance of the semiconductor device.

[0142] The dielectric constant of the dielectric layer 223 is less than 2.5.

[0143] In this embodiment, the dielectric constant of the dielectric layer 223 is less than 2.5, which is intended to reduce the parasitic capacitance between the conductive layer 217 and the subsequently formed metal layer 1 (M1). This is because the dielectric constant of the material between the conductive layer 217 and the metal layer 1 (M1) (the dielectric layer 223) is reduced, thereby reducing the parasitic capacitance between them.

[0144] Accordingly, the present invention also provides a semiconductor device, including a substrate 201; a fin 202 located on the substrate 201; an isolation structure 203 located on the substrate 201, covering a portion of the sidewalls of the fin 202 and having its top surface lower than the top surface of the fin 202; a gate structure 213 located on the substrate 201 and spanning the fin 202; a conductive layer 217 located on both sides of the gate structure 213; an initial first hard mask layer 215 located on the top surface of the end of the gate structure 213; and a second hard mask layer 222 located on the gate structure. The top surfaces of the conductive layer 217 on both sides of the center II of the gate structure 213; the dielectric layer 223 on the initial first hard mask layer 215 and the second hard mask layer 222; the first via 224 located in the dielectric layer 223, exposing the top surface of the center II of the gate structure 213 at its bottom; the second via 225 located in the dielectric layer 223, exposing the top surface of the conductive layer on one side of the end I of the gate structure 213 at its bottom; the first contact layer 226 located in the first via 224; and the second contact layer 227 located in the second via 225.

[0145] In this embodiment, the dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217. Thus, in the process of forming the first via 224 and the second via 225, only one photomask layer is needed to form the first via 224 and the second via 225 simultaneously. This avoids the need to use multiple photomask layers to form the first via 224 and the second via 225, thereby avoiding the problem of misalignment of multiple photomask layers, reducing the process difficulty of forming the first via 224 and the second via 225, and improving the accuracy of forming the first via 224 and the second via 225.

[0146] In this embodiment, since the second hard mask layer 222 is formed only on the conductive layer 217 on both sides of the center II of the gate structure 213, and not on the conductive layer 217 on both sides of the end I of the gate structure 213, the volume of the second hard mask layer 222 is greatly reduced. This significantly reduces the parasitic capacitance between the metal layer M1 and the conductive layer 217 when the metal layer M1 is subsequently formed, thereby helping to improve the performance of the formed semiconductor device.

[0147] In this embodiment, the center II of the gate structure 213 is located at the center line of the gate structure 213, or the center II of the gate structure 213 is located at a distance of 0 nm to 5 nm from the center line of the gate structure 213, and the center line is the symmetrical center line of the gate structure along the extension direction parallel to the fin 202.

[0148] In this embodiment, the dielectric constant of the dielectric layer is less than 2.5, and the dielectric constant of the dielectric layer 223 is less than 2.5. The purpose is to reduce the parasitic capacitance between the conductive layer 217 and the subsequently formed metal layer 1 (M1). This is because the dielectric constant of the material between the conductive layer 217 and the metal layer 1 (M1) (the dielectric layer 223) is reduced, thereby reducing the parasitic capacitance between them.

[0149] In this embodiment, the top surface of the gate structure 213 is not flush with the top surface of the conductive layer 217.

[0150] Second Embodiment

[0151] The difference between this embodiment and the first embodiment lies in the fact that the opening exposes the initial second hard mask layer on one side of the end of the gate structure and the initial first hard mask layer at the end of the gate structure. Please refer to [reference needed] for details. Figures 28 to 41 .

[0152] Please refer to the first embodiment for the process from providing the substrate to forming the initial first hard mask layer and the initial second hard mask layer. Figures 4 to 13 The process.

[0153] Please refer to Figure 28 A patterned layer 219 is formed on the initial first hard mask layer 215 and the initial second hard mask layer 218. The patterned layer 219 has an opening 228 that exposes the initial second hard mask layer 218 on the end I side of the gate structure 213 and the initial first hard mask layer 215 on the end I of the gate structure 213.

[0154] In this embodiment, the opening 228 also exposes the top surface of the initial hard mask layer 215 on the top of the secondary gate structure 214 on the side of the initial second hard mask layer 218 on the end I side of the gate structure 213.

[0155] In this embodiment, the patterning layer 219 is made of photoresist, specifically argon fluoride (ArF).

[0156] Please refer to Figure 29 The initial second hard mask layer 218 exposed by the opening 228 is etched away until the top surface of the conductive layer 217 is exposed.

[0157] In this embodiment, the etching process for the initial second hard mask layer 218 is a dry etching process.

[0158] Please refer to Figure 30 A second sacrificial layer 229 is formed on the top surface of the exposed conductive layer 217, and the second sacrificial layer 229 covers the initial first hard mask layer 215 located on top of the end I of the gate structure 213.

[0159] In this embodiment, the second sacrificial layer 229 also covers the surface of the initial first hard mask layer 215 at the top of the end I of the subgate structure 214.

[0160] In this embodiment, after the second sacrificial layer 229 is formed, the patterning layer 219 is removed.

[0161] Please refer to Figures 31 to 33 , Figure 33 yes Figure 31 and Figure 32 Top view, Figure 31 yes Figure 33 In the cross-sectional view along section AA, Figure 32 yes Figure 33 In the cross-sectional view of section BB, the initial first hard mask layer 215 on top of the center II of the gate structure 213 is removed to expose the top surface of the center II of the gate structure 213.

[0162] In this embodiment, the process for removing the initial first hard mask layer 215 is a dry etching process; in other embodiments, a wet etching process or an etching process combining a wet etching process and a dry etching process may also be used.

[0163] In this embodiment, the initial hard mask layer 215 on the center II corresponding to the subgate structure 214 and the gate structure 213 is also removed to expose the top surface of the center II of the subgate structure 214.

[0164] Please refer to Figure 34 , Figure 34 and Figure 32 With the view direction consistent, the second sacrificial layer 229 is removed, and a first hard mask layer 230 is formed on top of the end I of the gate structure 213.

[0165] In this embodiment, the first hard mask layer 230 is also formed on the top of the end I of the secondary gate structure 214 on one side of the conductive layer 217.

[0166] Please refer to Figures 35 to 37 , Figure 37 yes Figure 35 and Figure 36 Top view, Figure 35 yes Figure 37 In the cross-sectional view along section AA, Figure 36 Figure 37 In the cross-sectional view of section BB, a dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217.

[0167] Please refer to Figure 38 and Figure 39 , Figure 38 and Figure 35 The view orientation is consistent. Figure 39 and Figure 36 With the view direction consistent, the dielectric layer 223 is etched to form a first via 224 and a second via 225 in the dielectric layer 223. The bottom of the first via 224 exposes the top surface of the center II of the gate structure 213, and the bottom of the second via 225 exposes the top surface of the conductive layer 217 on the end I side of the gate structure 213.

[0168] Please refer to Figures 40 to 41 , Figure 40 and Figure 38 The view orientation is consistent. Figure 41 and Figure 39 With the views aligned, a first contact layer 226 is formed in the first through hole 224, and a second contact layer 227 is formed in the second through hole 225.

[0169] In this embodiment, the first contact layer 226 is located on the top surface of the center II of the gate structure 213 and is used to realize the electrical connection between the gate structure 213 and the outside. The material of the first contact layer 226 is a metal material, including tungsten, copper, aluminum, titanium, nickel or cobalt, etc.

[0170] In this embodiment, the second contact layer 227 is located on the top surface of the conductive layer 217 on one side of the end I of the gate structure 213, and is used to realize the electrical connection between the conductive layer 217 and the outside. The material of the second contact layer 227 is a metal material, including tungsten, copper, aluminum, titanium, nickel or cobalt, etc.

[0171] In this embodiment, please refer to Figure 40 and Figure 41 As can be seen, except for the first hard mask layer 230 on the end I of the gate structure 213 and the top surface of the end I of the sub-gate structure 214 on both sides of the second contact layer 227, the top of the gate structure 213 and the top of the sub-gate structure 214 do not have the first hard mask layer, and are replaced by the dielectric layer 223. The dielectric constant of the dielectric layer 223 material is small (k is less than 2.5). In this way, after the metal layer 1 (M1) is formed, the dielectric constant of the material between the gate structure and the metal layer 1 (M1) is reduced, thereby reducing the parasitic capacitance between the gate structure and the metal layer 1 (M1) and improving the electrical performance of the semiconductor device.

[0172] Accordingly, the present invention also provides a semiconductor device, comprising: a substrate 201; a fin 202 located on the substrate 201; an isolation structure 203 located on the substrate 201, covering a portion of the sidewalls of the fin 202 and having its top surface lower than the top surface of the fin 202; a gate structure 213 located on the substrate 201 and spanning the fin 202; a conductive layer 217 located on both sides of the gate structure 213; a first hard mask layer 230 located on the top surface of an end I of the gate structure 213; and an initial second hard mask layer 218 located on both sides of the conductive layer 217 at the center II of the gate structure 213. The top surface of the gate structure 213 and the top surface of the conductive layer 217 on one side of the end I of the gate structure 213; the dielectric layer 223, on the first hard mask layer 230 and the initial second hard mask layer 218; the first via 224, located in the dielectric layer 223, with the bottom exposed to the top surface of the center II of the gate structure 213; the second via 225, located in the dielectric layer 223, with the bottom exposed to the top surface of the conductive layer 217 on the other side of the end I of the gate structure 213; the first contact layer 226, located in the first via 224; and the second contact layer 227, located in the second via 226.

[0173] The center II of the gate structure 213 is located at the center line of the gate structure 213, or the center II of the gate structure 213 is located at a distance of 0 nm to 5 nm from the center line of the gate structure 213, wherein the center line is a symmetrical center line of the gate structure 213 along the extension direction parallel to the fin 201.

[0174] In this embodiment, the dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217. Thus, in the process of forming the first via 224 and the second via 225, only one photomask layer is needed to form the first via 224 and the second via 225 simultaneously. This avoids the need to use multiple photomask layers to form the first via 224 and the second via 225, thereby avoiding the problem of misalignment of multiple photomask layers, reducing the process difficulty of forming the first via 224 and the second via 225, and improving the accuracy of forming the first via 224 and the second via 225.

[0175] In this embodiment, except for the first hard mask layer 230 on the end I of the gate structure 213 and the top surface of the end I of the sub-gate structure 214 on both sides of the second contact layer 227, the top of the gate structure 213 and the top of the sub-gate structure 214 do not have the first hard mask layer, and are replaced by the dielectric layer 223. The dielectric constant of the dielectric layer 223 is small (k is less than 2.5). Thus, after the metal layer 1 (M1) is formed, the dielectric constant of the material between the gate structure 213 and the metal layer 1 (M1) is reduced, thereby reducing the parasitic capacitance between the gate structure and the metal layer 1 (M1) and improving the electrical performance of the semiconductor device.

[0176] The dielectric constant of the dielectric layer 223 is less than 2.5.

[0177] In this embodiment, the dielectric constant of the dielectric layer 223 is less than 2.5, which is intended to reduce the parasitic capacitance between the gate structure 213 and the subsequently formed metal layer 1 (M1). This is because the dielectric constant of the material (the dielectric layer 223) between the gate structure 213 and the metal layer 1 (M1) is reduced, thereby reducing the parasitic capacitance between them.

[0178] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate; a fin on the substrate; an isolation structure on the substrate covering part of the sidewall of the fin and having a top surface lower than the top surface of the fin; a gate structure on the substrate and across the fin, the gate structure comprising ends and a center, the ends adjacent to the center, the center between the adjacent ends; a conductive layer on both sides of the gate structure; a first hard mask layer on the top surface of the ends of the gate structure; a second hard mask layer on the top surface of the conductive layer on both sides of the center of the gate structure; a dielectric layer on the first hard mask layer and the second hard mask layer, the dielectric layer on the top surface of the center of the gate structure and covering the top surface of the conductive layer on both sides of the ends of the gate structure; a first via in the dielectric layer exposing the top surface of the center of the gate structure at the bottom; a second via in the dielectric layer exposing the top surface of the conductive layer on one side of the end of the gate structure at the bottom, wherein one mask layer forms the first via and the second via simultaneously; a first contact layer in the first via, the first contact layer on the top surface of the center of the gate structure for realizing electrical connection between the gate structure and the outside; a second contact layer in the second via, the second contact layer on the top surface of the conductive layer on one side of the end of the gate structure for realizing electrical connection between the conductive layer and the outside.

2. A semiconductor device, characterized by, Comprising: a substrate; a fin on the substrate; an isolation structure on the substrate covering part of the sidewall of the fin and having a top surface lower than the top surface of the fin; a gate structure on the substrate and across the fin, the gate structure comprising ends and a center, the ends adjacent to the center, the center between the adjacent ends; a conductive layer on both sides of the gate structure; a first hard mask layer on the top surface of the ends of the gate structure; a second hard mask layer on the top surface of the conductive layer on both sides of the center of the gate structure and on the top surface of the conductive layer on one side of the end of the gate structure; a dielectric layer on the first hard mask layer and the second hard mask layer, the dielectric layer on the top surface of the center of the gate structure and covering the top surface of the conductive layer on the other side of the end of the gate structure; a first via in the dielectric layer exposing the top surface of the center of the gate structure at the bottom; a second via in the dielectric layer exposing the top surface of the conductive layer on the other side of the end of the gate structure at the bottom, wherein one mask layer forms the first via and the second via simultaneously; a first contact layer in the first via, the first contact layer on the top surface of the center of the gate structure for realizing electrical connection between the gate structure and the outside; a second contact layer in the second via, the second contact layer on the top surface of the conductive layer on one side of the end of the gate structure for realizing electrical connection between the conductive layer and the outside.

3. The semiconductor device according to claim 1 or 2, wherein The center of the gate structure is located at a center line of the gate structure, or the center of the gate structure is located at a distance of 0nm to 5nm from the center line of the gate structure, the center line being a symmetric center line of the gate structure along the direction in which the fin extends.

4. The semiconductor device according to claim 1 or 2, wherein The dielectric constant of the dielectric layer is less than 2.

5.

5. The semiconductor device according to claim 1 or 2, wherein The top surface of the gate structure is not flush with the top surface of the conductive layer.

6. A method of forming a semiconductor device, characterized by, Comprising: Providing a substrate, the substrate having a gate structure and a conductive layer on both sides of the gate structure, the gate structure comprising end portions and a center portion, the end portions being adjacent to the center portion, the center portion being located between the adjacent end portions; Forming a dielectric layer on the gate structure and the conductive layer, the dielectric layer being located on the top surface of the center portion of the gate structure and covering the top surface of the conductive layer on both sides or one side of the end portions of the gate structure; Etching the dielectric layer to form a first via and a second via in the dielectric layer, the bottom of the first via exposing the top surface of the center portion of the gate structure, and the bottom of the second via exposing the top surface of the conductive layer on one side of the end portions of the gate structure, wherein one mask layer simultaneously forms the first via and the second via; Forming a first contact layer in the first via, the first contact layer being located on the top surface of the center portion of the gate structure, for realizing electrical connection between the gate structure and the outside; Forming a second contact layer in the second via, the second contact layer being located on the top surface of the conductive layer on one side of the end portions of the gate structure, for realizing electrical connection between the conductive layer and the outside.

7. The method for forming a semiconductor device according to Claim 6, wherein The dielectric constant of the dielectric layer is less than 2.

5.

8. The method for forming a semiconductor device according to Claim 6, wherein Before forming the dielectric layer on the gate structure and the conductive layer, further comprising: forming a second hard mask layer on the top of the conductive layer on both sides of the center portion of the gate structure.

9. The method for forming a semiconductor device according to Claim 8, wherein Further comprising: Forming a first hard mask layer on the top of the end portions of the gate structure.

10. The method of forming a semiconductor device of claim 9, wherein, The steps of forming the first hard mask layer and the second hard mask layer comprise: forming an initial first hard mask layer on the gate structure and an initial second hard mask layer on the conductive layer; forming a patterning layer on the initial first hard mask layer and the initial second hard mask layer, the patterning layer having an opening, the opening exposing the initial first hard mask layer on the top of the center portion of the gate structure and the initial second hard mask layer on both sides of the center portion of the gate structure; or the opening exposing the initial second hard mask layer on one side of the end portions of the gate structure and the initial first hard mask layer on the end portions of the gate structure.

11. The method for forming a semiconductor device according to Claim 10, wherein When the opening exposes the initial first hard mask layer on the top of the center portion of the gate structure and the initial second hard mask layer on both sides of the center portion of the gate structure, further comprising the step of: etching to remove the top surface of the opening exposing the initial first hard mask layer, to expose the top surface of the center portion of the gate structure; Forming a first sacrificial layer on the exposed top surface of the center portion of the gate structure, and the first sacrificial layer covering the top surface of the initial second hard mask layer on both sides of the center portion of the gate structure.

12. The method for forming a semiconductor device according to Claim 11, wherein After the first sacrificial layer is formed, further comprising the steps of: removing the initial second hard mask layer on both sides of the end of the gate structure to expose the top surface of the conductive layer on both sides of the end of the gate structure, forming a second hard mask layer on the conductive layer on both sides of the center of the gate structure; removing the first sacrificial layer.

13. The method for forming a semiconductor device according to Claim 10, wherein When the opening exposes the initial second hard mask layer on one side of the end of the gate structure and the initial first hard mask layer on the end of the gate structure, further comprising the step of: etching to remove the initial second hard mask layer exposed by the opening to expose the top surface of the conductive layer; A second sacrificial layer is formed on the top surface of the conductive layer exposed, and the second sacrificial layer covers the initial first hard mask layer on the top of the end of the gate structure.

14. The method for forming a semiconductor device according to Claim 13, wherein After the second sacrificial layer is formed, further comprising the steps of: removing the initial first hard mask layer on the top of the center of the gate structure to expose the top surface of the center of the gate structure, forming a first hard mask layer on the top of the end of the gate structure; The second sacrificial layer is removed.

15. The method for forming a semiconductor device according to Claim 6, wherein The center of the gate structure is located at the center line of the gate structure, or the center of the gate structure is located at a distance of 0nm to 5nm from the center line of the gate structure, and the center line is the center line of symmetry of the gate structure along the direction parallel to the fin extension.

16. The method for forming a semiconductor device according to Claim 6, wherein The substrate includes a substrate, a fin on the substrate, and an isolation structure covering part of the sidewall of the fin and having a top surface lower than the top surface of the fin.

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